From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::341; helo=mail-wm1-x341.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 34BF82194D3AE for ; Fri, 11 Jan 2019 10:04:54 -0800 (PST) Received: by mail-wm1-x341.google.com with SMTP id b11so3260399wmj.1 for ; Fri, 11 Jan 2019 10:04:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=LVhEe7+D0IIejGxrlfFRalCcVJWsN17o3l0Yj9jsncA=; b=PnjOv0eyZMfnu03aU4zIDI9HHk24XFMPS5lkQi2ax6KRLhET895OYEUJmtP0IQpgew kb06p8+EvkxRbEQluHnrjo6pYowZgYLDXBIk83tkjuTBFQoq5fd/oftqcqmG+VctHOh2 shHy4RIPEy0MoGAZCYjkjdzlmYIcEby42wAww= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=LVhEe7+D0IIejGxrlfFRalCcVJWsN17o3l0Yj9jsncA=; b=dgeUgguZkJ5b/NiZWvgb/oCToDvaqnJZGiyb5tYqkqLq3V6im3w03aZkjC6Il5w+0j nw9bDpPQYRxsXdSYmQ/QHyzPn7Yne9++thBWRBaSEmZ9JhWxPUS9lBOT3GRWwdog8EPn KyNSl5mFIM0j+uSn60V4g16W7QxPfoaexcLclYKHmQq5EAhlmb7w33xySlmt45+drVvO TKnXcXX8tOEHwqonoT8sXrd8oz/EwLZmyMNzySRP/cXLTxe8KVWe+TqlcZhrlQyfc+vj EbtzL/D6izH5ZCQeLshIcvWay27J03uPmaNj1jWGkX+j2yQcl3wUM531I/rpQs4mP2ba Q9zQ== X-Gm-Message-State: AJcUukf6tmdutPo3PqesLccgak5r567HaXGByXxvx1CunCfPi4JEFB31 6As6WFhQQzIpRVMUoTND0rFbAGu8xZk= X-Google-Smtp-Source: ALg8bN50MBk1wCKL+NV3ldPnHWySjzpi8Zh3er7pmcj1eG9tXdRfrEUDkAkGct3ut+dMDL7fd3uznQ== X-Received: by 2002:a1c:6243:: with SMTP id w64mr3117698wmb.153.1547229893501; Fri, 11 Jan 2019 10:04:53 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id 207sm6174349wmb.12.2019.01.11.10.04.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 Jan 2019 10:04:52 -0800 (PST) Date: Fri, 11 Jan 2019 18:04:51 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org Message-ID: <20190111180451.pcvkknshh6gbmlyx@bivouac.eciton.net> References: <20190104180432.24480-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20190104180432.24480-1-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH 1/2] ArmPkg/ArmMmuLib ARM: add missing support for non-shareable cached mappings X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Jan 2019 18:04:55 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Jan 04, 2019 at 07:04:31PM +0100, Ard Biesheuvel wrote: > We introduced support for non-shareable cached mappings to the AArch64 > version of ArmMmuLib a while ago, but the ARM version was left behind, > so fix it. Consider adding a reference to the corresponding aarch64 commit (829633e3a82)? Either way: Reviewed-by: Leif Lindholm > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > --- > ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c > index 889b22867dc7..b237321a8d8b 100644 > --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c > +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c > @@ -135,6 +135,11 @@ PopulateLevel2PageTable ( > case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK: > PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK; > break; > + case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE: > + case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE: > + PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK; > + PageAttributes &= ~TT_DESCRIPTOR_PAGE_S_SHARED; > + break; > case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH: > case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH: > PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_THROUGH; > @@ -239,6 +244,10 @@ FillTranslationTable ( > case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK: > Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0); > break; > + case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE: > + Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0); > + Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED; > + break; > case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH: > Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0); > break; > @@ -251,6 +260,10 @@ FillTranslationTable ( > case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK: > Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1); > break; > + case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE: > + Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1); > + Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED; > + break; > case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH: > Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1); > break; > -- > 2.17.1 >