From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::444; helo=mail-wr1-x444.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 490B8211B76B3 for ; Mon, 14 Jan 2019 03:24:30 -0800 (PST) Received: by mail-wr1-x444.google.com with SMTP id c14so22482435wrr.0 for ; Mon, 14 Jan 2019 03:24:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=0B1Ag6EKXLqzBNFCvCsWE9XRb7h3Xg/bklTvEgL8lbg=; b=C/kx4usAcFpGyWhLknD0xc7NEO4YhhtQXX3uWsOHtZW0f5MmGBkdPmZpkSe1k6aT99 RHLyEY03P7D+K3o1ygGvuBte6I9Nuwed46eMHhPnkJM/NfQUD2RAuVjeeGYWmA5AQvry RFIwraMkT+1v02kOVDHcpQGKydglR1Jq4/g6o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=0B1Ag6EKXLqzBNFCvCsWE9XRb7h3Xg/bklTvEgL8lbg=; b=sU5r7DtleAaCDpZe9poPGSl7w8MqW6xo38BgPlIkKBWs62CCFcSchyyBMRLU/seUeN Q4f+0buC2g676DE0+oqGHFLHnz9y9inNR1mgASsOd4IWNHzIMmpgl1UskCKPXE7hk/6i gOALg7PrEY7jztwEyp+9dVBtrCiAmavp4J+1JbQY/kIklEa5oxh9m6jaMiWG/Ro9Z7bX u56NJGtMz8QobdTt742s3VTV8OyQp2boWt7b8yASk51BBDQyuzhnd+hxg+z73neRk+Zs 9u0cDGJ+NaDmQAFxE1JznqcaI+fqJl/AW0KARQpvPNH3g3Haswo8E0nk9ZJcE18kkSI9 BqqA== X-Gm-Message-State: AJcUukeIUNsCxRUPucveUtmG2wHMswPFfEwQ2c5FgLXfF6B1O1yD+zuS oU0EMG0204ZEMrZ4jzE7I959+Q== X-Google-Smtp-Source: ALg8bN4P23pyYol6a+zcvkKtSa4RawxdXcmoMveI8wCIn7Y+g/kIAcTtgBeGShzE6G3xDY7k7Zp7Qw== X-Received: by 2002:adf:9d4c:: with SMTP id o12mr22486919wre.94.1547465066727; Mon, 14 Jan 2019 03:24:26 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id t63sm23054741wmt.8.2019.01.14.03.24.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 Jan 2019 03:24:25 -0800 (PST) Date: Mon, 14 Jan 2019 11:24:24 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org Message-ID: <20190114112424.weqnta4n4jijrszz@bivouac.eciton.net> References: <20181221150848.4783-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20181221150848.4783-1-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH] ArmPkg/ArmGicV3Dxe: use correct value for ARM_GICD_IROUTER X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 14 Jan 2019 11:24:30 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Dec 21, 2018 at 04:08:48PM +0100, Ard Biesheuvel wrote: > Use the correct value for ARM_GICD_IROUTER as per the GIC spec, > and fix the code that relies on the value being skewed by 32 x 8 > bytes. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > --- > ArmPkg/Include/Library/ArmGicLib.h | 2 +- > ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h > index 5775905ca91b..b52b77628ae1 100644 > --- a/ArmPkg/Include/Library/ArmGicLib.h > +++ b/ArmPkg/Include/Library/ArmGicLib.h > @@ -43,7 +43,7 @@ > #define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register > > // GICv3 specific registers > -#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers > +#define ARM_GICD_IROUTER 0x6000 // Interrupt Routing Registers Actually, whilst I agree the above would be more consistent, both revisions C and D of ARM IHI 0069 list the address offset of ARM_GICD_IROUTER as 0x6100 (and the preceding register space as "Reserved"). / Leif > > // GICD_CTLR bits > #define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE) > diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > index 1558db31713a..7d891873ba82 100644 > --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > @@ -466,7 +466,7 @@ GicV3DxeInitialize ( > } > > // Route the SPIs to the primary CPU. SPIs start at the INTID 32 > - for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) { > + for (Index = 32; Index < mGicNumInterrupts; Index++) { > MmioWrite32 ( > mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), > CpuTarget > -- > 2.19.2 >