From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::343; helo=mail-wm1-x343.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 554502119F075 for ; Mon, 14 Jan 2019 09:02:10 -0800 (PST) Received: by mail-wm1-x343.google.com with SMTP id y139so287557wmc.5 for ; Mon, 14 Jan 2019 09:02:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=R/GZKy622/3Jgpbz3gXD7o+t8oWxQIucI5nmW8qloTk=; b=RPGRYoPe0tn5JpKUivB4dctri5RdJhPA+MvIOlMUy/oJ5nQAXb5CehsaVn8vaLb7+7 6vONHLI+/8Vv89K4LJZbQCWXNMqhBLyuFXuUuvIogv9bgTfyj/egiuVSsEnjCor4Jqlm R6aYf2wJ8ftnRBnvOSWdi2LeqheFUWPi/DnIQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=R/GZKy622/3Jgpbz3gXD7o+t8oWxQIucI5nmW8qloTk=; b=ZL1mqS6+aST6QtbqmkZ+rjTiBGYF8cscUL16AQ0A23iOkvlGNLl9UspotxmVxX7XQu n8DSyK3kjnKh6ewsdjrVhiM/cZFb1gJnRdAQspZFRis59+Huq4Jek9X6ZFen5KzUG6hU U9mCrAavctyvyVizGHjxef0Tg8b2z/Oi4s6e8KzGy3bmMvAnSqvn0jdlyKnno2ycILNO bFMWD3Cvb5X3BxNGRZTfNvGA5+FpbfxXvnxCVyjjxbHilczhQOmLwCPGYWwEnfanlKnN 4itnC6WJpBA3PCFoFpit5AAQrPfvqVAWxZdGgtlhz+jt7XBr8B94g1tCKpHj7tijrfQ1 3vQg== X-Gm-Message-State: AJcUukeAl3l0vOORwtKXo5jlDQ9/c6S9wMQ9x1+F0DtfRgrfzKCU4JAw Gd0n2EzdKwYNY4nzl7Y6MgQqOTjNqUR5Mw== X-Google-Smtp-Source: ALg8bN5XvVybFnoBBrwv/y9y/lLcUPSFtnZ0rafNbixoiKGSGUMmwdtQGvYx0f6x+4nGpJYYSy1PKQ== X-Received: by 2002:a1c:dc86:: with SMTP id t128mr98059wmg.42.1547485328398; Mon, 14 Jan 2019 09:02:08 -0800 (PST) Received: from dogfood.home ([2a01:cb1d:112:6f00:2ced:5cd0:34f4:7bab]) by smtp.gmail.com with ESMTPSA id h184sm17224319wmf.0.2019.01.14.09.02.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 14 Jan 2019 09:02:07 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Mon, 14 Jan 2019 18:01:57 +0100 Message-Id: <20190114170205.9748-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 Subject: [PATCH edk2-platforms 0/8] Silicon/SynQuacer: add support for 32-bit mode X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 14 Jan 2019 17:02:10 -0000 This series fixes various issues that prevent the SynQuacer/DeveloperBox platform from being built or executed in 32-bit mode. Ard Biesheuvel (8): Silicon/SynQuacer/NetsecDxe: fix 32-bit build Silicon/SynQuacer/OpteeRngDxe: fix 32-bit build Silicon/SynQuacerPciHostBridgeLib: fix MMIO32-only configuration Silicon/SynQuacerMemoryInitPeiLib: don't map memory above MAX_ALLOC_ADDRESS Silicon/SynQuacerMemoryInitPeiLib: fix 32-bit build Silicon/SynQuacer/Stage2Tables: fix 32-bit build Platform/Socionext/DeveloperBox: disable EbcDxe for ARM builds Platform/Socionext/DeveloperBox: add resolution for ArmSoftFloatLib Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 7 ++++++- Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 2 ++ .../SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c | 6 +++--- .../Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h | 2 +- .../SynQuacer/Drivers/OpteeRngDxe/OpteeRng.c | 2 +- .../SynQuacerMemoryInitPeiLib.c | 11 ++++++++--- .../SynQuacerPciHostBridgeLib.c | 8 ++++++++ .../Socionext/SynQuacer/Stage2Tables/Stage2Tables.S | 12 +++++++++--- 8 files changed, 38 insertions(+), 12 deletions(-) -- 2.17.1