[PATCH edk2-platforms 0/8] Silicon/SynQuacer: add support for 32-bit mode

[PATCH edk2-platforms 0/8] Silicon/SynQuacer: add support for 32-bit mode

[Ard Biesheuvel]

This series fixes various issues that prevent the SynQuacer/DeveloperBox
platform from being built or executed in 32-bit mode.

Ard Biesheuvel (8):
  Silicon/SynQuacer/NetsecDxe: fix 32-bit build
  Silicon/SynQuacer/OpteeRngDxe: fix 32-bit build
  Silicon/SynQuacerPciHostBridgeLib: fix MMIO32-only configuration
  Silicon/SynQuacerMemoryInitPeiLib: don't map memory above
    MAX_ALLOC_ADDRESS
  Silicon/SynQuacerMemoryInitPeiLib: fix 32-bit build
  Silicon/SynQuacer/Stage2Tables: fix 32-bit build
  Platform/Socionext/DeveloperBox: disable EbcDxe for ARM builds
  Platform/Socionext/DeveloperBox: add resolution for ArmSoftFloatLib

 Platform/Socionext/DeveloperBox/DeveloperBox.dsc     |  7 ++++++-
 Platform/Socionext/DeveloperBox/DeveloperBox.fdf     |  2 ++
 .../SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c      |  6 +++---
 .../Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h    |  2 +-
 .../SynQuacer/Drivers/OpteeRngDxe/OpteeRng.c         |  2 +-
 .../SynQuacerMemoryInitPeiLib.c                      | 11 ++++++++---
 .../SynQuacerPciHostBridgeLib.c                      |  8 ++++++++
 .../Socionext/SynQuacer/Stage2Tables/Stage2Tables.S  | 12 +++++++++---
 8 files changed, 38 insertions(+), 12 deletions(-)

-- 
2.17.1

[PATCH edk2-platforms 1/8] Silicon/SynQuacer/NetsecDxe: fix 32-bit build

[Ard Biesheuvel]

Tweak the definition of pfdep_cpu_addr_t and add some intermediate
UINTN casts so that the NETSEC driver builds cleanly in 32-bit mode.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c             | 6 +++---
 Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c
index fa8ae79da28e..1bf1b3cb8f05 100644
--- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c
+++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c
@@ -103,9 +103,9 @@ Probe (
   ogma_err = ogma_init (
                (VOID *)(UINTN)LanDriver->Dev->Resources[0].AddrRangeMin,
                Handle, &Param,
-               (VOID *)dmac_hm_cmd_base, dmac_hm_cmd_size,
-               (VOID *)dmac_mh_cmd_base, dmac_mh_cmd_size,
-               (VOID *)core_cmd_base, core_cmd_size,
+               (VOID *)(UINTN)dmac_hm_cmd_base, dmac_hm_cmd_size,
+               (VOID *)(UINTN)dmac_mh_cmd_base, dmac_mh_cmd_size,
+               (VOID *)(UINTN)core_cmd_base, core_cmd_size,
                &LanDriver->Handle);
   if (ogma_err != OGMA_ERR_OK) {
     DEBUG ((DEBUG_ERROR, "NETSEC: ogma_init() failed with error code %d\n",
diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h
index d31a9c48bafc..95796b4cfe6a 100644
--- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h
+++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h
@@ -71,7 +71,7 @@ typedef struct {
 typedef VOID *pfdep_dev_handle_t;
 typedef PACKET_HANDLE *pfdep_pkt_handle_t;
 typedef EFI_PHYSICAL_ADDRESS pfdep_phys_addr_t;
-typedef UINT64 pfdep_cpu_addr_t;
+typedef UINTN pfdep_cpu_addr_t;
 
 typedef int pfdep_hard_lock_t;
 typedef int pfdep_soft_lock_t;
-- 
2.17.1

[PATCH edk2-platforms 2/8] Silicon/SynQuacer/OpteeRngDxe: fix 32-bit build

[Ard Biesheuvel]

Replace a UINT64 cast of a virtual address with a UINTN cast so
that this driver can be built for 32-bit ARM as well.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Silicon/Socionext/SynQuacer/Drivers/OpteeRngDxe/OpteeRng.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Silicon/Socionext/SynQuacer/Drivers/OpteeRngDxe/OpteeRng.c b/Silicon/Socionext/SynQuacer/Drivers/OpteeRngDxe/OpteeRng.c
index 089fad8b5ce5..e55d87ea4299 100644
--- a/Silicon/Socionext/SynQuacer/Drivers/OpteeRngDxe/OpteeRng.c
+++ b/Silicon/Socionext/SynQuacer/Drivers/OpteeRngDxe/OpteeRng.c
@@ -159,7 +159,7 @@ GetRNG (
     InvokeFunctionArg.Params[0].Attribute =
       OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT;
     InvokeFunctionArg.Params[0].Union.Memory.BufferAddress =
-      (UINT64) OutPointer;
+      (UINTN) OutPointer;
     InvokeFunctionArg.Params[0].Union.Memory.Size = ValueLength;
 
     Status = OpteeInvokeFunction (&InvokeFunctionArg);
-- 
2.17.1

[PATCH edk2-platforms 3/8] Silicon/SynQuacerPciHostBridgeLib: fix MMIO32-only configuration

[Ard Biesheuvel]

When running on 32-bit ARM, we cannot decode the MMIO64 region, and
so we don't set the EFI_PCI_HOST_BRIDGE_MEM64_DECODE flag in this
case. However, with that flag cleared, it is no longer permitted to
include a definition for the placement of the MMIO64 region either,
so remove those as well if MDE_CPU_ARM is set (which is the same
condition under which EFI_PCI_HOST_BRIDGE_MEM64_DECODE is cleared)

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c
index 7c096f0801dd..117cf6cfd81b 100644
--- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c
+++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c
@@ -109,8 +109,12 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = {
     { SYNQUACER_PCI_SEG0_MMIO32_MIN,
       SYNQUACER_PCI_SEG0_MMIO32_MAX,
       MAX_UINT64 - SYNQUACER_PCI_SEG0_MMIO32_XLATE + 1 },    // Mem
+#ifndef MDE_CPU_ARM
     { SYNQUACER_PCI_SEG0_MMIO64_MIN,
       SYNQUACER_PCI_SEG0_MMIO64_MAX },      // MemAbove4G
+#else
+    { MAX_UINT64, 0x0 },                    // MemAbove4G
+#endif
     { MAX_UINT64, 0x0 },                    // PMem
     { MAX_UINT64, 0x0 },                    // PMemAbove4G
     (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
@@ -130,8 +134,12 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = {
     { SYNQUACER_PCI_SEG1_MMIO32_MIN,
       SYNQUACER_PCI_SEG1_MMIO32_MAX,
       MAX_UINT64 - SYNQUACER_PCI_SEG1_MMIO32_XLATE + 1 },    // Mem
+#ifndef MDE_CPU_ARM
     { SYNQUACER_PCI_SEG1_MMIO64_MIN,
       SYNQUACER_PCI_SEG1_MMIO64_MAX },      // MemAbove4G
+#else
+    { MAX_UINT64, 0x0 },                    // MemAbove4G
+#endif
     { MAX_UINT64, 0x0 },                    // PMem
     { MAX_UINT64, 0x0 },                    // PMemAbove4G
     (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1]
-- 
2.17.1

[PATCH edk2-platforms 4/8] Silicon/SynQuacerMemoryInitPeiLib: don't map memory above MAX_ALLOC_ADDRESS

[Ard Biesheuvel]

When encountering memory that is above the threshold of what we can
map, don't add it to the virtual memory table. This table is only
used by the early MMU code that creates the 1:1 mapping, and since
it cannot be mapped in the first place, there is no point.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
index 1402ecafce4a..3955b6df84a0 100644
--- a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
+++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
@@ -156,17 +156,22 @@ DeclareDram (
 
   DramDescriptor = *VirtualMemoryTable + ARRAY_SIZE (mVirtualMemoryTable);
 
-  for (Idx = 0; Idx < RegionCount; Idx++, DramDescriptor++) {
+  for (Idx = 0; Idx < RegionCount; Idx++) {
     Status = DramInfo->GetRegion (Idx, &Base, &Size);
     ASSERT_EFI_ERROR (Status);
 
     BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,
       mDramResourceAttributes, Base, Size);
 
+    if (Base > MAX_ALLOC_ADDRESS - Size + 1) {
+      continue;
+    }
+
     DramDescriptor->PhysicalBase = Base;
     DramDescriptor->VirtualBase  = Base;
-    DramDescriptor->Length       = Size;
+    DramDescriptor->Length       = MIN (Size, MAX_ALLOC_ADDRESS - Base + 1);
     DramDescriptor->Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+    DramDescriptor++;
   }
 
   DramDescriptor->PhysicalBase = 0;
-- 
2.17.1

[PATCH edk2-platforms 5/8] Silicon/SynQuacerMemoryInitPeiLib: fix 32-bit build

[Ard Biesheuvel]

Add a missing intermediate UINTN case to fix the 32-bit build.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
index 3955b6df84a0..19151b93d571 100644
--- a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
+++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
@@ -201,7 +201,7 @@ CheckCapsule (
     // Coalesce the capsule into unused memory. CreateState() below will copy
     // it to a properly allocated buffer.
     //
-    *CapsuleBuffer = (VOID *)PcdGet64 (PcdSystemMemoryBase);
+    *CapsuleBuffer = (VOID *)(UINTN)PcdGet64 (PcdSystemMemoryBase);
     *CapsuleBufferLength = UefiMemoryBase - PcdGet64 (PcdSystemMemoryBase);
 
     PeiServicesSetBootMode (BOOT_ON_FLASH_UPDATE);
-- 
2.17.1

[PATCH edk2-platforms 6/8] Silicon/SynQuacer/Stage2Tables: fix 32-bit build

[Ard Biesheuvel]

The static stage2 page tables don't contain any code, but we are
relying on the linker to resolve the references to the next level
tables, so we can only use native word size quantities. So add a
CPP macro to emit the same quantity in different ways.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S
index af55f27bca47..28c7a6ac970f 100644
--- a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S
+++ b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S
@@ -32,6 +32,12 @@
 #define TT_S2_L3_PAGE               (0x1 << 1)
 #define TT_S2_VALID                 (0x1 << 0)
 
+#ifdef __aarch64__
+#define QWORD(x)    .quad (x)
+#else
+#define QWORD(x)    .long (x), 0
+#endif
+
   .altmacro
   .macro    for, start, count, do, arg2, arg3, arg4
   .if       \count == 1
@@ -69,7 +75,7 @@
   .section  ".rodata", "a", %progbits
   /* level 1 */
   s2_mem_entry  0      /* 0x0000_0000 - 0x3fff_ffff */
-  .quad   1f + TT_S2_TABLE /* 0x4000_0000 - 0x7fff_ffff */
+  QWORD   (1f + TT_S2_TABLE) /* 0x4000_0000 - 0x7fff_ffff */
   for       2, 246, s2_mem_entry  /* 0x8000_0000 - 0x3d_ffff_ffff */
   for     248,   8, s2_dev_entry  /* PCIe MMIO64 */
   for     256, 768, s2_mem_entry  /* 0x40_0000_0000 - 0xff_ffff_ffff */
@@ -77,12 +83,12 @@
   /* level 2 */
 1:for     0, 256, s2_mem_entry, 21, 0x40000000, 1
 
-  .quad   2f + TT_S2_TABLE /* 0x6000_0000 -> RC #0 bus 0 */
+  QWORD   (2f + TT_S2_TABLE) /* 0x6000_0000 -> RC #0 bus 0 */
   for     1, 15, s2_mem_entry, 21, 0x60000000
   for     0, 48, s2_mem_entry, 21, 0x62000000, 1
   for     0, 64, s2_dev_entry, 21, 0x68000000, 1 /* PCIe MMIO32 */
 
-  .quad   3f + TT_S2_TABLE /* 0x7000_0000 -> RC #1 bus 0 */
+  QWORD   (3f + TT_S2_TABLE) /* 0x7000_0000 -> RC #1 bus 0 */
   for     1, 15, s2_mem_entry, 21, 0x70000000
   for     0, 48, s2_mem_entry, 21, 0x72000000, 1
   for     0, 64, s2_dev_entry, 21, 0x78000000, 1 /* PCIe MMIO32 */
-- 
2.17.1

[PATCH edk2-platforms 7/8] Platform/Socionext/DeveloperBox: disable EbcDxe for ARM builds

[Ard Biesheuvel]

EBC and 32-bit ARM are fundamentally incompatible, so only enable
it on AArch64 builds.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 4 +++-
 Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 2 ++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
index e6922fa3880b..beacd02adcc6 100644
--- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
+++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
@@ -333,7 +333,6 @@ [Components.common]
   }
   MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
   MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
-  MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
   MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
   Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.inf
   MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf
@@ -462,3 +461,6 @@ [Components.common]
   }
 
   Platform/Socionext/DeveloperBox/OsInstallerMenuDxe/OsInstallerMenuDxe.inf
+
+[Components.AARCH64]
+  MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf
index f52bec60b928..bc9ed30fb0d2 100644
--- a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf
+++ b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf
@@ -157,7 +157,9 @@ [FV.FvMain]
   INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
   INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
   INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+!if $(ARCH) == AARCH64
   INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+!endif
   INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
   INF MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf
 
-- 
2.17.1

[PATCH edk2-platforms 8/8] Platform/Socionext/DeveloperBox: add resolution for ArmSoftFloatLib

[Ard Biesheuvel]

OpensslLib depends on ArmSoftFloatLib when built for 32-bit ARM, so
add the required resolution for it.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
index beacd02adcc6..e09c58d2dffa 100644
--- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
+++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
@@ -40,6 +40,9 @@ [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
   GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
   GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
 
+[LibraryClasses.ARM]
+ ArmSoftFloatLib|ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.inf
+
 [LibraryClasses.common.SEC]
   PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
   BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
-- 
2.17.1

Re: [PATCH edk2-platforms 6/8] Silicon/SynQuacer/Stage2Tables: fix 32-bit build

[Ard Biesheuvel]

On Mon, 14 Jan 2019 at 18:02, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
>
> The static stage2 page tables don't contain any code, but we are
> relying on the linker to resolve the references to the next level
> tables, so we can only use native word size quantities. So add a
> CPP macro to emit the same quantity in different ways.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
>  Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S | 12 +++++++++---

The 'elf64-little' in the .inf is now wrong as well, but it seems I
can just remove that and objcopy will detect the input format.

>  1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S
> index af55f27bca47..28c7a6ac970f 100644
> --- a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S
> +++ b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S
> @@ -32,6 +32,12 @@
>  #define TT_S2_L3_PAGE               (0x1 << 1)
>  #define TT_S2_VALID                 (0x1 << 0)
>
> +#ifdef __aarch64__
> +#define QWORD(x)    .quad (x)
> +#else
> +#define QWORD(x)    .long (x), 0
> +#endif
> +
>    .altmacro
>    .macro    for, start, count, do, arg2, arg3, arg4
>    .if       \count == 1
> @@ -69,7 +75,7 @@
>    .section  ".rodata", "a", %progbits
>    /* level 1 */
>    s2_mem_entry  0      /* 0x0000_0000 - 0x3fff_ffff */
> -  .quad   1f + TT_S2_TABLE /* 0x4000_0000 - 0x7fff_ffff */
> +  QWORD   (1f + TT_S2_TABLE) /* 0x4000_0000 - 0x7fff_ffff */
>    for       2, 246, s2_mem_entry  /* 0x8000_0000 - 0x3d_ffff_ffff */
>    for     248,   8, s2_dev_entry  /* PCIe MMIO64 */
>    for     256, 768, s2_mem_entry  /* 0x40_0000_0000 - 0xff_ffff_ffff */
> @@ -77,12 +83,12 @@
>    /* level 2 */
>  1:for     0, 256, s2_mem_entry, 21, 0x40000000, 1
>
> -  .quad   2f + TT_S2_TABLE /* 0x6000_0000 -> RC #0 bus 0 */
> +  QWORD   (2f + TT_S2_TABLE) /* 0x6000_0000 -> RC #0 bus 0 */
>    for     1, 15, s2_mem_entry, 21, 0x60000000
>    for     0, 48, s2_mem_entry, 21, 0x62000000, 1
>    for     0, 64, s2_dev_entry, 21, 0x68000000, 1 /* PCIe MMIO32 */
>
> -  .quad   3f + TT_S2_TABLE /* 0x7000_0000 -> RC #1 bus 0 */
> +  QWORD   (3f + TT_S2_TABLE) /* 0x7000_0000 -> RC #1 bus 0 */
>    for     1, 15, s2_mem_entry, 21, 0x70000000
>    for     0, 48, s2_mem_entry, 21, 0x72000000, 1
>    for     0, 64, s2_dev_entry, 21, 0x78000000, 1 /* PCIe MMIO32 */
> --
> 2.17.1
>

Re: [PATCH edk2-platforms 0/8] Silicon/SynQuacer: add support for 32-bit mode

[Leif Lindholm]

On Mon, Jan 14, 2019 at 06:01:57PM +0100, Ard Biesheuvel wrote:
> This series fixes various issues that prevent the SynQuacer/DeveloperBox
> platform from being built or executed in 32-bit mode.
> 
> Ard Biesheuvel (8):
>   Silicon/SynQuacer/NetsecDxe: fix 32-bit build
>   Silicon/SynQuacer/OpteeRngDxe: fix 32-bit build
>   Silicon/SynQuacerPciHostBridgeLib: fix MMIO32-only configuration
>   Silicon/SynQuacerMemoryInitPeiLib: don't map memory above
>     MAX_ALLOC_ADDRESS
>   Silicon/SynQuacerMemoryInitPeiLib: fix 32-bit build
>   Silicon/SynQuacer/Stage2Tables: fix 32-bit build
>   Platform/Socionext/DeveloperBox: disable EbcDxe for ARM builds
>   Platform/Socionext/DeveloperBox: add resolution for ArmSoftFloatLib

For the series:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

>  Platform/Socionext/DeveloperBox/DeveloperBox.dsc     |  7 ++++++-
>  Platform/Socionext/DeveloperBox/DeveloperBox.fdf     |  2 ++
>  .../SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c      |  6 +++---
>  .../Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h    |  2 +-
>  .../SynQuacer/Drivers/OpteeRngDxe/OpteeRng.c         |  2 +-
>  .../SynQuacerMemoryInitPeiLib.c                      | 11 ++++++++---
>  .../SynQuacerPciHostBridgeLib.c                      |  8 ++++++++
>  .../Socionext/SynQuacer/Stage2Tables/Stage2Tables.S  | 12 +++++++++---
>  8 files changed, 38 insertions(+), 12 deletions(-)
> 
> -- 
> 2.17.1
> 

Re: [PATCH edk2-platforms 0/8] Silicon/SynQuacer: add support for 32-bit mode

[Ard Biesheuvel]

On Tue, 15 Jan 2019 at 13:08, Leif Lindholm <leif.lindholm@linaro.org> wrote:
>
> On Mon, Jan 14, 2019 at 06:01:57PM +0100, Ard Biesheuvel wrote:
> > This series fixes various issues that prevent the SynQuacer/DeveloperBox
> > platform from being built or executed in 32-bit mode.
> >
> > Ard Biesheuvel (8):
> >   Silicon/SynQuacer/NetsecDxe: fix 32-bit build
> >   Silicon/SynQuacer/OpteeRngDxe: fix 32-bit build
> >   Silicon/SynQuacerPciHostBridgeLib: fix MMIO32-only configuration
> >   Silicon/SynQuacerMemoryInitPeiLib: don't map memory above
> >     MAX_ALLOC_ADDRESS
> >   Silicon/SynQuacerMemoryInitPeiLib: fix 32-bit build
> >   Silicon/SynQuacer/Stage2Tables: fix 32-bit build
> >   Platform/Socionext/DeveloperBox: disable EbcDxe for ARM builds
> >   Platform/Socionext/DeveloperBox: add resolution for ArmSoftFloatLib
>
> For the series:
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
>

Thanks

Pushed as ca70cbbcc000..e48031fd75e6

> >  Platform/Socionext/DeveloperBox/DeveloperBox.dsc     |  7 ++++++-
> >  Platform/Socionext/DeveloperBox/DeveloperBox.fdf     |  2 ++
> >  .../SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c      |  6 +++---
> >  .../Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h    |  2 +-
> >  .../SynQuacer/Drivers/OpteeRngDxe/OpteeRng.c         |  2 +-
> >  .../SynQuacerMemoryInitPeiLib.c                      | 11 ++++++++---
> >  .../SynQuacerPciHostBridgeLib.c                      |  8 ++++++++
> >  .../Socionext/SynQuacer/Stage2Tables/Stage2Tables.S  | 12 +++++++++---
> >  8 files changed, 38 insertions(+), 12 deletions(-)
> >
> > --
> > 2.17.1
> >

Re: [PATCH edk2-platforms 6/8] Silicon/SynQuacer/Stage2Tables: fix 32-bit build

[Leif Lindholm]

On Mon, Jan 14, 2019 at 06:52:07PM +0100, Ard Biesheuvel wrote:
> On Mon, 14 Jan 2019 at 18:02, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
> >
> > The static stage2 page tables don't contain any code, but we are
> > relying on the linker to resolve the references to the next level
> > tables, so we can only use native word size quantities. So add a
> > CPP macro to emit the same quantity in different ways.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> > ---
> >  Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S | 12 +++++++++---
> 
> The 'elf64-little' in the .inf is now wrong as well, but it seems I
> can just remove that and objcopy will detect the input format.

Hmm. Actually, no. When cross-compiling:

$ objcopy -O binary -j .rodata
/work/git/tianocore/Build/DeveloperBox/DEBUG_GCC5/AARCH64/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables/OUTPUT/Stage2Tables.elf
/work/git/tianocore/Build/DeveloperBox/DEBUG_GCC5/AARCH64/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables/OUTPUT/Stage2Tables.bin
objcopy: Unable to recognise the format of the input file
`/work/git/tianocore/Build/DeveloperBox/DEBUG_GCC5/AARCH64/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables/OUTPUT/Stage2Tables.elf'

If I put -I elf64-little back, the command succeeds.

If I explicitly call the cross-toolchain objcopy, the command succeeds
without that addition.

When building natively, this works fine without the flag.

Why do we even end up running the build machine native objcopy here?

/
    Leif

> >  1 file changed, 9 insertions(+), 3 deletions(-)
> >
> > diff --git a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S
> > index af55f27bca47..28c7a6ac970f 100644
> > --- a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S
> > +++ b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S
> > @@ -32,6 +32,12 @@
> >  #define TT_S2_L3_PAGE               (0x1 << 1)
> >  #define TT_S2_VALID                 (0x1 << 0)
> >
> > +#ifdef __aarch64__
> > +#define QWORD(x)    .quad (x)
> > +#else
> > +#define QWORD(x)    .long (x), 0
> > +#endif
> > +
> >    .altmacro
> >    .macro    for, start, count, do, arg2, arg3, arg4
> >    .if       \count == 1
> > @@ -69,7 +75,7 @@
> >    .section  ".rodata", "a", %progbits
> >    /* level 1 */
> >    s2_mem_entry  0      /* 0x0000_0000 - 0x3fff_ffff */
> > -  .quad   1f + TT_S2_TABLE /* 0x4000_0000 - 0x7fff_ffff */
> > +  QWORD   (1f + TT_S2_TABLE) /* 0x4000_0000 - 0x7fff_ffff */
> >    for       2, 246, s2_mem_entry  /* 0x8000_0000 - 0x3d_ffff_ffff */
> >    for     248,   8, s2_dev_entry  /* PCIe MMIO64 */
> >    for     256, 768, s2_mem_entry  /* 0x40_0000_0000 - 0xff_ffff_ffff */
> > @@ -77,12 +83,12 @@
> >    /* level 2 */
> >  1:for     0, 256, s2_mem_entry, 21, 0x40000000, 1
> >
> > -  .quad   2f + TT_S2_TABLE /* 0x6000_0000 -> RC #0 bus 0 */
> > +  QWORD   (2f + TT_S2_TABLE) /* 0x6000_0000 -> RC #0 bus 0 */
> >    for     1, 15, s2_mem_entry, 21, 0x60000000
> >    for     0, 48, s2_mem_entry, 21, 0x62000000, 1
> >    for     0, 64, s2_dev_entry, 21, 0x68000000, 1 /* PCIe MMIO32 */
> >
> > -  .quad   3f + TT_S2_TABLE /* 0x7000_0000 -> RC #1 bus 0 */
> > +  QWORD   (3f + TT_S2_TABLE) /* 0x7000_0000 -> RC #1 bus 0 */
> >    for     1, 15, s2_mem_entry, 21, 0x70000000
> >    for     0, 48, s2_mem_entry, 21, 0x72000000, 1
> >    for     0, 64, s2_dev_entry, 21, 0x78000000, 1 /* PCIe MMIO32 */
> > --
> > 2.17.1
> >