From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
To: edk2-devel@lists.01.org
Subject: [PATCH edk2-platforms 3/8] Silicon/SynQuacerPciHostBridgeLib: fix MMIO32-only configuration
Date: Mon, 14 Jan 2019 18:02:00 +0100 [thread overview]
Message-ID: <20190114170205.9748-4-ard.biesheuvel@linaro.org> (raw)
In-Reply-To: <20190114170205.9748-1-ard.biesheuvel@linaro.org>
When running on 32-bit ARM, we cannot decode the MMIO64 region, and
so we don't set the EFI_PCI_HOST_BRIDGE_MEM64_DECODE flag in this
case. However, with that flag cleared, it is no longer permitted to
include a definition for the placement of the MMIO64 region either,
so remove those as well if MDE_CPU_ARM is set (which is the same
condition under which EFI_PCI_HOST_BRIDGE_MEM64_DECODE is cleared)
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c
index 7c096f0801dd..117cf6cfd81b 100644
--- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c
+++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c
@@ -109,8 +109,12 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = {
{ SYNQUACER_PCI_SEG0_MMIO32_MIN,
SYNQUACER_PCI_SEG0_MMIO32_MAX,
MAX_UINT64 - SYNQUACER_PCI_SEG0_MMIO32_XLATE + 1 }, // Mem
+#ifndef MDE_CPU_ARM
{ SYNQUACER_PCI_SEG0_MMIO64_MIN,
SYNQUACER_PCI_SEG0_MMIO64_MAX }, // MemAbove4G
+#else
+ { MAX_UINT64, 0x0 }, // MemAbove4G
+#endif
{ MAX_UINT64, 0x0 }, // PMem
{ MAX_UINT64, 0x0 }, // PMemAbove4G
(EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
@@ -130,8 +134,12 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = {
{ SYNQUACER_PCI_SEG1_MMIO32_MIN,
SYNQUACER_PCI_SEG1_MMIO32_MAX,
MAX_UINT64 - SYNQUACER_PCI_SEG1_MMIO32_XLATE + 1 }, // Mem
+#ifndef MDE_CPU_ARM
{ SYNQUACER_PCI_SEG1_MMIO64_MIN,
SYNQUACER_PCI_SEG1_MMIO64_MAX }, // MemAbove4G
+#else
+ { MAX_UINT64, 0x0 }, // MemAbove4G
+#endif
{ MAX_UINT64, 0x0 }, // PMem
{ MAX_UINT64, 0x0 }, // PMemAbove4G
(EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1]
--
2.17.1
next prev parent reply other threads:[~2019-01-14 17:02 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-14 17:01 [PATCH edk2-platforms 0/8] Silicon/SynQuacer: add support for 32-bit mode Ard Biesheuvel
2019-01-14 17:01 ` [PATCH edk2-platforms 1/8] Silicon/SynQuacer/NetsecDxe: fix 32-bit build Ard Biesheuvel
2019-01-14 17:01 ` [PATCH edk2-platforms 2/8] Silicon/SynQuacer/OpteeRngDxe: " Ard Biesheuvel
2019-01-14 17:02 ` Ard Biesheuvel [this message]
2019-01-14 17:02 ` [PATCH edk2-platforms 4/8] Silicon/SynQuacerMemoryInitPeiLib: don't map memory above MAX_ALLOC_ADDRESS Ard Biesheuvel
2019-01-14 17:02 ` [PATCH edk2-platforms 5/8] Silicon/SynQuacerMemoryInitPeiLib: fix 32-bit build Ard Biesheuvel
2019-01-14 17:02 ` [PATCH edk2-platforms 6/8] Silicon/SynQuacer/Stage2Tables: " Ard Biesheuvel
2019-01-14 17:52 ` Ard Biesheuvel
2019-02-11 16:45 ` Leif Lindholm
2019-01-14 17:02 ` [PATCH edk2-platforms 7/8] Platform/Socionext/DeveloperBox: disable EbcDxe for ARM builds Ard Biesheuvel
2019-01-14 17:02 ` [PATCH edk2-platforms 8/8] Platform/Socionext/DeveloperBox: add resolution for ArmSoftFloatLib Ard Biesheuvel
2019-01-15 12:08 ` [PATCH edk2-platforms 0/8] Silicon/SynQuacer: add support for 32-bit mode Leif Lindholm
2019-01-16 20:51 ` Ard Biesheuvel
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