From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::441; helo=mail-wr1-x441.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B1611211B5A34 for ; Mon, 14 Jan 2019 09:02:13 -0800 (PST) Received: by mail-wr1-x441.google.com with SMTP id t27so23745020wra.6 for ; Mon, 14 Jan 2019 09:02:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=m00ekdIu5hEbjbOrJ1OkviusdoFKBw0MjXgOowFPnwo=; b=bVo3PczlXKVKu9sMkeQ1BgcI36XEKGrsnc1lycS1bsv2BZN4oqFbB+UMQOmgMIJ1pG VaCom32J0w2xKXSJAKvQBCYZkvDa8aENkuC0veR/gf0ifYMFklC4UYcsiHFljBYvApUm USlkpBU6UpLRXBSoboRsOsr3HxZdCMXOt3KGs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=m00ekdIu5hEbjbOrJ1OkviusdoFKBw0MjXgOowFPnwo=; b=q949MEhS932KO0H/G9mgH/MU7TKwHsGrhuwsLAKzTFw2Xc35xJZi+QfPpTX0WWTh2a bmsq0+shlDe/EVqDWl77Zc73d7bwPKJIz9ctdO6W2A5JARHOTo2z/iqoG3NKF7DHi5Hh GWMAPHeT4Ciz4LdNxqrPH/y4guy1NW2MH/CKIyvMfmLCkRN1SlQ/gzZKb0z9xWIM1PCy HJ40H2P4q92ZdYb1wT1lH+pPyAuX3jUe5veZTrnz01mZw07fkQ7OVZxwXOmUuyDCBgEb KCHv0Wn1qWCLtazMoF9o/r+twBuVnlCT9X3cVy7Gq6VONWP14FXJsNAsRde+IFanEXL7 XPCw== X-Gm-Message-State: AJcUukd/L7xuxiv/7opzWt0MLaKlhkx1rvTP0yc89OorWSjxUOakPVct DGRpherm6BIo47PvkVR0JGL+idT4vhddlA== X-Google-Smtp-Source: ALg8bN7d8shY8EqGzMUHbiIpClD2WJiSX51RGfBJCTX8zyMW5D+JSjM+FZepdAe5gdj+KQVXJLEVtQ== X-Received: by 2002:a5d:4046:: with SMTP id w6mr26256461wrp.92.1547485331904; Mon, 14 Jan 2019 09:02:11 -0800 (PST) Received: from dogfood.home ([2a01:cb1d:112:6f00:2ced:5cd0:34f4:7bab]) by smtp.gmail.com with ESMTPSA id h184sm17224319wmf.0.2019.01.14.09.02.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 14 Jan 2019 09:02:11 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Mon, 14 Jan 2019 18:02:00 +0100 Message-Id: <20190114170205.9748-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114170205.9748-1-ard.biesheuvel@linaro.org> References: <20190114170205.9748-1-ard.biesheuvel@linaro.org> Subject: [PATCH edk2-platforms 3/8] Silicon/SynQuacerPciHostBridgeLib: fix MMIO32-only configuration X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 14 Jan 2019 17:02:14 -0000 When running on 32-bit ARM, we cannot decode the MMIO64 region, and so we don't set the EFI_PCI_HOST_BRIDGE_MEM64_DECODE flag in this case. However, with that flag cleared, it is no longer permitted to include a definition for the placement of the MMIO64 region either, so remove those as well if MDE_CPU_ARM is set (which is the same condition under which EFI_PCI_HOST_BRIDGE_MEM64_DECODE is cleared) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c index 7c096f0801dd..117cf6cfd81b 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c @@ -109,8 +109,12 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = { { SYNQUACER_PCI_SEG0_MMIO32_MIN, SYNQUACER_PCI_SEG0_MMIO32_MAX, MAX_UINT64 - SYNQUACER_PCI_SEG0_MMIO32_XLATE + 1 }, // Mem +#ifndef MDE_CPU_ARM { SYNQUACER_PCI_SEG0_MMIO64_MIN, SYNQUACER_PCI_SEG0_MMIO64_MAX }, // MemAbove4G +#else + { MAX_UINT64, 0x0 }, // MemAbove4G +#endif { MAX_UINT64, 0x0 }, // PMem { MAX_UINT64, 0x0 }, // PMemAbove4G (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0] @@ -130,8 +134,12 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = { { SYNQUACER_PCI_SEG1_MMIO32_MIN, SYNQUACER_PCI_SEG1_MMIO32_MAX, MAX_UINT64 - SYNQUACER_PCI_SEG1_MMIO32_XLATE + 1 }, // Mem +#ifndef MDE_CPU_ARM { SYNQUACER_PCI_SEG1_MMIO64_MIN, SYNQUACER_PCI_SEG1_MMIO64_MAX }, // MemAbove4G +#else + { MAX_UINT64, 0x0 }, // MemAbove4G +#endif { MAX_UINT64, 0x0 }, // PMem { MAX_UINT64, 0x0 }, // PMemAbove4G (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1] -- 2.17.1