From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::443; helo=mail-wr1-x443.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 944D4211B7374 for ; Mon, 14 Jan 2019 09:02:17 -0800 (PST) Received: by mail-wr1-x443.google.com with SMTP id 96so23772611wrb.2 for ; Mon, 14 Jan 2019 09:02:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nzmx2pfWtP9mJ1hDXsn8VHtXLJrZZWVh8ZVeglPLbfc=; b=isQ8AsAZLOg9OpN0jLwUwz7wibu8F4g81TTnAIr4Ps7ylQcHotiY424Vhh1l6pwbBT BbnaxxpppZ6uVw/XF8ST81jnAb7O6jcFRvPW60uKrKTh9djtb1awgRFN5zM+nfr4ad69 FGnydEr9no4JrJes/Nr5gXnByi5RBgkvDSlmk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nzmx2pfWtP9mJ1hDXsn8VHtXLJrZZWVh8ZVeglPLbfc=; b=A9jmj2LNp6zS6CRVNva/OR3Z+gt2diBHDwXAveISnucZGu9PgDsnL6LdKLnp+xsVVc XRb66cH7vceqDTSTpmq6+2YHjG2aioYCpgN73clVKkOwSZGxb0C74a2FgPyAq7X+i2HU 77jC7OemWrnhMIl5lKJ/WLSE3tTud/b5TMrz5kqXudLsp8GKL4b5suX4nuLVaxQ1MIWD FFB9DaVzCXBC0tGyw7ESWqT83oRVXpDHRjGEuytUm9ZbFjb1uzbCn8sbSTVfWaGRqXA4 FXp/EM4M58VLu/jmeG33LOUbdLeofByib9+stRwWhJv9gxreN4hz0Vj710AJiK3Q7EvK +9zw== X-Gm-Message-State: AJcUukfzex6QsJvcQ6+FIYmd5rCpHqmMVq8lRgGLqN09s0FytEIFjICH zQ8bKockqUMNE89WMIDquFOa3eh6HLQ0jg== X-Google-Smtp-Source: ALg8bN5zt0alkh11Nj3L55P03ay6yamYr90IQXfW6CqrUuygJx3IFLgNupYTXrCMbGiKMJtxPxraUQ== X-Received: by 2002:adf:8544:: with SMTP id 62mr26365318wrh.1.1547485335799; Mon, 14 Jan 2019 09:02:15 -0800 (PST) Received: from dogfood.home ([2a01:cb1d:112:6f00:2ced:5cd0:34f4:7bab]) by smtp.gmail.com with ESMTPSA id h184sm17224319wmf.0.2019.01.14.09.02.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 14 Jan 2019 09:02:14 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Mon, 14 Jan 2019 18:02:03 +0100 Message-Id: <20190114170205.9748-7-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114170205.9748-1-ard.biesheuvel@linaro.org> References: <20190114170205.9748-1-ard.biesheuvel@linaro.org> Subject: [PATCH edk2-platforms 6/8] Silicon/SynQuacer/Stage2Tables: fix 32-bit build X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 14 Jan 2019 17:02:18 -0000 The static stage2 page tables don't contain any code, but we are relying on the linker to resolve the references to the next level tables, so we can only use native word size quantities. So add a CPP macro to emit the same quantity in different ways. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S index af55f27bca47..28c7a6ac970f 100644 --- a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S +++ b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S @@ -32,6 +32,12 @@ #define TT_S2_L3_PAGE (0x1 << 1) #define TT_S2_VALID (0x1 << 0) +#ifdef __aarch64__ +#define QWORD(x) .quad (x) +#else +#define QWORD(x) .long (x), 0 +#endif + .altmacro .macro for, start, count, do, arg2, arg3, arg4 .if \count == 1 @@ -69,7 +75,7 @@ .section ".rodata", "a", %progbits /* level 1 */ s2_mem_entry 0 /* 0x0000_0000 - 0x3fff_ffff */ - .quad 1f + TT_S2_TABLE /* 0x4000_0000 - 0x7fff_ffff */ + QWORD (1f + TT_S2_TABLE) /* 0x4000_0000 - 0x7fff_ffff */ for 2, 246, s2_mem_entry /* 0x8000_0000 - 0x3d_ffff_ffff */ for 248, 8, s2_dev_entry /* PCIe MMIO64 */ for 256, 768, s2_mem_entry /* 0x40_0000_0000 - 0xff_ffff_ffff */ @@ -77,12 +83,12 @@ /* level 2 */ 1:for 0, 256, s2_mem_entry, 21, 0x40000000, 1 - .quad 2f + TT_S2_TABLE /* 0x6000_0000 -> RC #0 bus 0 */ + QWORD (2f + TT_S2_TABLE) /* 0x6000_0000 -> RC #0 bus 0 */ for 1, 15, s2_mem_entry, 21, 0x60000000 for 0, 48, s2_mem_entry, 21, 0x62000000, 1 for 0, 64, s2_dev_entry, 21, 0x68000000, 1 /* PCIe MMIO32 */ - .quad 3f + TT_S2_TABLE /* 0x7000_0000 -> RC #1 bus 0 */ + QWORD (3f + TT_S2_TABLE) /* 0x7000_0000 -> RC #1 bus 0 */ for 1, 15, s2_mem_entry, 21, 0x70000000 for 0, 48, s2_mem_entry, 21, 0x72000000, 1 for 0, 64, s2_dev_entry, 21, 0x78000000, 1 /* PCIe MMIO32 */ -- 2.17.1