From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.120; helo=mga04.intel.com; envelope-from=chasel.chiu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 397CD211B5A57 for ; Mon, 14 Jan 2019 20:07:37 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Jan 2019 20:07:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,480,1539673200"; d="scan'208";a="114730656" Received: from cchiu4-mobl1.gar.corp.intel.com ([10.5.240.45]) by fmsmga007.fm.intel.com with ESMTP; 14 Jan 2019 20:07:35 -0800 From: "Chasel, Chiu" To: edk2-devel@lists.01.org Cc: Nate DeSimone , Star Zeng , Chasel Chiu Date: Tue, 15 Jan 2019 12:07:27 +0800 Message-Id: <20190115040727.2452-1-chasel.chiu@intel.com> X-Mailer: git-send-email 2.13.3.windows.1 Subject: [PATCH] MinPlatformPkg: Support TCO base locked by FSP X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 15 Jan 2019 04:07:37 -0000 REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1457 Per security recommendation TCO Base should be initialized and locked by FSP and MinPlatform should support both TCO Base locked and not locked scenarios. Cc: Nate DeSimone Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu --- Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c index 68b0b5dd4b..e135ef1f3e 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c @@ -1,7 +1,7 @@ /** @file PCH cycle deocding configuration and query library. -Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at @@ -352,17 +352,18 @@ PchTcoBaseSet ( } // // Verify TCO base is not locked. + // If it is locked already, skip following steps. // if ((MmioRead8 (SmbusBase + R_PCH_SMBUS_TCOCTL) & B_PCH_SMBUS_TCOCTL_TCO_BASE_LOCK) != 0) { - ASSERT (FALSE); - return EFI_DEVICE_ERROR; + return EFI_SUCCESS; } // // Disable TCO in SMBUS Device first before changing base address. + // Byte access to not touch the TCO_BASE_LOCK bit // - MmioAnd16 ( - SmbusBase + R_PCH_SMBUS_TCOCTL, - (UINT16) ~B_PCH_SMBUS_TCOCTL_TCO_BASE_EN + MmioAnd8 ( + SmbusBase + R_PCH_SMBUS_TCOCTL + 1, + (UINT8) ~(B_PCH_SMBUS_TCOCTL_TCO_BASE_EN >> 8) ); // // Program TCO in SMBUS Device @@ -373,11 +374,11 @@ PchTcoBaseSet ( Address ); // - // Enable TCO in SMBUS Device + // Enable TCO in SMBUS Device and lock TCO BASE // MmioOr16 ( SmbusBase + R_PCH_SMBUS_TCOCTL, - B_PCH_SMBUS_TCOCTL_TCO_BASE_EN + B_PCH_SMBUS_TCOCTL_TCO_BASE_EN | B_PCH_SMBUS_TCOCTL_TCO_BASE_LOCK ); // // Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] to [SMBUS PCI offset 50h[15:5], 1]. -- 2.13.3.windows.1