From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::341; helo=mail-wm1-x341.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B03FC211B6C22 for ; Thu, 17 Jan 2019 03:52:47 -0800 (PST) Received: by mail-wm1-x341.google.com with SMTP id n190so765945wmd.0 for ; Thu, 17 Jan 2019 03:52:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=mvQjk5LQMC/XmFGTco1GS58A47dLu6wNF5L7pwBX+zs=; b=Y5rx1m9VLkLhbqDvbK+Weeek5YE6CbBWiqOLcW7dYq/CxnIQdHAxbshOc/PQYuZKH7 imSVkCL66r+lI11bb1/jRNSJUivRAC2evu8Isg3K4KSJ/bTTvRcW3zlIvBC8eZwdsp4o kYsGmSyC8f4DUJoO2p4fcmO8MF4ef7Jm0MJsw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=mvQjk5LQMC/XmFGTco1GS58A47dLu6wNF5L7pwBX+zs=; b=QGN4JGx0RpyxxS72vkgOAmk5ohL02Fx2OUcqHc9kSKTFgzAwbRJxjkssZITWuCz1j2 3opCUI/tJNV8fTSBWwdx/8sMJqHy4EY6OZurQI8M4TSWPg9Fgoqp7BMJOYYVJ6CkGHBc 8iaY8jRbkubDoP5levMVMQFX7a1WZLXi8Qn0h/1eo/VziWZfeEg/NuwQptAGIhOevn4T LW39rWyKE5CopAuvFXmii3TLgJJF8BXQjZmuzGdzYUPHWQNEGQ+cmFSeAdD9c4w2C3kq SVNwOlhR/2oaTFsbD7w2AWl2qWvEaa/EoeCZG2eBsjYxsk2aAWZ03nZT78IesG58udFA oxhw== X-Gm-Message-State: AJcUukfpEmrabJQJdR/hTzZ11gjEJjbUkn3CvTsjcNaKa3pvx3Q7XYP3 G8B/29xMti2TW7MnMOtdrYEKlQ== X-Google-Smtp-Source: ALg8bN6khckV4BkF7i7AafsowpM0QIqZ/fwHE3bOOe1GXMDlKs8mdk74/w641VpKzwcM1av9CQODng== X-Received: by 2002:a1c:a00f:: with SMTP id j15mr10884678wme.84.1547725966059; Thu, 17 Jan 2019 03:52:46 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id w125sm43912560wmb.45.2019.01.17.03.52.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 17 Jan 2019 03:52:45 -0800 (PST) Date: Thu, 17 Jan 2019 11:52:43 +0000 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Message-ID: <20190117115243.vcx25svctqxu4upj@bivouac.eciton.net> References: <1547723715-4562-1-git-send-email-mw@semihalf.com> <1547723715-4562-9-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1547723715-4562-9-git-send-email-mw@semihalf.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [platforms: PATCH v3 08/12] Marvell/Drivers: MvGpioDxe: Introduce platform GPIO driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Jan 2019 11:52:48 -0000 X-List-Received-Date: Thu, 17 Jan 2019 11:52:48 -0000 X-List-Received-Date: Thu, 17 Jan 2019 11:52:48 -0000 X-List-Received-Date: Thu, 17 Jan 2019 11:52:48 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Jan 17, 2019 at 12:15:11PM +0100, Marcin Wojtas wrote: > Marvell Armada 7k/8k SoCs comprise integrated GPIO controllers, > one in AP806 and two in each south bridge hardware blocks. > > This patch introduces support for them. The new driver implements > a generic EMBEDDED_GPIO protocol. > > In order to ease description of used GPIO pins and controllers > of the Armada 7k8k platforms, add a common enum type. > > Based on original work of Jing Hua . > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm > --- > Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf | 44 +++ > Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h | 49 +++ > Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.c | 353 ++++++++++++++++++++ > 3 files changed, 446 insertions(+) > create mode 100644 Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf > create mode 100644 Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h > create mode 100644 Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.c > > diff --git a/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf b/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf > new file mode 100644 > index 0000000..5ff9130 > --- /dev/null > +++ b/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf > @@ -0,0 +1,44 @@ > +## @file > +# > +# Copyright (c) 2017, Marvell International Ltd. All rights reserved.
> +# > +# This program and the accompanying materials are licensed and made available > +# under the terms and conditions of the BSD License which accompanies this > +# distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR > +# IMPLIED. > +# > + > +[Defines] > + INF_VERSION = 0x0001001A > + BASE_NAME = MvGpioDxe > + FILE_GUID = 706eb761-b3b5-4f41-8558-5fd9217c0079 > + MODULE_TYPE = DXE_DRIVER > + VERSION_STRING = 1.0 > + ENTRY_POINT = MvGpioEntryPoint > + > +[Sources] > + MvGpioDxe.c > + MvGpioDxe.h > + > +[Packages] > + EmbeddedPkg/EmbeddedPkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + Silicon/Marvell/Marvell.dec > + > +[LibraryClasses] > + ArmadaSoCDescLib > + DebugLib > + MemoryAllocationLib > + UefiDriverEntryPoint > + UefiLib > + > +[Protocols] > + gEmbeddedGpioProtocolGuid > + gMarvellBoardDescProtocolGuid > + > +[Depex] > + TRUE > diff --git a/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h b/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h > new file mode 100644 > index 0000000..6e56ec1 > --- /dev/null > +++ b/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h > @@ -0,0 +1,49 @@ > +/** > +* > +* Copyright (c) 2018, Marvell International Ltd. All rights reserved. > +* > +* This program and the accompanying materials are licensed and made available > +* under the terms and conditions of the BSD License which accompanies this > +* distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > +#ifndef __MV_GPIO_H__ > +#define __MV_GPIO_H__ > + > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#include > + > +#define MV_GPIO_SIGNATURE SIGNATURE_64 ('M', 'V','_','G', 'P', 'I','O',' ') > + > +// Marvell MV_GPIO Controller Registers > +#define MV_GPIO_DATA_OUT_REG (0x0) > +#define MV_GPIO_OUT_EN_REG (0x4) > +#define MV_GPIO_BLINK_EN_REG (0x8) > +#define MV_GPIO_DATA_IN_POL_REG (0xc) > +#define MV_GPIO_DATA_IN_REG (0x10) > + > +typedef struct { > + EMBEDDED_GPIO GpioProtocol; > + GPIO_CONTROLLER *SoCGpio; > + UINTN GpioDeviceCount; > + UINTN Signature; > + EFI_HANDLE Handle; > +} MV_GPIO; > + > +#endif // __MV_GPIO_H__ > diff --git a/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.c b/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.c > new file mode 100644 > index 0000000..1d37ecc > --- /dev/null > +++ b/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.c > @@ -0,0 +1,353 @@ > +/** > +* > +* Copyright (c) 2018, Marvell International Ltd. All rights reserved. > +* > +* This program and the accompanying materials are licensed and made available > +* under the terms and conditions of the BSD License which accompanies this > +* distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +#include "MvGpioDxe.h" > + > +STATIC MV_GPIO *mGpioInstance; > + > +STATIC MV_GPIO_DEVICE_PATH mDevicePathTemplate = { > + { > + { > + HARDWARE_DEVICE_PATH, > + HW_VENDOR_DP, > + { > + (UINT8) (sizeof (VENDOR_DEVICE_PATH) + > + sizeof (MV_GPIO_DRIVER_TYPE)), > + (UINT8) ((sizeof (VENDOR_DEVICE_PATH) + > + sizeof (MV_GPIO_DRIVER_TYPE)) >> 8), > + }, > + }, > + EFI_CALLER_ID_GUID > + }, > + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, > + { > + END_DEVICE_PATH_TYPE, > + END_ENTIRE_DEVICE_PATH_SUBTYPE, > + { > + sizeof(EFI_DEVICE_PATH_PROTOCOL), > + 0 > + } > + } > +}; > + > +#if !defined(MDEPKG_NDEBUG) > +/** > + > +Routine Description: > + > + Verifies if controller index / GPIO pin values > + are within proper boundaries. > + > +Arguments: > + > + ControllerIndex - index of controller > + GpioPin - which pin to read > + > +Returns: > + > + EFI_SUCCESS - GPIO pin / controller index are proper > + EFI_INVALID_PARAMETER - GPIO pin / controller index is out of range > +**/ > +STATIC > +EFI_STATUS > +MvGpioValidate ( > + IN UINTN ControllerIndex, > + IN UINTN GpioPin > + ) > +{ > + if (ControllerIndex >= mGpioInstance->GpioDeviceCount) { > + DEBUG ((DEBUG_ERROR, > + "%a: Invalid GPIO ControllerIndex: %d\n", > + __FUNCTION__, > + ControllerIndex)); > + return EFI_INVALID_PARAMETER; > + } > + > + if (GpioPin >= mGpioInstance->SoCGpio[ControllerIndex].InternalGpioCount) { > + DEBUG ((DEBUG_ERROR, > + "%a: GPIO pin #%d not available in Controller#%d\n", > + __FUNCTION__, > + GpioPin, > + ControllerIndex)); > + return EFI_INVALID_PARAMETER; > + } > + > + return EFI_SUCCESS; > +} > +#endif > + > +/** > + > +Routine Description: > + > + Gets the mode (function) of a GPIO pin > + > +Arguments: > + > + This - pointer to protocol > + Gpio - which pin > + Mode - pointer to output mode value > + > +Returns: > + > + EFI_SUCCESS - mode value retrieved > + EFI_INVALID_PARAMETER - Mode is a null pointer or Gpio pin is out of range > + > +**/ > +STATIC > +EFI_STATUS > +MvGpioGetMode ( > + IN EMBEDDED_GPIO *This, > + IN EMBEDDED_GPIO_PIN Gpio, > + OUT EMBEDDED_GPIO_MODE *Mode > + ) > +{ > + UINTN ControllerIndex; > + UINTN BaseAddress; > + UINTN GpioPin; > + > + GpioPin = GPIO_PIN (Gpio); > + ControllerIndex = GPIO_PORT (Gpio); > + > + ASSERT_EFI_ERROR (MvGpioValidate (ControllerIndex, GpioPin)); > + > + BaseAddress = mGpioInstance->SoCGpio[ControllerIndex].RegisterBase; > + > + if (MmioRead32 (BaseAddress + MV_GPIO_OUT_EN_REG) & (1 << GpioPin)) { > + *Mode = GPIO_MODE_INPUT; > + } else { > + if (MmioRead32 (BaseAddress + MV_GPIO_DATA_IN_REG) & (1 << GpioPin)) { > + *Mode = GPIO_MODE_OUTPUT_1; > + } else { > + *Mode = GPIO_MODE_OUTPUT_0; > + } > + } > + > + return EFI_SUCCESS; > +} > + > +/** > + > +Routine Description: > + > + Gets the state of a GPIO pin > + > +Arguments: > + > + This - pointer to protocol > + Gpio - which pin to read > + Value - state of the pin > + > +Returns: > + > + EFI_SUCCESS - GPIO state returned in Value > + EFI_INVALID_PARAMETER - Value is NULL pointer or Gpio pin is out of range > +**/ > +STATIC > +EFI_STATUS > +MvGpioGet ( > + IN EMBEDDED_GPIO *This, > + IN EMBEDDED_GPIO_PIN Gpio, > + OUT UINTN *Value > + ) > +{ > + UINTN ControllerIndex; > + UINTN BaseAddress; > + UINTN GpioPin; > + > + GpioPin = GPIO_PIN (Gpio); > + ControllerIndex = GPIO_PORT (Gpio); > + > + ASSERT_EFI_ERROR (MvGpioValidate (ControllerIndex, GpioPin)); > + > + BaseAddress = mGpioInstance->SoCGpio[ControllerIndex].RegisterBase; > + > + if (MmioRead32 (BaseAddress + MV_GPIO_DATA_IN_REG) & (1 << GpioPin)) { > + *Value = 1; > + } else { > + *Value = 0; > + } > + > + return EFI_SUCCESS; > +} > + > +/** > + > +Routine Description: > + > + Sets the state of a GPIO pin > + > +Arguments: > + > + This - pointer to protocol > + Gpio - which pin to modify > + Mode - mode to set > + > +Returns: > + > + EFI_SUCCESS - GPIO set as requested > + EFI_UNSUPPORTED - Mode is not supported > + EFI_INVALID_PARAMETER - Gpio pin is out of range > +**/ > +STATIC > +EFI_STATUS > +MvGpioSet ( > + IN EMBEDDED_GPIO *This, > + IN EMBEDDED_GPIO_PIN Gpio, > + IN EMBEDDED_GPIO_MODE Mode > + ) > +{ > + UINTN ControllerIndex; > + UINTN BaseAddress; > + UINTN GpioPin; > + > + GpioPin = GPIO_PIN (Gpio); > + ControllerIndex = GPIO_PORT (Gpio); > + > + ASSERT_EFI_ERROR (MvGpioValidate (ControllerIndex, GpioPin)); > + > + BaseAddress = mGpioInstance->SoCGpio[ControllerIndex].RegisterBase; > + > + switch (Mode) { > + case GPIO_MODE_OUTPUT_0: > + MmioAnd32 (BaseAddress + MV_GPIO_DATA_OUT_REG, ~(1 << GpioPin)); > + MmioAnd32 (BaseAddress + MV_GPIO_OUT_EN_REG, ~(1 << GpioPin)); > + break; > + > + case GPIO_MODE_OUTPUT_1: > + MmioOr32 (BaseAddress + MV_GPIO_DATA_OUT_REG, (1 << GpioPin)); > + MmioAnd32 (BaseAddress + MV_GPIO_OUT_EN_REG, ~(1 << GpioPin)); > + break; > + > + case GPIO_MODE_INPUT: > + MmioOr32 (BaseAddress + MV_GPIO_OUT_EN_REG, (1 << GpioPin)); > + break; > + > + default: > + return EFI_UNSUPPORTED; > + } > + > + return EFI_SUCCESS; > +} > + > +/** > + > +Routine Description: > + > + Sets the pull-up / pull-down resistor of a GPIO pin > + > +Arguments: > + > + This - pointer to protocol > + Gpio - which pin > + Direction - pull-up, pull-down, or none > + > +Returns: > + > + EFI_UNSUPPORTED - Can not perform the requested operation > + > +**/ > +EFI_STATUS > +EFIAPI > +MvGpioSetPull ( > + IN EMBEDDED_GPIO *This, > + IN EMBEDDED_GPIO_PIN Gpio, > + IN EMBEDDED_GPIO_PULL Direction > + ) > +{ > + return EFI_UNSUPPORTED; > +} > + > +STATIC > +VOID > +MvGpioInitProtocol ( > + IN EMBEDDED_GPIO *GpioProtocol > + ) > +{ > + GpioProtocol->Get = MvGpioGet; > + GpioProtocol->Set = MvGpioSet; > + GpioProtocol->GetMode = MvGpioGetMode; > + GpioProtocol->SetPull = MvGpioSetPull; > +} > + > +EFI_STATUS > +EFIAPI > +MvGpioEntryPoint ( > + IN EFI_HANDLE ImageHandle, > + IN EFI_SYSTEM_TABLE *SystemTable > + ) > +{ > + MARVELL_BOARD_DESC_PROTOCOL *MvBoardProtocol; > + MV_BOARD_GPIO_DESCRIPTION *GpioDescription; > + MV_GPIO_DEVICE_PATH *GpioDevicePath; > + EFI_STATUS Status; > + > + GpioDevicePath = AllocateCopyPool (sizeof (MV_GPIO_DEVICE_PATH), > + &mDevicePathTemplate); > + if (GpioDevicePath == NULL) { > + return EFI_OUT_OF_RESOURCES; > + } > + > + mGpioInstance = AllocateZeroPool (sizeof (MV_GPIO)); > + if (mGpioInstance == NULL) { > + Status = EFI_OUT_OF_RESOURCES; > + goto ErrGpioInstanceAlloc; > + } > + > + /* Obtain list of available controllers */ > + Status = gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, > + NULL, > + (VOID **)&MvBoardProtocol); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, > + "%a: Cannot locate BoardDesc protocol\n", > + __FUNCTION__)); > + goto ErrLocateBoardDesc; > + } > + > + Status = MvBoardProtocol->GpioDescriptionGet (MvBoardProtocol, > + &GpioDescription); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, > + "%a: Cannot get GPIO board desc from BoardDesc protocol\n", > + __FUNCTION__)); > + goto ErrLocateBoardDesc; > + } > + > + mGpioInstance->Signature = MV_GPIO_SIGNATURE; > + mGpioInstance->GpioDeviceCount = GpioDescription->GpioDeviceCount; > + mGpioInstance->SoCGpio = GpioDescription->SoCGpio; > + > + MvGpioInitProtocol (&mGpioInstance->GpioProtocol); > + > + Status = gBS->InstallMultipleProtocolInterfaces (&(mGpioInstance->Handle), > + &gEmbeddedGpioProtocolGuid, > + &(mGpioInstance->GpioProtocol), > + &gEfiDevicePathProtocolGuid, > + (EFI_DEVICE_PATH_PROTOCOL *)GpioDevicePath, > + NULL); > + if (EFI_ERROR (Status)) { > + goto ErrLocateBoardDesc; > + } > + > + return EFI_SUCCESS; > + > +ErrLocateBoardDesc: > + gBS->FreePool (mGpioInstance); > + > +ErrGpioInstanceAlloc: > + gBS->FreePool (GpioDevicePath); > + > + return Status; > +} > -- > 2.7.4 >