From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::343; helo=mail-wm1-x343.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8D2EC211B509C for ; Mon, 21 Jan 2019 03:26:15 -0800 (PST) Received: by mail-wm1-x343.google.com with SMTP id t200so10444708wmt.0 for ; Mon, 21 Jan 2019 03:26:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=SKPnzv3z/lCm6gDnVOstx/hdwewiF7DD7q1I5jiny+s=; b=eqV/PIdc/Pa58bulkDDsIHHy6NJ/O30TFIrGpDeImYZNLOX3QEj1nG0xESaTum/STm 1qpy6zwPkrc7oZOE38Sconj4P8EpAFjytvKb4V2T1/WhGsic3vsr2Dq+6aBL8T05JtjD aJqlJCzHYSS3siYnlEQXCn2RsYvnwIubfcB1A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=SKPnzv3z/lCm6gDnVOstx/hdwewiF7DD7q1I5jiny+s=; b=BCKXaP6da1iPVSXPB52Uo9SkH30r691+e5ExqStQttCOWbYmBtuDHft1pMzhdPETGq LZEpUtvPTKYlH0vuzxlx4ck6jqb4VtsE0R6D3t4WnfopLpSRe9i39jngCpnBGQbYA6uY LN/4dQyZlqvbq0OB2TxeBOl1PbebESh35oGQqft7U4trn1PFrRDvFJRBol2jtTchfVWR j2ecLPNumI5cEYebDwpoL2uIJoHdR+TyooUPNeylKsXs0Fq+DL0GHCBjSybu4QU9g4mP K/W/Ea7mr9BeiBjxxAP5/DciW2GWZJD12yQ1f2a8SsMI+zcUXwHbOCU+j3K/OjoG6jI6 uu7w== X-Gm-Message-State: AJcUukekP/hjw07uNmpxi9YlONlIsramOHBX/5KN4GGYdKCDDKnKeJ20 hlVH80g/EHR79wsE8ndjDcnQkw== X-Google-Smtp-Source: ALg8bN41EIhwcdtcEMWwWxBGdjDgrSjGmBFZYghxOv2TkkzTdNWxgXGONxkcymFIAjuDSW/iSWinvQ== X-Received: by 2002:a7b:c2a9:: with SMTP id c9mr22889403wmk.44.1548069972110; Mon, 21 Jan 2019 03:26:12 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id n15sm75485353wrt.21.2019.01.21.03.26.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 Jan 2019 03:26:11 -0800 (PST) Date: Mon, 21 Jan 2019 11:26:09 +0000 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Message-ID: <20190121112609.ahwajugww4426avx@bivouac.eciton.net> References: <1548067931-18618-1-git-send-email-mw@semihalf.com> <1548067931-18618-2-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1548067931-18618-2-git-send-email-mw@semihalf.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [platforms: PATCH 1/3] Marvell: Armada7k8k: Shift PEI stack base X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 21 Jan 2019 11:26:16 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Jan 21, 2019 at 11:52:09AM +0100, Marcin Wojtas wrote: > Recent changes in the ARM-TF configure its runtime serices region > as protected, hence the hitherto PEI stack base address (0x41F0000) > violated it. > > In order to fix this, extend the region which is non-accessible > by the OS to cover both the ARM-TF (0x4000000 - 0x4200000) and OPTEE > (0x4400000 - 0x5400000) within a single area and set the PEI stack What is the single area? > base address between both images. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas > --- > Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc > index eafcd6e..c8c597f 100644 > --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc > +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc > @@ -376,12 +376,12 @@ > > gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|36 > > - gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x41F0000 > + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x43F0000 > gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000 > > # Secure region reservation > gMarvellTokenSpaceGuid.PcdSecureRegionBase|0x4000000 > - gMarvellTokenSpaceGuid.PcdSecureRegionSize|0x0200000 > + gMarvellTokenSpaceGuid.PcdSecureRegionSize|0x1400000 > > # TRNG > gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000 > -- > 2.7.4 >