From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::443; helo=mail-wr1-x443.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3720A211B76BE for ; Mon, 21 Jan 2019 03:51:45 -0800 (PST) Received: by mail-wr1-x443.google.com with SMTP id v13so22991428wrw.5 for ; Mon, 21 Jan 2019 03:51:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=Hz9V0CSs+3lrQaBJpqE+ZWBWuctA+ZaK1HJmR7H4EYo=; b=OvhF2LyNf5BJpGQHJFUZYU6GrKgcgaMIDuDXeoD4/tDSlTPZW4wdXAK39GjAQiZIZZ mjbsuQOtqPv6F43pLPe5HRcsqm/BTZ6D/B8kt7KI6ncPe6yOmXqz348jWIgcZamv5iqF 39+rRGulg8XKi6bYUVi78xxZv6SRtRGGR4TXQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=Hz9V0CSs+3lrQaBJpqE+ZWBWuctA+ZaK1HJmR7H4EYo=; b=qeXyGKvqp0GYFc8ceTAQ5octqBbGLgJVWi8Dcdu0cH69Lr584PVktiAiFTaMx4Ntly ++PicRrXKK0QicUpLTmWt9T6VlgO+zWSItBpEm0sE5HfHMgntp0w+BCKtF6xYKWM2yAL zB4YQeLWpGFeVxe2YTGRlT8QIYKDf7dp+DabIzZUD3hu0tgcEJuvpqbW9NnugtbNnvVq dGjghNNhRBCnkdLTn797pQa320oBb6DftDEn4QN+azyuYmunX2zyBsUiXvS5/mP3AzHS YM7mzL8s1e8UWsw5ehqwOoH1ZVQl610pN2O4SCgpHFGrSbwFVpXf9I+O9Xj3SY/O9MtG p7CQ== X-Gm-Message-State: AJcUukc75WvLl6HvN8G4oLCkej9czyrv0Hi64VswHrrcZbE0HsO0odQA WD8DzwOYb2D66JPRzbPJVvAlZw== X-Google-Smtp-Source: ALg8bN7cycjzPDEvT4+nhHTU2PZ2zitVMCvkHS+CtjKtILNT0eKMyAmzgfpBDlufkOlxpetPYp81wQ== X-Received: by 2002:adf:c888:: with SMTP id k8mr29179240wrh.6.1548071503228; Mon, 21 Jan 2019 03:51:43 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id x10sm116306074wrn.29.2019.01.21.03.51.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 Jan 2019 03:51:42 -0800 (PST) Date: Mon, 21 Jan 2019 11:51:40 +0000 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Message-ID: <20190121115140.qqva7s3ldq62k35w@bivouac.eciton.net> References: <1548067931-18618-1-git-send-email-mw@semihalf.com> <1548067931-18618-4-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1548067931-18618-4-git-send-email-mw@semihalf.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [platforms: PATCH 3/3] Marvell/Armada7k8k: Read DRAM settings from ARM-TF X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 21 Jan 2019 11:51:45 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Jan 21, 2019 at 11:52:11AM +0100, Marcin Wojtas wrote: > From: Grzegorz Jaszczyk > > The memory controller registers are marked as secure in the latest > ARM-TF for Armada SoCs. It is available however get the DRAM > information via SiP services in the EL3, so use it instead > of accessing the registers directly. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas > --- > Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf | 3 ++ > Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h | 27 ++-------- > Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c | 55 +++++--------------- > 3 files changed, 21 insertions(+), 64 deletions(-) > > diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf > index e888566..0c7f320 100644 > --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf > +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf > @@ -41,12 +41,15 @@ > [Packages] > ArmPkg/ArmPkg.dec > ArmPlatformPkg/ArmPlatformPkg.dec > + EmbeddedPkg/EmbeddedPkg.dec > MdeModulePkg/MdeModulePkg.dec > MdePkg/MdePkg.dec > Silicon/Marvell/Marvell.dec > > [LibraryClasses] > + ArmadaSoCDescLib > ArmLib > + ArmSmcLib > DebugLib > MemoryAllocationLib > MppLib > diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h > index cc30e4a..8a46df6 100644 > --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h > +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h > @@ -47,27 +47,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > #define DRAM_REMAP_TARGET \ > (MmioRead32 (CCU_MC_RTBR_REG) << TARGET_BASE_OFFS) > > -#define DRAM_CH0_MMAP_LOW_REG(cs) (0xf0020200 + (cs) * 0x8) > -#define DRAM_CS_VALID_ENABLED_MASK 0x1 > -#define DRAM_AREA_LENGTH_OFFS 16 > -#define DRAM_AREA_LENGTH_MASK (0x1f << DRAM_AREA_LENGTH_OFFS) > -#define DRAM_START_ADDRESS_L_OFFS 23 > -#define DRAM_START_ADDRESS_L_MASK (0x1ff << DRAM_START_ADDRESS_L_OFFS) > -#define DRAM_CH0_MMAP_HIGH_REG(cs) (0xf0020204 + (cs) * 0x8) > -#define DRAM_START_ADDR_HTOL_OFFS 32 > +/* Armada7k8k North Bridge index */ > +#define ARMADA7K8K_AP806_INDEX 0 > > -#define DRAM_MAX_CS_NUM 8 > - > -#define DRAM_CS_ENABLED(Cs) \ > - (MmioRead32 (DRAM_CH0_MMAP_LOW_REG (Cs)) & DRAM_CS_VALID_ENABLED_MASK) > -#define GET_DRAM_REGION_BASE(Cs) \ > - ((UINT64)MmioRead32 (DRAM_CH0_MMAP_HIGH_REG ((Cs))) << \ > - DRAM_START_ADDR_HTOL_OFFS) | \ > - (MmioRead32 (DRAM_CH0_MMAP_LOW_REG (Cs)) & DRAM_START_ADDRESS_L_MASK); > -#define GET_DRAM_REGION_SIZE_CODE(Cs) \ > - (MmioRead32 (DRAM_CH0_MMAP_LOW_REG ((Cs))) & \ > - DRAM_AREA_LENGTH_MASK) >> DRAM_AREA_LENGTH_OFFS > -#define DRAM_REGION_SIZE_EVEN(C) (((C) >= 7) && ((C) <= 26)) > -#define GET_DRAM_REGION_SIZE_EVEN(C) ((UINT64)1 << ((C) + 16)) > -#define DRAM_REGION_SIZE_ODD(C) ((C) <= 4) > -#define GET_DRAM_REGION_SIZE_ODD(C) ((UINT64)0x18000000 << (C)) > +/* Firmware related definition used for SMC calls */ > +#define MV_SIP_DRAM_SIZE 0x82000010 Hmm... This would end us up with having Marvell SMC calls spread across multiple files. Could you insert an intermediate patch which breaks out the ones from Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h into a separate (MarvellSmc.h?) include file? If you could further add _SMC_ID to the #defines (like in edk2 ArmPkg/Include/IndustryStandard/ArmStdSmc.h), that would make me very happy. (I'd be happy for you to drop _SIP, or keep it either side of the addition, as per your preference - we don't seem to have precedent here yet.) Regards, Leif > diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c > index 2a4f5ad..62e8467 100644 > --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c > +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c > @@ -33,11 +33,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > *******************************************************************************/ > > #include > +#include > #include > +#include > #include > #include > #include > #include > +#include > > #include "Armada7k8kLibMem.h" > > @@ -57,49 +60,19 @@ GetDramSize ( > IN OUT UINT64 *MemSize > ) > { > - UINT64 BaseAddr; > - UINT8 RegionCode; > - UINT8 Cs; > - > - *MemSize = 0; > - > - for (Cs = 0; Cs < DRAM_MAX_CS_NUM; Cs++) { > - > - /* Exit loop on first disabled DRAM CS */ > - if (!DRAM_CS_ENABLED (Cs)) { > - break; > - } > - > - /* > - * Sanity check for base address of next DRAM block. > - * Only continuous space will be used. > - */ > - BaseAddr = GET_DRAM_REGION_BASE (Cs); > - if (BaseAddr != *MemSize) { > - DEBUG ((DEBUG_ERROR, > - "%a: DRAM blocks are not contiguous, limit size to 0x%llx\n", > - __FUNCTION__, > - *MemSize)); > - return EFI_SUCCESS; > - } > - > - /* Decode area length for current CS from register value */ > - RegionCode = GET_DRAM_REGION_SIZE_CODE (Cs); > - > - if (DRAM_REGION_SIZE_EVEN (RegionCode)) { > - *MemSize += GET_DRAM_REGION_SIZE_EVEN (RegionCode); > - } else if (DRAM_REGION_SIZE_ODD (RegionCode)) { > - *MemSize += GET_DRAM_REGION_SIZE_ODD (RegionCode); > - } else { > - DEBUG ((DEBUG_ERROR, > - "%a: Invalid memory region code (0x%x) for CS#%d\n", > - __FUNCTION__, > - RegionCode, > - Cs)); > - return EFI_INVALID_PARAMETER; > - } > + ARM_SMC_ARGS SmcRegs = {0}; > + EFI_STATUS Status; > + > + SmcRegs.Arg0 = MV_SIP_DRAM_SIZE; > + Status = ArmadaSoCAp8xxBaseGet (&SmcRegs.Arg1, ARMADA7K8K_AP806_INDEX); > + if (EFI_ERROR (Status)) { > + return Status; > } > > + ArmCallSmc (&SmcRegs); > + > + *MemSize = SmcRegs.Arg0; > + > return EFI_SUCCESS; > } > > -- > 2.7.4 >