From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::341; helo=mail-wm1-x341.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 60D8B2194D387 for ; Tue, 22 Jan 2019 09:39:20 -0800 (PST) Received: by mail-wm1-x341.google.com with SMTP id y139so14934589wmc.5 for ; Tue, 22 Jan 2019 09:39:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=8XZ+ClDPFnh7HA9+6A6k5Kz9enSyRqpgLKDP83rgGvs=; b=HUlPuRWQTtQLPOCAngFFQXcIrLYn0WDJm69GRdNQ33mgDpfvP8e5GEFil+wVoE8yZ3 9LkItlHd7+dtfU88zGDe48nuGS7izPKvPaUU9iM5QKR3/6JUdh/BXXbNVNeju17QVuM5 8UgdkyShQK8GWO2UYTJ5NegE9NoJ6/RiQquSk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=8XZ+ClDPFnh7HA9+6A6k5Kz9enSyRqpgLKDP83rgGvs=; b=Q79GdNdmcKbilSHBKdCw0VC955MD58K6C0mjbajPBT4BILDitMMxQkufFvP/WIdhVx t6XXZlbKKzm8H9rLFQPzP4M9Qig7AKbNk5rBBU//0EH8WorI8+3L4SSuEPVJNSwOSlfa dg/YHSyybGsD/bsYXOXAYBtpgreJa61xWP10owA8vGqZmwF1QU88EoX405PNbUhJzL1p nwQXRc/u2Z2CsE+TNiyLqVet6gXBiXir3GLx5iwrSHUofdiqY3sSOTFmG6SEvjHE39w5 WG/LSSFLWKvfe499uvkmyTP6UNyBO4/r0wb58bouXmgtK47BTJd6MMwpICl5cDTp3rey /H0w== X-Gm-Message-State: AJcUukez1Id1DyYyk+sbAckx/uQwFK1UOkKwYHPuymCgi3S9JPAL/VZZ WfUOj9ZvtA4eH3IQ+b+NtqlGIw== X-Google-Smtp-Source: ALg8bN5h0YCvF/60q1WNhs4ehJK9cx8ryUtbmg8vB88P9y2uxWE/PxurpnmUpirshdhtcqkUd/8rqA== X-Received: by 2002:a1c:8148:: with SMTP id c69mr4626264wmd.126.1548178758716; Tue, 22 Jan 2019 09:39:18 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id 127sm100800318wmm.45.2019.01.22.09.39.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 Jan 2019 09:39:17 -0800 (PST) Date: Tue, 22 Jan 2019 17:39:16 +0000 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Message-ID: <20190122173916.p27cy5d7q6z4et7g@bivouac.eciton.net> References: <1548120742-11928-1-git-send-email-mw@semihalf.com> <1548120742-11928-5-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1548120742-11928-5-git-send-email-mw@semihalf.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [platforms: PATCH v2 4/4] Marvell/Armada7k8k: Read DRAM settings from ARM-TF X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Jan 2019 17:39:20 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Jan 22, 2019 at 02:32:22AM +0100, Marcin Wojtas wrote: > From: Grzegorz Jaszczyk > > The memory controller registers are marked as secure in the latest > ARM-TF for Armada SoCs. It is available however get the DRAM > information via SiP services in the EL3, so use it instead > of accessing the registers directly. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas (With the required include path change based on feedback on other patch:) Reviewed-by: Leif Lindholm > --- > Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf | 3 + > Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h | 25 -------- > Silicon/Marvell/Include/Library/MvSmc.h | 1 + > Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c | 60 ++++++-------------- > 4 files changed, 22 insertions(+), 67 deletions(-) > > diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf > index e888566..0c7f320 100644 > --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf > +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf > @@ -41,12 +41,15 @@ > [Packages] > ArmPkg/ArmPkg.dec > ArmPlatformPkg/ArmPlatformPkg.dec > + EmbeddedPkg/EmbeddedPkg.dec > MdeModulePkg/MdeModulePkg.dec > MdePkg/MdePkg.dec > Silicon/Marvell/Marvell.dec > > [LibraryClasses] > + ArmadaSoCDescLib > ArmLib > + ArmSmcLib > DebugLib > MemoryAllocationLib > MppLib > diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h > index cc30e4a..8101cf3 100644 > --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h > +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h > @@ -46,28 +46,3 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > (MmioRead32 (CCU_MC_RCR_REG) & REMAP_SIZE_MASK) + SIZE_1MB > #define DRAM_REMAP_TARGET \ > (MmioRead32 (CCU_MC_RTBR_REG) << TARGET_BASE_OFFS) > - > -#define DRAM_CH0_MMAP_LOW_REG(cs) (0xf0020200 + (cs) * 0x8) > -#define DRAM_CS_VALID_ENABLED_MASK 0x1 > -#define DRAM_AREA_LENGTH_OFFS 16 > -#define DRAM_AREA_LENGTH_MASK (0x1f << DRAM_AREA_LENGTH_OFFS) > -#define DRAM_START_ADDRESS_L_OFFS 23 > -#define DRAM_START_ADDRESS_L_MASK (0x1ff << DRAM_START_ADDRESS_L_OFFS) > -#define DRAM_CH0_MMAP_HIGH_REG(cs) (0xf0020204 + (cs) * 0x8) > -#define DRAM_START_ADDR_HTOL_OFFS 32 > - > -#define DRAM_MAX_CS_NUM 8 > - > -#define DRAM_CS_ENABLED(Cs) \ > - (MmioRead32 (DRAM_CH0_MMAP_LOW_REG (Cs)) & DRAM_CS_VALID_ENABLED_MASK) > -#define GET_DRAM_REGION_BASE(Cs) \ > - ((UINT64)MmioRead32 (DRAM_CH0_MMAP_HIGH_REG ((Cs))) << \ > - DRAM_START_ADDR_HTOL_OFFS) | \ > - (MmioRead32 (DRAM_CH0_MMAP_LOW_REG (Cs)) & DRAM_START_ADDRESS_L_MASK); > -#define GET_DRAM_REGION_SIZE_CODE(Cs) \ > - (MmioRead32 (DRAM_CH0_MMAP_LOW_REG ((Cs))) & \ > - DRAM_AREA_LENGTH_MASK) >> DRAM_AREA_LENGTH_OFFS > -#define DRAM_REGION_SIZE_EVEN(C) (((C) >= 7) && ((C) <= 26)) > -#define GET_DRAM_REGION_SIZE_EVEN(C) ((UINT64)1 << ((C) + 16)) > -#define DRAM_REGION_SIZE_ODD(C) ((C) <= 4) > -#define GET_DRAM_REGION_SIZE_ODD(C) ((UINT64)0x18000000 << (C)) > diff --git a/Silicon/Marvell/Include/Library/MvSmc.h b/Silicon/Marvell/Include/Library/MvSmc.h > index 2d1542a..0c90f11 100644 > --- a/Silicon/Marvell/Include/Library/MvSmc.h > +++ b/Silicon/Marvell/Include/Library/MvSmc.h > @@ -19,5 +19,6 @@ > #define MV_SMC_ID_COMPHY_POWER_ON 0x82000001 > #define MV_SMC_ID_COMPHY_POWER_OFF 0x82000002 > #define MV_SMC_ID_COMPHY_PLL_LOCK 0x82000003 > +#define MV_SMC_ID_DRAM_SIZE 0x82000010 > > #endif //__MV_SMC_H__ > diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c > index 2a4f5ad..8517deb 100644 > --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c > +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c > @@ -32,12 +32,18 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > > *******************************************************************************/ > > -#include > +#include > + > +#include > + > +#include > #include > +#include > #include > #include > #include > #include > +#include > > #include "Armada7k8kLibMem.h" > > @@ -57,49 +63,19 @@ GetDramSize ( > IN OUT UINT64 *MemSize > ) > { > - UINT64 BaseAddr; > - UINT8 RegionCode; > - UINT8 Cs; > - > - *MemSize = 0; > - > - for (Cs = 0; Cs < DRAM_MAX_CS_NUM; Cs++) { > - > - /* Exit loop on first disabled DRAM CS */ > - if (!DRAM_CS_ENABLED (Cs)) { > - break; > - } > - > - /* > - * Sanity check for base address of next DRAM block. > - * Only continuous space will be used. > - */ > - BaseAddr = GET_DRAM_REGION_BASE (Cs); > - if (BaseAddr != *MemSize) { > - DEBUG ((DEBUG_ERROR, > - "%a: DRAM blocks are not contiguous, limit size to 0x%llx\n", > - __FUNCTION__, > - *MemSize)); > - return EFI_SUCCESS; > - } > - > - /* Decode area length for current CS from register value */ > - RegionCode = GET_DRAM_REGION_SIZE_CODE (Cs); > - > - if (DRAM_REGION_SIZE_EVEN (RegionCode)) { > - *MemSize += GET_DRAM_REGION_SIZE_EVEN (RegionCode); > - } else if (DRAM_REGION_SIZE_ODD (RegionCode)) { > - *MemSize += GET_DRAM_REGION_SIZE_ODD (RegionCode); > - } else { > - DEBUG ((DEBUG_ERROR, > - "%a: Invalid memory region code (0x%x) for CS#%d\n", > - __FUNCTION__, > - RegionCode, > - Cs)); > - return EFI_INVALID_PARAMETER; > - } > + ARM_SMC_ARGS SmcRegs = {0}; > + EFI_STATUS Status; > + > + SmcRegs.Arg0 = MV_SMC_ID_DRAM_SIZE; > + Status = ArmadaSoCAp8xxBaseGet (&SmcRegs.Arg1, 0); > + if (EFI_ERROR (Status)) { > + return Status; > } > > + ArmCallSmc (&SmcRegs); > + > + *MemSize = SmcRegs.Arg0; > + > return EFI_SUCCESS; > } > > -- > 2.7.4 >