From: Leif Lindholm <leif.lindholm@linaro.org>
To: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: "edk2-devel@lists.01.org" <edk2-devel@lists.01.org>
Subject: Re: [PATCH 2/5] ArmPkg/ArmMmuLib AARCH64: get rid of needless TLB invalidation
Date: Wed, 23 Jan 2019 16:20:26 +0000 [thread overview]
Message-ID: <20190123162026.i3id7zabzmo52sin@bivouac.eciton.net> (raw)
In-Reply-To: <CAKv+Gu_t9-dWCH5NWgtgxPy3YJrQFM6eypZsARdwwFhUT64Qkw@mail.gmail.com>
On Wed, Jan 23, 2019 at 05:16:57PM +0100, Ard Biesheuvel wrote:
> On Wed, 23 Jan 2019 at 17:13, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> >
> > On Wed, Jan 23, 2019 at 04:55:28PM +0100, Ard Biesheuvel wrote:
> > > On Wed, 23 Jan 2019 at 16:46, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> > > >
> > > > On Mon, Jan 07, 2019 at 08:15:01AM +0100, Ard Biesheuvel wrote:
> > > > > Currently, we always invalidate the TLBs entirely after making
> > > > > any modification to the page tables. Now that we have introduced
> > > > > strict memory permissions in quite a number of places, such
> > > > > modifications occur much more often, and it is better for performance
> > > > > to flush only those TLB entries that are actually affected by
> > > > > the changes.
> > > > >
> > > > > Contributed-under: TianoCore Contribution Agreement 1.1
> > > > > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> > > > > ---
> > > > > ArmPkg/Include/Library/ArmMmuLib.h | 3 ++-
> > > > > ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 6 +++---
> > > > > ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 16 +++++++---------
> > > > > ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S | 14 ++++++++------
> > > > > 4 files changed, 20 insertions(+), 19 deletions(-)
> > > > >
> > > > > diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
> > > > > index d66df3e17a02..e1fabfcbea14 100644
> > > > > --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
> > > > > +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
> > > > > @@ -129,13 +129,14 @@ STATIC
> > > > > VOID
> > > > > ReplaceLiveEntry (
> > > > > IN UINT64 *Entry,
> > > > > - IN UINT64 Value
> > > > > + IN UINT64 Value,
> > > > > + IN UINT64 Address
> > > > > )
> > > > > {
> > > > > if (!ArmMmuEnabled ()) {
> > > > > *Entry = Value;
> > > > > } else {
> > > > > - ArmReplaceLiveTranslationEntry (Entry, Value);
> > > > > + ArmReplaceLiveTranslationEntry (Entry, Value, Address);
> > > > > }
> > > > > }
> > > > >
> > > > > @@ -296,7 +297,8 @@ GetBlockEntryListFromAddress (
> > > > >
> > > > > // Fill the BlockEntry with the new TranslationTable
> > > > > ReplaceLiveEntry (BlockEntry,
> > > > > - ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TableAttributes | TT_TYPE_TABLE_ENTRY);
> > > > > + (UINTN)TranslationTable | TableAttributes | TT_TYPE_TABLE_ENTRY,
> > > > > + RegionStart);
> > > >
> > >
> > > /me pages in the data ...
> > >
> > > > OK, this whole patch took a few times around the loop before I think I
> > > > caught on what was happening.
> > > >
> > > > I think I'm down to the only things confusing me being:
> > > > - The name "Address" to refer to something that is always the start
> > > > address of a 4KB-aligned translation region.
> > > > Is this because the function will be usable in other contexts in
> > > > later patches?
> > >
> > > I could change it to VirtualAddress if you prefer.
> > > It is only passed
> > > for TLB maintenance which is only needed at page granularity, and the
> > > low bits are shifted out anyway.
> >
> > Yeah, exactly. It would just be nice if the name reflected that. Not
> > sure VirtualAddress does. VirtualBase? PageBase?
> >
>
> Well, the argument passed in is called RegionStart, so let's just
> stick with that.
Sure. With that:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> > > > - Why drop the & TT_ADDRESS_MASK_DESCRIPTION_TABLE bit here?
> > > > Was it just always pointless and you decided to drop it while you
> > > > were at it?
> > >
> > > IIRC yes. It is a newly allocated page, so the masking does not do anything.
> >
> > Yeah, that's fair enough.
> > Just made me wonder if anything unobvious was going on :)
> >
> > /
> > Leif
next prev parent reply other threads:[~2019-01-23 16:20 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-07 7:14 [PATCH 0/5] memory/MMU hardening for AArch64 Ard Biesheuvel
2019-01-07 7:15 ` [PATCH 1/5] ArmPkg/ArmMmuLib AARCH64: fix out of bounds access Ard Biesheuvel
2019-01-14 12:00 ` Leif Lindholm
2019-01-14 18:48 ` Ard Biesheuvel
2019-01-07 7:15 ` [PATCH 2/5] ArmPkg/ArmMmuLib AARCH64: get rid of needless TLB invalidation Ard Biesheuvel
2019-01-23 15:46 ` Leif Lindholm
2019-01-23 15:55 ` Ard Biesheuvel
2019-01-23 16:12 ` Leif Lindholm
2019-01-23 16:16 ` Ard Biesheuvel
2019-01-23 16:20 ` Leif Lindholm [this message]
2019-01-28 12:29 ` Ard Biesheuvel
2019-01-28 18:01 ` Leif Lindholm
2019-01-29 10:32 ` Ard Biesheuvel
2019-01-07 7:15 ` [PATCH 3/5] ArmPkg/ArmMmuLib AARCH64: implement support for EFI_MEMORY_RP permissions Ard Biesheuvel
2019-01-14 14:29 ` Leif Lindholm
2019-01-14 14:59 ` Ard Biesheuvel
2019-01-14 15:06 ` Leif Lindholm
2019-01-07 7:15 ` [PATCH 4/5] ArmPkg/ArmMmuLib AARCH64: add support for read-only page tables Ard Biesheuvel
2019-01-07 7:15 ` [PATCH 5/5] ArmPkg/CpuDxe: switch to read-only page tables at EndOfDxe Ard Biesheuvel
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