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From: Michael Kubacki <michael.a.kubacki@intel.com>
To: edk2-devel@lists.01.org
Cc: Hao Wu <hao.a.wu@intel.com>, Liming Gao <liming.gao@intel.com>,
	Jiewen Yao <jiewen.yao@intel.com>,
	Michael D Kinney <michael.d.kinney@intel.com>
Subject: [edk2-platforms/devel-MinPlatform][PATCH v3 1/6] ClevoOpenBoardPkg: Add package and headers
Date: Fri, 25 Jan 2019 17:05:35 -0800	[thread overview]
Message-ID: <20190126010540.34444-2-michael.a.kubacki@intel.com> (raw)
In-Reply-To: <20190126010540.34444-1-michael.a.kubacki@intel.com>

Based on KabylakeOpenBoardPkg from the following branch:
https://github.com/tianocore/edk2-platforms/tree/devel-MinPlatform

Create the ClevoOpenBoardPkg to provide an initial board package
for Clevo boards. The ClevoOpenBoardPkg is intended to contain a
series of specific Clevo board instances such as the N1XXWU and
N1XXZU series. A given board instance serves as a board
implementation for use with the MinPlatformPkg.

* Common resources are shared at the top-level of ClevoOpenBoardPkg.
* Features are organized into the Features directory.
  * Features not mandatory to load the OS in the standard hardware
    configuration are considered advanced and only enabled when
    gMinPlatformPkgTokenSpaceGuid.PcdBootStage is greater than 5.

Cc: Hao Wu <hao.a.wu@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com>
---
 Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec  | 306 +++++++++++++++++++++
 .../Features/PciHotPlug/PciHotPlug.h               | 136 +++++++++
 .../Features/Tbt/Include/Acpi/TbtNvsAreaDef.h      |  68 +++++
 .../Features/Tbt/Include/Library/DxeTbtPolicyLib.h |  52 ++++
 .../Features/Tbt/Include/Library/PeiTbtPolicyLib.h |  47 ++++
 .../Features/Tbt/Include/Library/TbtCommonLib.h    | 247 +++++++++++++++++
 .../Features/Tbt/Include/Ppi/PeiTbtPolicy.h        |  35 +++
 .../Tbt/Include/Private/Library/PeiDTbtInitLib.h   | 114 ++++++++
 .../Include/Private/Library/PeiTbtCommonInitLib.h  |  47 ++++
 .../Features/Tbt/Include/Protocol/DxeTbtPolicy.h   | 116 ++++++++
 .../Features/Tbt/Include/Protocol/TbtNvsArea.h     |  48 ++++
 .../Features/Tbt/Include/TbtBoardInfo.h            |  28 ++
 .../Tbt/Include/TbtPolicyCommonDefinition.h        |  83 ++++++
 .../Library/DxeTbtPolicyLib/DxeTbtPolicyLibrary.h  |  28 ++
 .../Library/PeiTbtPolicyLib/PeiTbtPolicyLibrary.h  |  23 ++
 .../Features/Tbt/TbtInit/Smm/TbtSmiHandler.h       | 185 +++++++++++++
 .../Include/Acpi/GlobalNvsAreaDef.h                | 122 ++++++++
 .../Intel/ClevoOpenBoardPkg/Include/IoExpander.h   |  73 +++++
 .../Include/Library/GpioExpanderLib.h              | 128 +++++++++
 .../Include/Library/I2cAccessLib.h                 |  39 +++
 .../ClevoOpenBoardPkg/Include/PchHsioPtssTables.h  |  57 ++++
 .../Include/Protocol/GlobalNvsArea.h               |  53 ++++
 Platform/Intel/ClevoOpenBoardPkg/Include/SioRegs.h | 163 +++++++++++
 Platform/Intel/ClevoOpenBoardPkg/Contributions.txt | 218 +++++++++++++++
 Platform/Intel/ClevoOpenBoardPkg/License.txt       |  25 ++
 25 files changed, 2441 insertions(+)
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.h
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Acpi/TbtNvsAreaDef.h
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/DxeTbtPolicyLib.h
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/PeiTbtPolicyLib.h
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/TbtCommonLib.h
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Ppi/PeiTbtPolicy.h
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Private/Library/PeiDTbtInitLib.h
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Private/Library/PeiTbtCommonInitLib.h
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Protocol/DxeTbtPolicy.h
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Protocol/TbtNvsArea.h
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtBoardInfo.h
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtPolicyCommonDefinition.h
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLibrary.h
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLibrary.h
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHandler.h
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Include/IoExpander.h
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Include/Library/GpioExpanderLib.h
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Include/Library/I2cAccessLib.h
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Include/PchHsioPtssTables.h
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Include/Protocol/GlobalNvsArea.h
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Include/SioRegs.h
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Contributions.txt
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/License.txt

diff --git a/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec b/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec
new file mode 100644
index 0000000000..87bbfb2240
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec
@@ -0,0 +1,306 @@
+## @file
+# Clevo board declaration file.
+#
+# The DEC files are used by the utilities that parse DSC and
+# INF files to generate AutoGen.c and AutoGen.h files
+# for the build infrastructure.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+[Defines]
+DEC_SPECIFICATION = 0x00010017
+PACKAGE_NAME      = OpenBoardPkg
+PACKAGE_VERSION   = 0.1
+PACKAGE_GUID      = D04CCA80-5F71-478D-9A26-72BC751D0106
+
+[Includes]
+Include
+N1xxWU\Include
+Features\Tbt\Include
+
+[Guids]
+gBoardModuleTokenSpaceGuid            =  {0x72d1fff7, 0xa42a, 0x4219, {0xb9, 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4, 0x2a}}
+gTianoLogoGuid                        =  {0x7BB28B99, 0x61BB, 0x11D5, {0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}}
+gTbtInfoHobGuid                       =  {0x74a81eaa, 0x033c, 0x4783, {0xbe, 0x2b, 0x84, 0x85, 0x74, 0xa6, 0x97, 0xb7}}
+gPlatformModuleTokenSpaceGuid         =  {0x69d13bf0, 0xaf91, 0x4d96, {0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}}
+
+[Protocols]
+gTbtNvsAreaProtocolGuid               =  {0x4d6a54d1, 0xcd56, 0x47f3, {0x93, 0x6e, 0x7e, 0x51, 0xd9, 0x31, 0x15, 0x4f}}
+gDxeTbtPolicyProtocolGuid             =  {0x196bf9e3, 0x20d7, 0x4b7b, {0x89, 0xf9, 0x31, 0xc2, 0x72, 0x08, 0xc9, 0xb9}}
+
+[Ppis]
+gPeiTbtPolicyPpiGuid                  =  {0xd7e7e1e6, 0xcbec, 0x4f5f, {0xae, 0xd3, 0xfd, 0xc0, 0xa8, 0xb0, 0x7e, 0x25}}
+gPeiTbtPolicyBoardInitDonePpiGuid     =  {0x970f9c60, 0x8547, 0x49d7, { 0xa4, 0xb, 0x1e, 0xc4, 0xbc, 0x4e, 0xe8, 0x9b}}
+
+[LibraryClasses]
+
+[PcdsFixedAtBuild, PcdsPatchableInModule]
+
+[PcdsFixedAtBuild]
+
+gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|UINT16|0x10001004
+gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c03|UINT16|0x10001005
+
+gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort|0x4e|UINT16|0x90000018
+gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort|0x4f|UINT16|0x9000001F
+
+gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort|0x164E|UINT16|0x9000001C
+gBoardModuleTokenSpaceGuid.PcdSioBaseAddress|0x0680|UINT16|0x9000001D
+
+gBoardModuleTokenSpaceGuid.PcdLpcSioIndexDefaultPort|0x164E|UINT16|0x90000021
+gBoardModuleTokenSpaceGuid.PcdLpcSioDataDefaultPort|0x164F|UINT16|0x90000022
+
+## Tbt SW_SMI_DTBT_ENUMERATEgSetupVariableGuid
+gBoardModuleTokenSpaceGuid.PcdSwSmiDTbtEnumerate|0xF7|UINT8|0x000000110
+
+gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition|0x01|UINT8|0x90000015
+
+[PcdsDynamic]
+
+# Board GPIO Table
+gBoardModuleTokenSpaceGuid.PcdBoardGpioTable|0|UINT32|0x00000040
+gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize|0|UINT16|0x00000041
+gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2|0|UINT32|0x00000042
+gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2Size|0|UINT16|0x00000043
+gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem|0|UINT32|0x000000113
+gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize|0|UINT16|0x000000114
+
+# Board Expander GPIO Table
+gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable|0|UINT32|0x00000044
+gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize|0|UINT16|0x00000045
+gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2|0|UINT32|0x00000046
+gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2Size|0|UINT16|0x00000047
+
+# TouchPanel & SDHC CD GPIO Table
+gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel|0|UINT32|0x00000048
+
+# PCH-LP HSIO PTSS Table
+gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1|0|UINT32|0x0000004A
+gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2|0|UINT32|0x0000004B
+gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size|0|UINT16|0x0000004C
+gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size|0|UINT16|0x0000004D
+gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1|0|UINT32|0x0000004E
+gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2|0|UINT32|0x0000004F
+gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size|0|UINT16|0x00000050
+gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size|0|UINT16|0x00000051
+
+# PCH-H HSIO PTSS Table
+gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1|0|UINT32|0x00000052
+gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2|0|UINT32|0x00000053
+gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size|0|UINT16|0x00000054
+gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size|0|UINT16|0x00000055
+gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1|0|UINT32|0x00000056
+gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2|0|UINT32|0x00000057
+gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size|0|UINT16|0x00000058
+gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size|0|UINT16|0x00000059
+
+# HDA Verb Table
+gBoardModuleTokenSpaceGuid.PcdHdaVerbTable|0|UINT32|0x0000005A
+gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2|0|UINT32|0x0000005B
+gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable|0|UINT32|0x0000005C
+gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1|0|UINT32|0x0000005D
+gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2|0|UINT32|0x0000005E
+gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3|0|UINT32|0x0000005F
+gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable|0|UINT32|0x00000060
+
+# SA Misc Configuration
+gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd|0|UINT8|0x00000066
+gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment|0|UINT16|0x00000067
+gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit|0|UINT16|0x00000101
+
+# DRAM Configuration
+gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor|0|UINT32|0x00000068
+gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget|0|UINT32|0x00000069
+gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap|0|UINT32|0x0000006A
+gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize|0|UINT16|0x0000006B
+gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram|0|UINT32|0x0000006C
+gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize|0|UINT16|0x0000006D
+gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl|FALSE|BOOLEAN|0x0000006E
+gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved|FALSE|BOOLEAN|0x0000006F
+gBoardModuleTokenSpaceGuid.PcdMrcSpdData|0|UINT32|0x00000070
+gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize|0|UINT16|0x00000071
+
+# PEG RESET GPIO
+gBoardModuleTokenSpaceGuid.PcdPegGpioResetControl|FALSE|BOOLEAN|0x00000072
+gBoardModuleTokenSpaceGuid.PcdPegGpioResetSupoort|FALSE|BOOLEAN|0x00000073
+gBoardModuleTokenSpaceGuid.PcdPegResetGpioPad|0|UINT32|0x00000074
+gBoardModuleTokenSpaceGuid.PcdPegResetGpioActive|FALSE|BOOLEAN|0x00000075
+gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo|0|UINT32|0x00000079
+gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo|0|UINT8|0x0000007A
+gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo|0|UINT32|0x0000007B
+gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive|FALSE|BOOLEAN|0x0000007C
+gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo|0|UINT8|0x0000007D
+gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo|0|UINT32|0x0000007E
+gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive|FALSE|BOOLEAN|0x0000007F
+
+# SPD Address Table
+gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0|0|UINT8|0x00000099
+gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1|0|UINT8|0x0000009A
+gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2|0|UINT8|0x0000009B
+gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3|0|UINT8|0x0000009C
+
+# CA Vref Configuration
+gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig|0|UINT8|0x0000009D
+
+# Root Port Clock Info
+gBoardModuleTokenSpaceGuid.PcdRootPort0ClkInfo|0|UINT64|0x0000009E
+gBoardModuleTokenSpaceGuid.PcdRootPort1ClkInfo|0|UINT64|0x0000009F
+gBoardModuleTokenSpaceGuid.PcdRootPort2ClkInfo|0|UINT64|0x000000A0
+gBoardModuleTokenSpaceGuid.PcdRootPort3ClkInfo|0|UINT64|0x000000A1
+gBoardModuleTokenSpaceGuid.PcdRootPort4ClkInfo|0|UINT64|0x000000A2
+gBoardModuleTokenSpaceGuid.PcdRootPort5ClkInfo|0|UINT64|0x000000A3
+gBoardModuleTokenSpaceGuid.PcdRootPort6ClkInfo|0|UINT64|0x000000A4
+gBoardModuleTokenSpaceGuid.PcdRootPort7ClkInfo|0|UINT64|0x000000A5
+gBoardModuleTokenSpaceGuid.PcdRootPort8ClkInfo|0|UINT64|0x000000A6
+gBoardModuleTokenSpaceGuid.PcdRootPort9ClkInfo|0|UINT64|0x000000A7
+gBoardModuleTokenSpaceGuid.PcdRootPort10ClkInfo|0|UINT64|0x000000A8
+gBoardModuleTokenSpaceGuid.PcdRootPort11ClkInfo|0|UINT64|0x000000A9
+gBoardModuleTokenSpaceGuid.PcdRootPort12ClkInfo|0|UINT64|0x000000AA
+gBoardModuleTokenSpaceGuid.PcdRootPort13ClkInfo|0|UINT64|0x000000AB
+gBoardModuleTokenSpaceGuid.PcdRootPort14ClkInfo|0|UINT64|0x000000AC
+gBoardModuleTokenSpaceGuid.PcdRootPort15ClkInfo|0|UINT64|0x000000AD
+gBoardModuleTokenSpaceGuid.PcdRootPort16ClkInfo|0|UINT64|0x000000AE
+gBoardModuleTokenSpaceGuid.PcdRootPort17ClkInfo|0|UINT64|0x000000AF
+gBoardModuleTokenSpaceGuid.PcdRootPort18ClkInfo|0|UINT64|0x000000B0
+gBoardModuleTokenSpaceGuid.PcdRootPort19ClkInfo|0|UINT64|0x000000B1
+gBoardModuleTokenSpaceGuid.PcdRootPort20ClkInfo|0|UINT64|0x000000B2
+gBoardModuleTokenSpaceGuid.PcdRootPort21ClkInfo|0|UINT64|0x000000B3
+gBoardModuleTokenSpaceGuid.PcdRootPort22ClkInfo|0|UINT64|0x000000B4
+gBoardModuleTokenSpaceGuid.PcdRootPort23ClkInfo|0|UINT64|0x000000B5
+gBoardModuleTokenSpaceGuid.PcdRootPort24ClkInfo|0|UINT64|0x000000B6
+gBoardModuleTokenSpaceGuid.PcdRootPort25ClkInfo|0|UINT64|0x000000B7
+gBoardModuleTokenSpaceGuid.PcdRootPort26ClkInfo|0|UINT64|0x000000B8
+gBoardModuleTokenSpaceGuid.PcdRootPort27ClkInfo|0|UINT64|0x000000B9
+gBoardModuleTokenSpaceGuid.PcdRootPort28ClkInfo|0|UINT64|0x000000BA
+gBoardModuleTokenSpaceGuid.PcdRootPort29ClkInfo|0|UINT64|0x000000BB
+gBoardModuleTokenSpaceGuid.PcdRootPort30ClkInfo|0|UINT64|0x000000BC
+gBoardModuleTokenSpaceGuid.PcdRootPort31ClkInfo|0|UINT64|0x000000BD
+gBoardModuleTokenSpaceGuid.PcdRootPortLanClkInfo|0|UINT64|0x000000BE
+
+# USB 2.0 Port AFE
+gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe|0|UINT32|0x000000BF
+gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe|0|UINT32|0x000000C0
+gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe|0|UINT32|0x000000C1
+gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe|0|UINT32|0x000000C2
+gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe|0|UINT32|0x000000C3
+gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe|0|UINT32|0x000000C4
+gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe|0|UINT32|0x000000C5
+gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe|0|UINT32|0x000000C6
+gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe|0|UINT32|0x000000C7
+gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe|0|UINT32|0x000000C8
+gBoardModuleTokenSpaceGuid.PcdUsb20Port10Afe|0|UINT32|0x000000C9
+gBoardModuleTokenSpaceGuid.PcdUsb20Port11Afe|0|UINT32|0x000000CA
+gBoardModuleTokenSpaceGuid.PcdUsb20Port12Afe|0|UINT32|0x000000CB
+gBoardModuleTokenSpaceGuid.PcdUsb20Port13Afe|0|UINT32|0x000000CC
+gBoardModuleTokenSpaceGuid.PcdUsb20Port14Afe|0|UINT32|0x000000CD
+gBoardModuleTokenSpaceGuid.PcdUsb20Port15Afe|0|UINT32|0x000000CE
+
+# USB 2.0 Port Over Current Pin
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0|0|UINT8|0x000000CF
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1|0|UINT8|0x000000D0
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2|0|UINT8|0x000000D1
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3|0|UINT8|0x000000D2
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4|0|UINT8|0x000000D3
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5|0|UINT8|0x000000D4
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6|0|UINT8|0x000000D5
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7|0|UINT8|0x000000D6
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8|0|UINT8|0x000000D7
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9|0|UINT8|0x000000D8
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10|0|UINT8|0x000000D9
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11|0|UINT8|0x000000DA
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12|0|UINT8|0x000000DB
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13|0|UINT8|0x000000DC
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14|0|UINT8|0x000000DD
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15|0|UINT8|0x000000DE
+
+# USB 3.0 Port Over Current Pin
+gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0|0|UINT8|0x000000DF
+gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1|0|UINT8|0x000000E0
+gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2|0|UINT8|0x000000E1
+gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3|0|UINT8|0x000000E2
+gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4|0|UINT8|0x000000E3
+gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5|0|UINT8|0x000000E4
+gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6|0|UINT8|0x000000E5
+gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7|0|UINT8|0x000000E6
+gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8|0|UINT8|0x000000E7
+gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9|0|UINT8|0x000000E8
+
+# TBT
+gBoardModuleTokenSpaceGuid.PcdDTbtBootOn |0|UINT8|0x000000E9
+gBoardModuleTokenSpaceGuid.PcdDTbtUsbOn |0|UINT8|0x000000EA
+gBoardModuleTokenSpaceGuid.PcdDTbtGpio3ForcePwr |0|UINT8|0x000000EB
+gBoardModuleTokenSpaceGuid.PcdDTbtGpio3ForcePwrDly |0|UINT16|0x000000ED
+gBoardModuleTokenSpaceGuid.PcdDTbtControllerEn |0|UINT8|0x000000EE
+gBoardModuleTokenSpaceGuid.PcdDTbtControllerType |0|UINT8|0x000000EF
+gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber |0|UINT8|0x000000F0
+gBoardModuleTokenSpaceGuid.PcdDTbtGpioAccessType |0|UINT8|0x000000F1
+gBoardModuleTokenSpaceGuid.PcdExpander |0|UINT8|0x000000F2
+gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel |0|BOOLEAN|0x000000F3
+gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad |0|UINT32|0x000000F4
+gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad |0|UINT32|0x000000F5
+gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignature |0|UINT32|0x000000F6
+gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting |0|BOOLEAN|0x000000F7
+gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode |0|UINT8|0x000000F8
+gBoardModuleTokenSpaceGuid.PcdDTbtGpio5Filter |0|UINT8|0x000000F9
+gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport |0|UINT8|0x000000FA
+gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI |0|UINT8|0x000000FB
+gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify |0|UINT8|0x000000FC
+gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq|0|UINT8|0x000000FD
+gBoardModuleTokenSpaceGuid.PcdDTbtAspm |0|UINT8|0x000000FE
+gBoardModuleTokenSpaceGuid.PcdDTbtLtr | 0 | UINT8| 0x00000116
+gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch |0|UINT8|0x000000FF
+gBoardModuleTokenSpaceGuid.PcdRtd3Tbt |0|UINT8|0x00000100
+gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq |0|UINT8|0x0000010A
+gBoardModuleTokenSpaceGuid.PcdDTbtWin10Support |0|UINT8|0x000000102
+gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReqDelay |0|UINT16|0x00000103
+gBoardModuleTokenSpaceGuid.PcdRtd3TbtOffDelay |0|UINT16|0x00000104
+gBoardModuleTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd |0|UINT8|0x00000105
+gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemRsvd |0|UINT16|0x00000106
+gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax |0|UINT8|0x00000107
+gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd |0|UINT16|0x00000108
+gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax |0|UINT8|0x00000109
+gBoardModuleTokenSpaceGuid.PcdPchPcieRootPortHpe|0|UINT32|0x00000117
+
+# UCMC GPIO Table
+gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable|0|UINT32|0x000000111
+gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize|0|UINT16|0x000000112
+
+# Misc
+gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent|FALSE|BOOLEAN|0x000000EC
+
+gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable|1|UINT8|0x40000009
+gBoardModuleTokenSpaceGuid.PcdAcpiSleepState|1|UINT8|0x40000002
+gBoardModuleTokenSpaceGuid.PcdAcpiHibernate|1|UINT8|0x40000003
+gBoardModuleTokenSpaceGuid.PcdLowPowerS0Idle|0|UINT8|0x40000004
+gBoardModuleTokenSpaceGuid.PcdPciExpNative|0|UINT8|0x40000005
+gBoardModuleTokenSpaceGuid.PcdNativeAspmEnable|1|UINT8|0x40000006
+gBoardModuleTokenSpaceGuid.PcdDisableActiveTripPoints|1|UINT8|0x4000000A
+gBoardModuleTokenSpaceGuid.PcdDisablePassiveTripPoints|0|UINT8|0x4000000B
+gBoardModuleTokenSpaceGuid.PcdDisableCriticalTripPoints|1|UINT8|0x4000000C
+# 0: Type-C
+# 1: Stacked-Jack
+gBoardModuleTokenSpaceGuid.PcdAudioConnector|0|UINT8|0x40000012
+gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x40000013
+gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid|{0x22, 0x61, 0xd4, 0x4a, 0xeb, 0xff, 0x52, 0x4a, 0xbf, 0xb0, 0x51, 0x8c, 0xfc, 0xa0, 0x2d, 0xb0}|VOID*|0x40000014
+
+[PcdsDynamicEx]
+
+[PcdsDynamic, PcdsDynamicEx]
+
+[PcdsPatchableInModule]
+
+[PcdsFeatureFlag]
+  gBoardModuleTokenSpaceGuid.PcdIntelGopEnable      |TRUE|BOOLEAN|0xF0000062
+
+  gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport   |TRUE|BOOLEAN|0xF0000000
+
+  gBoardModuleTokenSpaceGuid.PcdTbtEnable           |FALSE|BOOLEAN|0x000000115
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.h b/Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.h
new file mode 100644
index 0000000000..4e20fa201a
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.h
@@ -0,0 +1,136 @@
+/**@file
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCI_HOT_PLUG_H_
+#define _PCI_HOT_PLUG_H_
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#include <Base.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <IndustryStandard/Acpi10.h>
+#include <Protocol/PciHotPlugInit.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Library/DevicePathLib.h>
+#include <Library/UefiLib.h>
+#include <Guid/HobList.h>
+#include <Library/HobLib.h>
+#include <Protocol/SaPolicy.h>
+
+#define PCI_HOT_PLUG_DRIVER_PRIVATE_SIGNATURE SIGNATURE_32 ('G', 'U', 'L', 'P')
+
+#define ACPI \
+  { \
+    { ACPI_DEVICE_PATH, ACPI_DP, { (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), (UINT8) \
+      ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) } }, EISA_PNP_ID (0x0A03), 0 \
+  }
+
+#define PCI(device, function) \
+  { \
+    { HARDWARE_DEVICE_PATH, HW_PCI_DP, { (UINT8) (sizeof (PCI_DEVICE_PATH)), (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) } }, \
+      (UINTN) function, (UINTN) device \
+  }
+
+#define END \
+  { \
+    END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { END_DEVICE_PATH_LENGTH, 0 } \
+  }
+
+#define LPC(eisaid, function) \
+  { \
+    { ACPI_DEVICE_PATH, ACPI_DP, { (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), (UINT8) \
+      ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) } }, EISA_PNP_ID (eisaid), function \
+  }
+
+typedef struct PCIE_HOT_PLUG_DEVICE_PATH {
+  ACPI_HID_DEVICE_PATH      PciRootBridgeNode;
+  PCI_DEVICE_PATH           PciRootPortNode;
+  EFI_DEVICE_PATH_PROTOCOL  EndDeviceNode;
+} PCIE_HOT_PLUG_DEVICE_PATH;
+
+typedef struct {
+  UINTN                           Signature;
+  EFI_HANDLE                      Handle; // Handle for protocol this driver installs on
+  EFI_PCI_HOT_PLUG_INIT_PROTOCOL  HotPlugInitProtocol;
+} PCI_HOT_PLUG_INSTANCE;
+
+/**
+  This procedure returns a list of Root Hot Plug controllers that require
+  initialization during boot process
+
+  @param[in]  This      The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol.
+  @param[out] HpcCount  The number of Root HPCs returned.
+  @param[out] HpcList   The list of Root HPCs. HpcCount defines the number of elements in this list.
+
+  @retval EFI_SUCCESS.
+**/
+EFI_STATUS
+EFIAPI
+GetRootHpcList (
+  IN  EFI_PCI_HOT_PLUG_INIT_PROTOCOL    *This,
+  OUT UINTN                             *PhpcCount,
+  OUT EFI_HPC_LOCATION                  **PhpcList
+  );
+
+/**
+  This procedure Initializes one Root Hot Plug Controller
+  This process may casue initialization of its subordinate buses
+
+  @param[in]  This            The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol.
+  @param[in]  HpcDevicePath   The Device Path to the HPC that is being initialized.
+  @param[in]  HpcPciAddress   The address of the Hot Plug Controller function on the PCI bus.
+  @param[in]  Event           The event that should be signaled when the Hot Plug Controller initialization is complete. Set to NULL if the caller wants to wait until the entire initialization process is complete. The event must be of the type EFI_EVT_SIGNAL.
+  @param[out] HpcState        The state of the Hot Plug Controller hardware. The type EFI_Hpc_STATE is defined in section 3.1.
+
+  @retval   EFI_SUCCESS.
+**/
+EFI_STATUS
+EFIAPI
+InitializeRootHpc (
+  IN  EFI_PCI_HOT_PLUG_INIT_PROTOCOL  *This,
+  IN  EFI_DEVICE_PATH_PROTOCOL        *PhpcDevicePath,
+  IN  UINT64                          PhpcPciAddress,
+  IN  EFI_EVENT                       Event, OPTIONAL
+  OUT EFI_HPC_STATE                   *PhpcState
+  );
+
+/**
+  Returns the resource padding required by the PCI bus that is controlled by the specified Hot Plug Controller.
+
+  @param[in]  This           The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol. initialized.
+  @param[in]  HpcDevicePath  The Device Path to the Hot Plug Controller.
+  @param[in]  HpcPciAddress  The address of the Hot Plug Controller function on the PCI bus.
+  @param[out] HpcState       The state of the Hot Plug Controller hardware. The type EFI_HPC_STATE is defined in section 3.1.
+  @param[out] Padding        This is the amount of resource padding required by the PCI bus under the control of the specified Hpc. Since the caller does not know the size of this buffer, this buffer is allocated by the callee and freed by the caller.
+  @param[out] Attribute      Describes how padding is accounted for.
+
+  @retval     EFI_SUCCESS.
+**/
+EFI_STATUS
+EFIAPI
+GetResourcePadding (
+  IN  EFI_PCI_HOT_PLUG_INIT_PROTOCOL  *This,
+  IN  EFI_DEVICE_PATH_PROTOCOL        *PhpcDevicePath,
+  IN  UINT64                          PhpcPciAddress,
+  OUT EFI_HPC_STATE                   *PhpcState,
+  OUT VOID                            **Padding,
+  OUT EFI_HPC_PADDING_ATTRIBUTES      *Attributes
+  );
+
+#endif
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Acpi/TbtNvsAreaDef.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Acpi/TbtNvsAreaDef.h
new file mode 100644
index 0000000000..2c6995a20d
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Acpi/TbtNvsAreaDef.h
@@ -0,0 +1,68 @@
+/**@file
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+  //
+  // Define TBT NVS Area operation region.
+  //
+#ifndef _TBT_NVS_AREA_DEF_H_
+#define _TBT_NVS_AREA_DEF_H_
+
+#pragma pack (push,1)
+typedef struct {
+  UINT8    ThunderboltSmiFunction;                  ///< Offset 0       Thunderbolt(TM) SMI Function Number
+  UINT8    ThunderboltHotSmi;                       ///< Offset 1       SMI on Hot Plug for TBT devices
+  UINT8    TbtWin10Support;                         ///< Offset 2       TbtWin10Support
+  UINT8    TbtGpioFilter;                           ///< Offset 3       Gpio filter to detect USB Hotplug event
+  UINT8    ThunderboltHotNotify;                    ///< Offset 4       Notify on Hot Plug for TBT devices
+  UINT8    TbtSelector;                             ///< Offset 5       Thunderbolt(TM) Root port selector
+  UINT8    WAKFinished;                             ///< Offset 6       WAK Finished
+  UINT8    DiscreteTbtSupport;                      ///< Offset 7       Thunderbolt(TM) support
+  UINT8    TbtAcpiRemovalSupport;                   ///< Offset 8       TbtAcpiRemovalSupport
+  UINT32   TbtFrcPwrEn;                             ///< Offset 9       TbtFrcPwrEn
+  UINT32   TbtFrcPwrGpioNo0;                        ///< Offset 13      TbtFrcPwrGpioNo
+  UINT8    TbtFrcPwrGpioLevel0;                     ///< Offset 17      TbtFrcPwrGpioLevel
+  UINT32   TbtCioPlugEventGpioNo0;                  ///< Offset 18      TbtCioPlugEventGpioNo
+  UINT32   TbtPcieRstGpioNo0;                       ///< Offset 22      TbtPcieRstGpioNo
+  UINT8    TbtPcieRstGpioLevel0;                    ///< Offset 26      TbtPcieRstGpioLevel
+  UINT8    CurrentDiscreteTbtRootPort;              ///< Offset 27      Current Port that has plug event
+  UINT8    RootportSelected0;                       ///< Offset 28      Root port Selected by the User
+  UINT8    RootportSelected0Type;                   ///< Offset 29      Root port Type
+  UINT8    RootportSelected1;                       ///< Offset 30      Root port Selected by the User
+  UINT8    RootportSelected1Type;                   ///< Offset 31      Root port Type
+  UINT8    RootportEnabled0;                        ///< Offset 32      Root port Enabled by the User
+  UINT8    RootportEnabled1;                        ///< Offset 33      Root port Enabled by the User
+  UINT32   TbtFrcPwrGpioNo1;                        ///< Offset 34      TbtFrcPwrGpioNo
+  UINT8    TbtFrcPwrGpioLevel1;                     ///< Offset 38      TbtFrcPwrGpioLevel
+  UINT32   TbtCioPlugEventGpioNo1;                  ///< Offset 39      TbtCioPlugEventGpioNo
+  UINT32   TbtPcieRstGpioNo1;                       ///< Offset 43      TbtPcieRstGpioNo
+  UINT8    TbtPcieRstGpioLevel1;                    ///< Offset 47      TbtPcieRstGpioLevel
+  UINT8    TBtCommonGpioSupport;                    ///< Offset 48      Set if Single GPIO is used for Multi/Different Controller Hot plug support
+  UINT8    CurrentDiscreteTbtRootPortType;          ///< Offset 49      Root Port type for which SCI Triggered
+  UINT8    TrOsup;                                  ///< Offset 50      Titan Ridge Osup command
+  UINT8    TbtAcDcSwitch;                           ///< Offset 51      TBT Dynamic AcDc L1
+  UINT8    DTbtControllerEn0;                       ///< Offset 52      DTbtController0 is enabled or not.
+  UINT8    DTbtControllerEn1;                       ///< Offset 53      DTbtController1 is enabled or not.
+  UINT8    TbtAspm;                                 ///< Offset 54      ASPM setting for all the PCIe device in TBT daisy chain.
+  UINT8    TbtL1SubStates;                          ///< Offset 55      L1 SubState for for all the PCIe device in TBT daisy chain.
+  UINT8    TbtSetClkReq;                            ///< Offset 56      CLK REQ for all the PCIe device in TBT daisy chain.
+  UINT8    TbtLtr;                                  ///< Offset 57      LTR for for all the PCIe device in TBT daisy chain.
+  UINT8    TbtPtm;                                  ///< Offset 58      PTM for for all the PCIe device in TBT daisy chain.
+  UINT8    TbtWakeupSupport;                        ///< Offset 59      Send Go2SxNoWake or GoSxWake according to TbtWakeupSupport
+  UINT16   Rtd3TbtOffDelay;                         ///< Offset 60      Rtd3TbtOffDelay TBT RTD3 Off Delay
+  UINT8    TbtSxWakeSwitchLogicEnable;              ///< Offset 62      TbtSxWakeSwitchLogicEnable Set True if TBT_WAKE_N will be routed to PCH WakeB at Sx entry point. HW logic is required.
+  UINT8    Rtd3TbtSupport;                          ///< Offset 63      Enable Rtd3 support for TBT. Corresponding to Rtd3Tbt in Setup.
+  UINT8    Rtd3TbtClkReq;                           ///< Offset 64      Enable TBT RTD3 CLKREQ mask.
+  UINT16   Rtd3TbtClkReqDelay;                      ///< Offset 65      TBT RTD3 CLKREQ mask delay.
+} TBT_NVS_AREA;
+
+#pragma pack(pop)
+#endif
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/DxeTbtPolicyLib.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/DxeTbtPolicyLib.h
new file mode 100644
index 0000000000..b69a1a888e
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/DxeTbtPolicyLib.h
@@ -0,0 +1,52 @@
+/** @file
+  Prototype of the DxeTbtPolicyLib library.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _DXE_TBT_POLICY_LIB_H_
+#define _DXE_TBT_POLICY_LIB_H_
+
+/**
+  Install TBT Policy.
+
+  @param[in] ImageHandle                Image handle of this driver.
+
+  @retval EFI_SUCCESS                   The policy is installed.
+  @retval EFI_OUT_OF_RESOURCES          Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+InstallTbtPolicy (
+  IN  EFI_HANDLE                    ImageHandle
+  );
+
+/**
+  Update Tbt Policy Callback.
+
+  @param[in] Event         A pointer to the Event that triggered the callback.
+  @param[in] Context       A pointer to private data registered with the callback function.
+
+**/
+VOID
+EFIAPI
+UpdateTbtPolicyCallback (
+  VOID
+  );
+
+/**
+  Print DXE TBT Policy
+**/
+VOID
+TbtPrintDxePolicyConfig (
+  VOID
+  );
+#endif // _DXE_TBT_POLICY_LIB_H_
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/PeiTbtPolicyLib.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/PeiTbtPolicyLib.h
new file mode 100644
index 0000000000..aff0717af6
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/PeiTbtPolicyLib.h
@@ -0,0 +1,47 @@
+/** @file
+  Prototype of the PeiTbtPolicyLib library.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PEI_TBT_POLICY_LIB_H_
+#define _PEI_TBT_POLICY_LIB_H_
+
+/**
+  Install Tbt Policy
+
+  @retval EFI_SUCCESS                   The policy is installed.
+  @retval EFI_OUT_OF_RESOURCES          Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+InstallPeiTbtPolicy (
+  VOID
+  );
+
+/**
+  Update PEI TBT Policy
+**/
+VOID
+EFIAPI
+UpdatePeiTbtPolicy (
+  VOID
+  );
+
+/**
+  Print PEI TBT Policy
+**/
+VOID
+EFIAPI
+TbtPrintPeiPolicyConfig (
+  VOID
+  );
+#endif // _DXE_TBT_POLICY_LIB_H_
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/TbtCommonLib.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/TbtCommonLib.h
new file mode 100644
index 0000000000..bdef416bad
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/TbtCommonLib.h
@@ -0,0 +1,247 @@
+/**@file
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _TBT_COMMON_LIB_H_
+#define _TBT_COMMON_LIB_H_
+
+#include <Library/BaseLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/GpioExpanderLib.h>
+
+#define DTBT_CONTROLLER                   0x00
+#define DTBT_TYPE_PCH                     0x01
+#define DTBT_TYPE_PEG                     0x02
+#define TBT2PCIE_DTBT_R                   0x548
+#define PCIE2TBT_DTBT_R                   0x54C
+
+//
+//  Thunderbolt FW OS capability
+//
+#define NO_OS_NATIVE_SUPPORT    0
+#define OS_NATIVE_SUPPORT_ONLY  1
+#define OS_NATIVE_SUPPORT_RTD3  2
+
+#define DTBT_SAVE_STATE_OFFSET  BIT0 // Bits 0-3 is for DTBT (only bit 0 is in use)
+/**
+Get Tbt2Pcie Register Offset
+
+@retval     Register  Register Variable
+**/
+
+#define GET_TBT2PCIE_REGISTER_ADDRESS(Segment, Bus, Device, Function, RegisterAddress) \
+RegisterAddress = PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, TBT2PCIE_DTBT_R); \
+
+/**
+Get Pcie2Tbt Register Offset
+
+@retval     Register  Register Variable
+**/
+
+#define GET_PCIE2TBT_REGISTER_ADDRESS(Segment, Bus, Device, Function, RegisterAddress) \
+RegisterAddress = PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, PCIE2TBT_DTBT_R); \
+
+#define PCIE2TBT_VLD_B                    BIT0
+#define TBT2PCIE_DON_R                    BIT0
+#define TBT_MAIL_BOX_DELAY                (100*1000)
+#define TBT_5S_TIMEOUT                    50
+#define TBT_1S_TIMEOUT                    10
+#define TBT_3S_TIMEOUT                    30
+
+#define PCIE2TBT_GO2SX                    (0x02 << 1)
+#define PCIE2TBT_GO2SX_NO_WAKE            (0x03 << 1)
+#define PCIE2TBT_SX_EXIT_TBT_CONNECTED    (0x04 << 1)
+#define PCIE2TBT_SX_EXIT_NO_TBT_CONNECTED (0x05 << 1)
+#define PCIE2TBT_OS_UP                    (0x06 << 1)
+#define PCIE2TBT_SET_SECURITY_LEVEL       (0x08 << 1)
+#define PCIE2TBT_GET_SECURITY_LEVEL       (0x09 << 1)
+#define PCIE2TBT_CM_AUTH_MODE_ENTER       (0x10 << 1)
+#define PCIE2TBT_CM_AUTH_MODE_EXIT        (0x11 << 1)
+#define PCIE2TBT_BOOT_ON                  (0x18 << 1)
+#define PCIE2TBT_BOOT_OFF                 (0x19 << 1)
+#define PCIE2TBT_USB_ON                   (0x19 << 1)
+#define PCIE2TBT_GET_ENUMERATION_METHOD   (0x1A << 1)
+#define PCIE2TBT_SET_ENUMERATION_METHOD   (0x1B << 1)
+#define PCIE2TBT_POWER_CYCLE              (0x1C << 1)
+#define PCIE2TBT_PREBOOTACL               (0x1E << 1)
+#define CONNECT_TOPOLOGY_COMMAND          (0x1F << 1)
+
+#define RESET_HR_BIT                      BIT0
+#define ENUMERATE_HR_BIT                  BIT1
+#define AUTO                              0x0
+
+//
+//Thunder Bolt Device IDs
+//
+
+//
+// Alpine Ridge HR device IDs
+//
+#define AR_HR_2C  0x1576
+#define AR_HR_4C  0x1578
+#define AR_XHC    0x15B5
+#define AR_XHC_4C 0x15B6
+#define AR_HR_LP  0x15C0
+//
+// Alpine Ridge C0 HR device IDs
+//
+#define AR_HR_C0_2C  0x15DA
+#define AR_HR_C0_4C  0x15D3
+//
+// Titan Ridge HR device IDs
+//
+#define TR_HR_2C  0x15E7
+#define TR_HR_4C  0x15EA
+//
+//End of Thunderbolt(TM) Device IDs
+//
+
+typedef struct _DEV_ID {
+  UINT8 Segment;
+  UINT8 Bus;
+  UINT8 Dev;
+  UINT8 Fun;
+} DEV_ID;
+
+//@todo Seems to only be used by Platform/TBT/Smm/TbtSmm.inf
+//@todo should refactor this to only be present in that driver
+//@todo also definitions like this should never be in a .h file anyway
+//@todo this is a quick hack to get things compiling for now
+#ifdef __GNUC__
+#pragma GCC diagnostic warning "-Wunused-variable"
+#endif
+
+/**
+Based on the Security Mode Selection, BIOS drives FORCE_PWR.
+
+@param[in]  GpioNumber
+@param[in]  Value
+**/
+VOID
+ForceDtbtPower(
+  IN  UINT8          GpioAccessType,
+  IN  UINT8          Expander,
+  IN  UINT32         GpioNumber,
+  IN  BOOLEAN        Value
+);
+
+/**
+  Get Security Level.
+  @param[in]  Bus       Bus number for Host Router (DTBT)
+  @param[in]  Device    Device number for Host Router (DTBT)
+  @param[in]  Function  Function number for Host Router (DTBT)
+  @param[in]  Timeout   Time out with 100 ms garnularity
+**/
+UINT8
+GetSecLevel (
+  IN    UINT8                   Bus,
+  IN    UINT8                   Device,
+  IN    UINT8                   Function,
+  IN    UINT8                   Command,
+  IN    UINT32                  Timeout
+  );
+
+/**
+  Set Security Level.
+  @param[in]  Data      Security State
+  @param[in]  Bus       Bus number for Host Router (DTBT)
+  @param[in]  Device    Device number for Host Router (DTBT)
+  @param[in]  Function  Function number for Host Router (DTBT)
+  @param[in]  Timeout   Time out with 100 ms garnularity
+**/
+BOOLEAN
+SetSecLevel (
+  IN    UINT8                   Data,
+  IN    UINT8                   Bus,
+  IN    UINT8                   Device,
+  IN    UINT8                   Function,
+  IN    UINT8                   Command,
+  IN    UINT32                  Timeout
+  );
+
+/**
+Execute TBT Mail Box Command
+
+@param[in]  Command   TBT Command
+@param[in]  Bus       Bus number for Host Router (DTBT)
+@param[in]  Device    Device number for Host Router (DTBT)
+@param[in]  Function  Function number for Host Router (DTBT)
+@param[in]  Timeout   Time out with 100 ms garnularity
+@Retval     true      if command executes succesfully
+**/
+BOOLEAN
+TbtSetPcie2TbtCommand(
+  IN    UINT8                   Command,
+  IN    UINT8                   Bus,
+  IN    UINT8                   Device,
+  IN    UINT8                   Function,
+  IN    UINT32                  Timeout
+);
+/**
+  Check connected TBT controller is supported or not by DeviceID
+
+  @param[in]  DeviceID              DeviceID of of TBT controller
+
+
+  @retval     TRUE                  Valid DeviceID
+  @retval     FALSE                 Invalid DeviceID
+**/
+
+BOOLEAN
+IsTbtHostRouter (
+  IN    UINT16  DeviceID
+  );
+
+/**
+  Get Pch/Peg Pcie Root Port Device and Function Number for TBT by Root Port physical Number
+
+  @param[in]  RpNumber              Root port physical number. (0-based)
+  @param[out] RpDev                 Return corresponding root port device number.
+  @param[out] RpFun                 Return corresponding root port function number.
+
+  @retval     EFI_SUCCESS           Root port device and function is retrieved
+**/
+EFI_STATUS
+EFIAPI
+GetDTbtRpDevFun(
+  IN  BOOLEAN Type,
+  IN  UINTN   RpNumber,
+  OUT UINTN   *RpDev,
+  OUT UINTN   *RpFunc
+  );
+
+/**
+  Internal function to Wait for Tbt2PcieDone Bit.to Set or clear
+  @param[in]  CommandOffsetAddress      Tbt2Pcie Register Address
+  @param[in]  TimeOut                   Time out with 100 ms garnularity
+  @param[in]  Tbt2PcieDone              Wait condition (wait for Bit to Clear/Set)
+  @param[out] *Tbt2PcieValue Function   Register value
+**/
+BOOLEAN
+InternalWaitforCommandCompletion (
+  IN  UINT64   CommandOffsetAddress,
+  IN  UINT32   TimeOut,
+  IN  BOOLEAN  Tbt2PcieDone,
+  OUT UINT32   *Tbt2PcieValue
+  );
+
+VOID
+GetRootporttoSetResourcesforTbt (
+  IN UINTN                              RpIndex,
+  OUT UINT8                             *RsvdExtraBusNum,
+  OUT UINT16                            *RsvdPcieMegaMem,
+  OUT UINT8                             *PcieMemAddrRngMax,
+  OUT UINT16                            *RsvdPciePMegaMem,
+  OUT UINT8                             *PciePMemAddrRngMax,
+  OUT BOOLEAN                           *SetResourceforTbt
+  );
+
+#endif
\ No newline at end of file
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Ppi/PeiTbtPolicy.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Ppi/PeiTbtPolicy.h
new file mode 100644
index 0000000000..a9ed0701fd
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Ppi/PeiTbtPolicy.h
@@ -0,0 +1,35 @@
+/** @file
+TBT PEI Policy
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PEI_TBT_POLICY_H_
+#define _PEI_TBT_POLICY_H_
+
+#include <TbtPolicyCommonDefinition.h>
+
+#pragma pack(push, 1)
+
+#define PEI_TBT_POLICY_REVISION 1
+
+/**
+ TBT PEI configuration\n
+  <b>Revision 1</b>:
+  - Initial version.
+**/
+typedef struct _PEI_TBT_POLICY {
+  DTBT_COMMON_CONFIG     DTbtCommonConfig;                  ///< dTbt Common Configuration
+  DTBT_CONTROLLER_CONFIG DTbtControllerConfig;              ///< dTbt Controller Configuration
+} PEI_TBT_POLICY;
+
+#pragma pack(pop)
+
+#endif
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Private/Library/PeiDTbtInitLib.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Private/Library/PeiDTbtInitLib.h
new file mode 100644
index 0000000000..c19347584f
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Private/Library/PeiDTbtInitLib.h
@@ -0,0 +1,114 @@
+/**@file
+  PEI DTBT Init Dispatch library Header file
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __PEI_DTBT_INIT_LIB_H__
+#define __PEI_DTBT_INIT_LIB_H__
+
+#include <Ppi/PeiTbtPolicy.h>
+
+/**
+  set tPCH25 Timing to 10 ms for DTBT.
+
+  @param[in]  PEI_TBT_POLICY   PeiTbtConfig
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     EFI_UNSUPPORTED  dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtSetTPch25Timing (
+  IN  PEI_TBT_POLICY  *PeiTbtConfig
+);
+
+/**
+  Do ForcePower for DTBT Controller
+
+  @param[in]  PEI_TBT_POLICY   PeiTbtConfig
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     EFI_UNSUPPORTED  dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtForcePower (
+  IN  PEI_TBT_POLICY  *PeiTbtConfig
+);
+
+/**
+  Clear VGA Registers for DTBT.
+
+  @param[in]  PEI_TBT_POLICY   PeiTbtConfig
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     EFI_UNSUPPORTED  dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtClearVgaRegisters (
+  IN  PEI_TBT_POLICY  *PeiTbtConfig
+);
+
+/**
+  Exectue Mail box command "Boot On".
+
+  @param[in]  PEI_TBT_POLICY   PeiTbtConfig
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     EFI_UNSUPPORTED  dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtBootOn (
+  IN  PEI_TBT_POLICY  *PeiTbtConfig
+);
+
+/**
+  Exectue Mail box command "USB On".
+
+  @param[in]  PEI_TBT_POLICY   PeiTbtConfig
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     EFI_UNSUPPORTED  dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtUsbOn (
+  IN  PEI_TBT_POLICY  *PeiTbtConfig
+);
+
+/**
+  Exectue Mail box command "Sx Exit".
+
+  @param[in]  PEI_TBT_POLICY   PeiTbtConfig
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     EFI_UNSUPPORTED  dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtSxExitFlow (
+  IN  PEI_TBT_POLICY  *PeiTbtConfig
+);
+/**
+  Initialize Thunderbolt(TM)
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     others
+**/
+EFI_STATUS
+EFIAPI
+TbtInit (
+  VOID
+);
+
+#endif
\ No newline at end of file
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Private/Library/PeiTbtCommonInitLib.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Private/Library/PeiTbtCommonInitLib.h
new file mode 100644
index 0000000000..6dfcef0343
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Private/Library/PeiTbtCommonInitLib.h
@@ -0,0 +1,47 @@
+/**@file
+  PEI TBT Common Init Dispatch library Header file
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __PEI_TBT_COMMON_INIT_LIB_H__
+#define __PEI_TBT_COMMON_INIT_LIB_H__
+
+#include <Library/PeiServicesLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/GpioLib.h>
+#include <Library/TimerLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PcdLib.h>
+#include <Library/TbtCommonLib.h>
+#include <IndustryStandard/Pci22.h>
+#include <Library/PchPmcLib.h>
+
+VOID
+TbtSetSxMode(
+IN    BOOLEAN                 Type,
+IN    UINT8                   Bus,
+IN    UINT8                   Device,
+IN    UINT8                   Function,
+IN    UINT8                   TbtBootOn
+);
+
+VOID
+TbtClearVgaRegisters(
+IN    UINTN                   Segment,
+IN    UINTN                   Bus,
+IN    UINTN                   Device,
+IN    UINTN                   Function
+);
+
+#endif
\ No newline at end of file
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Protocol/DxeTbtPolicy.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Protocol/DxeTbtPolicy.h
new file mode 100644
index 0000000000..ab5a829755
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Protocol/DxeTbtPolicy.h
@@ -0,0 +1,116 @@
+/** @file
+TBT DXE Policy
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _DXE_TBT_POLICY_H_
+#define _DXE_TBT_POLICY_H_
+
+#include <TbtPolicyCommonDefinition.h>
+
+#pragma pack(push, 1)
+
+#define DXE_TBT_POLICY_REVISION 1
+
+//
+// TBT Common Data Structure
+//
+typedef struct _TBT_COMMON_CONFIG{
+  /**
+    TBT Security Level
+    <b>0: SL0 No Security</b>, 1: SL1 User Authorization, 2: SL2 Secure Connect, 3: SL3 Display Port and USB
+  **/
+  UINT32   SecurityMode      : 3;
+  /**
+    BIOS W/A for Hot plug of 12V USB devices cause electrical noise on PCH GPIOs
+    <b>0: Disabled</b>, 1: Enabled
+  **/
+  UINT32   Gpio5Filter       : 1;
+  /**
+    Send Go2SxNoWake or GoSxWake according to TbtWakeupSupport
+    <b>0: Disabled</b>, 1: Enabled
+  **/
+  UINT32   TbtWakeupSupport  : 1;
+  /**
+    SMI TBT enumeration
+    <b>0: Disabled</b>, 1: Enabled
+  **/
+  UINT32   TbtHotSMI         : 1;
+  /**
+    Notify PCIe RP after Hot-Plug/Hot-Unplug occurred.
+    <b>0: Disabled</b>, 1: Enabled
+  **/
+  UINT32   TbtHotNotify      : 1;
+  /**
+    CLK REQ for all the PCIe device in TBT daisy chain.
+    <b>0: Disabled</b>, 1: Enabled
+  **/
+  UINT32   TbtSetClkReq      : 1;
+  /**
+    ASPM setting for all the PCIe device in TBT daisy chain.
+    <b>0: Disabled</b>, 1: L0s, 2: L1, 3: L0sL1
+  **/
+  UINT32   TbtAspm           : 2;
+  /**
+    LTR for for all the PCIe device in TBT daisy chain.
+    <b>0: Disabled</b>, 1: Enabled
+  **/
+  UINT32   TbtLtr            : 1;
+  /**
+    TBT Dynamic AC/DC L1.
+    <b>0: Disabled</b>, 1: Enabled
+  **/
+  UINT32   TbtAcDcSwitch     : 1;
+  /**
+    TBT RTD3 Support.
+    <b>0: Disabled</b>, 1: Enabled
+  **/
+  UINT32   Rtd3Tbt           : 1;
+  /**
+    TBT ClkReq for RTD3 Flow.
+    <b>0: Disabled</b>, 1: Enabled
+  **/
+  UINT32   Rtd3TbtClkReq     : 1;
+  /**
+    TBT Win10support for Tbt FW execution mode.
+    <b>0: Disabled</b>, 1: Native, 2: Native + RTD3
+  **/
+  UINT32   Win10Support      : 2;
+  UINT32   Rsvd0             : 17; ///< Reserved bits
+  UINT16  Rtd3TbtClkReqDelay;
+  UINT16  Rtd3TbtOffDelay;
+} TBT_COMMON_CONFIG;
+
+//
+// dTBT Resource Data Structure
+//
+typedef struct _DTBT_RESOURCE_CONFIG{
+  UINT8  DTbtPcieExtraBusRsvd;     ///< Preserve Bus resource for PCIe RP that connect to dTBT Host Router
+  UINT16 DTbtPcieMemRsvd;          ///< Preserve MEM resource for PCIe RP that connect to dTBT Host Router
+  UINT8  DTbtPcieMemAddrRngMax;    ///< Alignment of Preserve MEM resource for PCIe RP that connect to dTBT Host Router
+  UINT16 DTbtPciePMemRsvd;         ///< Preserve PMEM resource for PCIe RP that connect to dTBT Host Router
+  UINT8  DTbtPciePMemAddrRngMax;   ///< Alignment of Preserve PMEM resource for PCIe RP that connect to dTBT Host Router
+  UINT8  Reserved[1];      ///< Reserved for DWORD alignment
+} DTBT_RESOURCE_CONFIG;
+
+/**
+ TBT DXE configuration\n
+  <b>Revision 1</b>:
+  - Initial version.
+**/
+typedef struct _DXE_TBT_POLICY_PROTOCOL {
+  TBT_COMMON_CONFIG      TbtCommonConfig;                                  ///< Tbt Common Information
+  DTBT_RESOURCE_CONFIG   DTbtResourceConfig;   ///< dTbt Resource Configuration
+} DXE_TBT_POLICY_PROTOCOL;
+
+#pragma pack(pop)
+
+#endif
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Protocol/TbtNvsArea.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Protocol/TbtNvsArea.h
new file mode 100644
index 0000000000..9296a05821
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Protocol/TbtNvsArea.h
@@ -0,0 +1,48 @@
+/** @file
+  This file defines the TBT NVS Area Protocol.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _TBT_NVS_AREA_H_
+#define _TBT_NVS_AREA_H_
+
+//
+// Platform NVS Area definition
+//
+#include <Acpi\TbtNvsAreaDef.h>
+
+//
+// Includes
+//
+#define TBT_NVS_DEVICE_ENABLE 1
+#define TBT_NVS_DEVICE_DISABLE 0
+
+//
+// Forward reference for pure ANSI compatibility
+//
+typedef struct _TBT_NVS_AREA_PROTOCOL TBT_NVS_AREA_PROTOCOL;
+
+///
+/// Extern the GUID for protocol users.
+///
+extern EFI_GUID gTbtNvsAreaProtocolGuid;
+
+#define TBT_NVS_AREA_REVISION_1       1
+
+//
+// Platform NVS Area Protocol
+//
+typedef struct _TBT_NVS_AREA_PROTOCOL {
+  TBT_NVS_AREA     *Area;
+} TBT_NVS_AREA_PROTOCOL;
+
+#endif // _TBT_NVS_AREA_H_
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtBoardInfo.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtBoardInfo.h
new file mode 100644
index 0000000000..8b37ab77e5
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtBoardInfo.h
@@ -0,0 +1,28 @@
+/** @file
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _TBT_INFO_GUID_H_
+#define _TBT_INFO_GUID_H_
+#include <TbtPolicyCommonDefinition.h>
+
+#pragma pack(1)
+//
+// TBT Info HOB
+//
+typedef struct _TBT_INFO_HOB {
+  EFI_HOB_GUID_TYPE      EfiHobGuidType;
+  DTBT_COMMON_CONFIG     DTbtCommonConfig;                                  ///< dTbt Common Configuration
+  DTBT_CONTROLLER_CONFIG DTbtControllerConfig;                             ///< dTbt Controller Configuration
+} TBT_INFO_HOB;
+#pragma pack()
+
+#endif
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtPolicyCommonDefinition.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtPolicyCommonDefinition.h
new file mode 100644
index 0000000000..d88e7cb7b6
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtPolicyCommonDefinition.h
@@ -0,0 +1,83 @@
+/** @file
+TBT Policy Common definition.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _TBT_POLICY_COMMON_H_
+#define _TBT_POLICY_COMMON_H_
+
+#include <Library/GpioLib.h>
+#include <IndustryStandard/Pci22.h>
+
+#define TYPE_PCIE           0x01
+#define TYPE_PEG            0x02
+
+#pragma pack(push, 1)
+
+//
+// dTBT Force Power GPIO Data Structure
+//
+typedef struct _DTBT_FORCE_POWER_GPIO_CONFIG {
+  UINT8          GpioAccessType;     ///< Where the GPIO comes from [a.k.a how to access the GPIO],Where the GPIO comes from. 0: Disabled; 1: PCH, 2: I/O Expander
+  UINT8          Expander;           ///< Applicable to GpioAccessType = IoExpander {TCA6424A} type
+  GPIO_PAD       GpioPad;                 ///< GPIO Pad Number
+  BOOLEAN        GpioLevel;               ///< 0 = Active Low; 1 = Active High
+  UINT8          Reserved[1];             ///< Reserved for DWORD alignment
+} DTBT_FORCE_POWER_GPIO_CONFIG;
+
+//
+// dTBT CIO Plug Event GPIO Data Structure
+//
+typedef struct _DTBT_CIO_PLUG_EVENT_GPIO_CONFIG {
+  GPIO_PAD       GpioPad;                 ///< GPIO Pad Number
+  UINT32         AcpiGpeSignature;        ///< AcpiPlatform driver will change the XTBT method to the _Lxx or _Exx that we assign in this item.
+  BOOLEAN        AcpiGpeSignaturePorting; ///< 0 = No porting required(for 2-tier GPI GPE event architecture), 1 = Porting required(for 1-tier GPI GPE event architecture)
+  UINT8          Reserved[3];             ///< Reserved for DWORD alignment
+} DTBT_CIO_PLUG_EVENT_GPIO_CONFIG;
+
+//
+// dTBT PCIE Reset GPIO Data Structure
+//
+typedef struct _DTBT_PCIE_RESET_GPIO_CONFIG {
+  GPIO_PAD       GpioPad;                 ///< GPIO Pad Number
+  BOOLEAN        GpioLevel;               ///< 0 = Active Low; 1 = Active High
+  UINT8          Reserved[3];             ///< Reserved for DWORD alignment
+} DTBT_PCIE_RESET_GPIO_CONFIG;
+
+//
+// dTBT Controller Data Structure
+//
+typedef struct _DTBT_CONTROLLER_CONFIG{
+  UINT8                           DTbtControllerEn; ///< Enable/Disable DTbtController.
+  UINT8                           Type;             ///< 01-Pcie RP, 02- PEG,Reserved. <Specific according to Board Design>
+  UINT8                           PcieRpNumber;     ///< RP Number/ PEG Port (0,1,2) that connecet to dTBT controller. <Specific according to Board Design>
+  DTBT_FORCE_POWER_GPIO_CONFIG    ForcePwrGpio;     ///< The GPIO pin that can force dTBT Power On. <Specific according to Board Design>
+  DTBT_CIO_PLUG_EVENT_GPIO_CONFIG CioPlugEventGpio; ///< The GPIO pin that can generate Hot-Plug event. <Specific according to Board Design>
+  DTBT_PCIE_RESET_GPIO_CONFIG     PcieRstGpio;      ///< The GPIO pin that is use to perform Reset when platform enters to Sx, it is required for platforms where PCI_RST pin connected to Tbt is controlled with GPIO <Specific according to Board Design>
+  UINT8                           Reserved[1];      ///< Reserved for DWORD alignment
+} DTBT_CONTROLLER_CONFIG;
+
+//
+// dTBT Controller Data Structure
+//
+typedef struct _DTBT_COMMON_CONFIG{
+  UINT8            TbtBootOn;                    ///< Send BootOn Mailbox command when TbtBootOn is enabled.
+  UINT8            TbtUsbOn;                     ///< Send UsbOn Mailbox command when TbtBootOn is enabled.
+  UINT8            Gpio3ForcePwr;                ///< Force GPIO to power on or not
+  UINT16           Gpio3ForcePwrDly;             ///< The delay time after do ForcePwr
+  BOOLEAN          DTbtSharedGpioConfiguration;  ///< Multiple DTBT controllers share the same GPIO pin <Specific according to Board Design>
+  BOOLEAN          PcieRstSupport;               ///< 0 = Not Support, 1 = Supported. it is required for platforms where PCI_RST pin connected to Tbt is controlled with GPIO
+  UINT8            Reserved[1];                  ///< Reserved for DWORD alignment
+} DTBT_COMMON_CONFIG;
+
+#pragma pack(pop)
+
+#endif
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLibrary.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLibrary.h
new file mode 100644
index 0000000000..6dd1015c61
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLibrary.h
@@ -0,0 +1,28 @@
+/** @file
+  Header file for the DxeTBTPolicy library.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _DXE_TBT_POLICY_LIBRARY_H_
+#define _DXE_TBT_POLICY_LIBRARY_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <ConfigBlock.h>
+#include <Library/ConfigBlockLib.h>
+#include <Guid/EventGroup.h>
+
+#endif // _DXE_TBT_POLICY_LIBRARY_H_
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLibrary.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLibrary.h
new file mode 100644
index 0000000000..b85faef320
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLibrary.h
@@ -0,0 +1,23 @@
+/** @file
+  Header file for the PeiTBTPolicy library.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PEI_TBT_POLICY_LIBRARY_H_
+#define _PEI_TBT_POLICY_LIBRARY_H_
+
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#endif // _PEI_TBT_POLICY_LIBRARY_H_
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHandler.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHandler.h
new file mode 100644
index 0000000000..095d8d44f5
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHandler.h
@@ -0,0 +1,185 @@
+/**@file
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _TBT_SMI_HANDLER_H_
+#define _TBT_SMI_HANDLER_H_
+
+#include <Library/TbtCommonLib.h>
+#include <Library/IoLib.h>
+#include <IndustryStandard/Pci.h>
+
+#ifdef PROGRESS_CODE
+#undef PROGRESS_CODE
+#endif
+
+#define MAX_TBT_DEPTH         6
+
+#define P2P_BRIDGE            (((PCI_CLASS_BRIDGE) << 8) | (PCI_CLASS_BRIDGE_P2P))
+
+#define BAR_ALIGN(v, a)       ((((v) - 1) | (a)) + 1)
+
+#define CMD_BUS_MASTER        BIT2
+#define CMD_BM_IO             (CMD_BUS_MASTER | BIT0)
+#define CMD_BM_MEM            (CMD_BUS_MASTER | BIT1)
+#define CMD_BM_MEM_IO         (CMD_BUS_MASTER | BIT1 | BIT0)
+
+#define DEF_CACHE_LINE_SIZE   0x20
+#define DEF_RES_IO_PER_DEV    4
+#define DEF_RES_MEM_PER_DEV   32
+#define DEF_RES_PMEM_PER_DEV  32
+
+#define DOCK_BUSSES           8
+
+#define DISBL_IO_REG1C        0x01F1
+#define DISBL_MEM32_REG20     0x0000FFF0
+#define DISBL_PMEM_REG24      0x0001FFF1
+
+#define count(x)              (sizeof (x) / sizeof ((x)[0]))
+
+#define PCIE_CAP_ID_SSID_SSVID 0x0D
+#define INVALID_PCI_DEVICE    0xFFFFFFFF
+#define PCI_TBT_VESC_REG2     0x510
+
+typedef struct _PortInfo {
+  UINT8   IoBase;
+  UINT8   IoLimit;
+  UINT16  MemBase;
+  UINT16  MemLimit;
+  UINT64  PMemBase64;
+  UINT64  PMemLimit64;
+  UINT8   BusNumLimit;
+  UINT8   ConfedEP;
+} PORT_INFO;
+
+typedef struct _MEM_REGS {
+  UINT32  Base;
+  UINT32  Limit;
+} MEM_REGS;
+
+typedef struct _PMEM_REGS {
+  UINT64  Base64;
+  UINT64  Limit64;
+} PMEM_REGS;
+
+typedef struct _IO_REGS {
+  UINT16  Base;
+  UINT16  Limit;
+} IO_REGS;
+
+typedef struct _BRDG_RES_CONFIG {
+  UINT8   Cmd;
+  UINT8   Cls;
+  UINT8   IoBase;
+  UINT8   IoLimit;
+  UINT16  MemBase;
+  UINT16  MemLimit;
+  UINT64  PMemBase64;
+  UINT64  PMemLimit64;
+} BRDG_RES_CONFIG;
+
+typedef struct _BRDG_CONFIG {
+  DEV_ID          DevId;
+  UINT8           PBus;
+  UINT8           SBus;
+  UINT8           SubBus;
+  BOOLEAN         IsDSBridge;
+  BRDG_RES_CONFIG Res;
+} BRDG_CONFIG;
+
+enum {
+  HR_US_PORT,
+  HR_DS_PORT0,
+  HR_DS_PORT3,
+  HR_DS_PORT4,
+  HR_DS_PORT5,
+  HR_DS_PORT6,
+  MAX_CFG_PORTS
+};
+
+enum {
+  HR_DS_PORT1   = HR_DS_PORT3
+};
+
+//
+// Alpine Ridge
+//
+enum {
+  AR_DS_PORT1 = HR_DS_PORT3,
+  AR_DS_PORT2,
+  AR_DS_PORT3,
+  AR_DS_PORT4
+};
+
+typedef struct _HR_CONFIG {
+  UINT16  DeviceId;
+  UINT8   HRBus;
+  UINT8   MinDSNumber;
+  UINT8   MaxDSNumber;
+  UINT8   BridgeLoops;
+} HR_CONFIG;
+
+STATIC const BRDG_RES_CONFIG  NOT_IN_USE_BRIDGE = {
+  CMD_BUS_MASTER,
+  0,
+  DISBL_IO_REG1C & 0xFF,
+  DISBL_IO_REG1C >> 8,
+  DISBL_MEM32_REG20 & 0xFFFF,
+  DISBL_MEM32_REG20 >> 16,
+  DISBL_PMEM_REG24 & 0xFFFF,
+  DISBL_PMEM_REG24 >> 16
+};
+
+typedef union _BRDG_CIO_MAP_REG {
+  UINT32  AB_REG;
+  struct {
+    UINT32  NumOfDSPorts : 5;
+    UINT32  CioPortMap : 27;
+  } Bits;
+} BRDG_CIO_MAP_REG;
+
+//
+// Functions
+//
+VOID
+ThunderboltCallback (
+  IN UINT8 Type
+  );
+
+VOID
+TbtDisablePCIDevicesAndBridges (
+  IN UINT8 Type
+  );
+
+VOID
+EndOfThunderboltCallback(
+  IN   UINTN      RpSegment,
+  IN   UINTN      RpBus,
+  IN   UINTN      RpDevice,
+  IN   UINTN      RpFunction
+);
+
+VOID
+ConfigureTbtAspm(
+  IN UINT8       Type,
+  IN UINT16      Aspm
+);
+
+UINT8
+PcieFindCapId (
+  IN UINT8   Segment,
+  IN UINT8   Bus,
+  IN UINT8   Device,
+  IN UINT8   Function,
+  IN UINT8   CapId
+  );
+
+#endif
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h b/Platform/Intel/ClevoOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h
new file mode 100644
index 0000000000..a1fa221d76
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h
@@ -0,0 +1,122 @@
+/** @file
+  ACPI DSDT table
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+  // Define a Global region of ACPI NVS Region that may be used for any
+  // type of implementation.  The starting offset and size will be fixed
+  // up by the System BIOS during POST.  Note that the Size must be a word
+  // in size to be fixed up correctly.
+
+#ifndef _GLOBAL_NVS_AREA_DEF_H_
+#define _GLOBAL_NVS_AREA_DEF_H_
+
+#pragma pack (push,1)
+typedef struct {
+  //
+  // Miscellaneous Dynamic Registers:
+  //
+  UINT16   OperatingSystem;                         ///< Offset 0       Operating System
+  UINT8    SmiFunction;                             ///< Offset 2       SMI Function Call (ASL to SMI via I/O Trap)
+  UINT32   Port80DebugValue;                        ///< Offset 3       Port 80 Debug Port Value
+  UINT8    PowerState;                              ///< Offset 7       Power State (AC Mode = 1)
+  //
+  // Thermal Policy Registers:
+  //
+  UINT8    EnableDigitalThermalSensor;              ///< Offset 8       Digital Thermal Sensor Enable
+  UINT8    DigitalThermalSensorSmiFunction;         ///< Offset 9       DTS SMI Function Call
+  //
+  // CPU Identification Registers:
+  //
+  UINT8    ApicEnable;                              ///< Offset 10      APIC Enabled by SBIOS (APIC Enabled = 1)
+  UINT8    ThreadCount;                             ///< Offset 11      Number of Enabled Threads
+  //
+  // PCIe Hot Plug
+  //
+  UINT8    PcieOSCControl;                          ///< Offset 12      PCIE OSC Control
+  UINT8    NativePCIESupport;                       ///< Offset 13      Native PCIE Setup Value
+  //
+  // Global Variables
+  //
+  UINT8    DisplaySupportFlag;                      ///< Offset 14      _DOS Display Support Flag.
+  UINT8    InterruptModeFlag;                       ///< Offset 15      Global IOAPIC/8259 Interrupt Mode Flag.
+  UINT8    L01Counter;                              ///< Offset 16      Global L01 Counter.
+  UINT8    LtrEnable[24];                           ///< Offset 17      Latency Tolerance Reporting Enable
+                                                    ///< Offset 18      Latency Tolerance Reporting Enable
+                                                    ///< Offset 19      Latency Tolerance Reporting Enable
+                                                    ///< Offset 20      Latency Tolerance Reporting Enable
+                                                    ///< Offset 21      Latency Tolerance Reporting Enable
+                                                    ///< Offset 22      Latency Tolerance Reporting Enable
+                                                    ///< Offset 23      Latency Tolerance Reporting Enable
+                                                    ///< Offset 24      Latency Tolerance Reporting Enable
+                                                    ///< Offset 25      Latency Tolerance Reporting Enable
+                                                    ///< Offset 26      Latency Tolerance Reporting Enable
+                                                    ///< Offset 27      Latency Tolerance Reporting Enable
+                                                    ///< Offset 28      Latency Tolerance Reporting Enable
+                                                    ///< Offset 29      Latency Tolerance Reporting Enable
+                                                    ///< Offset 30      Latency Tolerance Reporting Enable
+                                                    ///< Offset 31      Latency Tolerance Reporting Enable
+                                                    ///< Offset 32      Latency Tolerance Reporting Enable
+                                                    ///< Offset 33      Latency Tolerance Reporting Enable
+                                                    ///< Offset 34      Latency Tolerance Reporting Enable
+                                                    ///< Offset 35      Latency Tolerance Reporting Enable
+                                                    ///< Offset 36      Latency Tolerance Reporting Enable
+                                                    ///< Offset 37      Latency Tolerance Reporting Enable
+                                                    ///< Offset 38      Latency Tolerance Reporting Enable
+                                                    ///< Offset 39      Latency Tolerance Reporting Enable
+                                                    ///< Offset 40      Latency Tolerance Reporting Enable
+  UINT8    ObffEnable[24];                          ///< Offset 41      Optimized Buffer Flush and Fill
+                                                    ///< Offset 42      Optimized Buffer Flush and Fill
+                                                    ///< Offset 43      Optimized Buffer Flush and Fill
+                                                    ///< Offset 44      Optimized Buffer Flush and Fill
+                                                    ///< Offset 45      Optimized Buffer Flush and Fill
+                                                    ///< Offset 46      Optimized Buffer Flush and Fill
+                                                    ///< Offset 47      Optimized Buffer Flush and Fill
+                                                    ///< Offset 48      Optimized Buffer Flush and Fill
+                                                    ///< Offset 49      Optimized Buffer Flush and Fill
+                                                    ///< Offset 50      Optimized Buffer Flush and Fill
+                                                    ///< Offset 51      Optimized Buffer Flush and Fill
+                                                    ///< Offset 52      Optimized Buffer Flush and Fill
+                                                    ///< Offset 53      Optimized Buffer Flush and Fill
+                                                    ///< Offset 54      Optimized Buffer Flush and Fill
+                                                    ///< Offset 55      Optimized Buffer Flush and Fill
+                                                    ///< Offset 56      Optimized Buffer Flush and Fill
+                                                    ///< Offset 57      Optimized Buffer Flush and Fill
+                                                    ///< Offset 58      Optimized Buffer Flush and Fill
+                                                    ///< Offset 59      Optimized Buffer Flush and Fill
+                                                    ///< Offset 60      Optimized Buffer Flush and Fill
+                                                    ///< Offset 61      Optimized Buffer Flush and Fill
+                                                    ///< Offset 62      Optimized Buffer Flush and Fill
+                                                    ///< Offset 63      Optimized Buffer Flush and Fill
+                                                    ///< Offset 64      Optimized Buffer Flush and Fill
+  UINT8    Rtd3Support;                             ///< Offset 65      Runtime D3 support.
+  UINT8    LowPowerS0Idle;                          ///< Offset 66      Low Power S0 Idle Enable
+  UINT8    VirtualGpioButtonSxBitmask;              ///< Offset 67      Virtual GPIO button Notify Sleep State Change
+  UINT8    PstateCapping;                           ///< Offset 68      P-state Capping
+  UINT8    Ps2MouseEnable;                          ///< Offset 69      Ps2 Mouse Enable
+  UINT8    Ps2KbMsEnable;                           ///< Offset 70      Ps2 Keyboard and Mouse Enable
+  //
+  // Driver Mode
+  //
+  UINT32   GpioIrqRoute;                            ///< Offset 71      GPIO IRQ
+  UINT8    PL1LimitCS;                              ///< Offset 75      set PL1 limit when entering CS
+  UINT16   PL1LimitCSValue;                         ///< Offset 76      PL1 limit value
+  UINT8    TenSecondPowerButtonEnable;              ///< Offset 78      10sec Power button support
+  UINT8    PciDelayOptimizationEcr;                 ///< Offset 79      Pci Delay Optimization Ecr
+  UINT8    TbtSupport;                              ///< Offset 80      Thunderbolt(TM) support
+  UINT8    TbtNativeOsHotPlug;                      ///< Offset 81      TbtNativeOsHotPlug
+  UINT8    TbtSelector;                             ///< Offset 82      Thunderbolt(TM) Root port selector
+  UINT8    TbtSelector1;                            ///< Offset 83      Thunderbolt(TM) Root port selector
+} EFI_GLOBAL_NVS_AREA;
+
+#pragma pack(pop)
+#endif
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Include/IoExpander.h b/Platform/Intel/ClevoOpenBoardPkg/Include/IoExpander.h
new file mode 100644
index 0000000000..3a0c628319
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Include/IoExpander.h
@@ -0,0 +1,73 @@
+/** @file
+  GPIO definition table for N1xxWU
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _IO_EXPANDER_H_
+#define _IO_EXPANDER_H_
+
+typedef struct {
+  UINT32 IoExpanderNumber   : 1;  // IO Expander Number (0/1)
+  UINT32 GpioPinNumber      : 5;  // GPIO Pin Number (0 to 23)
+  UINT32 GpioDirection      : 1;  // GPIO Pin Direction (Input/Output)
+  UINT32 GpioLevel          : 1;  // GPIO Pin Output Level (High/Low)
+  UINT32 GpioInversion     : 1;  // GPIO Pin Inversion (Enabled/Disabled)
+  UINT32 Reserved           : 23; // Reserved
+} IO_EXPANDER_GPIO_CONFIG;
+
+//SKL PCH LP GPIO Expander Number
+#define IO_EXPANDER_0            0
+#define IO_EXPANDER_1            1
+
+//SKL PCH LP GPIO Pin Mapping
+#define IO_EXPANDER_GPIO_0        0   // P00
+#define IO_EXPANDER_GPIO_1        1   // P01
+#define IO_EXPANDER_GPIO_2        2   // P02
+#define IO_EXPANDER_GPIO_3        3   // P03
+#define IO_EXPANDER_GPIO_4        4   // P04
+#define IO_EXPANDER_GPIO_5        5   // P05
+#define IO_EXPANDER_GPIO_6        6   // P06
+#define IO_EXPANDER_GPIO_7        7   // P07
+#define IO_EXPANDER_GPIO_8        8   // P10
+#define IO_EXPANDER_GPIO_9        9   // P11
+#define IO_EXPANDER_GPIO_10       10  // P12
+#define IO_EXPANDER_GPIO_11       11  // P13
+#define IO_EXPANDER_GPIO_12       12  // P14
+#define IO_EXPANDER_GPIO_13       13  // P15
+#define IO_EXPANDER_GPIO_14       14  // P16
+#define IO_EXPANDER_GPIO_15       15  // P17
+#define IO_EXPANDER_GPIO_16       16  // P20
+#define IO_EXPANDER_GPIO_17       17  // P21
+#define IO_EXPANDER_GPIO_18       18  // P22
+#define IO_EXPANDER_GPIO_19       19  // P23
+#define IO_EXPANDER_GPIO_20       20  // P24
+#define IO_EXPANDER_GPIO_21       21  // P25
+#define IO_EXPANDER_GPIO_22       22  // P26
+#define IO_EXPANDER_GPIO_23       23  // P27
+
+//SKL PCH LP GPIO Expander GPIO Direction
+#define IO_EXPANDER_GPIO_OUTPUT   0
+#define IO_EXPANDER_GPIO_INPUT    1
+
+//SKL PCH LP GPIO Expaner GPIO Output Level
+#define IO_EXPANDER_GPO_LEVEL_LOW    0
+#define IO_EXPANDER_GPO_LEVEL_HIGH   1
+
+//SKL PCH LP GPIO Expaner GPIO Inversion Status
+#define IO_EXPANDER_GPI_INV_DISABLED  0
+#define IO_EXPANDER_GPI_INV_ENABLED   1
+#define IO_EXPANDER_GPIO_RESERVED     0x00
+
+//GPIO Table Terminator
+#define END_OF_GPIO_TABLE 0xFFFFFFFF
+
+#endif
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Include/Library/GpioExpanderLib.h b/Platform/Intel/ClevoOpenBoardPkg/Include/Library/GpioExpanderLib.h
new file mode 100644
index 0000000000..3395d631ce
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Include/Library/GpioExpanderLib.h
@@ -0,0 +1,128 @@
+/** @file
+  Support for IO expander TCA6424.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _GPIO_EXPANDER_LIB_H_
+#define _GPIO_EXPANDER_LIB_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+#include <Library/IoLib.h>
+#include <Library/UefiLib.h>
+#include <PchAccess.h>
+#include <Library/PchSerialIoLib.h>
+
+/**
+  Set the Direction value for the given Expander Gpio pin.
+
+  This function is to Set the direction value for the GPIO
+  Pin within the giving Expander.
+
+  @param[in]  Expander    Expander Value with in the Contoller
+  @param[in]  Pin         Pin with in the Expnader Value
+  @param[in]  Value       none
+**/
+VOID
+GpioExpSetDirection (
+  IN UINT8 Expander,
+  IN UINT8 Pin,
+  IN UINT8 Direction
+  );
+/**
+  Set the input value for the given Expander Gpio pin.
+
+  This function is to get the input value for the GPIO
+  Pin within the giving Expander.
+
+  @param[in]  Expander    Expander Value with in the Contoller
+  @param[in]  Pin         Pin with in the Expnader Value
+  @param[in]  Value       none
+
+**/
+VOID
+GpioExpSetPolarity  (
+  IN UINT8 Expander,
+  IN UINT8 Pin,
+  IN UINT8 Polarity
+  );
+/**
+  Set the Output value for the given Expander Gpio pin.
+
+  This function is to Set the Output value for the GPIO
+  Pin within the giving Expander.
+
+  @param[in]  Expander    Expander Value with in the Contoller
+  @param[in]  Pin         Pin with in the Expnader Value
+  @param[in]  Value       none
+
+**/
+VOID
+GpioExpSetOutput    (
+  IN UINT8 Expander,
+  IN UINT8 Pin,
+  IN UINT8 Value
+  );
+/**
+  Returns the data from register value giving in the input.
+
+  This function is to get the data from the Expander
+  Registers by following the I2C Protocol communication
+
+
+  @param[in]  Bar0       Bar address of the SerialIo Controller
+  @param[in]  Address    Expander Value with in the Contoller
+  @param[in]  Register   Address of Input/Output/Configure/Polarity
+                         registers with in the Expander
+
+  @retval     UINT8      Value returned from the register
+**/
+UINT8
+GpioExpGetInput     (
+  IN UINT8 Expander,
+  IN UINT8 Pin
+  );
+
+/**
+  Configures all registers of a single IO Expander in one go.
+
+  @param[in]  Expander    Expander number (0/1)
+  @param[in]  Direction   Bit-encoded direction values. BIT0 is for pin0, etc. 0=output, 1=input
+  @param[in]  Polarity    Bit-encoded input inversion values. BIT0 is for pin0, etc. 0=normal, 1=inversion
+  @param[in]  Output      Bit-encoded output state, ignores polarity, only applicable if direction=INPUT. BIT0 is for pin0, etc. 0=low, 1=high
+
+**/
+VOID
+GpioExpBulkConfig (
+  IN UINT8  Expander,
+  IN UINT32 Direction,
+  IN UINT32 Polarity,
+  IN UINT32 Output
+  );
+
+/**
+  Returns the Controller on which GPIO expander is present.
+
+  This function returns the Controller value
+
+  @param[out] Controller              Pointer to a Controller value on
+                                      which I2C expander is configured.
+
+  @retval     EFI_SUCCESS              non.
+**/
+EFI_STATUS
+GpioExpGetController (
+  OUT UINT8 *Controller
+  );
+
+#endif
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Include/Library/I2cAccessLib.h b/Platform/Intel/ClevoOpenBoardPkg/Include/Library/I2cAccessLib.h
new file mode 100644
index 0000000000..6dd91ef7a8
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Include/Library/I2cAccessLib.h
@@ -0,0 +1,39 @@
+/** @file
+  Support for IO expander TCA6424.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _I2C_ACCESS_LIB_H_
+#define _I2C_ACCESS_LIB_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+#include <Library/IoLib.h>
+#include <Library/UefiLib.h>
+#include <PchAccess.h>
+#include <Library/PchSerialIoLib.h>
+
+#define WAIT_1_SECOND            1600000000 //1.6 * 10^9
+
+EFI_STATUS
+I2cWriteRead (
+  IN UINTN  MmioBase,
+  IN UINT8  SlaveAddress,
+  IN UINT8  WriteLength,
+  IN UINT8  *WriteBuffer,
+  IN UINT8  ReadLength,
+  IN UINT8  *ReadBuffer,
+  IN UINT64  TimeBudget
+  );
+
+#endif
\ No newline at end of file
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Include/PchHsioPtssTables.h b/Platform/Intel/ClevoOpenBoardPkg/Include/PchHsioPtssTables.h
new file mode 100644
index 0000000000..412211ea2c
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Include/PchHsioPtssTables.h
@@ -0,0 +1,57 @@
+/** @file*
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PCH_HSIO_PTSSTABLES_H_
+#define PCH_HSIO_PTSSTABLES_H_
+
+#include <PchAccess.h>
+
+///
+/// SATA PTSS Topology Types
+///
+typedef enum {
+  PchSataTopoUnknown = 0x00,
+  PchSataTopoIsata,
+  PchSataTopoDirectConnect,
+  PchSataTopoFlex,
+  PchSataTopoM2
+} PCH_SATA_TOPOLOGY;
+
+///
+/// PCIe PTSS Topology Types
+///
+typedef enum {
+  PchPcieTopoUnknown = 0x00,
+  PchPcieTopox1,
+  PchPcieTopox4,
+  PchPcieTopoSataE,
+  PchPcieTopoM2
+} PCH_PCIE_TOPOLOGY;
+
+///
+/// The PCH_SBI_PTSS_HSIO_TABLE block describes HSIO PTSS settings for PCH.
+///
+typedef struct {
+  UINT8       LaneNum;
+  UINT8       PhyMode;
+  UINT16      Offset;
+  UINT32      Value;
+  UINT32      BitMask;
+} PCH_SBI_PTSS_HSIO_TABLE;
+
+typedef struct {
+  PCH_SBI_PTSS_HSIO_TABLE   PtssTable;
+  UINT16                    Topology;
+} HSIO_PTSS_TABLES;
+
+#endif // PCH_HSIO_PTSSTABLES_H_
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Include/Protocol/GlobalNvsArea.h b/Platform/Intel/ClevoOpenBoardPkg/Include/Protocol/GlobalNvsArea.h
new file mode 100644
index 0000000000..5f72bcf1b9
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Include/Protocol/GlobalNvsArea.h
@@ -0,0 +1,53 @@
+/** @file
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _GLOBAL_NVS_AREA_H_
+#define _GLOBAL_NVS_AREA_H_
+
+//
+// Includes
+//
+#define GLOBAL_NVS_DEVICE_ENABLE 1
+#define GLOBAL_NVS_DEVICE_DISABLE 0
+
+//
+// Forward reference for pure ANSI compatibility
+//
+
+typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL EFI_GLOBAL_NVS_AREA_PROTOCOL;
+
+//
+// Global NVS Area Protocol GUID
+//
+#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \
+{ 0x74e1e48, 0x8132, 0x47a1, 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc }
+
+#define GLOBAL_NVS_AREA_REVISION       16
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid;
+
+//
+// Global NVS Area definition
+//
+#include <Acpi/GlobalNvsAreaDef.h>
+
+//
+// Global NVS Area Protocol
+//
+typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL {
+  EFI_GLOBAL_NVS_AREA     *Area;
+} EFI_GLOBAL_NVS_AREA_PROTOCOL;
+
+#endif
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Include/SioRegs.h b/Platform/Intel/ClevoOpenBoardPkg/Include/SioRegs.h
new file mode 100644
index 0000000000..f9aa5d4f18
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Include/SioRegs.h
@@ -0,0 +1,163 @@
+/** @file
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SIO_REG_H_
+#define _SIO_REG_H_
+
+#define REG_LOGICAL_DEVICE        0x07
+#define ACTIVATE                  0x30
+
+#define BASE_ADDRESS_HIGH0        0x60
+#define BASE_ADDRESS_LOW0         0x61
+#define BASE_ADDRESS_HIGH1        0x62
+#define BASE_ADDRESS_LOW1         0x63
+#define BASE_ADDRESS_HIGH2        0x64
+#define BASE_ADDRESS_LOW2         0x65
+#define BASE_ADDRESS_HIGH3        0x66
+#define BASE_ADDRESS_LOW3         0x67
+#define PRIMARY_INTERRUPT_SELECT  0x70
+#define WAKEUP_ON_IRQ_EN          0x70
+#define INTERRUPT_TYPE            0x71
+#define DMA_CHANNEL_SELECT0       0x74
+#define DMA_CHANNEL_SELECT1       0x75
+
+
+
+//
+//Port address for PILOT - III
+//
+#define PILOTIII_CHIP_ID         0x03
+#define PILOTIII_SIO_INDEX_PORT  0x04E
+#define PILOTIII_SIO_DATA_PORT   (PILOTIII_SIO_INDEX_PORT+1)
+
+#define PILOTIII_UNLOCK      0x5A
+#define PILOTIII_LOCK        0xA5
+
+//
+// logical device in PILOT-III
+//
+#define PILOTIII_SIO_PSR     0x00
+#define PILOTIII_SIO_COM2    0x01
+#define PILOTIII_SIO_COM1    0x02
+#define PILOTIII_SIO_SWCP    0x03
+#define PILOTIII_SIO_GPIO    0x04
+#define PILOTIII_SIO_WDT     0x05
+#define PILOTIII_SIO_KCS3    0x08
+#define PILOTIII_SIO_KCS4    0x09
+#define PILOTIII_SIO_KCS5    0x0A
+#define PILOTIII_SIO_BT      0x0B
+#define PILOTIII_SIO_SMIC    0x0C
+#define PILOTIII_SIO_MAILBOX 0x0D
+#define PILOTIII_SIO_RTC     0x0E
+#define PILOTIII_SIO_SPI     0x0F
+#define PILOTIII_SIO_TAP     0x10
+//
+// Regisgers for Pilot-III
+//
+#define PILOTIII_CHIP_ID_REG               0x20
+#define PILOTIII_LOGICAL_DEVICE            REG_LOGICAL_DEVICE
+#define PILOTIII_ACTIVATE                  ACTIVATE
+#define PILOTIII_BASE_ADDRESS_HIGH0        BASE_ADDRESS_HIGH0
+#define PILOTIII_BASE_ADDRESS_LOW0         BASE_ADDRESS_LOW0
+#define PILOTIII_BASE_ADDRESS_HIGH1        BASE_ADDRESS_HIGH1
+#define PILOTIII_BASE_ADDRESS_LOW1         BASE_ADDRESS_LOW1
+#define PILOTIII_PRIMARY_INTERRUPT_SELECT  PRIMARY_INTERRUPT_SELECT
+
+//
+// Port address for PC8374
+//
+#define PC8374_SIO_INDEX_PORT  0x02E
+#define PC8374_SIO_DATA_PORT   (PC8374_SIO_INDEX_PORT+1)
+
+//
+// Logical device in PC8374
+//
+#define PC8374_SIO_FLOPPY  0x00
+#define PC8374_SIO_PARA    0x01
+#define PC8374_SIO_COM2    0x02
+#define PC8374_SIO_COM1    0x03
+#define PC8374_SIO_MOUSE   0x05
+#define PC8374_SIO_KYBD    0x06
+#define PC8374_SIO_GPIO    0x07
+
+//
+// Registers specific for PC8374
+//
+#define PC8374_CLOCK_SELECT  0x2D
+#define PC8374_CLOCK_CONFIG  0x29
+
+//
+// Registers for PC8374
+//
+#define PC8374_LOGICAL_DEVICE            REG_LOGICAL_DEVICE
+#define PC8374_ACTIVATE                  ACTIVATE
+#define PC8374_BASE_ADDRESS_HIGH0        BASE_ADDRESS_HIGH0
+#define PC8374_BASE_ADDRESS_LOW0         BASE_ADDRESS_LOW0
+#define PC8374_PRIMARY_INTERRUPT_SELECT  PRIMARY_INTERRUPT_SELECT
+#define PC8374_DMA_CHANNEL_SELECT        DMA_CHANNEL_SELECT0
+
+#define PC87427_SERVERIO_CNF2           0x22
+
+
+//
+// Pilot III Mailbox Data Register definitions
+//
+#define MBDAT00_OFFSET                  0x00
+#define MBDAT01_OFFSET                  0x01
+#define MBDAT02_OFFSET                  0x02
+#define MBDAT03_OFFSET                  0x03
+#define MBDAT04_OFFSET                  0x04
+#define MBDAT05_OFFSET                  0x05
+#define MBDAT06_OFFSET                  0x06
+#define MBDAT07_OFFSET                  0x07
+#define MBDAT08_OFFSET                  0x08
+#define MBDAT09_OFFSET                  0x09
+#define MBDAT10_OFFSET                  0x0A
+#define MBDAT11_OFFSET                  0x0B
+#define MBDAT12_OFFSET                  0x0C
+#define MBDAT13_OFFSET                  0x0D
+#define MBDAT14_OFFSET                  0x0E
+#define MBDAT15_OFFSET                  0x0F
+#define MBST0_OFFSET                    0x10
+#define MBST1_OFFSET                    0x11
+#define MBBINT_OFFSET                   0x12
+
+//
+// Mailbox Bit definitions...
+//
+#define   MBBINT_MBBIST_BIT               0x80
+// If both are there, use the default one
+//
+#define  W83527_EXIST     BIT2
+#define  PC8374_EXIST     BIT1
+#define  PILOTIII_EXIST   BIT0
+#define  DEFAULT_SIO      PILOTIII_EXIST
+#define  DEFAULT_KDB      PC8374_EXIST
+
+#define IPMI_DEFAULT_SMM_IO_BASE           0xca2
+//
+// For Pilot III
+//
+
+#define PILOTIII_SWC_BASE_ADDRESS          0xA00
+#define PILOTIII_PM1b_EVT_BLK_BASE_ADDRESS 0x0A80
+#define PILOTIII_PM1b_CNT_BLK_BASE_ADDRESS 0x0A84
+#define PILOTIII_GPE1_BLK_BASE_ADDRESS     0x0A86
+#define PILOTIII_KCS3_DATA_BASE_ADDRESS    0x0CA4
+#define PILOTIII_KCS3_CMD_BASE_ADDRESS     0x0CA5
+#define PILOTIII_KCS4_DATA_BASE_ADDRESS    0x0CA2
+#define PILOTIII_KCS4_CMD_BASE_ADDRESS     0x0CA3
+#define PILOTIII_MAILBOX_BASE_ADDRESS      0x0600
+#define PILOTIII_MAILBOX_MASK              0xFFE0
+#define BMC_KCS_BASE_ADDRESS               0x0CA0
+#endif
diff --git a/Platform/Intel/ClevoOpenBoardPkg/Contributions.txt b/Platform/Intel/ClevoOpenBoardPkg/Contributions.txt
new file mode 100644
index 0000000000..f87cbd73c6
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/Contributions.txt
@@ -0,0 +1,218 @@
+
+======================
+= Code Contributions =
+======================
+
+To make a contribution to a TianoCore project, follow these steps.
+1. Create a change description in the format specified below to
+   use in the source control commit log.
+2. Your commit message must include your "Signed-off-by" signature,
+   and "Contributed-under" message.
+3. Your "Contributed-under" message explicitly states that the
+   contribution is made under the terms of the specified
+   contribution agreement.  Your "Contributed-under" message
+   must include the name of contribution agreement and version.
+   For example: Contributed-under: TianoCore Contribution Agreement 1.0
+   The "TianoCore Contribution Agreement" is included below in
+   this document.
+4. Submit your code to the TianoCore project using the process
+   that the project documents on its web page.  If the process is
+   not documented, then submit the code on development email list
+   for the project.
+5. It is preferred that contributions are submitted using the same
+   copyright license as the base project. When that is not possible,
+   then contributions using the following licenses can be accepted:
+   * BSD (2-clause): http://opensource.org/licenses/BSD-2-Clause
+   * BSD (3-clause): http://opensource.org/licenses/BSD-3-Clause
+   * MIT: http://opensource.org/licenses/MIT
+   * Python-2.0: http://opensource.org/licenses/Python-2.0
+   * Zlib: http://opensource.org/licenses/Zlib
+
+   Contributions of code put into the public domain can also be
+   accepted.
+
+   Contributions using other licenses might be accepted, but further
+   review will be required.
+
+=====================================================
+= Change Description / Commit Message / Patch Email =
+=====================================================
+
+Your change description should use the standard format for a
+commit message, and must include your "Signed-off-by" signature
+and the "Contributed-under" message.
+
+== Sample Change Description / Commit Message =
+
+=== Start of sample patch email message ===
+
+From: Contributor Name <contributor@example.com>
+Subject: [PATCH] CodeModule: Brief-single-line-summary
+
+Full-commit-message
+
+Contributed-under: TianoCore Contribution Agreement 1.0
+Signed-off-by: Contributor Name <contributor@example.com>
+---
+
+An extra message for the patch email which will not be considered part
+of the commit message can be added here.
+
+Patch content inline or attached
+
+=== End of sample patch email message ===
+
+=== Notes for sample patch email ===
+
+* The first line of commit message is taken from the email's subject
+  line following [PATCH]. The remaining portion of the commit message
+  is the email's content until the '---' line.
+* git format-patch is one way to create this format
+
+=== Definitions for sample patch email ===
+
+* "CodeModule" is a short idenfier for the affected code.  For
+  example MdePkg, or MdeModulePkg UsbBusDxe.
+* "Brief-single-line-summary" is a short summary of the change.
+* The entire first line should be less than ~70 characters.
+* "Full-commit-message" a verbose multiple line comment describing
+  the change.  Each line should be less than ~70 characters.
+* "Contributed-under" explicitely states that the contribution is
+  made under the terms of the contribtion agreement.  This
+  agreement is included below in this document.
+* "Signed-off-by" is the contributor's signature identifying them
+  by their real/legal name and their email address.
+
+========================================
+= TianoCore Contribution Agreement 1.0 =
+========================================
+
+INTEL CORPORATION ("INTEL") MAKES AVAILABLE SOFTWARE, DOCUMENTATION,
+INFORMATION AND/OR OTHER MATERIALS FOR USE IN THE TIANOCORE OPEN SOURCE
+PROJECT (COLLECTIVELY "CONTENT"). USE OF THE CONTENT IS GOVERNED BY THE
+TERMS AND CONDITIONS OF THIS AGREEMENT BETWEEN YOU AND INTEL AND/OR THE
+TERMS AND CONDITIONS OF LICENSE AGREEMENTS OR NOTICES INDICATED OR
+REFERENCED BELOW. BY USING THE CONTENT, YOU AGREE THAT YOUR USE OF THE
+CONTENT IS GOVERNED BY THIS AGREEMENT AND/OR THE TERMS AND CONDITIONS
+OF ANY APPLICABLE LICENSE AGREEMENTS OR NOTICES INDICATED OR REFERENCED
+BELOW. IF YOU DO NOT AGREE TO THE TERMS AND CONDITIONS OF THIS
+AGREEMENT AND THE TERMS AND CONDITIONS OF ANY APPLICABLE LICENSE
+AGREEMENTS OR NOTICES INDICATED OR REFERENCED BELOW, THEN YOU MAY NOT
+USE THE CONTENT.
+
+Unless otherwise indicated, all Content made available on the TianoCore
+site is provided to you under the terms and conditions of the BSD
+License ("BSD"). A copy of the BSD License is available at
+http://opensource.org/licenses/bsd-license.php
+or when applicable, in the associated License.txt file.
+
+Certain other content may be made available under other licenses as
+indicated in or with such Content. (For example, in a License.txt file.)
+
+You accept and agree to the following terms and conditions for Your
+present and future Contributions submitted to TianoCore site. Except
+for the license granted to Intel hereunder, You reserve all right,
+title, and interest in and to Your Contributions.
+
+== SECTION 1: Definitions ==
+* "You" or "Contributor" shall mean the copyright owner or legal
+  entity authorized by the copyright owner that is making a
+  Contribution hereunder. All other entities that control, are
+  controlled by, or are under common control with that entity are
+  considered to be a single Contributor. For the purposes of this
+  definition, "control" means (i) the power, direct or indirect, to
+  cause the direction or management of such entity, whether by
+  contract or otherwise, or (ii) ownership of fifty percent (50%)
+  or more of the outstanding shares, or (iii) beneficial ownership
+  of such entity.
+* "Contribution" shall mean any original work of authorship,
+  including any modifications or additions to an existing work,
+  that is intentionally submitted by You to the TinaoCore site for
+  inclusion in, or documentation of, any of the Content. For the
+  purposes of this definition, "submitted" means any form of
+  electronic, verbal, or written communication sent to the
+  TianoCore site or its representatives, including but not limited
+  to communication on electronic mailing lists, source code
+  control systems, and issue tracking systems that are managed by,
+  or on behalf of, the TianoCore site for the purpose of
+  discussing and improving the Content, but excluding
+  communication that is conspicuously marked or otherwise
+  designated in writing by You as "Not a Contribution."
+
+== SECTION 2: License for Contributions ==
+* Contributor hereby agrees that redistribution and use of the
+  Contribution in source and binary forms, with or without
+  modification, are permitted provided that the following
+  conditions are met:
+** Redistributions of source code must retain the Contributor's
+   copyright notice, this list of conditions and the following
+   disclaimer.
+** Redistributions in binary form must reproduce the Contributor's
+   copyright notice, this list of conditions and the following
+   disclaimer in the documentation and/or other materials provided
+   with the distribution.
+* Disclaimer. None of the names of Contributor, Intel, or the names
+  of their respective contributors may be used to endorse or
+  promote products derived from this software without specific
+  prior written permission.
+* Contributor grants a license (with the right to sublicense) under
+  claims of Contributor's patents that Contributor can license that
+  are infringed by the Contribution (as delivered by Contributor) to
+  make, use, distribute, sell, offer for sale, and import the
+  Contribution and derivative works thereof solely to the minimum
+  extent necessary for licensee to exercise the granted copyright
+  license; this patent license applies solely to those portions of
+  the Contribution that are unmodified. No hardware per se is
+  licensed.
+* EXCEPT AS EXPRESSLY SET FORTH IN SECTION 3 BELOW, THE
+  CONTRIBUTION IS PROVIDED BY THE CONTRIBUTOR "AS IS" AND ANY
+  EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+  PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+  CONTRIBUTOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THE
+  CONTRIBUTION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+  DAMAGE.
+
+== SECTION 3: Representations ==
+* You represent that You are legally entitled to grant the above
+  license. If your employer(s) has rights to intellectual property
+  that You create that includes Your Contributions, You represent
+  that You have received permission to make Contributions on behalf
+  of that employer, that Your employer has waived such rights for
+  Your Contributions.
+* You represent that each of Your Contributions is Your original
+  creation (see Section 4 for submissions on behalf of others).
+  You represent that Your Contribution submissions include complete
+  details of any third-party license or other restriction
+  (including, but not limited to, related patents and trademarks)
+  of which You are personally aware and which are associated with
+  any part of Your Contributions.
+
+== SECTION 4: Third Party Contributions ==
+* Should You wish to submit work that is not Your original creation,
+  You may submit it to TianoCore site separately from any
+  Contribution, identifying the complete details of its source
+  and of any license or other restriction (including, but not
+  limited to, related patents, trademarks, and license agreements)
+  of which You are personally aware, and conspicuously marking the
+  work as "Submitted on behalf of a third-party: [named here]".
+
+== SECTION 5: Miscellaneous ==
+* Applicable Laws. Any claims arising under or relating to this
+  Agreement shall be governed by the internal substantive laws of
+  the State of Delaware or federal courts located in Delaware,
+  without regard to principles of conflict of laws.
+* Language. This Agreement is in the English language only, which
+  language shall be controlling in all respects, and all versions
+  of this Agreement in any other language shall be for accommodation
+  only and shall not be binding. All communications and notices made
+  or given pursuant to this Agreement, and all documentation and
+  support to be provided, unless otherwise noted, shall be in the
+  English language.
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/License.txt b/Platform/Intel/ClevoOpenBoardPkg/License.txt
new file mode 100644
index 0000000000..7e5d5e5ee4
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/License.txt
@@ -0,0 +1,25 @@
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+* Redistributions of source code must retain the above copyright
+  notice, this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in
+  the documentation and/or other materials provided with the
+  distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
-- 
2.16.2.windows.1



  reply	other threads:[~2019-01-26  1:06 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-26  1:05 [edk2-platforms/devel-MinPlatform][PATCH v3 0/6] Add initial ClevoOpenBoardPkg Michael Kubacki
2019-01-26  1:05 ` Michael Kubacki [this message]
2019-01-26  1:05 ` [edk2-platforms/devel-MinPlatform][PATCH v3 2/6] ClevoOpenBoardPkg/N1xxWU: Add headers Michael Kubacki
2019-01-26  1:05 ` [edk2-platforms/devel-MinPlatform][PATCH v3 3/6] ClevoOpenBoardPkg: Add library instances Michael Kubacki
2019-01-26  1:05 ` [edk2-platforms/devel-MinPlatform][PATCH v3 4/6] ClevoOpenBoardPkg/N1xxWU: " Michael Kubacki
2019-01-26  1:05 ` [edk2-platforms/devel-MinPlatform][PATCH v3 5/6] ClevoOpenBoardPkg: Add modules Michael Kubacki
2019-01-26  1:05 ` [edk2-platforms/devel-MinPlatform][PATCH v3 6/6] ClevoOpenBoardPkg/N1xxWU: Add DSC and build files Michael Kubacki
2019-02-01 12:18 ` [edk2-platforms/devel-MinPlatform][PATCH v3 0/6] Add initial ClevoOpenBoardPkg Gao, Liming

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