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From: Leif Lindholm <leif.lindholm@linaro.org>
To: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: "edk2-devel@lists.01.org" <edk2-devel@lists.01.org>
Subject: Re: [PATCH 2/5] ArmPkg/ArmMmuLib AARCH64: get rid of needless TLB invalidation
Date: Mon, 28 Jan 2019 18:01:02 +0000	[thread overview]
Message-ID: <20190128180102.et36pybogdptwy25@bivouac.eciton.net> (raw)
In-Reply-To: <CAKv+Gu_0S9tCWAdrDNh1-PJ9MoqzP4YUFAhCwhwtYJYFDi--gA@mail.gmail.com>

On Mon, Jan 28, 2019 at 01:29:54PM +0100, Ard Biesheuvel wrote:
> > > > > > > @@ -296,7 +297,8 @@ GetBlockEntryListFromAddress (
> > > > > > >
> > > > > > >          // Fill the BlockEntry with the new TranslationTable
> > > > > > >          ReplaceLiveEntry (BlockEntry,
> > > > > > > -          ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TableAttributes | TT_TYPE_TABLE_ENTRY);
> > > > > > > +          (UINTN)TranslationTable | TableAttributes | TT_TYPE_TABLE_ENTRY,
> > > > > > > +          RegionStart);
> > > > > >
> > > > >
> > > > > /me pages in the data ...
> > > > >
> > > > > > OK, this whole patch took a few times around the loop before I think I
> > > > > > caught on what was happening.
> > > > > >
> > > > > > I think I'm down to the only things confusing me being:
> > > > > > - The name "Address" to refer to something that is always the start
> > > > > >   address of a 4KB-aligned translation region.
> > > > > >   Is this because the function will be usable in other contexts in
> > > > > >   later patches?
> > > > >
> > > > > I could change it to VirtualAddress if you prefer.
> > > > > It is only passed
> > > > > for TLB maintenance which is only needed at page granularity, and the
> > > > > low bits are shifted out anyway.
> > > >
> > > > Yeah, exactly. It would just be nice if the name reflected that. Not
> > > > sure VirtualAddress does. VirtualBase? PageBase?
> > > >
> > >
> > > Well, the argument passed in is called RegionStart, so let's just
> > > stick with that.
> >
> > Sure. With that:
> > Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> >
> 
> Thanks
> 
> GIven the discussion in the other thread regarding shareability
> upgrades of barriers and TLB maintenance instructions when running
> under virt, mind if I fold in the hunk below? (and add a mention to
> the commit log)
> 
> --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S
> +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S
> @@ -35,7 +35,7 @@
>    // flush translations for the target address from the TLBs
>    lsr   x2, x2, #12
>    tlbi  vae\el, x2
> -  dsb   sy
> +  dsb   nsh

So, this one, definitely. MMU is off, shareability is a shady concept
at best, so it's arguably a fix.

>    // re-enable the MMU
>    msr   sctlr_el\el, x8
> @@ -58,7 +58,7 @@ ASM_FUNC(ArmReplaceLiveTranslationEntry)
>    // clean and invalidate first so that we don't clobber
>    // adjacent entries that are dirty in the caches
>    dc    civac, x0
> -  dsb   ish
> +  dsb   nsh

This one I guess is safe because we know we're never going to get
pre-empted or migrated (because interrupts are disabled and we don't
do that sort of thing)?

If that's the rationale:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

/
    Leif

>    EL1_OR_EL2_OR_EL3(x3)
>  1:__replace_entry 1
> 
> The first one reduces the scope of the tlb maintenance of a live entry
> to the current CPU (and when running under virt, the hypervisor will
> upgrade this to inner shareable)
> The second one prevents the cache maintenance from being broadcast
> unnecessarily, and will be upgraded back to ish in the same way when
> running under virt.


  reply	other threads:[~2019-01-28 18:01 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-07  7:14 [PATCH 0/5] memory/MMU hardening for AArch64 Ard Biesheuvel
2019-01-07  7:15 ` [PATCH 1/5] ArmPkg/ArmMmuLib AARCH64: fix out of bounds access Ard Biesheuvel
2019-01-14 12:00   ` Leif Lindholm
2019-01-14 18:48     ` Ard Biesheuvel
2019-01-07  7:15 ` [PATCH 2/5] ArmPkg/ArmMmuLib AARCH64: get rid of needless TLB invalidation Ard Biesheuvel
2019-01-23 15:46   ` Leif Lindholm
2019-01-23 15:55     ` Ard Biesheuvel
2019-01-23 16:12       ` Leif Lindholm
2019-01-23 16:16         ` Ard Biesheuvel
2019-01-23 16:20           ` Leif Lindholm
2019-01-28 12:29             ` Ard Biesheuvel
2019-01-28 18:01               ` Leif Lindholm [this message]
2019-01-29 10:32                 ` Ard Biesheuvel
2019-01-07  7:15 ` [PATCH 3/5] ArmPkg/ArmMmuLib AARCH64: implement support for EFI_MEMORY_RP permissions Ard Biesheuvel
2019-01-14 14:29   ` Leif Lindholm
2019-01-14 14:59     ` Ard Biesheuvel
2019-01-14 15:06       ` Leif Lindholm
2019-01-07  7:15 ` [PATCH 4/5] ArmPkg/ArmMmuLib AARCH64: add support for read-only page tables Ard Biesheuvel
2019-01-07  7:15 ` [PATCH 5/5] ArmPkg/CpuDxe: switch to read-only page tables at EndOfDxe Ard Biesheuvel

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