* [platforms: PATCH v3 0/5] Armada7k8k memory handling update
@ 2019-01-28 9:45 Marcin Wojtas
2019-01-28 9:45 ` [platforms: PATCH v3 1/5] Marvell/Armada7k8k: Refactor reserving memory regions Marcin Wojtas
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: Marcin Wojtas @ 2019-01-28 9:45 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, mw, jsd, jaz, kostap
Hi,
The third version of the patchset moves the new common
header for Marvell SMC ID's to the IndustryStandard directory.
What is more important, now 3 regions (described by new PCDs)
are reserved separately. For that purpose a preparation
patch was added, which extract existing reservation code
into a new subroutine. More details can be found in
the changelog below and the commit messages.
Patches are available in the github:
https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/dram-upstream-r20190128
I'm looking forward to the comments and remarks.
Best regards,
Marcin
Changelog:
v2 -> v3
* 1/5
- New patch - extract memory reservation to a separate routine
* 2/2
- Add new PCDs and reserve 3 regions (ARM-TF, PEI stack, OP-TEE)
separately
- Update commit message accordingly
* 3/5
- Move MvSmc.h to Include/IndustryStandard
* 4,5/5
- Add Leif's RB
v1 -> v2:
* 1/4
- Improve commit log - mention single area size and new PEI stack base
* 2/4 (new patch)
- Add common header for Marvell SMC ID's
* 3/4
- Add function description comment
- Define and use ARMADA7K8K_AP806_INDEX
- Change function argument to EFI_PHYSICAL_ADDRESS
* 4/4
- Move new SMC ID to MvSmc.h
- Include ArmadaSoCDescLib.h directly (instead indirectly via BoardDesc.h)
- Remove ARMADA7K8K_AP806_INDEX macro
Grzegorz Jaszczyk (2):
Marvell/Library: ArmadaSoCDescLib: Add North Bridge description
Marvell/Armada7k8k: Read DRAM settings from ARM-TF
Marcin Wojtas (3):
Marvell/Armada7k8k: Refactor reserving memory regions
Marvell/Armada7k8k: Shift PEI stack base and extend memory reservation
Marvell/Library: Introduce common header for the SMC ID's
Silicon/Marvell/Marvell.dec | 8 +-
Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 16 ++-
Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf | 3 +
Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf | 8 +-
Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h | 25 -----
Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 6 ++
Silicon/Marvell/Include/IndustryStandard/MvSmc.h | 24 +++++
Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 28 +++++
Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h | 8 +-
Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c | 60 ++++-------
Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.c | 107 +++++++++++++-------
Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 34 +++++++
Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 14 +--
13 files changed, 220 insertions(+), 121 deletions(-)
create mode 100644 Silicon/Marvell/Include/IndustryStandard/MvSmc.h
--
2.7.4
^ permalink raw reply [flat|nested] 11+ messages in thread
* [platforms: PATCH v3 1/5] Marvell/Armada7k8k: Refactor reserving memory regions
2019-01-28 9:45 [platforms: PATCH v3 0/5] Armada7k8k memory handling update Marcin Wojtas
@ 2019-01-28 9:45 ` Marcin Wojtas
2019-01-28 9:45 ` [platforms: PATCH v3 2/5] Marvell/Armada7k8k: Shift PEI stack base and extend memory reservation Marcin Wojtas
` (4 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Marcin Wojtas @ 2019-01-28 9:45 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, mw, jsd, jaz, kostap
Extract reserving memory region in the Hob list
into a separate routine. It is a preparation for adding
multiple of such regions in a following patch.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.c | 95 +++++++++++++-------
1 file changed, 61 insertions(+), 34 deletions(-)
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.c
index 53119f4..3e7902f 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.c
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.c
@@ -49,40 +49,31 @@ InitMmu (
Routine Description:
-
+ Remove the reserved region from a System Memory Hob that covers it.
Arguments:
FileHandle - Handle of the file being invoked.
PeiServices - Describes the list of possible PEI Services.
-Returns:
-
- Status - EFI_SUCCESS if the boot mode could be set
-
--*/
-EFI_STATUS
-EFIAPI
-MemoryPeim (
- IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
- IN UINT64 UefiMemorySize
+STATIC
+VOID
+ReserveMemoryRegion (
+ IN EFI_PHYSICAL_ADDRESS ReservedRegionBase,
+ IN UINT32 ReservedRegionSize
)
{
- ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
- UINT64 ResourceLength;
- EFI_PEI_HOB_POINTERS NextHob;
- EFI_PHYSICAL_ADDRESS SecureTop;
+ EFI_PHYSICAL_ADDRESS ReservedRegionTop;
EFI_PHYSICAL_ADDRESS ResourceTop;
+ EFI_PEI_HOB_POINTERS NextHob;
+ UINT64 ResourceLength;
- // Get Virtual Memory Map from the Platform Library
- ArmPlatformGetVirtualMemoryMap (&MemoryTable);
-
- SecureTop = (EFI_PHYSICAL_ADDRESS)FixedPcdGet64 (PcdSecureRegionBase) +
- FixedPcdGet32 (PcdSecureRegionSize);
+ ReservedRegionTop = ReservedRegionBase + ReservedRegionSize;
//
- // Search for System Memory Hob that covers the secure firmware,
+ // Search for System Memory Hob that covers the reserved region,
// and punch a hole in it
//
for (NextHob.Raw = GetHobList ();
@@ -91,31 +82,32 @@ MemoryPeim (
NextHob.Raw)) {
if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
- (FixedPcdGet64 (PcdSecureRegionBase) >= NextHob.ResourceDescriptor->PhysicalStart) &&
- (SecureTop <= NextHob.ResourceDescriptor->PhysicalStart +
+ (ReservedRegionBase >= NextHob.ResourceDescriptor->PhysicalStart) &&
+ (ReservedRegionTop <= NextHob.ResourceDescriptor->PhysicalStart +
NextHob.ResourceDescriptor->ResourceLength))
{
ResourceAttributes = NextHob.ResourceDescriptor->ResourceAttribute;
ResourceLength = NextHob.ResourceDescriptor->ResourceLength;
ResourceTop = NextHob.ResourceDescriptor->PhysicalStart + ResourceLength;
- if (FixedPcdGet64 (PcdSecureRegionBase) == NextHob.ResourceDescriptor->PhysicalStart) {
+ if (ReservedRegionBase == NextHob.ResourceDescriptor->PhysicalStart) {
//
// This region starts right at the start of the reserved region, so we
// can simply move its start pointer and reduce its length by the same
// value
//
- NextHob.ResourceDescriptor->PhysicalStart += FixedPcdGet32 (PcdSecureRegionSize);
- NextHob.ResourceDescriptor->ResourceLength -= FixedPcdGet32 (PcdSecureRegionSize);
+ NextHob.ResourceDescriptor->PhysicalStart += ReservedRegionSize;
+ NextHob.ResourceDescriptor->ResourceLength -= ReservedRegionSize;
} else if ((NextHob.ResourceDescriptor->PhysicalStart +
- NextHob.ResourceDescriptor->ResourceLength) == SecureTop) {
+ NextHob.ResourceDescriptor->ResourceLength) ==
+ ReservedRegionTop) {
//
// This region ends right at the end of the reserved region, so we
// can simply reduce its length by the size of the region.
//
- NextHob.ResourceDescriptor->ResourceLength -= FixedPcdGet32 (PcdSecureRegionSize);
+ NextHob.ResourceDescriptor->ResourceLength -= ReservedRegionSize;
} else {
//
@@ -123,28 +115,63 @@ MemoryPeim (
// each one touching the reserved region at either end, but not covering
// it.
//
- NextHob.ResourceDescriptor->ResourceLength = FixedPcdGet64 (PcdSecureRegionBase) -
- NextHob.ResourceDescriptor->PhysicalStart;
+ NextHob.ResourceDescriptor->ResourceLength =
+ ReservedRegionBase - NextHob.ResourceDescriptor->PhysicalStart;
// Create the System Memory HOB for the remaining region (top of the FD)
BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,
ResourceAttributes,
- SecureTop,
- ResourceTop - SecureTop);
+ ReservedRegionTop,
+ ResourceTop - ReservedRegionTop);
}
//
- // Reserve the memory space occupied by the secure firmware
+ // Reserve the memory space.
//
BuildResourceDescriptorHob (EFI_RESOURCE_MEMORY_RESERVED,
0,
- FixedPcdGet64 (PcdSecureRegionBase),
- FixedPcdGet32 (PcdSecureRegionSize));
+ ReservedRegionBase,
+ ReservedRegionSize);
break;
}
NextHob.Raw = GET_NEXT_HOB (NextHob);
}
+}
+
+/*++
+
+Routine Description:
+
+
+
+Arguments:
+
+ FileHandle - Handle of the file being invoked.
+ PeiServices - Describes the list of possible PEI Services.
+
+Returns:
+
+ Status - EFI_SUCCESS if the boot mode could be set
+
+--*/
+EFI_STATUS
+EFIAPI
+MemoryPeim (
+ IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
+ IN UINT64 UefiMemorySize
+ )
+{
+ ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
+
+ // Get Virtual Memory Map from the Platform Library
+ ArmPlatformGetVirtualMemoryMap (&MemoryTable);
+
+ // Reserve memory region for secure firmware
+ ReserveMemoryRegion (
+ (EFI_PHYSICAL_ADDRESS)FixedPcdGet64 (PcdSecureRegionBase),
+ FixedPcdGet32 (PcdSecureRegionSize)
+ );
// Build Memory Allocation Hob
InitMmu (MemoryTable);
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [platforms: PATCH v3 2/5] Marvell/Armada7k8k: Shift PEI stack base and extend memory reservation
2019-01-28 9:45 [platforms: PATCH v3 0/5] Armada7k8k memory handling update Marcin Wojtas
2019-01-28 9:45 ` [platforms: PATCH v3 1/5] Marvell/Armada7k8k: Refactor reserving memory regions Marcin Wojtas
@ 2019-01-28 9:45 ` Marcin Wojtas
2019-01-28 9:45 ` [platforms: PATCH v3 3/5] Marvell/Library: Introduce common header for the SMC ID's Marcin Wojtas
` (3 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Marcin Wojtas @ 2019-01-28 9:45 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, mw, jsd, jaz, kostap
Recent changes in the ARM-TF configure its runtime serices region
as protected, hence the hitherto PEI stack base address (0x41F0000)
violated it. Additional region needs to also be reserved to cover
OP-TEE
In order to fix this, add more regions which are non-accessible
by the OS to cover:
* the ARM-TF (0x4000000 - 0x4200000)
* OP-TEE (0x4400000 - 0x5400000)
* additional reserved region (0x4200000 - 0x4400000)
Describe regions with the new PCDs and set the PEI stack base address
in the latter (0x43F0000).
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Marvell.dec | 8 ++++++--
Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 16 ++++++++++++----
Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf | 8 ++++++--
Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.c | 18 +++++++++++++++---
4 files changed, 39 insertions(+), 11 deletions(-)
diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec
index c34d783..c927078 100644
--- a/Silicon/Marvell/Marvell.dec
+++ b/Silicon/Marvell/Marvell.dec
@@ -211,8 +211,12 @@
# normal world. These PCDs describe such a region, which will be converted
# to 'reserved' memory before DXE is entered.
#
- gMarvellTokenSpaceGuid.PcdSecureRegionBase|0x0|UINT64|0x50000000
- gMarvellTokenSpaceGuid.PcdSecureRegionSize|0x0|UINT32|0x50000001
+ gMarvellTokenSpaceGuid.PcdArmTFRegionBase|0x0|UINT64|0x50000000
+ gMarvellTokenSpaceGuid.PcdArmTFRegionSize|0x0|UINT32|0x50000001
+ gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionBase|0x0|UINT64|0x50000002
+ gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionSize|0x0|UINT32|0x50000003
+ gMarvellTokenSpaceGuid.PcdOpTeeRegionBase|0x0|UINT64|0x50000004
+ gMarvellTokenSpaceGuid.PcdOpTeeRegionSize|0x0|UINT32|0x50000005
[Protocols]
gMarvellBoardDescProtocolGuid = { 0xebed8738, 0xd4a6, 0x4001, { 0xa9, 0xc9, 0x52, 0xb0, 0xcb, 0x7d, 0xdb, 0xf9 }}
diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
index eafcd6e..1e2d248 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
@@ -376,12 +376,20 @@
gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|36
- gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x41F0000
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x43F0000
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000
- # Secure region reservation
- gMarvellTokenSpaceGuid.PcdSecureRegionBase|0x4000000
- gMarvellTokenSpaceGuid.PcdSecureRegionSize|0x0200000
+ # ARM-TF region reservation
+ gMarvellTokenSpaceGuid.PcdArmTFRegionBase|0x4000000
+ gMarvellTokenSpaceGuid.PcdArmTFRegionSize|0x200000
+
+ # Additional region reservation (e.g. for PEI stack base)
+ gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionBase|0x4200000
+ gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionSize|0x200000
+
+ # OP-TEE region reservation
+ gMarvellTokenSpaceGuid.PcdOpTeeRegionBase|0x4400000
+ gMarvellTokenSpaceGuid.PcdOpTeeRegionSize|0x1000000
# TRNG
gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf
index 096495d..360de90 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf
@@ -42,5 +42,9 @@
gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
[FixedPcd]
- gMarvellTokenSpaceGuid.PcdSecureRegionBase
- gMarvellTokenSpaceGuid.PcdSecureRegionSize
+ gMarvellTokenSpaceGuid.PcdArmTFRegionBase
+ gMarvellTokenSpaceGuid.PcdArmTFRegionSize
+ gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionBase
+ gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionSize
+ gMarvellTokenSpaceGuid.PcdOpTeeRegionBase
+ gMarvellTokenSpaceGuid.PcdOpTeeRegionSize
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.c
index 3e7902f..571f77e 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.c
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.c
@@ -167,10 +167,22 @@ MemoryPeim (
// Get Virtual Memory Map from the Platform Library
ArmPlatformGetVirtualMemoryMap (&MemoryTable);
- // Reserve memory region for secure firmware
+ // Reserve memory region for ARM-TF
ReserveMemoryRegion (
- (EFI_PHYSICAL_ADDRESS)FixedPcdGet64 (PcdSecureRegionBase),
- FixedPcdGet32 (PcdSecureRegionSize)
+ (EFI_PHYSICAL_ADDRESS)FixedPcdGet64 (PcdArmTFRegionBase),
+ FixedPcdGet32 (PcdArmTFRegionSize)
+ );
+
+ // Reserve additional memory region (e.g. for PEI stack)
+ ReserveMemoryRegion (
+ (EFI_PHYSICAL_ADDRESS)FixedPcdGet64 (PcdAuxiliaryReservedRegionBase),
+ FixedPcdGet32 (PcdAuxiliaryReservedRegionSize)
+ );
+
+ // Reserve memory region for OP-TEE
+ ReserveMemoryRegion (
+ (EFI_PHYSICAL_ADDRESS)FixedPcdGet64 (PcdOpTeeRegionBase),
+ FixedPcdGet32 (PcdOpTeeRegionSize)
);
// Build Memory Allocation Hob
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [platforms: PATCH v3 3/5] Marvell/Library: Introduce common header for the SMC ID's
2019-01-28 9:45 [platforms: PATCH v3 0/5] Armada7k8k memory handling update Marcin Wojtas
2019-01-28 9:45 ` [platforms: PATCH v3 1/5] Marvell/Armada7k8k: Refactor reserving memory regions Marcin Wojtas
2019-01-28 9:45 ` [platforms: PATCH v3 2/5] Marvell/Armada7k8k: Shift PEI stack base and extend memory reservation Marcin Wojtas
@ 2019-01-28 9:45 ` Marcin Wojtas
2019-01-28 9:45 ` [platforms: PATCH v3 4/5] Marvell/Library: ArmadaSoCDescLib: Add North Bridge description Marcin Wojtas
` (2 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Marcin Wojtas @ 2019-01-28 9:45 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, mw, jsd, jaz, kostap
Marvell firmware allows to use SiP services other than
for ComPhy handling. In order to avoid spreading the SMC
ID's definitions across many files, introduce common header
for that purpose.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Include/IndustryStandard/MvSmc.h | 23 ++++++++++++++++++++
Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h | 8 +++----
Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 14 ++++++------
3 files changed, 33 insertions(+), 12 deletions(-)
create mode 100644 Silicon/Marvell/Include/IndustryStandard/MvSmc.h
diff --git a/Silicon/Marvell/Include/IndustryStandard/MvSmc.h b/Silicon/Marvell/Include/IndustryStandard/MvSmc.h
new file mode 100644
index 0000000..2d1542a
--- /dev/null
+++ b/Silicon/Marvell/Include/IndustryStandard/MvSmc.h
@@ -0,0 +1,23 @@
+/**
+*
+* Copyright (C) 2019, Marvell International Ltd. and its affiliates.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __MV_SMC_H__
+#define __MV_SMC_H__
+
+/* Marvell SiP services SMC ID's */
+#define MV_SMC_ID_COMPHY_POWER_ON 0x82000001
+#define MV_SMC_ID_COMPHY_POWER_OFF 0x82000002
+#define MV_SMC_ID_COMPHY_PLL_LOCK 0x82000003
+
+#endif //__MV_SMC_H__
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h b/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h
index d156af6..9fd6602 100644
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h
@@ -35,16 +35,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#ifndef __COMPHY_SIP_SVC_H__
#define __COMPHY_SIP_SVC_H__
+#include <IndustryStandard/MvSmc.h>
+
/*
* All values in this file are defined externally and used
* for the SerDes configuration via SiP services.
*/
-/* Firmware related definitions used for SMC calls */
-#define MV_SIP_COMPHY_POWER_ON 0x82000001
-#define MV_SIP_COMPHY_POWER_OFF 0x82000002
-#define MV_SIP_COMPHY_PLL_LOCK 0x82000003
-
+/* Helper macros for passing ComPhy parameters to the EL3 */
#define COMPHY_FW_MODE_FORMAT(mode) (mode << 12)
#define COMPHY_FW_FORMAT(mode, idx, speeds) \
((mode << 12) | (idx << 8) | (speeds << 2))
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
index 2abb006..4f85676 100755
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
@@ -163,7 +163,7 @@ ComPhySataPowerUp (
ComPhySataMacPowerDown (Desc[ChipId].SoC->AhciBaseAddress);
- Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON,
+ Status = ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON,
ComPhyBase,
Lane,
COMPHY_FW_FORMAT (COMPHY_SATA_MODE,
@@ -175,7 +175,7 @@ ComPhySataPowerUp (
ComPhySataPhyPowerUp (Desc[ChipId].SoC->AhciBaseAddress);
- Status = ComPhySmc (MV_SIP_COMPHY_PLL_LOCK,
+ Status = ComPhySmc (MV_SMC_ID_COMPHY_PLL_LOCK,
ComPhyBase,
Lane,
COMPHY_FW_FORMAT (COMPHY_SATA_MODE,
@@ -234,7 +234,7 @@ ComPhyCp110Init (
case COMPHY_TYPE_PCIE1:
case COMPHY_TYPE_PCIE2:
case COMPHY_TYPE_PCIE3:
- Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON,
+ Status = ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON,
PtrChipCfg->ComPhyBaseAddr,
Lane,
COMPHY_FW_PCIE_FORMAT (PcieWidth,
@@ -269,7 +269,7 @@ ComPhyCp110Init (
break;
case COMPHY_TYPE_USB3_HOST0:
case COMPHY_TYPE_USB3_HOST1:
- Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON,
+ Status = ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON,
PtrChipCfg->ComPhyBaseAddr,
Lane,
COMPHY_FW_MODE_FORMAT (COMPHY_USB3H_MODE));
@@ -278,7 +278,7 @@ ComPhyCp110Init (
case COMPHY_TYPE_SGMII1:
case COMPHY_TYPE_SGMII2:
case COMPHY_TYPE_SGMII3:
- Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON,
+ Status = ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON,
PtrChipCfg->ComPhyBaseAddr,
Lane,
COMPHY_FW_FORMAT (COMPHY_SGMII_MODE,
@@ -286,7 +286,7 @@ ComPhyCp110Init (
PtrComPhyMap->Speed));
break;
case COMPHY_TYPE_SFI:
- Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON,
+ Status = ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON,
PtrChipCfg->ComPhyBaseAddr,
Lane,
COMPHY_FW_FORMAT (COMPHY_SFI_MODE,
@@ -295,7 +295,7 @@ ComPhyCp110Init (
break;
case COMPHY_TYPE_RXAUI0:
case COMPHY_TYPE_RXAUI1:
- Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON,
+ Status = ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON,
PtrChipCfg->ComPhyBaseAddr,
Lane,
COMPHY_FW_MODE_FORMAT (COMPHY_RXAUI_MODE));
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [platforms: PATCH v3 4/5] Marvell/Library: ArmadaSoCDescLib: Add North Bridge description
2019-01-28 9:45 [platforms: PATCH v3 0/5] Armada7k8k memory handling update Marcin Wojtas
` (2 preceding siblings ...)
2019-01-28 9:45 ` [platforms: PATCH v3 3/5] Marvell/Library: Introduce common header for the SMC ID's Marcin Wojtas
@ 2019-01-28 9:45 ` Marcin Wojtas
2019-01-28 9:45 ` [platforms: PATCH v3 5/5] Marvell/Armada7k8k: Read DRAM settings from ARM-TF Marcin Wojtas
2019-01-30 16:47 ` [platforms: PATCH v3 0/5] Armada7k8k memory handling update Leif Lindholm
5 siblings, 0 replies; 11+ messages in thread
From: Marcin Wojtas @ 2019-01-28 9:45 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, mw, jsd, jaz, kostap
From: Grzegorz Jaszczyk <jaz@semihalf.com>
For upcomming patch there is need to get AP806 base, provide required
getter function for it.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 6 ++++
Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 28 ++++++++++++++++
Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 34 ++++++++++++++++++++
3 files changed, 68 insertions(+)
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
index bfc8639..c2d7933 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
@@ -22,9 +22,15 @@
// Common macros
//
#define MV_SOC_CP_BASE(Cp) (0xF2000000 + ((Cp) * 0x2000000))
+#define MV_SOC_AP806_BASE 0xF0000000
#define MV_SOC_AP806_COUNT 1
//
+// Armada7k8k default North Bridge index
+//
+#define ARMADA7K8K_AP806_INDEX 0
+
+//
// Platform description of AHCI controllers
//
#define MV_SOC_AHCI_BASE(Cp) (MV_SOC_CP_BASE (Cp) + 0x540000)
diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
index 26b075a..fc17c3a 100644
--- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
+++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
@@ -20,6 +20,34 @@
#include <Protocol/EmbeddedGpio.h>
//
+// North Bridge description
+//
+
+/**
+
+Routine Description:
+
+ Get base address of the SoC North Bridge.
+
+Arguments:
+
+ ApBase - Base address of the North Bridge.
+ ApIndex - Index of the North Bridge.
+
+Returns:
+
+ EFI_SUCCESS - Proper base address is returned.
+ EFI_INVALID_PARAMETER - The index is out of range.
+
+**/
+EFI_STATUS
+EFIAPI
+ArmadaSoCAp8xxBaseGet (
+ IN OUT EFI_PHYSICAL_ADDRESS *ApBase,
+ IN UINTN ApIndex
+ );
+
+//
// ComPhy SoC description
//
typedef struct {
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
index 5b72c20..584f445 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
@@ -28,6 +28,40 @@
#include "Armada7k8kSoCDescLib.h"
+/**
+
+Routine Description:
+
+ Get base address of the SoC North Bridge.
+
+Arguments:
+
+ ApBase - Base address of the North Bridge.
+ ApIndex - Index of the North Bridge.
+
+Returns:
+
+ EFI_SUCCESS - Proper base address is returned.
+ EFI_INVALID_PARAMETER - The index is out of range.
+
+**/
+EFI_STATUS
+EFIAPI
+ArmadaSoCAp8xxBaseGet (
+ IN OUT EFI_PHYSICAL_ADDRESS *ApBase,
+ IN UINTN ApIndex
+ )
+{
+ if (ApIndex != ARMADA7K8K_AP806_INDEX) {
+ DEBUG ((DEBUG_ERROR, "%a: Only one AP806 in A7K/A8K SoC\n", __FUNCTION__));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *ApBase = MV_SOC_AP806_BASE;
+
+ return EFI_SUCCESS;
+}
+
EFI_STATUS
EFIAPI
ArmadaSoCDescComPhyGet (
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [platforms: PATCH v3 5/5] Marvell/Armada7k8k: Read DRAM settings from ARM-TF
2019-01-28 9:45 [platforms: PATCH v3 0/5] Armada7k8k memory handling update Marcin Wojtas
` (3 preceding siblings ...)
2019-01-28 9:45 ` [platforms: PATCH v3 4/5] Marvell/Library: ArmadaSoCDescLib: Add North Bridge description Marcin Wojtas
@ 2019-01-28 9:45 ` Marcin Wojtas
2019-01-30 16:47 ` [platforms: PATCH v3 0/5] Armada7k8k memory handling update Leif Lindholm
5 siblings, 0 replies; 11+ messages in thread
From: Marcin Wojtas @ 2019-01-28 9:45 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, mw, jsd, jaz, kostap
From: Grzegorz Jaszczyk <jaz@semihalf.com>
The memory controller registers are marked as secure in the latest
ARM-TF for Armada SoCs. It is available however get the DRAM
information via SiP services in the EL3, so use it instead
of accessing the registers directly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf | 3 +
Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h | 25 --------
Silicon/Marvell/Include/IndustryStandard/MvSmc.h | 1 +
Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c | 60 ++++++--------------
4 files changed, 22 insertions(+), 67 deletions(-)
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf
index e888566..0c7f320 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf
@@ -41,12 +41,15 @@
[Packages]
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/Marvell/Marvell.dec
[LibraryClasses]
+ ArmadaSoCDescLib
ArmLib
+ ArmSmcLib
DebugLib
MemoryAllocationLib
MppLib
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h
index cc30e4a..8101cf3 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h
@@ -46,28 +46,3 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
(MmioRead32 (CCU_MC_RCR_REG) & REMAP_SIZE_MASK) + SIZE_1MB
#define DRAM_REMAP_TARGET \
(MmioRead32 (CCU_MC_RTBR_REG) << TARGET_BASE_OFFS)
-
-#define DRAM_CH0_MMAP_LOW_REG(cs) (0xf0020200 + (cs) * 0x8)
-#define DRAM_CS_VALID_ENABLED_MASK 0x1
-#define DRAM_AREA_LENGTH_OFFS 16
-#define DRAM_AREA_LENGTH_MASK (0x1f << DRAM_AREA_LENGTH_OFFS)
-#define DRAM_START_ADDRESS_L_OFFS 23
-#define DRAM_START_ADDRESS_L_MASK (0x1ff << DRAM_START_ADDRESS_L_OFFS)
-#define DRAM_CH0_MMAP_HIGH_REG(cs) (0xf0020204 + (cs) * 0x8)
-#define DRAM_START_ADDR_HTOL_OFFS 32
-
-#define DRAM_MAX_CS_NUM 8
-
-#define DRAM_CS_ENABLED(Cs) \
- (MmioRead32 (DRAM_CH0_MMAP_LOW_REG (Cs)) & DRAM_CS_VALID_ENABLED_MASK)
-#define GET_DRAM_REGION_BASE(Cs) \
- ((UINT64)MmioRead32 (DRAM_CH0_MMAP_HIGH_REG ((Cs))) << \
- DRAM_START_ADDR_HTOL_OFFS) | \
- (MmioRead32 (DRAM_CH0_MMAP_LOW_REG (Cs)) & DRAM_START_ADDRESS_L_MASK);
-#define GET_DRAM_REGION_SIZE_CODE(Cs) \
- (MmioRead32 (DRAM_CH0_MMAP_LOW_REG ((Cs))) & \
- DRAM_AREA_LENGTH_MASK) >> DRAM_AREA_LENGTH_OFFS
-#define DRAM_REGION_SIZE_EVEN(C) (((C) >= 7) && ((C) <= 26))
-#define GET_DRAM_REGION_SIZE_EVEN(C) ((UINT64)1 << ((C) + 16))
-#define DRAM_REGION_SIZE_ODD(C) ((C) <= 4)
-#define GET_DRAM_REGION_SIZE_ODD(C) ((UINT64)0x18000000 << (C))
diff --git a/Silicon/Marvell/Include/IndustryStandard/MvSmc.h b/Silicon/Marvell/Include/IndustryStandard/MvSmc.h
index 2d1542a..0c90f11 100644
--- a/Silicon/Marvell/Include/IndustryStandard/MvSmc.h
+++ b/Silicon/Marvell/Include/IndustryStandard/MvSmc.h
@@ -19,5 +19,6 @@
#define MV_SMC_ID_COMPHY_POWER_ON 0x82000001
#define MV_SMC_ID_COMPHY_POWER_OFF 0x82000002
#define MV_SMC_ID_COMPHY_PLL_LOCK 0x82000003
+#define MV_SMC_ID_DRAM_SIZE 0x82000010
#endif //__MV_SMC_H__
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c
index 2a4f5ad..f7bcf52 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c
@@ -32,8 +32,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
-#include <Base.h>
+#include <Uefi.h>
+
+#include <IndustryStandard/ArmStdSmc.h>
+#include <IndustryStandard/MvSmc.h>
+
+#include <Library/ArmadaSoCDescLib.h>
#include <Library/ArmPlatformLib.h>
+#include <Library/ArmSmcLib.h>
#include <Library/DebugLib.h>
#include <Library/HobLib.h>
#include <Library/IoLib.h>
@@ -57,49 +63,19 @@ GetDramSize (
IN OUT UINT64 *MemSize
)
{
- UINT64 BaseAddr;
- UINT8 RegionCode;
- UINT8 Cs;
-
- *MemSize = 0;
-
- for (Cs = 0; Cs < DRAM_MAX_CS_NUM; Cs++) {
-
- /* Exit loop on first disabled DRAM CS */
- if (!DRAM_CS_ENABLED (Cs)) {
- break;
- }
-
- /*
- * Sanity check for base address of next DRAM block.
- * Only continuous space will be used.
- */
- BaseAddr = GET_DRAM_REGION_BASE (Cs);
- if (BaseAddr != *MemSize) {
- DEBUG ((DEBUG_ERROR,
- "%a: DRAM blocks are not contiguous, limit size to 0x%llx\n",
- __FUNCTION__,
- *MemSize));
- return EFI_SUCCESS;
- }
-
- /* Decode area length for current CS from register value */
- RegionCode = GET_DRAM_REGION_SIZE_CODE (Cs);
-
- if (DRAM_REGION_SIZE_EVEN (RegionCode)) {
- *MemSize += GET_DRAM_REGION_SIZE_EVEN (RegionCode);
- } else if (DRAM_REGION_SIZE_ODD (RegionCode)) {
- *MemSize += GET_DRAM_REGION_SIZE_ODD (RegionCode);
- } else {
- DEBUG ((DEBUG_ERROR,
- "%a: Invalid memory region code (0x%x) for CS#%d\n",
- __FUNCTION__,
- RegionCode,
- Cs));
- return EFI_INVALID_PARAMETER;
- }
+ ARM_SMC_ARGS SmcRegs = {0};
+ EFI_STATUS Status;
+
+ SmcRegs.Arg0 = MV_SMC_ID_DRAM_SIZE;
+ Status = ArmadaSoCAp8xxBaseGet (&SmcRegs.Arg1, 0);
+ if (EFI_ERROR (Status)) {
+ return Status;
}
+ ArmCallSmc (&SmcRegs);
+
+ *MemSize = SmcRegs.Arg0;
+
return EFI_SUCCESS;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [platforms: PATCH v3 0/5] Armada7k8k memory handling update
2019-01-28 9:45 [platforms: PATCH v3 0/5] Armada7k8k memory handling update Marcin Wojtas
` (4 preceding siblings ...)
2019-01-28 9:45 ` [platforms: PATCH v3 5/5] Marvell/Armada7k8k: Read DRAM settings from ARM-TF Marcin Wojtas
@ 2019-01-30 16:47 ` Leif Lindholm
2019-01-31 7:01 ` Marcin Wojtas
5 siblings, 1 reply; 11+ messages in thread
From: Leif Lindholm @ 2019-01-30 16:47 UTC (permalink / raw)
To: Marcin Wojtas; +Cc: edk2-devel, ard.biesheuvel, nadavh, jsd, jaz, kostap
Thanks for the rework.
(We should probably move that broken-out function to ArmPkg at some point.)
For the series:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Pushed as b0bb325f20..0a7d8e7d93.
On Mon, Jan 28, 2019 at 10:45:10AM +0100, Marcin Wojtas wrote:
> Hi,
>
> The third version of the patchset moves the new common
> header for Marvell SMC ID's to the IndustryStandard directory.
> What is more important, now 3 regions (described by new PCDs)
> are reserved separately. For that purpose a preparation
> patch was added, which extract existing reservation code
> into a new subroutine. More details can be found in
> the changelog below and the commit messages.
>
> Patches are available in the github:
> https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/dram-upstream-r20190128
>
> I'm looking forward to the comments and remarks.
>
> Best regards,
> Marcin
>
> Changelog:
> v2 -> v3
> * 1/5
> - New patch - extract memory reservation to a separate routine
>
> * 2/2
> - Add new PCDs and reserve 3 regions (ARM-TF, PEI stack, OP-TEE)
> separately
> - Update commit message accordingly
>
> * 3/5
> - Move MvSmc.h to Include/IndustryStandard
>
> * 4,5/5
> - Add Leif's RB
>
> v1 -> v2:
> * 1/4
> - Improve commit log - mention single area size and new PEI stack base
>
> * 2/4 (new patch)
> - Add common header for Marvell SMC ID's
>
> * 3/4
> - Add function description comment
> - Define and use ARMADA7K8K_AP806_INDEX
> - Change function argument to EFI_PHYSICAL_ADDRESS
>
> * 4/4
> - Move new SMC ID to MvSmc.h
> - Include ArmadaSoCDescLib.h directly (instead indirectly via BoardDesc.h)
> - Remove ARMADA7K8K_AP806_INDEX macro
>
> Grzegorz Jaszczyk (2):
> Marvell/Library: ArmadaSoCDescLib: Add North Bridge description
> Marvell/Armada7k8k: Read DRAM settings from ARM-TF
>
> Marcin Wojtas (3):
> Marvell/Armada7k8k: Refactor reserving memory regions
> Marvell/Armada7k8k: Shift PEI stack base and extend memory reservation
> Marvell/Library: Introduce common header for the SMC ID's
>
> Silicon/Marvell/Marvell.dec | 8 +-
> Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 16 ++-
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf | 3 +
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf | 8 +-
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h | 25 -----
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 6 ++
> Silicon/Marvell/Include/IndustryStandard/MvSmc.h | 24 +++++
> Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 28 +++++
> Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h | 8 +-
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c | 60 ++++-------
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.c | 107 +++++++++++++-------
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 34 +++++++
> Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 14 +--
> 13 files changed, 220 insertions(+), 121 deletions(-)
> create mode 100644 Silicon/Marvell/Include/IndustryStandard/MvSmc.h
>
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [platforms: PATCH v3 0/5] Armada7k8k memory handling update
2019-01-30 16:47 ` [platforms: PATCH v3 0/5] Armada7k8k memory handling update Leif Lindholm
@ 2019-01-31 7:01 ` Marcin Wojtas
2019-01-31 10:27 ` Leif Lindholm
0 siblings, 1 reply; 11+ messages in thread
From: Marcin Wojtas @ 2019-01-31 7:01 UTC (permalink / raw)
To: Leif Lindholm
Cc: edk2-devel-01, Ard Biesheuvel, nadavh, jsd@semihalf.com,
Grzegorz Jaszczyk, Kostya Porotchkin
Hi Leif,
Thanks a lot. While at it - do you think ArmPkg/Include/Library/ArmLib.h
/ ArmPkg/Library/ArmLib/ArmLib.c would be a proper place for it?
Best regards,
Marcin
śr., 30 sty 2019 o 17:47 Leif Lindholm <leif.lindholm@linaro.org>
napisał(a):
> Thanks for the rework.
>
> (We should probably move that broken-out function to ArmPkg at some point.)
>
> For the series:
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
>
> Pushed as b0bb325f20..0a7d8e7d93.
>
> On Mon, Jan 28, 2019 at 10:45:10AM +0100, Marcin Wojtas wrote:
> > Hi,
> >
> > The third version of the patchset moves the new common
> > header for Marvell SMC ID's to the IndustryStandard directory.
> > What is more important, now 3 regions (described by new PCDs)
> > are reserved separately. For that purpose a preparation
> > patch was added, which extract existing reservation code
> > into a new subroutine. More details can be found in
> > the changelog below and the commit messages.
> >
> > Patches are available in the github:
> >
> https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/dram-upstream-r20190128
> >
> > I'm looking forward to the comments and remarks.
> >
> > Best regards,
> > Marcin
> >
> > Changelog:
> > v2 -> v3
> > * 1/5
> > - New patch - extract memory reservation to a separate routine
> >
> > * 2/2
> > - Add new PCDs and reserve 3 regions (ARM-TF, PEI stack, OP-TEE)
> > separately
> > - Update commit message accordingly
> >
> > * 3/5
> > - Move MvSmc.h to Include/IndustryStandard
> >
> > * 4,5/5
> > - Add Leif's RB
> >
> > v1 -> v2:
> > * 1/4
> > - Improve commit log - mention single area size and new PEI stack base
> >
> > * 2/4 (new patch)
> > - Add common header for Marvell SMC ID's
> >
> > * 3/4
> > - Add function description comment
> > - Define and use ARMADA7K8K_AP806_INDEX
> > - Change function argument to EFI_PHYSICAL_ADDRESS
> >
> > * 4/4
> > - Move new SMC ID to MvSmc.h
> > - Include ArmadaSoCDescLib.h directly (instead indirectly via
> BoardDesc.h)
> > - Remove ARMADA7K8K_AP806_INDEX macro
> >
> > Grzegorz Jaszczyk (2):
> > Marvell/Library: ArmadaSoCDescLib: Add North Bridge description
> > Marvell/Armada7k8k: Read DRAM settings from ARM-TF
> >
> > Marcin Wojtas (3):
> > Marvell/Armada7k8k: Refactor reserving memory regions
> > Marvell/Armada7k8k: Shift PEI stack base and extend memory reservation
> > Marvell/Library: Introduce common header for the SMC ID's
> >
> > Silicon/Marvell/Marvell.dec
> | 8 +-
> > Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
> | 16 ++-
> > Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf
> | 3 +
> >
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf
> | 8 +-
> > Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h
> | 25 -----
> >
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
> | 6 ++
> > Silicon/Marvell/Include/IndustryStandard/MvSmc.h
> | 24 +++++
> > Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
> | 28 +++++
> > Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h
> | 8 +-
> > Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c
> | 60 ++++-------
> >
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.c
> | 107 +++++++++++++-------
> >
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
> | 34 +++++++
> > Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
> | 14 +--
> > 13 files changed, 220 insertions(+), 121 deletions(-)
> > create mode 100644 Silicon/Marvell/Include/IndustryStandard/MvSmc.h
> >
> > --
> > 2.7.4
> >
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [platforms: PATCH v3 0/5] Armada7k8k memory handling update
2019-01-31 7:01 ` Marcin Wojtas
@ 2019-01-31 10:27 ` Leif Lindholm
2019-01-31 12:06 ` Marcin Wojtas
0 siblings, 1 reply; 11+ messages in thread
From: Leif Lindholm @ 2019-01-31 10:27 UTC (permalink / raw)
To: Marcin Wojtas
Cc: edk2-devel-01, Ard Biesheuvel, nadavh, jsd@semihalf.com,
Grzegorz Jaszczyk, Kostya Porotchkin
On Thu, Jan 31, 2019 at 08:01:08AM +0100, Marcin Wojtas wrote:
> Hi Leif,
>
> Thanks a lot. While at it - do you think ArmPkg/Include/Library/ArmLib.h
> / ArmPkg/Library/ArmLib/ArmLib.c would be a proper place for it?
As good a place as any. While not ARM-architecture specific, I feel
it's probably ARM-platform specific.
I mean, hopefully we'll some day we'll get a sane reporting mechanism
of Secure-reserved regions by ARM-TF and we can drop this juggling in
Non-secure firmware.
Best Regards,
Leif
> Best regards,
> Marcin
>
> śr., 30 sty 2019 o 17:47 Leif Lindholm <leif.lindholm@linaro.org>
> napisał(a):
>
> > Thanks for the rework.
> >
> > (We should probably move that broken-out function to ArmPkg at some point.)
> >
> > For the series:
> > Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> >
> > Pushed as b0bb325f20..0a7d8e7d93.
> >
> > On Mon, Jan 28, 2019 at 10:45:10AM +0100, Marcin Wojtas wrote:
> > > Hi,
> > >
> > > The third version of the patchset moves the new common
> > > header for Marvell SMC ID's to the IndustryStandard directory.
> > > What is more important, now 3 regions (described by new PCDs)
> > > are reserved separately. For that purpose a preparation
> > > patch was added, which extract existing reservation code
> > > into a new subroutine. More details can be found in
> > > the changelog below and the commit messages.
> > >
> > > Patches are available in the github:
> > >
> > https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/dram-upstream-r20190128
> > >
> > > I'm looking forward to the comments and remarks.
> > >
> > > Best regards,
> > > Marcin
> > >
> > > Changelog:
> > > v2 -> v3
> > > * 1/5
> > > - New patch - extract memory reservation to a separate routine
> > >
> > > * 2/2
> > > - Add new PCDs and reserve 3 regions (ARM-TF, PEI stack, OP-TEE)
> > > separately
> > > - Update commit message accordingly
> > >
> > > * 3/5
> > > - Move MvSmc.h to Include/IndustryStandard
> > >
> > > * 4,5/5
> > > - Add Leif's RB
> > >
> > > v1 -> v2:
> > > * 1/4
> > > - Improve commit log - mention single area size and new PEI stack base
> > >
> > > * 2/4 (new patch)
> > > - Add common header for Marvell SMC ID's
> > >
> > > * 3/4
> > > - Add function description comment
> > > - Define and use ARMADA7K8K_AP806_INDEX
> > > - Change function argument to EFI_PHYSICAL_ADDRESS
> > >
> > > * 4/4
> > > - Move new SMC ID to MvSmc.h
> > > - Include ArmadaSoCDescLib.h directly (instead indirectly via
> > BoardDesc.h)
> > > - Remove ARMADA7K8K_AP806_INDEX macro
> > >
> > > Grzegorz Jaszczyk (2):
> > > Marvell/Library: ArmadaSoCDescLib: Add North Bridge description
> > > Marvell/Armada7k8k: Read DRAM settings from ARM-TF
> > >
> > > Marcin Wojtas (3):
> > > Marvell/Armada7k8k: Refactor reserving memory regions
> > > Marvell/Armada7k8k: Shift PEI stack base and extend memory reservation
> > > Marvell/Library: Introduce common header for the SMC ID's
> > >
> > > Silicon/Marvell/Marvell.dec
> > | 8 +-
> > > Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
> > | 16 ++-
> > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf
> > | 3 +
> > >
> > Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf
> > | 8 +-
> > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h
> > | 25 -----
> > >
> > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
> > | 6 ++
> > > Silicon/Marvell/Include/IndustryStandard/MvSmc.h
> > | 24 +++++
> > > Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
> > | 28 +++++
> > > Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h
> > | 8 +-
> > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c
> > | 60 ++++-------
> > >
> > Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.c
> > | 107 +++++++++++++-------
> > >
> > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
> > | 34 +++++++
> > > Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
> > | 14 +--
> > > 13 files changed, 220 insertions(+), 121 deletions(-)
> > > create mode 100644 Silicon/Marvell/Include/IndustryStandard/MvSmc.h
> > >
> > > --
> > > 2.7.4
> > >
> >
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [platforms: PATCH v3 0/5] Armada7k8k memory handling update
2019-01-31 10:27 ` Leif Lindholm
@ 2019-01-31 12:06 ` Marcin Wojtas
2019-01-31 12:12 ` Leif Lindholm
0 siblings, 1 reply; 11+ messages in thread
From: Marcin Wojtas @ 2019-01-31 12:06 UTC (permalink / raw)
To: Leif Lindholm
Cc: edk2-devel-01, Ard Biesheuvel, nadavh, jsd@semihalf.com,
Grzegorz Jaszczyk, Kostya Porotchkin
czw., 31 sty 2019 o 11:28 Leif Lindholm <leif.lindholm@linaro.org> napisał(a):
>
> On Thu, Jan 31, 2019 at 08:01:08AM +0100, Marcin Wojtas wrote:
> > Hi Leif,
> >
> > Thanks a lot. While at it - do you think ArmPkg/Include/Library/ArmLib.h
> > / ArmPkg/Library/ArmLib/ArmLib.c would be a proper place for it?
>
> As good a place as any. While not ARM-architecture specific, I feel
> it's probably ARM-platform specific.
>
> I mean, hopefully we'll some day we'll get a sane reporting mechanism
> of Secure-reserved regions by ARM-TF and we can drop this juggling in
> Non-secure firmware.
>
Agree on ARM-TF dependency, but the code is IMO pretty generic itself.
In the merged version I also used this routine to cut out a hole in
the HoB for the reason not related to NS region - therefore I think
even MdePkg/Library would be good to go :)
Marcin
> > Best regards,
> > Marcin
> >
> > śr., 30 sty 2019 o 17:47 Leif Lindholm <leif.lindholm@linaro.org>
> > napisał(a):
> >
> > > Thanks for the rework.
> > >
> > > (We should probably move that broken-out function to ArmPkg at some point.)
> > >
> > > For the series:
> > > Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> > >
> > > Pushed as b0bb325f20..0a7d8e7d93.
> > >
> > > On Mon, Jan 28, 2019 at 10:45:10AM +0100, Marcin Wojtas wrote:
> > > > Hi,
> > > >
> > > > The third version of the patchset moves the new common
> > > > header for Marvell SMC ID's to the IndustryStandard directory.
> > > > What is more important, now 3 regions (described by new PCDs)
> > > > are reserved separately. For that purpose a preparation
> > > > patch was added, which extract existing reservation code
> > > > into a new subroutine. More details can be found in
> > > > the changelog below and the commit messages.
> > > >
> > > > Patches are available in the github:
> > > >
> > > https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/dram-upstream-r20190128
> > > >
> > > > I'm looking forward to the comments and remarks.
> > > >
> > > > Best regards,
> > > > Marcin
> > > >
> > > > Changelog:
> > > > v2 -> v3
> > > > * 1/5
> > > > - New patch - extract memory reservation to a separate routine
> > > >
> > > > * 2/2
> > > > - Add new PCDs and reserve 3 regions (ARM-TF, PEI stack, OP-TEE)
> > > > separately
> > > > - Update commit message accordingly
> > > >
> > > > * 3/5
> > > > - Move MvSmc.h to Include/IndustryStandard
> > > >
> > > > * 4,5/5
> > > > - Add Leif's RB
> > > >
> > > > v1 -> v2:
> > > > * 1/4
> > > > - Improve commit log - mention single area size and new PEI stack base
> > > >
> > > > * 2/4 (new patch)
> > > > - Add common header for Marvell SMC ID's
> > > >
> > > > * 3/4
> > > > - Add function description comment
> > > > - Define and use ARMADA7K8K_AP806_INDEX
> > > > - Change function argument to EFI_PHYSICAL_ADDRESS
> > > >
> > > > * 4/4
> > > > - Move new SMC ID to MvSmc.h
> > > > - Include ArmadaSoCDescLib.h directly (instead indirectly via
> > > BoardDesc.h)
> > > > - Remove ARMADA7K8K_AP806_INDEX macro
> > > >
> > > > Grzegorz Jaszczyk (2):
> > > > Marvell/Library: ArmadaSoCDescLib: Add North Bridge description
> > > > Marvell/Armada7k8k: Read DRAM settings from ARM-TF
> > > >
> > > > Marcin Wojtas (3):
> > > > Marvell/Armada7k8k: Refactor reserving memory regions
> > > > Marvell/Armada7k8k: Shift PEI stack base and extend memory reservation
> > > > Marvell/Library: Introduce common header for the SMC ID's
> > > >
> > > > Silicon/Marvell/Marvell.dec
> > > | 8 +-
> > > > Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
> > > | 16 ++-
> > > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf
> > > | 3 +
> > > >
> > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf
> > > | 8 +-
> > > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h
> > > | 25 -----
> > > >
> > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
> > > | 6 ++
> > > > Silicon/Marvell/Include/IndustryStandard/MvSmc.h
> > > | 24 +++++
> > > > Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
> > > | 28 +++++
> > > > Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h
> > > | 8 +-
> > > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c
> > > | 60 ++++-------
> > > >
> > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.c
> > > | 107 +++++++++++++-------
> > > >
> > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
> > > | 34 +++++++
> > > > Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
> > > | 14 +--
> > > > 13 files changed, 220 insertions(+), 121 deletions(-)
> > > > create mode 100644 Silicon/Marvell/Include/IndustryStandard/MvSmc.h
> > > >
> > > > --
> > > > 2.7.4
> > > >
> > >
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [platforms: PATCH v3 0/5] Armada7k8k memory handling update
2019-01-31 12:06 ` Marcin Wojtas
@ 2019-01-31 12:12 ` Leif Lindholm
0 siblings, 0 replies; 11+ messages in thread
From: Leif Lindholm @ 2019-01-31 12:12 UTC (permalink / raw)
To: Marcin Wojtas
Cc: edk2-devel-01, Ard Biesheuvel, nadavh, jsd@semihalf.com,
Grzegorz Jaszczyk, Kostya Porotchkin
On Thu, Jan 31, 2019 at 01:06:15PM +0100, Marcin Wojtas wrote:
> czw., 31 sty 2019 o 11:28 Leif Lindholm <leif.lindholm@linaro.org> napisał(a):
> >
> > On Thu, Jan 31, 2019 at 08:01:08AM +0100, Marcin Wojtas wrote:
> > > Hi Leif,
> > >
> > > Thanks a lot. While at it - do you think ArmPkg/Include/Library/ArmLib.h
> > > / ArmPkg/Library/ArmLib/ArmLib.c would be a proper place for it?
> >
> > As good a place as any. While not ARM-architecture specific, I feel
> > it's probably ARM-platform specific.
> >
> > I mean, hopefully we'll some day we'll get a sane reporting mechanism
> > of Secure-reserved regions by ARM-TF and we can drop this juggling in
> > Non-secure firmware.
>
> Agree on ARM-TF dependency, but the code is IMO pretty generic itself.
> In the merged version I also used this routine to cut out a hole in
> the HoB for the reason not related to NS region - therefore I think
> even MdePkg/Library would be good to go :)
I don't really disagree with you, but that would be something to take
up with MdeModulePkg maintainers.
Also, I'm not seeing an obvious existing library to put it into. Would
it really be worth creating a new one for just this function?
/
Leif
> Marcin
>
> > > Best regards,
> > > Marcin
> > >
> > > śr., 30 sty 2019 o 17:47 Leif Lindholm <leif.lindholm@linaro.org>
> > > napisał(a):
> > >
> > > > Thanks for the rework.
> > > >
> > > > (We should probably move that broken-out function to ArmPkg at some point.)
> > > >
> > > > For the series:
> > > > Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> > > >
> > > > Pushed as b0bb325f20..0a7d8e7d93.
> > > >
> > > > On Mon, Jan 28, 2019 at 10:45:10AM +0100, Marcin Wojtas wrote:
> > > > > Hi,
> > > > >
> > > > > The third version of the patchset moves the new common
> > > > > header for Marvell SMC ID's to the IndustryStandard directory.
> > > > > What is more important, now 3 regions (described by new PCDs)
> > > > > are reserved separately. For that purpose a preparation
> > > > > patch was added, which extract existing reservation code
> > > > > into a new subroutine. More details can be found in
> > > > > the changelog below and the commit messages.
> > > > >
> > > > > Patches are available in the github:
> > > > >
> > > > https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/dram-upstream-r20190128
> > > > >
> > > > > I'm looking forward to the comments and remarks.
> > > > >
> > > > > Best regards,
> > > > > Marcin
> > > > >
> > > > > Changelog:
> > > > > v2 -> v3
> > > > > * 1/5
> > > > > - New patch - extract memory reservation to a separate routine
> > > > >
> > > > > * 2/2
> > > > > - Add new PCDs and reserve 3 regions (ARM-TF, PEI stack, OP-TEE)
> > > > > separately
> > > > > - Update commit message accordingly
> > > > >
> > > > > * 3/5
> > > > > - Move MvSmc.h to Include/IndustryStandard
> > > > >
> > > > > * 4,5/5
> > > > > - Add Leif's RB
> > > > >
> > > > > v1 -> v2:
> > > > > * 1/4
> > > > > - Improve commit log - mention single area size and new PEI stack base
> > > > >
> > > > > * 2/4 (new patch)
> > > > > - Add common header for Marvell SMC ID's
> > > > >
> > > > > * 3/4
> > > > > - Add function description comment
> > > > > - Define and use ARMADA7K8K_AP806_INDEX
> > > > > - Change function argument to EFI_PHYSICAL_ADDRESS
> > > > >
> > > > > * 4/4
> > > > > - Move new SMC ID to MvSmc.h
> > > > > - Include ArmadaSoCDescLib.h directly (instead indirectly via
> > > > BoardDesc.h)
> > > > > - Remove ARMADA7K8K_AP806_INDEX macro
> > > > >
> > > > > Grzegorz Jaszczyk (2):
> > > > > Marvell/Library: ArmadaSoCDescLib: Add North Bridge description
> > > > > Marvell/Armada7k8k: Read DRAM settings from ARM-TF
> > > > >
> > > > > Marcin Wojtas (3):
> > > > > Marvell/Armada7k8k: Refactor reserving memory regions
> > > > > Marvell/Armada7k8k: Shift PEI stack base and extend memory reservation
> > > > > Marvell/Library: Introduce common header for the SMC ID's
> > > > >
> > > > > Silicon/Marvell/Marvell.dec
> > > > | 8 +-
> > > > > Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
> > > > | 16 ++-
> > > > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf
> > > > | 3 +
> > > > >
> > > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf
> > > > | 8 +-
> > > > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h
> > > > | 25 -----
> > > > >
> > > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
> > > > | 6 ++
> > > > > Silicon/Marvell/Include/IndustryStandard/MvSmc.h
> > > > | 24 +++++
> > > > > Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
> > > > | 28 +++++
> > > > > Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h
> > > > | 8 +-
> > > > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c
> > > > | 60 ++++-------
> > > > >
> > > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.c
> > > > | 107 +++++++++++++-------
> > > > >
> > > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
> > > > | 34 +++++++
> > > > > Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
> > > > | 14 +--
> > > > > 13 files changed, 220 insertions(+), 121 deletions(-)
> > > > > create mode 100644 Silicon/Marvell/Include/IndustryStandard/MvSmc.h
> > > > >
> > > > > --
> > > > > 2.7.4
> > > > >
> > > >
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2019-01-31 12:12 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-01-28 9:45 [platforms: PATCH v3 0/5] Armada7k8k memory handling update Marcin Wojtas
2019-01-28 9:45 ` [platforms: PATCH v3 1/5] Marvell/Armada7k8k: Refactor reserving memory regions Marcin Wojtas
2019-01-28 9:45 ` [platforms: PATCH v3 2/5] Marvell/Armada7k8k: Shift PEI stack base and extend memory reservation Marcin Wojtas
2019-01-28 9:45 ` [platforms: PATCH v3 3/5] Marvell/Library: Introduce common header for the SMC ID's Marcin Wojtas
2019-01-28 9:45 ` [platforms: PATCH v3 4/5] Marvell/Library: ArmadaSoCDescLib: Add North Bridge description Marcin Wojtas
2019-01-28 9:45 ` [platforms: PATCH v3 5/5] Marvell/Armada7k8k: Read DRAM settings from ARM-TF Marcin Wojtas
2019-01-30 16:47 ` [platforms: PATCH v3 0/5] Armada7k8k memory handling update Leif Lindholm
2019-01-31 7:01 ` Marcin Wojtas
2019-01-31 10:27 ` Leif Lindholm
2019-01-31 12:06 ` Marcin Wojtas
2019-01-31 12:12 ` Leif Lindholm
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox