From: Michael Kubacki <michael.a.kubacki@intel.com>
To: edk2-devel@lists.01.org
Cc: Hao Wu <hao.a.wu@intel.com>, Liming Gao <liming.gao@intel.com>,
Jiewen Yao <jiewen.yao@intel.com>,
Michael D Kinney <michael.d.kinney@intel.com>
Subject: [edk2-platforms/devel-MinPlatform][PATCH v4 4/7] ClevoOpenBoardPkg/N1xxWU: Add library instances
Date: Wed, 30 Jan 2019 22:11:14 -0800 [thread overview]
Message-ID: <20190131061117.36916-5-michael.a.kubacki@intel.com> (raw)
In-Reply-To: <20190131061117.36916-1-michael.a.kubacki@intel.com>
Based on KabylakeOpenBoardPkg from the following branch:
https://github.com/tianocore/edk2-platforms/tree/devel-MinPlatform
Library instances used for the N1xxWU Clevo board instance.
* BasePlatformHookLib - Performs board-specific initialization of
hardware devices required for CPU access to the serial port.
* DxeBoardAcpiTableLib - Board-specific ACPI table management in DXE.
* DxeMultiBoardAcpiSupportLib - Multi-board ACPI table management in DXE.
* DxeSiliconPolicyUpdateLib - Updates silicon policies in DXE.
* PeiBoardInitPostMemLib - PEI post-memory board-specific initialization.
This library implements board APIs declared in MinPlatformPkg.
* PeiBoardInitPreMemLib - PEI pre-memory board-specific initialization.
This library implements board APIs declared in MinPlatformPkg.
* PeiMultiBoardInitPostMemLib - PEI post-memory multi-board initialization.
This library implements board APIs declared in MinPlatformPkg.
* PeiMultiBoardInitPreMemLib - PEI pre-memory multi-board initialization.
This library implements board APIs declared in MinPlatformPkg.
* PeiSiliconPolicyUpdateLibFsp - Performs FSP silicon policy
initialization.
* SmmBoardAcpiEnableLib - Board-specific ACPI enabling in SMM.
* SmmMultiBoardAcpiSupportLib - Multi-board ACPI support in SMM.
Cc: Hao Wu <hao.a.wu@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com>
---
.../PeiSiliconPolicyUpdateLibFsp.inf | 149 +++++
.../BasePlatformHookLib/BasePlatformHookLib.inf | 57 ++
.../Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf | 53 ++
.../BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf | 54 ++
.../Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf | 53 ++
.../BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf | 54 ++
.../BoardInitLib/PeiBoardInitPostMemLib.inf | 59 ++
.../Library/BoardInitLib/PeiBoardInitPreMemLib.inf | 138 +++++
.../BoardInitLib/PeiMultiBoardInitPostMemLib.inf | 61 ++
.../BoardInitLib/PeiMultiBoardInitPreMemLib.inf | 140 +++++
.../DxeSiliconPolicyUpdateLib.inf | 55 ++
.../PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c | 121 ++++
.../PeiFspMiscUpdUpdateLib.c | 93 +++
.../PeiFspPolicyUpdateLib.c | 192 ++++++
.../PeiPchPolicyUpdate.c | 159 +++++
.../PeiPchPolicyUpdatePreMem.c | 254 ++++++++
.../PeiSaPolicyUpdate.c | 90 +++
.../PeiSaPolicyUpdatePreMem.c | 74 +++
.../BasePlatformHookLib/BasePlatformHookLib.c | 668 +++++++++++++++++++++
.../Library/BoardAcpiLib/DxeBoardAcpiTableLib.c | 42 ++
.../BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c | 49 ++
.../Library/BoardAcpiLib/DxeN1xxWUAcpiTableLib.c | 80 +++
.../Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c | 68 +++
.../BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c | 87 +++
.../Library/BoardAcpiLib/SmmN1xxWUAcpiEnableLib.c | 45 ++
.../Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 174 ++++++
.../N1xxWU/Library/BoardInitLib/N1xxWUGpioTable.c | 375 ++++++++++++
.../Library/BoardInitLib/N1xxWUHdaVerbTables.c | 238 ++++++++
.../Library/BoardInitLib/N1xxWUHsioPtssTables.c | 111 ++++
.../N1xxWU/Library/BoardInitLib/N1xxWUSpdTable.c | 432 +++++++++++++
.../Library/BoardInitLib/PeiBoardInitPostMemLib.c | 45 ++
.../Library/BoardInitLib/PeiBoardInitPreMemLib.c | 111 ++++
.../BoardInitLib/PeiMultiBoardInitPostMemLib.c | 46 ++
.../BoardInitLib/PeiMultiBoardInitPreMemLib.c | 88 +++
.../N1xxWU/Library/BoardInitLib/PeiN1xxWUDetect.c | 72 +++
.../Library/BoardInitLib/PeiN1xxWUInitPostMemLib.c | 215 +++++++
.../Library/BoardInitLib/PeiN1xxWUInitPreMemLib.c | 236 ++++++++
.../DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c | 181 ++++++
.../DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c | 71 +++
.../DxeSiliconPolicyUpdateLib.c | 60 ++
40 files changed, 5350 insertions(+)
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BasePlatformHookLib/BasePlatformHookLib.inf
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BasePlatformHookLib/BasePlatformHookLib.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeN1xxWUAcpiTableLib.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmN1xxWUAcpiEnableLib.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUGpioTable.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUHdaVerbTables.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUHsioPtssTables.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUSpdTable.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardInitPostMemLib.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardInitPreMemLib.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxWUDetect.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxWUInitPostMemLib.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxWUInitPreMemLib.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
new file mode 100644
index 0000000000..bc938a0436
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
@@ -0,0 +1,149 @@
+## @file
+# FSP wrapper silicon policy update library.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SiliconPolicyUpdateLibFsp
+ FILE_GUID = 4E83003B-49A9-459E-AAA6-1CA3C6D04FB2
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SiliconPolicyUpdateLib
+
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+################################################################################
+#
+# Sources Section - list of files that are required for the build to succeed.
+#
+################################################################################
+
+[Sources]
+ PeiFspPolicyUpdateLib.c
+ PeiPchPolicyUpdatePreMem.c
+ PeiPchPolicyUpdate.c
+ PeiSaPolicyUpdatePreMem.c
+ PeiSaPolicyUpdate.c
+ PeiFspMiscUpdUpdateLib.c
+ PcieDeviceTable.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ KabylakeSiliconPkg/SiPkg.dec
+ KabylakeFspBinPkg/KabylakeFspBinPkg.dec
+ ClevoOpenBoardPkg/OpenBoardPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+
+[LibraryClasses.IA32]
+ FspWrapperApiLib
+ OcWdtLib
+ PchResetLib
+ FspWrapperPlatformLib
+ BaseMemoryLib
+ CpuPlatformLib
+ DebugLib
+ HobLib
+ IoLib
+ PcdLib
+ PostCodeLib
+ SmbusLib
+ MmPciLib
+ ConfigBlockLib
+ PeiSaPolicyLib
+ PchGbeLib
+ PchInfoLib
+ PchHsioLib
+ PchPcieRpLib
+ MemoryAllocationLib
+ CpuMailboxLib
+ DebugPrintErrorLevelLib
+ SiPolicyLib
+ PchGbeLib
+ TimerLib
+ GpioLib
+ PeiLib
+
+[Pcd]
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES
+
+ gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1
+ gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2
+ gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size
+ gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size
+ gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
+ gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
+ gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
+ gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
+
+ gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1
+ gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2
+ gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size
+ gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size
+ gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1
+ gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2
+ gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size
+ gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size
+
+ gBoardModuleTokenSpaceGuid.PcdHdaVerbTable
+ gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2
+ gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable
+ gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1
+ gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2
+ gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3
+ gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable
+
+ gBoardModuleTokenSpaceGuid.PcdAudioConnector
+
+ gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid
+
+[Guids]
+ gFspNonVolatileStorageHobGuid ## CONSUMES
+ gTianoLogoGuid ## CONSUMES
+ gEfiMemoryOverwriteControlDataGuid
+
+[Depex]
+ gEdkiiVTdInfoPpiGuid
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BasePlatformHookLib/BasePlatformHookLib.inf
new file mode 100644
index 0000000000..0b631a79ea
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BasePlatformHookLib/BasePlatformHookLib.inf
@@ -0,0 +1,57 @@
+### @file
+# Platform Hook Library instance for Clevo N1xxWU board.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BasePlatformHookLib
+ FILE_GUID = E22ADCC6-ED90-4A90-9837-C8E7FF9E963D
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = PlatformHookLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ MmPciLib
+ PciLib
+ PchCycleDecodingLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ ClevoOpenBoardPkg/OpenBoardPkg.dec
+ KabylakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdLpcSioIndexDefaultPort ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdLpcSioDataDefaultPort ## CONSUMES
+
+[FixedPcd]
+ gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSUMES
+
+[Sources]
+ BasePlatformHookLib.c
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf
new file mode 100644
index 0000000000..4b2529d695
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf
@@ -0,0 +1,53 @@
+### @file
+# Clevo N1xxWU board DXE ACPI table functionality.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = DxeBoardAcpiTableLib
+ FILE_GUID = 6562E0AE-90D8-4D41-8C97-81286B4BE7D2
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = BoardAcpiTableLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciLib
+ AslUpdateLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ ClevoOpenBoardPkg/OpenBoardPkg.dec
+ KabylakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable
+ gMinPlatformPkgTokenSpaceGuid.PcdPciExpNative
+ gMinPlatformPkgTokenSpaceGuid.PcdNativeAspmEnable
+ gMinPlatformPkgTokenSpaceGuid.PcdLowPowerS0Idle
+ gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress
+
+[Sources]
+ DxeN1xxWUAcpiTableLib.c
+ DxeBoardAcpiTableLib.c
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf
new file mode 100644
index 0000000000..f191b04eee
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf
@@ -0,0 +1,54 @@
+### @file
+# Clevo N1xxWU multi-board DXE ACPI table support functionality.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = DxeN1xxWUMultiBoardAcpiTableLib
+ FILE_GUID = 8E6A3B38-53E0-48C0-970F-058F380FCB80
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = DxeN1xxWUMultiBoardAcpiSupportLibConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciLib
+ AslUpdateLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ ClevoOpenBoardPkg/OpenBoardPkg.dec
+ KabylakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable
+ gBoardModuleTokenSpaceGuid.PcdPciExpNative
+ gBoardModuleTokenSpaceGuid.PcdNativeAspmEnable
+ gBoardModuleTokenSpaceGuid.PcdLowPowerS0Idle
+ gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress
+
+[Sources]
+ DxeN1xxWUAcpiTableLib.c
+ DxeMultiBoardAcpiSupportLib.c
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
new file mode 100644
index 0000000000..efeebff979
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
@@ -0,0 +1,53 @@
+### @file
+# Clevo N1xxWU board SMM ACPI table enable/disable functionality.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = SmmBoardAcpiEnableLib
+ FILE_GUID = 549E69AE-D3B3-485B-9C17-AF16E20A58AD
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = BoardAcpiEnableLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciLib
+ MmPciLib
+ PchCycleDecodingLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ ClevoOpenBoardPkg/OpenBoardPkg.dec
+ KabylakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES
+
+[Protocols]
+
+[Sources]
+ SmmN1xxWUAcpiEnableLib.c
+ SmmSiliconAcpiEnableLib.c
+ SmmBoardAcpiEnableLib.c
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
new file mode 100644
index 0000000000..f75f8844d9
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
@@ -0,0 +1,54 @@
+### @file
+# SMM multi-board ACPI support functionality.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = SmmN1xxWUMultiBoardAcpiSupportLib
+ FILE_GUID = 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = SmmN1xxWUMultiBoardAcpiSupportLibConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciLib
+ MmPciLib
+ PchCycleDecodingLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ ClevoOpenBoardPkg/OpenBoardPkg.dec
+ KabylakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES
+
+[Protocols]
+
+[Sources]
+ SmmN1xxWUAcpiEnableLib.c
+ SmmSiliconAcpiEnableLib.c
+ SmmMultiBoardAcpiSupportLib.c
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardInitPostMemLib.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
new file mode 100644
index 0000000000..3c8705d997
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
@@ -0,0 +1,59 @@
+## @file
+# Component information file for N1xxWUInitLib in PEI post memory phase.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiBoardPostMemInitLib
+ FILE_GUID = 7fcc3900-d38d-419f-826b-72481e8b5509
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = BoardInitLib
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ GpioExpanderLib
+ PcdLib
+ SiliconInitLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ ClevoOpenBoardPkg/OpenBoardPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ KabylakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ PeiN1xxWUInitPostMemLib.c
+ N1xxWUGpioTable.c
+ N1xxWUHdaVerbTables.c
+ PeiBoardInitPostMemLib.c
+
+[FixedPcd]
+
+[Pcd]
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTable
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel
+
+ gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable
+ gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize
+
+ gBoardModuleTokenSpaceGuid.PcdHdaVerbTable
+
+ gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable
+ gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
new file mode 100644
index 0000000000..0dbbafd0f6
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
@@ -0,0 +1,138 @@
+## @file
+# Component information file for PEI N1xxWU Board Init Pre-Mem Library
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiBoardInitPreMemLib
+ FILE_GUID = ec3675bc-1470-417d-826e-37378140213d
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = BoardInitLib
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PcdLib
+ SiliconInitLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ ClevoOpenBoardPkg/OpenBoardPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ KabylakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ PeiN1xxWUDetect.c
+ PeiN1xxWUInitPreMemLib.c
+ N1xxWUHsioPtssTables.c
+ N1xxWUSpdTable.c
+ PeiBoardInitPreMemLib.c
+
+[Pcd]
+ gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort
+
+ # PCH-LP HSIO PTSS Table
+ gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
+ gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
+ gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
+ gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
+
+ # PCH-H HSIO PTSS Table
+ #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1
+ #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2
+ #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size
+ #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size
+
+ # SA Misc Config
+ gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize
+
+ # PEG Reset By GPIO
+ gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo
+ gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo
+ gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo
+ gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive
+ gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo
+ gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo
+ gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive
+
+
+ # SPD Address Table
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3
+
+ # CA Vref Configuration
+
+ # Root Port Clock Info
+ gBoardModuleTokenSpaceGuid.PcdRootPort0ClkInfo
+ gBoardModuleTokenSpaceGuid.PcdRootPort4ClkInfo
+ gBoardModuleTokenSpaceGuid.PcdRootPort5ClkInfo
+ gBoardModuleTokenSpaceGuid.PcdRootPort7ClkInfo
+ gBoardModuleTokenSpaceGuid.PcdRootPort8ClkInfo
+ gBoardModuleTokenSpaceGuid.PcdRootPort9ClkInfo
+ gBoardModuleTokenSpaceGuid.PcdRootPortLanClkInfo
+
+ # USB 2.0 Port AFE
+ gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe
+ gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe
+ gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe
+ gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe
+ gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe
+ gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe
+ gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe
+ gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe
+ gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe
+ gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe
+
+ # USB 2.0 Port Over Current Pin
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13
+
+ # USB 3.0 Port Over Current Pin
+ gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0
+ gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1
+ gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2
+ gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3
+ gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4
+ gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5
+
+ # Misc
+ gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent
+
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
new file mode 100644
index 0000000000..dc35136a0d
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
@@ -0,0 +1,61 @@
+## @file
+# Component information file for N1xxWUInitLib in PEI post memory phase.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiN1xxWUMultiBoardInitLib
+ FILE_GUID = C7D39F17-E5BA-41D9-8DFE-FF9017499280
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = PeiN1xxWUMultiBoardInitLibConstructor
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ GpioExpanderLib
+ PcdLib
+ SiliconInitLib
+ MultiBoardInitSupportLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ ClevoOpenBoardPkg/OpenBoardPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ KabylakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ PeiN1xxWUInitPostMemLib.c
+ N1xxWUGpioTable.c
+ N1xxWUHdaVerbTables.c
+ PeiMultiBoardInitPostMemLib.c
+
+[FixedPcd]
+
+[Pcd]
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTable
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel
+
+ gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable
+ gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize
+
+ gBoardModuleTokenSpaceGuid.PcdHdaVerbTable
+
+ gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable
+ gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
new file mode 100644
index 0000000000..c0df18faa3
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
@@ -0,0 +1,140 @@
+## @file
+# Component information file for PEI N1xxWU Board Init Pre-Mem Library
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiN1xxWUMultiBoardInitPreMemLib
+ FILE_GUID = EA05BD43-136F-45EE-BBBA-27D75817574F
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = PeiN1xxWUMultiBoardInitPreMemLibConstructor
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PcdLib
+ SiliconInitLib
+ MultiBoardInitSupportLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ ClevoOpenBoardPkg/OpenBoardPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ KabylakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ PeiN1xxWUInitPreMemLib.c
+ N1xxWUHsioPtssTables.c
+ N1xxWUSpdTable.c
+ PeiMultiBoardInitPreMemLib.c
+ PeiN1xxWUDetect.c
+
+[Pcd]
+ gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort
+
+ # PCH-LP HSIO PTSS Table
+ gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
+ gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
+ gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
+ gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
+
+ # PCH-H HSIO PTSS Table
+ #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1
+ #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2
+ #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size
+ #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size
+
+ # SA Misc Config
+ gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize
+
+ # PEG Reset By GPIO
+ gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo
+ gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo
+ gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo
+ gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive
+ gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo
+ gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo
+ gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive
+
+
+ # SPD Address Table
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3
+
+ # CA Vref Configuration
+
+ # Root Port Clock Info
+ gBoardModuleTokenSpaceGuid.PcdRootPort0ClkInfo
+ gBoardModuleTokenSpaceGuid.PcdRootPort4ClkInfo
+ gBoardModuleTokenSpaceGuid.PcdRootPort5ClkInfo
+ gBoardModuleTokenSpaceGuid.PcdRootPort7ClkInfo
+ gBoardModuleTokenSpaceGuid.PcdRootPort8ClkInfo
+ gBoardModuleTokenSpaceGuid.PcdRootPort9ClkInfo
+ gBoardModuleTokenSpaceGuid.PcdRootPortLanClkInfo
+
+ # USB 2.0 Port AFE
+ gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe
+ gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe
+ gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe
+ gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe
+ gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe
+ gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe
+ gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe
+ gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe
+ gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe
+ gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe
+
+ # USB 2.0 Port Over Current Pin
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12
+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13
+
+ # USB 3.0 Port Over Current Pin
+ gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0
+ gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1
+ gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2
+ gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3
+ gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4
+ gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5
+
+ # Misc
+ gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent
+
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
new file mode 100644
index 0000000000..c6ffd6d40e
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
@@ -0,0 +1,55 @@
+## @file
+# Component information file for DXE silicon policy update library
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = DxeSiliconUpdateLib
+ FILE_GUID = C523609D-E354-416B-B24F-33468D4BD21D
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SiliconUpdateLib
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ DebugLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ KabylakeSiliconPkg/SiPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ ClevoOpenBoardPkg/OpenBoardPkg.dec
+
+[Sources]
+ DxeSiliconPolicyUpdateLib.c
+ DxeGopPolicyInit.c
+ DxeSaPolicyUpdate.c
+
+[Pcd]
+ gBoardModuleTokenSpaceGuid.PcdIntelGopEnable
+ gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid
+
+[Protocols]
+ gEfiFirmwareVolume2ProtocolGuid ## CONSUMES
+ gSaPolicyProtocolGuid ## CONSUMES
+ gDxeSiPolicyProtocolGuid ## PRODUCES
+ gGopPolicyProtocolGuid ## PRODUCES
+
+[Guids]
+ gMiscDxeConfigGuid
+
+[Depex]
+ gEfiVariableArchProtocolGuid
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c
new file mode 100644
index 0000000000..40366af4cf
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c
@@ -0,0 +1,121 @@
+/** @file
+ Intel PCH PEI Policy initialization.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/HobLib.h>
+#include <Guid/GlobalVariable.h>
+#include <Library/PchGbeLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchHsioLib.h>
+#include <Library/PchSerialIoLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <GpioConfig.h>
+#include <GpioPinsSklH.h>
+#include <Library/DebugLib.h>
+#include <Library/PchGbeLib.h>
+
+#define PCI_CLASS_NETWORK 0x02
+#define PCI_CLASS_NETWORK_ETHERNET 0x00
+#define PCI_CLASS_NETWORK_OTHER 0x80
+
+GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = {
+ //
+ // Intel PRO/Wireless
+ //
+ { 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ //
+ // Intel WiMAX/WiFi Link
+ //
+ { 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ //
+ // Intel Crane Peak WLAN NIC
+ //
+ { 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ //
+ // Intel Crane Peak w/BT WLAN NIC
+ //
+ { 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ //
+ // Intel Kelsey Peak WiFi, WiMax
+ //
+ { 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ //
+ // Intel Centrino Wireless-N 105
+ //
+ { 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ //
+ // Intel Centrino Wireless-N 135
+ //
+ { 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ //
+ // Intel Centrino Wireless-N 2200
+ //
+ { 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ //
+ // Intel Centrino Wireless-N 2230
+ //
+ { 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ //
+ // Intel Centrino Wireless-N 6235
+ //
+ { 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ //
+ // Intel CampPeak 2 Wifi
+ //
+ { 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ //
+ // Intel WilkinsPeak 1 Wifi
+ //
+ { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
+ //
+ // Intel Wilkins Peak 2 Wifi
+ //
+ { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
+ //
+ // Intel Wilkins Peak PF Wifi
+ //
+ { 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+
+ //
+ // End of Table
+ //
+ { 0 }
+};
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
new file mode 100644
index 0000000000..df5a11ab2d
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
@@ -0,0 +1,93 @@
+/** @file
+ Implementation of Fsp Misc UPD Initialization.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+
+#include <Library/DebugLib.h>
+#include <Library/PeiLib.h>
+#include <Library/ConfigBlockLib.h>
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <Library/PciLib.h>
+#include <Guid/MemoryOverwriteControl.h>
+#include <PchAccess.h>
+
+/**
+ Performs FSP Misc UPD initialization.
+
+ @param[in][out] FspmUpd Pointer to FSPM_UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMiscUpdUpdatePreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ EFI_STATUS Status;
+ UINTN VariableSize;
+ VOID *MemorySavedData;
+ UINT8 MorControl;
+ VOID *MorControlPtr;
+
+ //
+ // Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths.
+ //
+ VariableSize = 0;
+ MemorySavedData = NULL;
+ Status = PeiGetVariable (
+ L"MemoryConfig",
+ &gFspNonVolatileStorageHobGuid,
+ &MemorySavedData,
+ &VariableSize
+ );
+ DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" gFspNonVolatileStorageHobGuid - %r\n", Status));
+ DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize));
+ FspmUpd->FspmArchUpd.NvsBufferPtr = MemorySavedData;
+
+ if (FspmUpd->FspmArchUpd.NvsBufferPtr != NULL) {
+ //
+ // Set the DISB bit in PCH (DRAM Initialization Scratchpad Bit - GEN_PMCON_A[23]),
+ // after memory Data is saved to NVRAM.
+ //
+ PciOr32 ((UINTN)PCI_LIB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PCH_PMC_GEN_PMCON_A), B_PCH_PMC_GEN_PMCON_A_DISB);
+ }
+
+ //
+ // MOR
+ //
+ MorControl = 0;
+ MorControlPtr = &MorControl;
+ VariableSize = sizeof (MorControl);
+ Status = PeiGetVariable (
+ MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME,
+ &gEfiMemoryOverwriteControlDataGuid,
+ &MorControlPtr,
+ &VariableSize
+ );
+ DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status));
+ if (MOR_CLEAR_MEMORY_VALUE (MorControl)) {
+ FspmUpd->FspmConfig.CleanMemory = (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK);
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c
new file mode 100644
index 0000000000..91d0f03191
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c
@@ -0,0 +1,192 @@
+/** @file
+ Provides FSP policy update functionality.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/FspWrapperApiLib.h>
+#include <Library/SiliconPolicyUpdateLib.h>
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+/**
+ Performs FSP Misc UPD initialization.
+
+ @param[in][out] FspmUpd Pointer to FSPM_UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMiscUpdUpdatePreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ );
+
+/**
+ Performs FSP PCH PEI Policy pre mem initialization.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyUpdatePreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ );
+
+/**
+ Performs FSP PCH PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyUpdate (
+ IN OUT FSPS_UPD *FspsUpd
+ );
+
+/**
+ Performs FSP SA PEI Policy initialization in pre-memory.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyUpdatePreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ );
+
+/**
+ Performs FSP SA PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyUpdate (
+ IN OUT FSPS_UPD *FspsUpd
+ );
+
+VOID
+InternalPrintVariableData (
+ IN UINT8 *Data8,
+ IN UINTN DataSize
+ )
+{
+ UINTN Index;
+
+ for (Index = 0; Index < DataSize; Index++) {
+ if (Index % 0x10 == 0) {
+ DEBUG ((DEBUG_INFO, "\n%08X:", Index));
+ }
+ DEBUG ((DEBUG_INFO, " %02X", *Data8++));
+ }
+ DEBUG ((DEBUG_INFO, "\n"));
+}
+
+/**
+ Performs silicon pre-mem policy update.
+
+ The meaning of Policy is defined by silicon code.
+ It could be the raw data, a handle, a PPI, etc.
+
+ The input Policy must be returned by SiliconPolicyDonePreMem().
+
+ 1) In FSP path, the input Policy should be FspmUpd.
+ A platform may use this API to update the FSPM UPD policy initialized
+ by the silicon module or the default UPD data.
+ The output of FSPM UPD data from this API is the final UPD data.
+
+ 2) In non-FSP path, the board may use additional way to get
+ the silicon policy data field based upon the input Policy.
+
+ @param[in, out] Policy Pointer to policy.
+
+ @return the updated policy.
+**/
+VOID *
+EFIAPI
+SiliconPolicyUpdatePreMem (
+ IN OUT VOID *FspmUpd
+ )
+{
+ FSPM_UPD *FspmUpdDataPtr;
+
+ FspmUpdDataPtr = FspmUpd;
+ PeiFspSaPolicyUpdatePreMem (FspmUpdDataPtr);
+ PeiFspPchPolicyUpdatePreMem (FspmUpdDataPtr);
+ PeiFspMiscUpdUpdatePreMem (FspmUpdDataPtr);
+
+ InternalPrintVariableData ((VOID *)FspmUpdDataPtr, sizeof(FSPM_UPD));
+
+ return FspmUpd;
+}
+
+/**
+ Performs silicon post-mem policy update.
+
+ The meaning of Policy is defined by silicon code.
+ It could be the raw data, a handle, a PPI, etc.
+
+ The input Policy must be returned by SiliconPolicyDonePostMem().
+
+ 1) In FSP path, the input Policy should be FspsUpd.
+ A platform may use this API to update the FSPS UPD policy initialized
+ by the silicon module or the default UPD data.
+ The output of FSPS UPD data from this API is the final UPD data.
+
+ 2) In non-FSP path, the board may use additional way to get
+ the silicon policy data field based upon the input Policy.
+
+ @param[in, out] Policy Pointer to policy.
+
+ @return the updated policy.
+**/
+VOID *
+EFIAPI
+SiliconPolicyUpdatePostMem (
+ IN OUT VOID *FspsUpd
+ )
+{
+ FSPS_UPD *FspsUpdDataPtr;
+
+ FspsUpdDataPtr = FspsUpd;
+ PeiFspSaPolicyUpdate (FspsUpdDataPtr);
+ PeiFspPchPolicyUpdate (FspsUpdDataPtr);
+
+ InternalPrintVariableData ((VOID *)FspsUpdDataPtr, sizeof(FSPS_UPD));
+
+ return FspsUpd;
+}
+
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c
new file mode 100644
index 0000000000..a50b2f2b7c
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c
@@ -0,0 +1,159 @@
+/** @file
+ Intel PCH PEI Policy initialization.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/HobLib.h>
+#include <Guid/GlobalVariable.h>
+#include <Library/PchGbeLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchHsioLib.h>
+#include <Library/PchSerialIoLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <GpioConfig.h>
+#include <GpioPinsSklH.h>
+#include <Library/DebugLib.h>
+#include <Library/PchGbeLib.h>
+
+extern PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[];
+
+/**
+ Add verb table helper function.
+ This function calculates verbtable number and shows verb table information.
+
+ @param[in,out] VerbTableEntryNum Input current VerbTable number and output the number after adding new table
+ @param[in,out] VerbTableArray Pointer to array of VerbTable
+ @param[in] VerbTable VerbTable which is going to add into array
+**/
+STATIC
+VOID
+InternalAddVerbTable (
+ IN OUT UINT8 *VerbTableEntryNum,
+ IN OUT UINT32 *VerbTableArray,
+ IN HDAUDIO_VERB_TABLE *VerbTable
+ )
+{
+ if (VerbTable == NULL) {
+ DEBUG ((DEBUG_ERROR, "InternalAddVerbTable wrong input: VerbTable == NULL\n"));
+ return;
+ }
+
+ VerbTableArray[*VerbTableEntryNum] = (UINT32) VerbTable;
+ *VerbTableEntryNum += 1;
+
+ DEBUG ((DEBUG_INFO,
+ "Add verb table for vendor = 0x%04X devId = 0x%04X (size = %d DWords)\n",
+ VerbTable->Header.VendorId,
+ VerbTable->Header.DeviceId,
+ VerbTable->Header.DataDwords)
+ );
+}
+
+enum HDAUDIO_CODEC_SELECT {
+ PchHdaCodecPlatformOnboard = 0,
+ PchHdaCodecExternalKit = 1
+};
+
+/**
+ Add verb table function.
+ This function update the verb table number and verb table ptr of policy.
+
+ @param[in] HdAudioConfig HDAudie config block
+ @param[in] CodecType Platform codec type indicator
+ @param[in] AudioConnectorType Platform audio connector type
+**/
+STATIC
+VOID
+InternalAddPlatformVerbTables (
+ IN OUT FSPS_UPD *FspsUpd,
+ IN UINT8 CodecType,
+ IN UINT8 AudioConnectorType
+ )
+{
+ UINT8 VerbTableEntryNum;
+ UINT32 VerbTableArray[32];
+ UINT32 *VerbTablePtr;
+
+ VerbTableEntryNum = 0;
+
+ InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdDisplayAudioHdaVerbTable));
+
+ if (CodecType == PchHdaCodecPlatformOnboard) {
+ DEBUG ((DEBUG_INFO, "HDA Policy: Onboard codec selected\n"));
+ if ((VOID *) (UINTN) PcdGet32 (PcdExtHdaVerbTable) != NULL) {
+ if (AudioConnectorType == 0) { //Type-C Audio connector selected in Bios Setup menu
+ InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdExtHdaVerbTable));
+ InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL);
+ InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL);
+ DEBUG ((DEBUG_INFO, "HDA: Type-C Audio connector selected!\n"));
+ } else { //Stacked Jack Audio connector selected in Bios Setup menu
+ InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable));
+ InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable2));
+ InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL);
+ DEBUG ((DEBUG_INFO, "HDA: Stacked-Jack Audio connector selected!\n"));
+ }
+ } else {
+ InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable));
+ InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable2));
+ InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL);
+ }
+ } else {
+ DEBUG ((DEBUG_INFO, "HDA Policy: External codec kit selected\n"));
+ InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable1));
+ InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable2));
+ InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable3));
+ }
+
+ FspsUpd->FspsConfig.PchHdaVerbTableEntryNum = VerbTableEntryNum;
+
+ VerbTablePtr = (UINT32 *) AllocateZeroPool (sizeof (UINT32) * VerbTableEntryNum);
+ CopyMem (VerbTablePtr, VerbTableArray, sizeof (UINT32) * VerbTableEntryNum);
+ FspsUpd->FspsConfig.PchHdaVerbTablePtr = (UINT32) VerbTablePtr;
+}
+
+/**
+ Performs FSP PCH PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyUpdate (
+ IN OUT FSPS_UPD *FspsUpd
+ )
+{
+
+ FspsUpd->FspsConfig.PchSubSystemVendorId = V_PCH_INTEL_VENDOR_ID;
+ FspsUpd->FspsConfig.PchSubSystemId = V_PCH_DEFAULT_SID;
+
+ FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr = (UINT32) mPcieDeviceTable;
+
+ InternalAddPlatformVerbTables (FspsUpd, PchHdaCodecPlatformOnboard, PcdGet8 (PcdAudioConnector));
+
+DEBUG_CODE_BEGIN();
+if ((PcdGet8 (PcdSerialIoUartDebugEnable) == 1) &&
+ FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 (PcdSerialIoUartNumber)] == PchSerialIoDisabled ) {
+ FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 (PcdSerialIoUartNumber)] = PchSerialIoLegacyUart;
+ }
+DEBUG_CODE_END();
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..b3661f3439
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c
@@ -0,0 +1,254 @@
+/** @file
+ Intel PCH PEI Policy initialization.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/HobLib.h>
+#include <Guid/GlobalVariable.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchHsioLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <PchHsioPtssTables.h>
+#include <Library/DebugLib.h>
+
+VOID
+InstallPlatformHsioPtssTable (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ HSIO_PTSS_TABLES *UnknowPtssTables;
+ HSIO_PTSS_TABLES *SpecificPtssTables;
+ HSIO_PTSS_TABLES *PtssTables;
+ UINT8 PtssTableIndex;
+ UINT32 UnknowTableSize;
+ UINT32 SpecificTableSize;
+ UINT32 TableSize;
+ UINT32 Entry;
+ UINT8 LaneNum;
+ UINT8 Index;
+ UINT8 MaxSataPorts;
+ UINT8 MaxPciePorts;
+ UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS];
+ UINT8 PciePort;
+ UINTN RpBase;
+ UINTN RpDevice;
+ UINTN RpFunction;
+ UINT32 StrapFuseCfg;
+ UINT8 PcieControllerCfg;
+ EFI_STATUS Status;
+
+ UnknowPtssTables = NULL;
+ UnknowTableSize = 0;
+ SpecificPtssTables = NULL;
+ SpecificTableSize = 0;
+
+ if (GetPchGeneration () == SklPch) {
+ switch (PchStepping ()) {
+ case PchLpB0:
+ case PchLpB1:
+ UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable1);
+ UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable1Size);
+ SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable1);
+ SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable1Size);
+ break;
+ case PchLpC0:
+ case PchLpC1:
+ UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable2);
+ UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable2Size);
+ SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable2);
+ SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable2Size);
+ break;
+ case PchHB0:
+ case PchHC0:
+ UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable1);
+ UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable1Size);
+ SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable1);
+ SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable1Size);
+ break;
+ case PchHD0:
+ case PchHD1:
+ UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2);
+ UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size);
+ SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2);
+ SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size);
+ break;
+ default:
+ UnknowPtssTables = NULL;
+ UnknowTableSize = 0;
+ SpecificPtssTables = NULL;
+ SpecificTableSize = 0;
+ DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n"));
+ }
+ } else {
+ switch (PchStepping ()) {
+ case KblPchHA0:
+ UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2);
+ UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size);
+ SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2);
+ SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size);
+ break;
+ default:
+ UnknowPtssTables = NULL;
+ UnknowTableSize = 0;
+ SpecificPtssTables = NULL;
+ SpecificTableSize = 0;
+ DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n"));
+ }
+ }
+
+ PtssTableIndex = 0;
+ MaxSataPorts = GetPchMaxSataPortNum ();
+ MaxPciePorts = GetPchMaxPciePortNum ();
+ ZeroMem (PcieTopologyReal, sizeof (PcieTopologyReal));
+
+ //Populate PCIe topology based on lane configuration
+ for (PciePort = 0; PciePort < MaxPciePorts; PciePort += 4) {
+ Status = GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction);
+ ASSERT_EFI_ERROR (Status);
+
+ RpBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (UINT32) RpFunction);
+ StrapFuseCfg = MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG);
+ PcieControllerCfg = (UINT8) ((StrapFuseCfg & B_PCH_PCIE_STRPFUSECFG_RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC);
+ DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value = %d\n", PciePort, PcieControllerCfg));
+ }
+ for (Index = 0; Index < MaxPciePorts; Index++) {
+ DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology = %d\n", Index, PcieTopologyReal[Index]));
+ }
+
+ //Case 1: BoardId is known, Topology is known/unknown
+ //Case 1a: SATA
+ PtssTables = SpecificPtssTables;
+ TableSize = SpecificTableSize;
+ for (Index = 0; Index < MaxSataPorts; Index++) {
+ if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
+ for (Entry = 0; Entry < TableSize; Entry++) {
+ if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
+ (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA)
+ )
+ {
+ PtssTableIndex++;
+ if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) &&
+ (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {
+ FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = TRUE;
+ FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;
+ } else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8)) {
+ if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) {
+ FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] = TRUE;
+ FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0);
+ }
+ if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) {
+ FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] = TRUE;
+ FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0);
+ }
+ } else {
+ ASSERT (FALSE);
+ }
+ }
+ }
+ }
+ }
+ //Case 1b: PCIe
+ for (Index = 0; Index < MaxPciePorts; Index++) {
+ if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
+ for (Entry = 0; Entry < TableSize; Entry++) {
+ if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
+ (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) &&
+ (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) {
+ PtssTableIndex++;
+ if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) &&
+ (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) {
+ FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] = TRUE;
+ FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0);
+ } else {
+ ASSERT (FALSE);
+ }
+ }
+ }
+ }
+ }
+ //Case 2: BoardId is unknown, Topology is known/unknown
+ if (PtssTableIndex == 0) {
+ DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be applied\n"));
+
+ PtssTables = UnknowPtssTables;
+ TableSize = UnknowTableSize;
+
+ for (Index = 0; Index < MaxSataPorts; Index++) {
+ if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
+ for (Entry = 0; Entry < TableSize; Entry++) {
+ if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
+ (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA)
+ )
+ {
+ if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) &&
+ (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {
+ FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = TRUE;
+ FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;
+ } else if (PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8) {
+ if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) {
+ FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] = TRUE;
+ FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0);
+ }
+ if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) {
+ FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] = TRUE;
+ FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0);
+ }
+ } else {
+ ASSERT (FALSE);
+ }
+ }
+ }
+ }
+ }
+ for (Index = 0; Index < MaxPciePorts; Index++) {
+ if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
+ for (Entry = 0; Entry < TableSize; Entry++) {
+ if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
+ (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) &&
+ (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) {
+ if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) &&
+ (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) {
+ FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] = TRUE;
+ FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0);
+ } else {
+ ASSERT (FALSE);
+ }
+ }
+ }
+ }
+ }
+ }
+}
+
+/**
+ Performs FSP PCH PEI Policy pre mem initialization.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyUpdatePreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ InstallPlatformHsioPtssTable (FspmUpd);
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
new file mode 100644
index 0000000000..e445ddef72
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
@@ -0,0 +1,90 @@
+/** @file
+ Intel System Agent policy initialization.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include <Guid/MemoryTypeInformation.h>
+#include <Library/HobLib.h>
+#include <PchAccess.h>
+#include <SaAccess.h>
+#include <Pi/PiFirmwareFile.h>
+#include <Pi/PiPeiCis.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/PeiLib.h>
+
+/**
+ Performs FSP SA PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyUpdate (
+ IN OUT FSPS_UPD *FspsUpd
+ )
+{
+ VOID *Buffer;
+ VOID *MemBuffer;
+ UINT32 Size;
+
+ DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n"));
+
+ FspsUpd->FspsConfig.PeiGraphicsPeimInit = 1;
+
+ Size = 0;
+ Buffer = NULL;
+ PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size);
+ if (Buffer == NULL) {
+ DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
+ } else {
+ MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
+ if ((MemBuffer != NULL) && (Buffer != NULL)) {
+ CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
+ FspsUpd->FspsConfig.GraphicsConfigPtr = (UINT32)(UINTN)MemBuffer;
+ } else {
+ DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n"));
+ FspsUpd->FspsConfig.GraphicsConfigPtr = 0;
+ }
+ }
+ DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.GraphicsConfigPtr));
+ DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size));
+
+ Size = 0;
+ Buffer = NULL;
+ PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, &Size);
+ if (Buffer == NULL) {
+ DEBUG((DEBUG_WARN, "Could not locate Logo\n"));
+ } else {
+ MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
+ if ((MemBuffer != NULL) && (Buffer != NULL)) {
+ CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
+ FspsUpd->FspsConfig.LogoPtr = (UINT32)(UINTN)MemBuffer;
+ FspsUpd->FspsConfig.LogoSize = Size;
+ } else {
+ DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n"));
+ FspsUpd->FspsConfig.LogoPtr = 0;
+ FspsUpd->FspsConfig.LogoSize = 0;
+ }
+ }
+ DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.LogoPtr));
+ DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.LogoSize));
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..c8d6fe4036
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
@@ -0,0 +1,74 @@
+/** @file
+ Intel System Agent policy initialization.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include <CpuRegs.h>
+#include <Library/CpuPlatformLib.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Guid/MemoryOverwriteControl.h>
+#include <Library/HobLib.h>
+#include <PchAccess.h>
+#include <SaAccess.h>
+#include <Library/CpuMailboxLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsSklH.h>
+
+
+/**
+ Performs FSP SA PEI Policy initialization in pre-memory.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyUpdatePreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ VOID *Buffer;
+
+ CopyMem((VOID *)(UINTN)FspmUpd->FspmConfig.MemorySpdPtr00, (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize));
+ CopyMem((VOID *)(UINTN)FspmUpd->FspmConfig.MemorySpdPtr10, (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize));
+
+ DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings...\n"));
+ Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap);
+ if (Buffer) {
+ CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12);
+ CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*) Buffer + 12, 12);
+ }
+ Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram);
+ if (Buffer) {
+ CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, 8);
+ CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1, (UINT8*) Buffer + 8, 8);
+ }
+
+ DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp Target Settings...\n"));
+ Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor);
+ if (Buffer) {
+ CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6);
+ }
+ Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget);
+ if (Buffer) {
+ CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10);
+ }
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BasePlatformHookLib/BasePlatformHookLib.c
new file mode 100644
index 0000000000..637f46cb46
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BasePlatformHookLib/BasePlatformHookLib.c
@@ -0,0 +1,668 @@
+/** @file
+ Platform Hook Library
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/PlatformHookLib.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <Library/PcdLib.h>
+#include <SystemAgent/Include/SaAccess.h>
+#include <SioRegs.h>
+#include <Library/MmPciLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Register/PchRegsLpc.h>
+#include <PchAccess.h>
+
+#define COM1_BASE 0x3f8
+#define COM2_BASE 0x2f8
+
+#define SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS 0x0690
+
+#define LPC_SIO_INDEX_DEFAULT_PORT_2 0x2E
+#define LPC_SIO_DATA_DEFAULT_PORT_2 0x2F
+#define LPC_SIO_GPIO_REGISTER_ADDRESS_2 0x0A20
+
+#define LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT 0x2E
+#define LEGACY_DAUGHTER_CARD_SIO_DATA_PORT 0x2F
+#define LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT 0x4E
+#define LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT 0x4F
+
+typedef struct {
+ UINT8 Register;
+ UINT8 Value;
+} EFI_SIO_TABLE;
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTable[] = {
+ {0x002, 0x88}, // Power On UARTs
+ {0x024, COM1_BASE >> 2},
+ {0x025, COM2_BASE >> 2},
+ {0x028, 0x043}, // IRQ of UARTs, UART2 IRQ=3,UART1 IRQ=4,
+ {0x029, 0x080}, // SIRQ_CLKRUN_EN
+ {0x02A, 0x000},
+ {0x02B, 0x0DE},
+ {0x00A, 0x040},
+ {0x00C, 0x00E},
+ {0x02c, 0x002},
+ {0x030, FixedPcdGet16 (PcdSioBaseAddress) >> 4},
+ {0x03b, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS >> 8},
+ {0x03c, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS & 0xff},
+ {0x03a, 0x00A}, // LPC Docking Enabling
+ {0x031, 0x01f},
+ {0x032, 0x000},
+ {0x033, 0x004},
+ {0x038, 0x0FB},
+ {0x035, 0x0FE},
+ {0x036, 0x000},
+ {0x037, 0x0FF},
+ {0x039, 0x000},
+ {0x034, 0x001},
+ {0x012, FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & 0xFF}, // Relocate configuration ports base address
+ {0x013, (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) >> 8) & 0xFF} // to ensure SIO config address can be accessed in OS
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableSmsc1000[] = {
+ {0x002, 0x88}, // Power On UARTs
+ {0x007, 0x00},
+ {0x024, COM1_BASE >> 2},
+ {0x025, COM2_BASE >> 2},
+ {0x028, 0x043}, // IRQ of UARTs, UART2 IRQ=3,UART1 IRQ=4,
+ {0x029, 0x080}, // SIRQ_CLKRUN_EN
+ {0x02A, 0x000},
+ {0x02B, 0x0DE},
+ {0x00A, 0x040},
+ {0x00C, 0x00E},
+ {0x030, FixedPcdGet16 (PcdSioBaseAddress) >> 4},
+ {0x03b, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS >> 8},
+ {0x03c, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS & 0xff},
+ {0x03a, 0x00A}, // LPC Docking Enabling
+ {0x031, 0x01f},
+ {0x032, 0x000},
+ {0x033, 0x004},
+ {0x038, 0x0FB},
+ {0x035, 0x0FE},
+ {0x036, 0x000},
+ {0x037, 0x0FE},
+ {0x039, 0x000},
+ {0x034, 0x001}
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWpcn381u[] = {
+ {0x29, 0x0A0}, // Enable super I/O clock and set to 48MHz
+ {0x22, 0x003}, //
+ {0x07, 0x003}, // Select UART0 device
+ {0x60, (COM1_BASE >> 8)}, // Set Base Address MSB
+ {0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB
+ {0x70, 0x004}, // Set to IRQ4
+ {0x30, 0x001}, // Enable it with Activation bit
+ {0x07, 0x002}, // Select UART1 device
+ {0x60, (COM2_BASE >> 8)}, // Set Base Address MSB
+ {0x61, (COM2_BASE & 0x00FF)}, // Set Base Address LSB
+ {0x70, 0x003}, // Set to IRQ3
+ {0x30, 0x001}, // Enable it with Activation bit
+ {0x07, 0x007}, // Select GPIO device
+ {0x60, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 >> 8)}, // Set Base Address MSB
+ {0x61, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 & 0x00FF)}, // Set Base Address LSB
+ {0x30, 0x001}, // Enable it with Activation bit
+ {0x21, 0x001}, // Global Device Enable
+ {0x26, 0x000} // Fast Enable UART 0 & 1 as their enable & activation bit
+};
+
+//
+// National PC8374L
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mDesktopSioTable[] = {
+ {0x007, 0x03}, // Select Com1
+ {0x061, 0xF8}, // 0x3F8
+ {0x060, 0x03}, // 0x3F8
+ {0x070, 0x04}, // IRQ4
+ {0x030, 0x01} // Active
+};
+
+//
+// IT8628
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableSerialPort[] = {
+ {0x023, 0x09}, // Clock Selection register
+ {0x007, 0x01}, // Com1 Logical Device Number select
+ {0x061, 0xF8}, // Serial Port 1 Base Address MSB Register
+ {0x060, 0x03}, // Serial Port 1 Base Address LSB Register
+ {0x070, 0x04}, // Serial Port 1 Interrupt Level Select
+ {0x030, 0x01}, // Serial Port 1 Activate
+ {0x007, 0x02}, // Com1 Logical Device Number select
+ {0x061, 0xF8}, // Serial Port 2 Base Address MSB Register
+ {0x060, 0x02}, // Serial Port 2 Base Address MSB Register
+ {0x070, 0x03}, // Serial Port 2 Interrupt Level Select
+ {0x030, 0x01} // Serial Port 2 Activate
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableParallelPort[] = {
+ {0x007, 0x03}, // Parallel Port Logical Device Number select
+ {0x030, 0x00}, // Parallel port Activate
+ {0x061, 0x78}, // Parallel Port Base Address 1 MSB Register
+ {0x060, 0x03}, // Parallel Port Base Address 1 LSB Register
+ {0x063, 0x78}, // Parallel Port Base Address 2 MSB Register
+ {0x062, 0x07}, // Parallel Port Base Address 1 LSB Register
+ {0x0F0, 0x03} // Special Configuration register
+};
+
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWinbondX374[] = {
+ {0x07, 0x03}, // Select UART0 device
+ {0x60, (COM1_BASE >> 8)}, // Set Base Address MSB
+ {0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB
+ {0x70, 0x04}, // Set to IRQ4
+ {0x30, 0x01} // Enable it with Activation bit
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTablePilot3[] = {
+ {0x07, 0x02}, // Set logical device SP Serial port Com0
+ {0x61, 0xF8}, // Write Base Address LSB register 0x3F8
+ {0x60, 0x03}, // Write Base Address MSB register 0x3F8
+ {0x70, 0x04}, // Write IRQ1 value (IRQ 1) keyboard
+ {0x30, 0x01} // Enable serial port with Activation bit
+};
+
+/**
+ Detect if a National 393 SIO is docked. If yes, enable the docked SIO
+ and its serial port, and disable the onboard serial port.
+
+ @retval EFI_SUCCESS Operations performed successfully.
+**/
+STATIC
+VOID
+CheckNationalSio (
+ VOID
+ )
+{
+ UINT8 Data8;
+
+ //
+ // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f).
+ // We use (0x2e, 0x2f) which is determined by BADD default strapping
+ //
+
+ //
+ // Read the Pc87393 signature
+ //
+ IoWrite8 (0x2e, 0x20);
+ Data8 = IoRead8 (0x2f);
+
+ if (Data8 == 0xea) {
+ //
+ // Signature matches - National PC87393 SIO is docked
+ //
+
+ //
+ // Enlarge the LPC decode scope to accommodate the Docking LPC Switch
+ // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated at
+ // SIO_BASE_ADDRESS + 0x10)
+ //
+ PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) & (UINT16)~0x7F), 0x20);
+
+ //
+ // Enable port switch
+ //
+ IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06);
+
+ //
+ // Turn on docking power
+ //
+ IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c);
+
+ IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c);
+
+ IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc);
+
+ //
+ // Enable port switch
+ //
+ IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7);
+
+ //
+ // GPIO setting
+ //
+ IoWrite8 (0x2e, 0x24);
+ IoWrite8 (0x2f, 0x29);
+
+ //
+ // Enable chip clock
+ //
+ IoWrite8 (0x2e, 0x29);
+ IoWrite8 (0x2f, 0x1e);
+
+
+ //
+ // Enable serial port
+ //
+
+ //
+ // Select com1
+ //
+ IoWrite8 (0x2e, 0x7);
+ IoWrite8 (0x2f, 0x3);
+
+ //
+ // Base address: 0x3f8
+ //
+ IoWrite8 (0x2e, 0x60);
+ IoWrite8 (0x2f, 0x03);
+ IoWrite8 (0x2e, 0x61);
+ IoWrite8 (0x2f, 0xf8);
+
+ //
+ // Interrupt: 4
+ //
+ IoWrite8 (0x2e, 0x70);
+ IoWrite8 (0x2f, 0x04);
+
+ //
+ // Enable bank selection
+ //
+ IoWrite8 (0x2e, 0xf0);
+ IoWrite8 (0x2f, 0x82);
+
+ //
+ // Activate
+ //
+ IoWrite8 (0x2e, 0x30);
+ IoWrite8 (0x2f, 0x01);
+
+ //
+ // Disable onboard serial port
+ //
+ IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55);
+
+ //
+ // Power Down UARTs
+ //
+ IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2);
+ IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00);
+
+ //
+ // Dissable COM1 decode
+ //
+ IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24);
+ IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);
+
+ //
+ // Disable COM2 decode
+ //
+ IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25);
+ IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);
+
+ //
+ // Disable interrupt
+ //
+ IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28);
+ IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0);
+
+ IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);
+
+ //
+ // Enable floppy
+ //
+
+ //
+ // Select floppy
+ //
+ IoWrite8 (0x2e, 0x7);
+ IoWrite8 (0x2f, 0x0);
+
+ //
+ // Base address: 0x3f0
+ //
+ IoWrite8 (0x2e, 0x60);
+ IoWrite8 (0x2f, 0x03);
+ IoWrite8 (0x2e, 0x61);
+ IoWrite8 (0x2f, 0xf0);
+
+ //
+ // Interrupt: 6
+ //
+ IoWrite8 (0x2e, 0x70);
+ IoWrite8 (0x2f, 0x06);
+
+ //
+ // DMA 2
+ //
+ IoWrite8 (0x2e, 0x74);
+ IoWrite8 (0x2f, 0x02);
+
+ //
+ // Activate
+ //
+ IoWrite8 (0x2e, 0x30);
+ IoWrite8 (0x2f, 0x01);
+
+ } else {
+
+ //
+ // No National pc87393 SIO is docked, turn off dock power and
+ // disable port switch
+ //
+ // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf);
+ // IoWrite8 (0x690, 0);
+
+ //
+ // If no National pc87393, just return
+ //
+ return;
+ }
+}
+
+
+/**
+Check whether the IT8628 SIO present on LPC. If yes, enable its serial
+ports, parallel port, and port 80.
+
+@retval EFI_SUCCESS Operations performed successfully.
+**/
+STATIC
+VOID
+It8628SioSerialPortInit (
+ VOID
+ )
+{
+ UINT8 ChipId0 = 0;
+ UINT8 ChipId1 = 0;
+ UINT16 LpcIoDecondeRangeSet = 0;
+ UINT16 LpcIoDecoodeSet = 0;
+ UINT8 Index;
+ UINTN LpcBaseAddr;
+
+
+ //
+ // Enable I/O decoding for COM1 (3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh.
+ //
+ LpcBaseAddr = MmPciBase (
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_LPC,
+ PCI_FUNCTION_NUMBER_PCH_LPC
+ );
+
+ LpcIoDecondeRangeSet = (UINT16) MmioRead16 (LpcBaseAddr + R_PCH_LPC_IOD);
+ LpcIoDecoodeSet = (UINT16) MmioRead16 (LpcBaseAddr + R_PCH_LPC_IOE);
+ MmioWrite16 ((LpcBaseAddr + R_PCH_LPC_IOD), (LpcIoDecondeRangeSet | ((V_PCH_LPC_IOD_COMB_2F8 << 4) | V_PCH_LPC_IOD_COMA_3F8)));
+ MmioWrite16 ((LpcBaseAddr + R_PCH_LPC_IOE), (LpcIoDecoodeSet | (B_PCH_LPC_IOE_SE | B_PCH_LPC_IOE_CBE | B_PCH_LPC_IOE_CAE)));
+
+ //
+ // Enter MB PnP Mode
+ //
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x87);
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x01);
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x55);
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x55);
+
+ //
+ // Read Chip Id of SIO IT8628 (registers 0x20 and 0x21)
+ //
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x20);
+ ChipId0 = IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2);
+
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x21);
+ ChipId1 = IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2);
+
+ //
+ // Enable Serial Port 1, Port 2
+ //
+ if ((ChipId0 == 0x86) && (ChipId1 == 0x28)) {
+ for (Index = 0; Index < sizeof (mSioIt8628TableSerialPort) / sizeof (EFI_SIO_TABLE); Index++) {
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Index].Register);
+ IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Index].Value);
+ }
+ }
+
+ //
+ // Exit MB PnP Mode
+ //
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x02);
+ IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, 0x02);
+
+ return;
+}
+
+
+/**
+ Performs platform specific initialization required for the CPU to access
+ the hardware associated with a SerialPortLib instance. This function does
+ not initialize the serial port hardware itself. Instead, it initializes
+ hardware devices that are required for the CPU to access the serial port
+ hardware. This function may be called more than once.
+
+ @retval RETURN_SUCCESS The platform specific initialization succeeded.
+ @retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed.
+
+**/
+RETURN_STATUS
+EFIAPI
+PlatformHookSerialPortInitialize (
+ VOID
+ )
+{
+ UINT16 ConfigPort;
+ UINT16 IndexPort;
+ UINT16 DataPort;
+ UINT16 DeviceId;
+ UINT8 Index;
+ UINT16 AcpiBase;
+
+ //
+ // Set the ICH ACPI Base Address (Reg#40h) and ACPI Enable bit
+ // in ACPI Controll (Reg#44h bit7) for PrePpiStall function use.
+ //
+ IndexPort = 0;
+ DataPort = 0;
+ Index = 0;
+ AcpiBase = 0;
+ PchAcpiBaseGet (&AcpiBase);
+ if (AcpiBase == 0) {
+ PchAcpiBaseSet (PcdGet16 (PcdAcpiBaseAddress));
+ }
+
+ //
+ // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h.
+ //
+ PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange));
+ PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding));
+
+ // Configure Sio IT8628
+ It8628SioSerialPortInit ();
+
+ DeviceId = MmioRead16 (MmPciBase (SA_MC_BUS, 0, 0) + R_SA_MC_DEVICE_ID);
+ if (IS_SA_DEVICE_ID_MOBILE (DeviceId)) {
+ //
+ // if no EC, it is SV Bidwell Bar board
+ //
+ if ((IoRead8 (0x66) != 0xFF) && (IoRead8 (0x62) != 0xFF)) {
+ //
+ // Super I/O initialization for SMSC SI1007
+ //
+ ConfigPort = FixedPcdGet16 (PcdLpcSioConfigDefaultPort);
+ DataPort = PcdGet16 (PcdLpcSioDataDefaultPort);
+ IndexPort = PcdGet16 (PcdLpcSioIndexDefaultPort);
+
+ //
+ // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF;
+ //
+ PchLpcGenIoRangeSet (FixedPcdGet16 (PcdSioBaseAddress) & (~0x7F), 0x10);
+
+ //
+ // Program and Enable Default Super IO Configuration Port Addresses and range
+ //
+ PchLpcGenIoRangeSet (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x10);
+
+ //
+ // Enter Config Mode
+ //
+ IoWrite8 (ConfigPort, 0x55);
+
+ //
+ // Check for SMSC SIO1007
+ //
+ IoWrite8 (IndexPort, 0x0D); // SMSC SIO1007 Device ID register is 0x0D
+ if (IoRead8 (DataPort) == 0x20) { // SMSC SIO1007 Device ID is 0x20
+ //
+ // Configure SIO
+ //
+ for (Index = 0; Index < sizeof (mSioTable) / sizeof (EFI_SIO_TABLE); Index++) {
+ IoWrite8 (IndexPort, mSioTable[Index].Register);
+ IoWrite8 (DataPort, mSioTable[Index].Value);
+ }
+
+ //
+ // Exit Config Mode
+ //
+ IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);
+
+ //
+ // GPIO 15-17:IN 10-14:OUT Enable RS232 ref: Page42 of CRB_SCH
+ //
+ IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0c, 0x1f);
+ }
+
+ //
+ // Check if a National Pc87393 SIO is docked
+ //
+ CheckNationalSio ();
+
+ //
+ // Super I/O initialization for SMSC SIO1000
+ //
+ ConfigPort = PcdGet16 (PcdLpcSioIndexPort);
+ IndexPort = PcdGet16 (PcdLpcSioIndexPort);
+ DataPort = PcdGet16 (PcdLpcSioDataPort);
+
+ //
+ // Enter Config Mode
+ //
+ IoWrite8 (ConfigPort, 0x55);
+
+ //
+ // Check for SMSC SIO1000
+ //
+ if (IoRead8 (ConfigPort) != 0xFF) {
+ //
+ // Configure SIO
+ //
+ for (Index = 0; Index < sizeof (mSioTableSmsc1000) / sizeof (EFI_SIO_TABLE); Index++) {
+ IoWrite8 (IndexPort, mSioTableSmsc1000[Index].Register);
+ IoWrite8 (DataPort, mSioTableSmsc1000[Index].Value);
+ }
+
+ //
+ // Exit Config Mode
+ //
+ IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);
+ }
+
+ //
+ // Super I/O initialization for Winbond WPCN381U
+ //
+ IndexPort = LPC_SIO_INDEX_DEFAULT_PORT_2;
+ DataPort = LPC_SIO_DATA_DEFAULT_PORT_2;
+
+ //
+ // Check for Winbond WPCN381U
+ //
+ IoWrite8 (IndexPort, 0x20); // Winbond WPCN381U Device ID register is 0x20
+ if (IoRead8 (DataPort) == 0xF4) { // Winbond WPCN381U Device ID is 0xF4
+ //
+ // Configure SIO
+ //
+ for (Index = 0; Index < sizeof (mSioTableWpcn381u) / sizeof (EFI_SIO_TABLE); Index++) {
+ IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register);
+ IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value);
+ }
+ }
+ } //EC is not exist, skip mobile board detection for SV board
+
+ //
+ //add for SV Bidwell Bar board
+ //
+ if (IoRead8 (COM1_BASE) == 0xFF) {
+ //
+ // Super I/O initialization for Winbond WPCD374 (LDC2) and 8374 (LDC)
+ // Looking for LDC2 card first
+ //
+ IoWrite8 (LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT, 0x55);
+ if (IoRead8 (LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT) == 0x55) {
+ IndexPort = LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT;
+ DataPort = LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT;
+ } else {
+ IndexPort = LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT;
+ DataPort = LEGACY_DAUGHTER_CARD_SIO_DATA_PORT;
+ }
+
+ IoWrite8 (IndexPort, 0x20); // Winbond x374 Device ID register is 0x20
+ if (IoRead8 (DataPort) == 0xF1) { // Winbond x374 Device ID is 0xF1
+ for (Index = 0; Index < sizeof (mSioTableWinbondX374) / sizeof (EFI_SIO_TABLE); Index++) {
+ IoWrite8 (IndexPort, mSioTableWinbondX374[Index].Register);
+ IoWrite8 (DataPort, mSioTableWinbondX374[Index].Value);
+ }
+ }
+ }// end of Bidwell Bar SIO initialization
+ } else if (IS_SA_DEVICE_ID_DESKTOP (DeviceId) || IS_SA_DEVICE_ID_SERVER (DeviceId)) {
+ //
+ // If we are in debug mode, we will allow serial status codes
+ //
+
+ //
+ // National PC8374 SIO & Winbond WPCD374 (LDC2)
+ //
+ IndexPort = LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT;
+
+ IoWrite8 (IndexPort, 0x55);
+ if (IoRead8 (IndexPort) == 0x55) {
+ IndexPort = LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT;
+ DataPort = LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT;
+ } else {
+ IndexPort = LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT;
+ DataPort = LEGACY_DAUGHTER_CARD_SIO_DATA_PORT;
+ }
+
+ //
+ // Configure SIO
+ //
+ IoWrite8 (IndexPort, 0x20); // Winbond x374 Device ID register is 0x20
+ if (IoRead8 (DataPort) == 0xF1) { // Winbond x374 Device ID is 0xF1
+ for (Index = 0; Index < sizeof (mDesktopSioTable) / sizeof (EFI_SIO_TABLE); Index++) {
+ IoWrite8 (IndexPort, mDesktopSioTable[Index].Register);
+ //PrePpiStall (200);
+ IoWrite8 (DataPort, mDesktopSioTable[Index].Value);
+ //PrePpiStall (200);
+ }
+ return RETURN_SUCCESS;
+ }
+ //
+ // Configure Pilot3 SIO
+ //
+ IoWrite8 (PILOTIII_SIO_INDEX_PORT, PILOTIII_UNLOCK); //Enter config mode.
+ IoWrite8 (PILOTIII_SIO_INDEX_PORT, PILOTIII_CHIP_ID_REG); // Pilot3 SIO Device ID register is 0x20.
+ if (IoRead8 (PILOTIII_SIO_DATA_PORT) == PILOTIII_CHIP_ID) { // Pilot3 SIO Device ID register is 0x03.
+ //
+ // Configure SIO
+ //
+ for (Index = 0; Index < sizeof (mSioTablePilot3) / sizeof (EFI_SIO_TABLE); Index++) {
+ IoWrite8 (PILOTIII_SIO_INDEX_PORT, mSioTablePilot3[Index].Register);
+ IoWrite8 (PILOTIII_SIO_DATA_PORT, mSioTablePilot3[Index].Value);
+ }
+ }
+ IoWrite8 (PILOTIII_SIO_INDEX_PORT , PILOTIII_LOCK); //Exit config mode.
+ }
+
+
+ return RETURN_SUCCESS;
+}
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c
new file mode 100644
index 0000000000..19593cfadf
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c
@@ -0,0 +1,42 @@
+/** @file
+ DXE board-specific ACPI functionality.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+EFI_STATUS
+EFIAPI
+N1xxWUBoardUpdateAcpiTable (
+ IN OUT EFI_ACPI_COMMON_HEADER *Table,
+ IN OUT EFI_ACPI_TABLE_VERSION *Version
+ );
+
+EFI_STATUS
+EFIAPI
+BoardUpdateAcpiTable (
+ IN OUT EFI_ACPI_COMMON_HEADER *Table,
+ IN OUT EFI_ACPI_TABLE_VERSION *Version
+ )
+{
+ N1xxWUBoardUpdateAcpiTable (Table, Version);
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c
new file mode 100644
index 0000000000..7eb19ba594
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c
@@ -0,0 +1,49 @@
+/** @file
+ DXE multi-board ACPI table support functionality.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/MultiBoardAcpiSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <N1xxWUId.h>
+
+EFI_STATUS
+EFIAPI
+N1xxWUBoardUpdateAcpiTable (
+ IN OUT EFI_ACPI_COMMON_HEADER *Table,
+ IN OUT EFI_ACPI_TABLE_VERSION *Version
+ );
+
+BOARD_ACPI_TABLE_FUNC mN1xxWUBoardAcpiTableFunc = {
+ N1xxWUBoardUpdateAcpiTable
+};
+
+EFI_STATUS
+EFIAPI
+DxeN1xxWUMultiBoardAcpiSupportLibConstructor (
+ VOID
+ )
+{
+ if (LibPcdGetSku () == BoardIdN1xxWU) {
+ return RegisterBoardAcpiTableFunc (&mN1xxWUBoardAcpiTableFunc);
+ }
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeN1xxWUAcpiTableLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeN1xxWUAcpiTableLib.c
new file mode 100644
index 0000000000..9137bed899
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeN1xxWUAcpiTableLib.c
@@ -0,0 +1,80 @@
+/** @file
+ Clevo N1xxWU board DXE ACPI table functionality.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/AslUpdateLib.h>
+#include <Protocol/GlobalNvsArea.h>
+
+#include <N1xxWUId.h>
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_GLOBAL_NVS_AREA_PROTOCOL mGlobalNvsArea;
+
+VOID
+N1xxWUUpdateGlobalNvs (
+ VOID
+ )
+{
+
+ //
+ // Allocate and initialize the NVS area for SMM and ASL communication.
+ //
+ mGlobalNvsArea.Area = (VOID *)(UINTN)PcdGet64 (PcdAcpiGnvsAddress);
+
+ //
+ // Update global NVS area for ASL and SMM init code to use
+ //
+
+ //
+ // Enable PowerState
+ //
+ mGlobalNvsArea.Area->PowerState = 1; // AC =1; for mobile platform, will update this value in SmmPlatform.c
+
+ mGlobalNvsArea.Area->NativePCIESupport = PcdGet8 (PcdPciExpNative);
+
+ //
+ // Enable APIC
+ //
+ mGlobalNvsArea.Area->ApicEnable = GLOBAL_NVS_DEVICE_ENABLE;
+
+ //
+ // Low Power S0 Idle - Enabled/Disabled
+ //
+ mGlobalNvsArea.Area->LowPowerS0Idle = PcdGet8 (PcdLowPowerS0Idle);
+
+ mGlobalNvsArea.Area->Ps2MouseEnable = FALSE;
+ mGlobalNvsArea.Area->Ps2KbMsEnable = PcdGet8 (PcdPs2KbMsEnable);
+}
+
+EFI_STATUS
+EFIAPI
+N1xxWUBoardUpdateAcpiTable (
+ IN OUT EFI_ACPI_COMMON_HEADER *Table,
+ IN OUT EFI_ACPI_TABLE_VERSION *Version
+ )
+{
+ if (Table->Signature == EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {
+ N1xxWUUpdateGlobalNvs ();
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c
new file mode 100644
index 0000000000..99dae10e57
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c
@@ -0,0 +1,68 @@
+/** @file
+ Clevo N1xxWU board SMM ACPI table enable/disable functionality.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+EFI_STATUS
+EFIAPI
+N1xxWUBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+N1xxWUBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+BoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ SiliconEnableAcpi (EnableSci);
+ return N1xxWUBoardEnableAcpi (EnableSci);
+}
+
+EFI_STATUS
+EFIAPI
+BoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ SiliconDisableAcpi (DisableSci);
+ return N1xxWUBoardDisableAcpi (DisableSci);
+}
+
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
new file mode 100644
index 0000000000..19de0b842e
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
@@ -0,0 +1,87 @@
+/** @file
+ SMM multi-board ACPI support functionality.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/MultiBoardAcpiSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <N1xxWUId.h>
+
+EFI_STATUS
+EFIAPI
+N1xxWUBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+N1xxWUBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+N1xxWUMultiBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ SiliconEnableAcpi (EnableSci);
+ return N1xxWUBoardEnableAcpi (EnableSci);
+}
+
+EFI_STATUS
+EFIAPI
+N1xxWUMultiBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ SiliconDisableAcpi (DisableSci);
+ return N1xxWUBoardDisableAcpi (DisableSci);
+}
+
+BOARD_ACPI_ENABLE_FUNC mN1xxWUBoardAcpiEnableFunc = {
+ N1xxWUMultiBoardEnableAcpi,
+ N1xxWUMultiBoardDisableAcpi,
+};
+
+EFI_STATUS
+EFIAPI
+SmmN1xxWUMultiBoardAcpiSupportLibConstructor (
+ VOID
+ )
+{
+ if (LibPcdGetSku () == BoardIdN1xxWU) {
+ return RegisterBoardAcpiEnableFunc (&mN1xxWUBoardAcpiEnableFunc);
+ }
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmN1xxWUAcpiEnableLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmN1xxWUAcpiEnableLib.c
new file mode 100644
index 0000000000..82d5c40bf2
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmN1xxWUAcpiEnableLib.c
@@ -0,0 +1,45 @@
+/** @file
+ Platform Hook Library instances
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <N1xxWUId.h>
+
+EFI_STATUS
+EFIAPI
+N1xxWUBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ // enable additional board register
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+N1xxWUBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ // enable additional board register
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
new file mode 100644
index 0000000000..93765b1ae3
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
@@ -0,0 +1,174 @@
+/** @file
+ SMM ACPI enable library.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <PchAccess.h>
+#include <Library/MmPciLib.h>
+#include <Library/PchCycleDecodingLib.h>
+
+/**
+ Clear Port 80h
+
+ SMI handler to enable ACPI mode
+
+ Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI
+
+ Disables the SW SMI Timer.
+ ACPI events are disabled and ACPI event status is cleared.
+ SCI mode is then enabled.
+
+ Clear SLP SMI status
+ Enable SLP SMI
+
+ Disable SW SMI Timer
+
+ Clear all ACPI event status and disable all ACPI events
+
+ Disable PM sources except power button
+ Clear status bits
+
+ Disable GPE0 sources
+ Clear status bits
+
+ Disable GPE1 sources
+ Clear status bits
+
+ Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+
+ Enable SCI
+**/
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ UINT32 OutputValue;
+ UINT32 SmiEn;
+ UINT32 SmiSts;
+ UINT32 ULKMC;
+ UINTN LpcBaseAddress;
+ UINT16 AcpiBaseAddr;
+ UINT32 Pm1Cnt;
+
+ LpcBaseAddress = MmPciBase (
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_LPC,
+ PCI_FUNCTION_NUMBER_PCH_LPC
+ );
+
+ //
+ // Get the ACPI Base Address
+ //
+ PchAcpiBaseGet (&AcpiBaseAddr);
+
+ //
+ // BIOS must also ensure that CF9GR is cleared and locked before handing control to the
+ // OS in order to prevent the host from issuing global resets and resetting ME
+ //
+ // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global Reset
+ // MmioWrite32 (
+ // PmcBaseAddress + R_PCH_PMC_ETR3),
+ // PmInit);
+
+ //
+ // Clear Port 80h
+ //
+ IoWrite8 (0x80, 0);
+
+ //
+ // Disable SW SMI Timer and clean the status
+ //
+ SmiEn = IoRead32 (AcpiBaseAddr + R_PCH_SMI_EN);
+ SmiEn &= ~(B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB);
+ IoWrite32 (AcpiBaseAddr + R_PCH_SMI_EN, SmiEn);
+
+ SmiSts = IoRead32 (AcpiBaseAddr + R_PCH_SMI_STS);
+ SmiSts |= B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB;
+ IoWrite32 (AcpiBaseAddr + R_PCH_SMI_STS, SmiSts);
+
+ //
+ // Disable port 60/64 SMI trap if they are enabled
+ //
+ ULKMC = MmioRead32 (LpcBaseAddress + R_PCH_LPC_ULKMC) & ~(B_PCH_LPC_ULKMC_60REN | B_PCH_LPC_ULKMC_60WEN | B_PCH_LPC_ULKMC_64REN | B_PCH_LPC_ULKMC_64WEN | B_PCH_LPC_ULKMC_A20PASSEN);
+ MmioWrite32 (LpcBaseAddress + R_PCH_LPC_ULKMC, ULKMC);
+
+ //
+ // Disable PM sources except power button
+ //
+ IoWrite16 (AcpiBaseAddr + R_PCH_ACPI_PM1_EN, B_PCH_ACPI_PM1_EN_PWRBTN);
+
+ //
+ // Clear PM status except Power Button status for RapidStart Resume
+ //
+ IoWrite16 (AcpiBaseAddr + R_PCH_ACPI_PM1_STS, 0xFEFF);
+
+ //
+ // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+ //
+ IoWrite8 (R_PCH_RTC_INDEX_ALT, R_PCH_RTC_REGD);
+ IoWrite8 (R_PCH_RTC_TARGET_ALT, 0x0);
+
+ //
+ // Write ALT_GPI_SMI_EN to disable GPI1 (SMC_EXTSMI#)
+ //
+ OutputValue = IoRead32 (AcpiBaseAddr + 0x38);
+ OutputValue = OutputValue & ~(1 << (UINTN) PcdGet8 (PcdSmcExtSmiBitPosition));
+ IoWrite32 (AcpiBaseAddr + 0x38, OutputValue);
+
+
+ //
+ // Enable SCI
+ //
+ if (EnableSci) {
+ Pm1Cnt = IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT);
+ Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN;
+ IoWrite32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ UINT16 AcpiBaseAddr;
+ UINT32 Pm1Cnt;
+
+ //
+ // Get the ACPI Base Address
+ //
+ PchAcpiBaseGet (&AcpiBaseAddr);
+
+ //
+ // Disable SCI
+ //
+ if (DisableSci) {
+ Pm1Cnt = IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT);
+ Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SCI_EN;
+ IoWrite32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUGpioTable.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUGpioTable.c
new file mode 100644
index 0000000000..bc7554ae2b
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUGpioTable.c
@@ -0,0 +1,375 @@
+/** @file
+ GPIO definition table for N1xxWU
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _N1_XX_WU_GPIO_TABLE_H_
+#define _N1_XX_WU_GPIO_TABLE_H_
+
+#include <PiPei.h>
+#include <GpioPinsSklLp.h>
+#include <Library/GpioLib.h>
+#include <GpioConfig.h>
+#include <IoExpander.h>
+
+
+#define END_OF_GPIO_TABLE 0xFFFFFFFF
+
+GPIO_INIT_CONFIG mGpioTableN1xxWU[] =
+{
+//skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//H_RCIN_N
+//skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0
+//skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1
+//skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2
+//skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3
+//skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//LPC_FRAME_ESPI_CS_N
+//skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//INT_SERIRQ
+ {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_S0ix_R_N
+// skip for PM_CLKRUN_N {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_CLKRUN_N
+//skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK
+// skip for PCH_CLK_PCI_TPM {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//PCH_CLK_PCI_TPM
+ {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//EC_HID_INTR
+ {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N
+//skip for SUS_PWR_ACK_R {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SUS_PWR_ACK_R
+//skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N
+//skip for SUSACK_R_N {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SUSACK_R_N
+ {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_SEL
+ {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_EN_N
+ {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_0_SENSOR
+ {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_1_SENSOR
+ {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_2_SENSOR
+ {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CHUB_IRQ
+ {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP_N
+ {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//FPS_DRDY
+ {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID0
+ {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID1
+ {GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRALERTB
+ {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}},//TCH_PAD_INTR_R_N
+ {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_KILL_N
+ {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_BT_UART_WAKE_N
+ // {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT1_N
+ // {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT2_LAN_N
+ // {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N
+ // {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WIGIG_N
+ // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WLAN_N
+ {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EXT_PWR_GATEB
+ {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP_S0_N
+ {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST_N
+ {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_PWREN
+ // {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_DFU, NOT OWNED BY BIOS
+ {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N
+ {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//TBT_CIO_PLUG_EVENT_N
+ {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//PCH_SLOT1_WAKE_N
+ {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GSPI1_CS_R1_N
+ {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_CLK_R1
+ {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MISO_R1
+ {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1
+ {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N
+ {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK
+ {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_DATA
+ {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N
+ {GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CLK
+ {GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DATA
+ {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N
+ {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CLK, OWNED BY ME
+ {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_DATA, OWNED BY ME
+ {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RXD
+ {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_TXD
+ {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RTS_N
+ {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_CTS_N
+ {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD
+ {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD
+ {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N
+ {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N
+ {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SDA
+ {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SCL
+ {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SDA
+ {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SCL
+ {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RXD
+ {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_TXD
+ {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RTS_N
+ {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_CTS_N
+ {GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CS_N
+ {GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CLK
+ {GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MISO
+ {GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MOSI
+ {GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FLASH_STROBE
+ {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SDA
+ {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SCL
+ {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SDA
+ {GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SCL
+ {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//HOME_BTN
+ {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SCREEN_LOCK_PCH
+ {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_UP_PCH
+ {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_DOWN_PCH
+ {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA
+ {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK
+ {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RTS_N
+ {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N
+ {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_1
+ {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DMIC_DATA_1
+ {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_0
+ {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DMIC_DATA_0
+ {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO2
+ {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO3
+ {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCLK
+ {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//SPI_TPM_HDR_IRQ_N
+ {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_ODD_PRSNT_N
+ {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N
+ {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_DFU_N
+ {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_RESET
+ {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R
+ // {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R, NOT OWNED BY BIOS
+ {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SATA_LED_N
+ {GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_0_WP1_OTG_N
+ {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_1_WP4_N
+ {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N
+ // {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_IRQ, NOT OWNED BY BIOS
+ {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HPD_Q
+ {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HPD_Q
+ {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNone}},//SMC_EXTSMI_R_N
+ {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//SMC_RUNTIME_SCI_R_N
+ {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD
+ {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CTRL_CLK
+ {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_CTRL_DATA
+ {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CTRL_CLK
+ {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_CTRL_DATA
+ {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_CODEC_IRQ
+ {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_RST_N
+ {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SCLK
+ {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SFRM
+ {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TXD
+ {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RXD
+ {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA
+ {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL
+ {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA
+ {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL
+ {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA
+ {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL
+ {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA
+ {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL
+ {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD
+ {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA0
+ {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA1
+ {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA2
+ {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA3
+ {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA4
+ {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA5
+ {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA6
+ {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA7
+ {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCLK
+ {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK
+ {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET
+ {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD
+ {GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA0
+ {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA1
+ {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA2
+ {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA3
+ {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB
+ {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK
+ {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP
+ {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N
+ {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R
+ {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N
+ {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R_N
+ {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N
+ {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N
+ {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N
+ {GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_INTRUDET_N
+ {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK
+ {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_N
+ {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N
+ {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENABLE
+ {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of Table
+};
+
+UINT16 mGpioTableN1xxWUSize = sizeof (mGpioTableN1xxWU) / sizeof (GPIO_INIT_CONFIG) - 1;
+
+GPIO_INIT_CONFIG mGpioTableN1xxWUUcmcDevice[] =
+{
+ { GPIO_SKL_LP_GPP_B0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone } }, //GPP_B0
+ { GPIO_SKL_LP_GPP_B1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone } }, //GPP_B1
+};
+
+UINT16 mGpioTableN1xxWUUcmcDeviceSize = sizeof (mGpioTableN1xxWUUcmcDevice) / sizeof (GPIO_INIT_CONFIG);
+
+GPIO_INIT_CONFIG mGpioTableN1xxWUTouchpanel =
+ {GPIO_SKL_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}};
+
+GPIO_INIT_CONFIG mGpioTableN1xxWUSdhcSidebandCardDetect =
+ {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntBothEdge, GpioHostDeepReset, GpioTermNone}}; //SD_CDB D3
+
+//IO Expander Table for SKL RVP7, RVP13 and RVP15
+IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[] =
+{
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//EINK_PWREN_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//DGPU_PRSNT_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SW_GFX_PWERGD_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P26
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P27
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP4_PWREN_IOEXP
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_OTG_WP1_PWREN_IOEXP
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED}//M.2_WIGIG_PWREN_IOEXP
+};
+
+UINT16 mGpioTableIoExpanderSize = sizeof (mGpioTableIoExpander) / sizeof (IO_EXPANDER_GPIO_CONFIG);
+
+//IO Expander Table for KBL -Refresh
+IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeRDdr4[] =
+{
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//Unused pin
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RTD3_USB_PD1_PWR_EN
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//HRESET_PD1_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N
+ //{IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_RST_CNTRL_R
+ // We want the initial state to be high.
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_RST_CNTRL_R
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_WAKE_CTRL_R_N
+ // Turn off WWAN power and will turn it on later.
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_PWREN_IOEXP
+};
+UINT16 mGpioTableIoExpanderSizeKabylakeRDdr4 = sizeof (mGpioTableIoExpanderKabylakeRDdr4) / sizeof (IO_EXPANDER_GPIO_CONFIG);
+
+//IO Expander Table for KBL -kc
+IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeKcDdr3[] =
+{
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//EINK_PWREN_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P26
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P27
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP4_PWREN_IOEXP
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_OTG_WP1_PWREN_IOEXP
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_PWREN_IOEXP
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FPS_LOCK_N
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_FLEX_PWREN
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB_UART_SEL
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_DOCK_PWREN_IOEXP_R
+};
+UINT16 mGpioTableIoExpanderSizeKabylakeKcDdr3 = sizeof (mGpioTableIoExpanderKabylakeKcDdr3) / sizeof (IO_EXPANDER_GPIO_CONFIG);
+//IO Expander Table Full table for N 1XX WU
+IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderN1xxWU[] =
+{
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//EINK_PWREN_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//DGPU_PRSNT_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED },//SW_GFX_DGPU_SEL (KBL_RVP3_BOARD)
+//{IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP (SKL_RVP3_BOARD)
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SW_GFX_PWERGD_IOEXP
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P26
+ {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P27
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP4_PWREN_IOEXP
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_INPUT, IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED },//Not Connected (KBK_RVP3_BOARD)
+//{IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_OTG_WP1_PWREN_IOEXP (SKL_RVP3_BOARD)
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_PWREN_IOEXP
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN (KBL_RVP3_BOARD)
+ {IO_EXPANDER_1, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FPS_LOCK_N (KBL_RVP3_BOARD)
+};
+
+UINT16 mGpioTableIoExpanderN1xxWUSize = sizeof (mGpioTableIoExpanderN1xxWU) / sizeof (IO_EXPANDER_GPIO_CONFIG);
+
+#endif // _N1_XX_WU_GPIO_TABLE_H_
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUHdaVerbTables.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUHdaVerbTables.c
new file mode 100644
index 0000000000..28c906e560
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUHdaVerbTables.c
@@ -0,0 +1,238 @@
+/** @file
+ HDA Verb table for N1xxWU
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _N1_XX_WU_HDA_VERB_TABLES_H_
+#define _N1_XX_WU_HDA_VERB_TABLES_H_
+
+#include <Ppi/SiPolicy.h>
+
+HDAUDIO_VERB_TABLE HdaVerbTableAlc286Rvp3 = HDAUDIO_VERB_TABLE_INIT (
+ //
+ // VerbTable: (Realtek ALC286) for RVP3
+ // Revision ID = 0xff
+ // Codec Verb Table for SKL PCH boards
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0286
+ //
+ 0x10EC, 0x0286,
+ 0xFF, 0xFF,
+ //===================================================================================================
+ //
+ // Realtek Semiconductor Corp.
+ //
+ //===================================================================================================
+
+ //Realtek High Definition Audio Configuration - Version : 5.0.2.9
+ //Realtek HD Audio Codec : ALC286
+ //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
+ //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0286&SUBSYS_10EC108E
+ //The number of verb command block : 16
+
+ // NID 0x12 : 0x411111F0
+ // NID 0x13 : 0x40000000
+ // NID 0x14 : 0x9017011F
+ // NID 0x17 : 0x90170110
+ // NID 0x18 : 0x03A11040
+ // NID 0x19 : 0x411111F0
+ // NID 0x1A : 0x411111F0
+ // NID 0x1D : 0x4066A22D
+ // NID 0x1E : 0x411111F0
+ // NID 0x21 : 0x03211020
+
+
+ //===== HDA Codec Subsystem ID Verb-table =====
+ //HDA Codec Subsystem ID : 0x10EC108E
+ 0x0017208E,
+ 0x00172110,
+ 0x001722EC,
+ 0x00172310,
+
+ //===== Pin Widget Verb-table =====
+ //Widget node 0x01 :
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ //Pin widget 0x12 - DMIC
+ 0x01271CF0,
+ 0x01271D11,
+ 0x01271E11,
+ 0x01271F41,
+ //Pin widget 0x13 - DMIC
+ 0x01371C00,
+ 0x01371D00,
+ 0x01371E00,
+ 0x01371F40,
+ //Pin widget 0x14 - SPEAKER-OUT (Port-D)
+ 0x01771C1F,
+ 0x01771D01,
+ 0x01771E17,
+ 0x01771F90,
+ //Pin widget 0x17 - I2S-OUT
+ 0x01771C10,
+ 0x01771D01,
+ 0x01771E17,
+ 0x01771F90,
+ //Pin widget 0x18 - MIC1 (Port-B)
+ 0x01871C40,
+ 0x01871D10,
+ 0x01871EA1,
+ 0x01871F03,
+ //Pin widget 0x19 - I2S-IN
+ 0x01971CF0,
+ 0x01971D11,
+ 0x01971E11,
+ 0x01971F41,
+ //Pin widget 0x1A - LINE1 (Port-C)
+ 0x01A71CF0,
+ 0x01A71D11,
+ 0x01A71E11,
+ 0x01A71F41,
+ //Pin widget 0x1D - PC-BEEP
+ 0x01D71C2D,
+ 0x01D71DA2,
+ 0x01D71E66,
+ 0x01D71F40,
+ //Pin widget 0x1E - S/PDIF-OUT
+ 0x01E71CF0,
+ 0x01E71D11,
+ 0x01E71E11,
+ 0x01E71F41,
+ //Pin widget 0x21 - HP-OUT (Port-A)
+ 0x02171C20,
+ 0x02171D10,
+ 0x02171E21,
+ 0x02171F03,
+ //Widget node 0x20 :
+ 0x02050071,
+ 0x02040014,
+ 0x02050010,
+ 0x02040C22,
+ //Widget node 0x20 - 1 :
+ 0x0205004F,
+ 0x02045029,
+ 0x0205004F,
+ 0x02045029,
+ //Widget node 0x20 - 2 :
+ 0x0205002B,
+ 0x02040DD0,
+ 0x0205002D,
+ 0x02047020,
+ //Widget node 0x20 - 3 :
+ 0x0205000E,
+ 0x02046C80,
+ 0x01771F90,
+ 0x01771F90,
+ //TI AMP settings :
+ 0x02050022,
+ 0x0204004C,
+ 0x02050023,
+ 0x02040000,
+ 0x02050025,
+ 0x02040000,
+ 0x02050026,
+ 0x0204B010,
+
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+
+ 0x02050022,
+ 0x0204004C,
+ 0x02050023,
+ 0x02040002,
+ 0x02050025,
+ 0x02040011,
+ 0x02050026,
+ 0x0204B010,
+
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+
+ 0x02050022,
+ 0x0204004C,
+ 0x02050023,
+ 0x0204000D,
+ 0x02050025,
+ 0x02040010,
+ 0x02050026,
+ 0x0204B010,
+
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+
+ 0x02050022,
+ 0x0204004C,
+ 0x02050023,
+ 0x02040025,
+ 0x02050025,
+ 0x02040008,
+ 0x02050026,
+ 0x0204B010,
+
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+
+ 0x02050022,
+ 0x0204004C,
+ 0x02050023,
+ 0x02040002,
+ 0x02050025,
+ 0x02040000,
+ 0x02050026,
+ 0x0204B010,
+
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+
+ 0x02050022,
+ 0x0204004C,
+ 0x02050023,
+ 0x02040003,
+ 0x02050025,
+ 0x02040000,
+ 0x02050026,
+ 0x0204B010
+);
+
+#endif // _N1_XX_WU_HDA_VERB_TABLES_H_
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUHsioPtssTables.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUHsioPtssTables.c
new file mode 100644
index 0000000000..5f71865469
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUHsioPtssTables.c
@@ -0,0 +1,111 @@
+/** @file
+ N1xxWU HSIO PTSS H File
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef N1_XX_WU_HSIO_PTSS_H_
+#define N1_XX_WU_HSIO_PTSS_H_
+
+#include <PchHsioPtssTables.h>
+
+#ifndef HSIO_PTSS_TABLE_SIZE
+#define HSIO_PTSS_TABLE_SIZE(A) A##_Size = sizeof (A) / sizeof (HSIO_PTSS_TABLES)
+#endif
+
+//BoardId N1xxWU
+HSIO_PTSS_TABLES PchLpHsioPtss_Cx_N1xxWU[] = {
+ {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+ {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoM2},
+ {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoM2},
+ {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
+ {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+ {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32) ~0x3F000000}, PchSataTopoDirectConnect},
+ {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoM2},
+ {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
+ {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
+ {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+ {{12, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+ {{13, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+ {{14, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+ {{15, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
+ {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoM2},
+ {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopox1},
+ {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
+ {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00322900, (UINT32) ~0x3F3F00}, PchSataTopoM2},
+ {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
+ {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00382C00, (UINT32) ~0x3F3F00}, PchSataTopoDirectConnect},
+ {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
+ {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoM2},
+ {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopox1},
+ {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
+ {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
+ {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}
+};
+
+UINT16 PchLpHsioPtss_Cx_N1xxWU_Size = sizeof(PchLpHsioPtss_Cx_N1xxWU) / sizeof(HSIO_PTSS_TABLES);
+
+HSIO_PTSS_TABLES PchLpHsioPtss_Bx_N1xxWU[] = {
+ {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+ {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchPcieTopoUnknown},
+ {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
+ {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+ {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32) ~0x3F000000}, PchSataTopoDirectConnect},
+ {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
+ {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
+ {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+ {{12, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+ {{13, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+ {{14, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+ {{15, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
+ {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopox1},
+ {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
+ {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00322900, (UINT32) ~0x3F3F00}, PchPcieTopoUnknown},
+ {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
+ {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00382C00, (UINT32) ~0x3F3F00}, PchSataTopoDirectConnect},
+ {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
+ {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopox1},
+ {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+ {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
+ {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
+ {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
+};
+
+UINT16 PchLpHsioPtss_Bx_N1xxWU_Size = sizeof(PchLpHsioPtss_Bx_N1xxWU) / sizeof(HSIO_PTSS_TABLES);
+
+#endif // N1_XX_WU_HSIO_PTSS_H_
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUSpdTable.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUSpdTable.c
new file mode 100644
index 0000000000..afc7315665
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUSpdTable.c
@@ -0,0 +1,432 @@
+/** @file
+ GPIO definition table for N1xxWU
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _N1_XX_WU_SPD_TABLE_H_
+#define _N1_XX_WU_SPD_TABLE_H_
+
+//
+// DQByteMap[0] - ClkDQByteMap:
+// If clock is per rank, program to [0xFF, 0xFF]
+// If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
+// If clock is shared by 2 ranks but does not go to all bytes,
+// Entry[i] defines which DQ bytes Group i services
+// DQByteMap[1] - CmdNDQByteMap: Entry[0] is CmdN/CAA and Entry[1] is CmdN/CAB
+// DQByteMap[2] - CmdSDQByteMap: Entry[0] is CmdS/CAA and Entry[1] is CmdS/CAB
+// DQByteMap[3] - CkeDQByteMap : Entry[0] is CKE /CAA and Entry[1] is CKE /CAB
+// For DDR, DQByteMap[3:1] = [0xFF, 0]
+// DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] since we have 1 CTL / rank
+// Variable only exists to make the code easier to use
+// DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] since we have 1 CA Vref
+// Variable only exists to make the code easier to use
+//
+//
+// DQ byte mapping to CMD/CTL/CLK, from the CPU side - for SKL RVP3, SKL SDS - used by SKL/KBL MRC
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqByteMapSklRvp3[2][6][2] = {
+ // Channel 0:
+ {
+ { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
+ { 0x00, 0xF0 }, // CmdN does not have CAA, CAB goes to Bytes[7:4]
+ { 0x0F, 0xF0 }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[7:4]
+ { 0x0F, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB
+ { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
+ { 0xFF, 0x00 } // CA Vref is one for all bytes
+ },
+ // Channel 1:
+ {
+ { 0x33, 0xCC }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
+ { 0x00, 0xCC }, // CmdN does not have CAA, CAB goes to Bytes[7:4]
+ { 0x33, 0xCC }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[7:4]
+ { 0x33, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB
+ { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
+ { 0xFF, 0x00 } // CA Vref is one for all bytes
+ }
+};
+
+//
+// DQS byte swizzling between CPU and DRAM - for SKL DOE RVP
+//
+
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqsMapCpu2DramSklRvp3[2][8] = {
+ { 0, 1, 3, 2, 4, 5, 6, 7 }, // Channel 0
+ { 1, 0, 4, 5, 2, 3, 6, 7 } // Channel 1
+};
+
+// Samsung K4E6E304ED-EGCF 178b QDP LPDDR3, 4Gb die (256Mx16), x16
+// or Hynix H9CCNNNBLTALAR-NUD
+// or similar
+// 1867, 14-17-17-40
+// 2 ranks per channel, 2 SDRAMs per rank, 8x4Gb = 4GB total per channel
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp16Spd[] = {
+ 0x24, ///< 0 Number of Serial PD Bytes Written / SPD Device Size
+ 0x20, ///< 1 SPD Revision
+ 0x0F, ///< 2 DRAM Device Type
+ 0x0E, ///< 3 Module Type
+ 0x14, ///< 4 SDRAM Density and Banks: 8 Banks, 4 Gb SDRAM density
+ 0x12, ///< 5 SDRAM Addressing: 14 Rows, 11 Columns
+ 0xB5, ///< 6 SDRAM Package Type: QDP, 1 Channel per die, Signal Loading Matrix 1
+ 0x00, ///< 7 SDRAM Optional Features
+ 0x00, ///< 8 SDRAM Thermal and Refresh Options
+ 0x00, ///< 9 Other SDRAM Optional Features
+ 0x00, ///< 10 Reserved - must be coded as 0x00
+ 0x03, ///< 11 Module Nominal Voltage, VDD
+ 0x0A, ///< 12 Module Organization, SDRAM width: 16 bits, 2 Ranks
+ 0x23, ///< 13 Module Memory Bus Width: 2 channels, 64 bit channel bus width
+ 0x00, ///< 14 Module Thermal Sensor
+ 0x00, ///< 15 Extended Module Type
+ 0x00, ///< 16 Reserved - must be coded as 0x00
+ 0x00, ///< 17 Timebases
+ 0x09, ///< 18 SDRAM Minimum Cycle Time (tCKmin): tCKmin = 1.071ns (LPDDR3-1867)
+ 0xFF, ///< 19 SDRAM Minimum Cycle Time (tCKmax)
+ 0xD4, ///< 20 CAS Latencies Supported, First Byte (tCK): 14, 12, 10, 8
+ 0x00, ///< 21 CAS Latencies Supported, Second Byte
+ 0x00, ///< 22 CAS Latencies Supported, Third Byte
+ 0x00, ///< 23 CAS Latencies Supported, Fourth Byte
+ 0x78, ///< 24 Minimum CAS Latency Time (tAAmin) = 14.994 ns
+ 0x00, ///< 25 Read and Write Latency Set Options
+ 0x90, ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin)
+ 0xA8, ///< 27 Minimum Row Precharge Delay Time for all banks (tRPab)
+ 0x90, ///< 28 Minimum Row Precharge Delay Time per bank (tRPpb)
+ 0x10, ///< 29 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Least Significant Byte
+ 0x04, ///< 30 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Most Significant Byte
+ 0xE0, ///< 31 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Least Significant Byte
+ 0x01, ///< 32 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Most Significant Byte
+ 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bit Mapping
+ 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bit Mapping
+ 0, 0, ///< 78 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0x00, ///< 120 Fine Offset for Minimum Row Precharge Delay Time per bank (tRPpb)
+ 0x00, ///< 121 Fine Offset for Minimum Row Precharge Delay Time for all banks (tRPab)
+ 0x00, ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+ 0xFA, ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin): 14.994 ns (LPDDR3-1867)
+ 0x7F, ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax): 32.002 ns
+ 0xCA, ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin): 1.071 ns (LPDDR-1867)
+ 0x00, ///< 126 CRC A
+ 0x00, ///< 127 CRC B
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 322 Module Manufacturing Location
+ 0x00, ///< 323 Module Manufacturing Date Year
+ 0x00, ///< 324 Module Manufacturing Date Week
+ 0x55, ///< 325 Module Serial Number A
+ 0x00, ///< 326 Module Serial Number B
+ 0x00, ///< 327 Module Serial Number C
+ 0x00, ///< 328 Module Serial Number D
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
+ 0x00, ///< 349 Module Revision Code
+ 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 352 DRAM Stepping
+ 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
+ 0, 0 ///< 510 - 511
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp16SpdSize = sizeof (mSkylakeRvp16Spd);
+
+//Hynix H9CCNNNBJTMLAR-NUD, DDP, LPDDR3, 8Gb die
+//1867
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp3Spd110[] = {
+ 0x91, ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
+ 0x20, ///< 1 SPD Revision
+ 0xF1, ///< 2 DRAM Device Type
+ 0x03, ///< 3 Module Type
+ 0x05, ///< 4 SDRAM Density and Banks, 8Gb
+ 0x19, ///< 5 SDRAM Addressing: 15 Rows, 10 Columns
+ 0x05, ///< 6 Module Nominal Voltage
+ 0x0B, ///< 7 Module Organization: 32 bits, 2 Ranks
+ 0x03, ///< 8 Module Memory Bus Width
+ 0x11, ///< 9 Fine Timebase (FTB) Dividend / Divisor
+ 0x01, ///< 10 Medium Timebase (MTB) Dividend
+ 0x08, ///< 11 Medium Timebase (MTB) Divisor
+ 0x09, ///< 12 SDRAM Minimum Cycle Time (tCKmin): tCKmin = 1.071 ns (LPDDR3-1867)
+ 0x00, ///< 13 Reserved0
+ 0x50, ///< 14 CAS Latencies supported (tCK): 14, 12, 10, 8 (LSB)
+ 0x05, ///< 15 CAS Latencies supported (tCK): 14, 12, 10, 8 (LSB)
+ 0x78, ///< 16 Minimum CAS Latency (tAAmin) = 14.994 ns
+ 0x78, ///< 17 Minimum Write Recovery Time (tWRmin)
+ 0x90, ///< 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
+ 0x50, ///< 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
+ 0x90, ///< 20 Minimum Row Precharge Delay Time (tRPmin)
+ 0x11, ///< 21 Upper Nibbles for tRAS and tRC
+ 0x50, ///< 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
+ 0xE0, ///< 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
+ 0x90, ///< 24 Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte
+ 0x06, ///< 25 Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant Byte
+ 0x3C, ///< 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
+ 0x3C, ///< 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+ 0x01, ///< 28 Upper Nibble for tFAW
+ 0x90, ///< 29 Minimum Four Activate Window Delay Time (tFAWmin)
+ 0x00, ///< 30 SDRAM Optional Features
+ 0x00, ///< 31 SDRAMThermalAndRefreshOptions
+ 0x00, ///< 32 ModuleThermalSensor
+ 0x00, ///< 33 SDRAM Device Type
+ 0xCA, ///< 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin): 1.071 ns (LPDDR3-1867)
+ 0xFA, ///< 35 Fine Offset for Minimum CAS Latency Time (tAAmin): 14.994 ns (LPDDR3-1867)
+ 0x00, ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+ 0x00, ///< 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
+ 0x00, ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
+ 0xA8, ///< 39 Row precharge time for all banks (tRPab)
+ 0x00, ///< 40 FTB for Row precharge time for all banks (tRPab)
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 41 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, ///< 60 - 61
+ 0x00, ///< 62 Reference Raw Card Used
+ 0x00, ///< 63 Address Mapping from Edge Connector to DRAM
+ 0x00, ///< 64 ThermalHeatSpreaderSolution
+ 0, 0, 0, 0, 0, ///< 65 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, ///< 110 - 116
+ 0x00, ///< 117 Module Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 118 Module Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 119 Module Manufacturing Location
+ 0x00, ///< 120 Module Manufacturing Date Year
+ 0x00, ///< 121 Module Manufacturing Date creation work week
+ 0x55, ///< 122 Module Serial Number A
+ 0x00, ///< 123 Module Serial Number B
+ 0x00, ///< 124 Module Serial Number C
+ 0x00, ///< 125 Module Serial Number D
+ 0x00, ///< 126 CRC A
+ 0x00 ///< 127 CRC B
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp3Spd110Size = sizeof (mSkylakeRvp3Spd110);
+
+//
+// Micron MT52L512M32D2PF 78b DDP LPDDR3, 8Gb die (256Mx32), x32
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mKblRSpdLpddr32133[] = {
+ 0x91, ///< 0 128 SPD bytes used, 256 total, CRC covers 0..116
+ 0x20, ///< 1 SPD Revision 2.0
+ 0xF1, ///< 2 DRAM Type: LPDDR3 SDRAM
+ 0x03, ///< 3 Module Type: SO-DIMM
+ 0x05, ///< 4 8 Banks, 8 Gb SDRAM density
+ 0x19, ///< 5 SDRAM Addressing: 15 Rows, 10 Columns
+ 0x05, ///< 6 Module Nominal Voltage VDD: 1.2v
+ 0x0B, ///< 7 SDRAM width: 32 bits, 2 Ranks
+ 0x03, ///< 8 SDRAM bus width: 64 bits, no ECC
+ 0x11, ///< 9 Fine Timebase (FTB) granularity: 1 ps
+ 0x01, ///< 10 Medium Timebase (MTB) : 0.125 ns
+ 0x08, ///< 11 Medium Timebase Divisor
+ 0x08, ///< 12 tCKmin = 0.938 ns (LPDDR3-2133)
+ 0x00, ///< 13 Reserved
+ 0x50, ///< 14 CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (LSB)
+ 0x15, ///< 15 CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (MSB)
+ 0x78, ///< 16 Minimum CAS Latency (tAAmin) = 15.008 ns
+ 0x78, ///< 17 tWR = 15 ns
+ 0x90, ///< 18 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0x50, ///< 19 tRRD = 10 ns
+ 0x90, ///< 20 Minimum row precharge time (tRPmin) = 18 ns
+ 0x11, ///< 21 Upper nibbles for tRAS and tRC
+ 0x50, ///< 22 tRASmin = 42 ns
+ 0xE0, ///< 23 tRCmin = (tRASmin + tRPmin) = 60 ns
+ 0x90, ///< 24 tRFCmin = (tRFCab) = 210 ns (8Gb)
+ 0x06, ///< 25 tRFCmin MSB
+ 0x3C, ///< 26 tWTRmin = 7.5 ns
+ 0x3C, ///< 27 tRTPmin = 7.5 ns
+ 0x01, ///< 28 tFAWmin upper nibble
+ 0x90, ///< 29 tFAWmin = 50 ns
+ 0x00, ///< 30 SDRAM Optional Features - none
+ 0x00, ///< 31 SDRAM Thermal / Refresh options - none
+ 0x00, ///< 32 ModuleThermalSensor
+ 0x00, ///< 33 SDRAM Device Type
+ 0xC2, ///< 34 FTB for tCKmin = 0.938 ns (LPDDR3-2133)
+ 0x08, ///< 35 FTB for tAAmin = 15.008 ns (LPDDR3-2133)
+ 0x00, ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+ 0x00, ///< 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
+ 0x00, ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
+ 0xA8, ///< 39 Row precharge time for all banks (tRPab)= 21 ns
+ 0x00, ///< 40 FTB for Row precharge time for all banks (tRPab) = 0
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 41 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, ///< 60 - 61
+ 0x00, ///< 62 Reference Raw Card Used
+ 0x00, ///< 63 Rank1 Mapping: Standard
+ 0x00, ///< 64 ThermalHeatSpreaderSolution
+ 0, 0, 0, 0, 0, ///< 65 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, ///< 110 - 116
+ 0x00, ///< 117 Module Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 118 Module Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 119 Module Manufacturing Location
+ 0x00, ///< 120 Module Manufacturing Date Year
+ 0x00, ///< 121 Module Manufacturing Date creation work week
+ 0x55, ///< 122 Module ID: Module Serial Number
+ 0x00, ///< 123 Module Serial Number B
+ 0x00, ///< 124 Module Serial Number C
+ 0x00, ///< 125 Module Serial Number D
+ 0x00, ///< 126 CRC A
+ 0x00 ///< 127 CRC B
+};
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mKblRSpdLpddr32133Size = sizeof (mKblRSpdLpddr32133);
+
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSpdLpddr32133[] = {
+ 0x24, ///< 0 Number of Serial PD Bytes Written / SPD Device Size
+ 0x01, ///< 1 SPD Revision
+ 0x0F, ///< 2 DRAM Device Type
+ 0x0E, ///< 3 Module Type
+ 0x15, ///< 4 SDRAM Density and Banks: 8 Banks, 8 Gb SDRAM density
+ 0x19, ///< 5 SDRAM Addressing: 15 Rows, 10 Columns
+ 0x90, ///< 6 SDRAM Package Type: QDP, 1 Channel per die, Signal Loading Matrix 1
+ 0x00, ///< 7 SDRAM Optional Features
+ 0x00, ///< 8 SDRAM Thermal and Refresh Options
+ 0x00, ///< 9 Other SDRAM Optional Features
+ 0x00, ///< 10 Reserved - must be coded as 0x00
+ 0x0B, ///< 11 Module Nominal Voltage, VDD
+ 0x0B, ///< 12 Module Organization, SDRAM width: 32 bits, 2 Ranks
+ 0x03, ///< 13 Module Memory Bus Width: 2 channels, 64 bit channel bus width
+ 0x00, ///< 14 Module Thermal Sensor
+ 0x00, ///< 15 Extended Module Type
+ 0x00, ///< 16 Reserved - must be coded as 0x00
+ 0x00, ///< 17 Timebases
+ 0x08, ///< 18 SDRAM Minimum Cycle Time (tCKmin)
+ 0xFF, ///< 19 SDRAM Minimum Cycle Time (tCKmax)
+ 0xD4, ///< 20 CAS Latencies Supported, First Byte
+ 0x01, ///< 21 CAS Latencies Supported, Second Byte
+ 0x00, ///< 22 CAS Latencies Supported, Third Byte
+ 0x00, ///< 23 CAS Latencies Supported, Fourth Byte
+ 0x78, ///< 24 Minimum CAS Latency Time (tAAmin)
+ 0x00, ///< 25 Read and Write Latency Set Options
+ 0x90, ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin)
+ 0xA8, ///< 27 Minimum Row Precharge Delay Time for all banks (tRPab)
+ 0x90, ///< 28 Minimum Row Precharge Delay Time per bank (tRPpb)
+ 0x90, ///< 29 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Least Significant Byte
+ 0x06, ///< 30 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Most Significant Byte
+ 0xD0, ///< 31 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Least Significant Byte
+ 0x02, ///< 32 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Most Significant Byte
+ 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bit Mapping
+ 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bit Mapping
+ 0, 0, ///< 78 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0x00, ///< 120 Fine Offset for Minimum Row Precharge Delay Time per bank (tRPpb)
+ 0x00, ///< 121 Fine Offset for Minimum Row Precharge Delay Time for all banks (tRPab)
+ 0x00, ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+ 0x08, ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)
+ 0x7F, ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax)
+ 0xC2, ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+ 0x00, ///< 126 CRC A
+ 0x00, ///< 127 CRC B
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 322 Module Manufacturing Location
+ 0x00, ///< 323 Module Manufacturing Date Year
+ 0x00, ///< 324 Module Manufacturing Date Week
+ 0x55, ///< 325 Module Serial Number A
+ 0x00, ///< 326 Module Serial Number B
+ 0x00, ///< 327 Module Serial Number C
+ 0x00, ///< 328 Module Serial Number D
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
+ 0x00, ///< 349 Module Revision Code
+ 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 352 DRAM Stepping
+ 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
+ 0, 0 ///< 510 - 511
+};
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSpdLpddr32133Size = sizeof (mSpdLpddr32133);
+
+#endif // _N1_XX_WU_SPD_TABLE_H_
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardInitPostMemLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardInitPostMemLib.c
new file mode 100644
index 0000000000..1433176ca8
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardInitPostMemLib.c
@@ -0,0 +1,45 @@
+/** @file
+ Board post-memory initialization.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+EFI_STATUS
+EFIAPI
+N1xxWUBoardInitBeforeSiliconInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+BoardInitBeforeSiliconInit (
+ VOID
+ )
+{
+ N1xxWUBoardInitBeforeSiliconInit ();
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitAfterSiliconInit (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardInitPreMemLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardInitPreMemLib.c
new file mode 100644
index 0000000000..2596880bfc
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardInitPreMemLib.c
@@ -0,0 +1,111 @@
+/** @file
+ Board post-memory initialization.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+EFI_STATUS
+EFIAPI
+N1xxWUBoardDetect (
+ VOID
+ );
+
+EFI_BOOT_MODE
+EFIAPI
+N1xxWUBoardBootModeDetect (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+N1xxWUBoardDebugInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+N1xxWUBoardInitBeforeMemoryInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+BoardDetect (
+ VOID
+ )
+{
+ N1xxWUBoardDetect ();
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardDebugInit (
+ VOID
+ )
+{
+ N1xxWUBoardDebugInit ();
+ return EFI_SUCCESS;
+}
+
+EFI_BOOT_MODE
+EFIAPI
+BoardBootModeDetect (
+ VOID
+ )
+{
+ return N1xxWUBoardBootModeDetect ();
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitBeforeMemoryInit (
+ VOID
+ )
+{
+ N1xxWUBoardInitBeforeMemoryInit ();
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitAfterMemoryInit (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitBeforeTempRamExit (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitAfterTempRamExit (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c
new file mode 100644
index 0000000000..c58842d9f4
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c
@@ -0,0 +1,46 @@
+/** @file
+ Multi-board post-memory initialization.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/MultiBoardInitSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <N1xxWUId.h>
+
+EFI_STATUS
+EFIAPI
+N1xxWUBoardInitBeforeSiliconInit (
+ VOID
+ );
+
+BOARD_POST_MEM_INIT_FUNC mN1xxWUBoardInitFunc = {
+ N1xxWUBoardInitBeforeSiliconInit,
+ NULL, // BoardInitAfterSiliconInit
+};
+
+EFI_STATUS
+EFIAPI
+PeiN1xxWUMultiBoardInitLibConstructor (
+ VOID
+ )
+{
+ if (LibPcdGetSku () == BoardIdN1xxWU) {
+ return RegisterBoardPostMemInit (&mN1xxWUBoardInitFunc);
+ }
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c
new file mode 100644
index 0000000000..a027b22e7d
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c
@@ -0,0 +1,88 @@
+/** @file
+ Board pre-memory initialization.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/MultiBoardInitSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <N1xxWUId.h>
+
+EFI_STATUS
+EFIAPI
+N1xxWUBoardDetect (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+N1xxWUMultiBoardDetect (
+ VOID
+ );
+
+EFI_BOOT_MODE
+EFIAPI
+N1xxWUBoardBootModeDetect (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+N1xxWUBoardDebugInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+N1xxWUBoardInitBeforeMemoryInit (
+ VOID
+ );
+
+BOARD_DETECT_FUNC mN1xxWUBoardDetectFunc = {
+ N1xxWUMultiBoardDetect
+};
+
+BOARD_PRE_MEM_INIT_FUNC mN1xxWUBoardPreMemInitFunc = {
+ N1xxWUBoardDebugInit,
+ N1xxWUBoardBootModeDetect,
+ N1xxWUBoardInitBeforeMemoryInit,
+ NULL, // BoardInitAfterMemoryInit
+ NULL, // BoardInitBeforeTempRamExit
+ NULL, // BoardInitAfterTempRamExit
+};
+
+EFI_STATUS
+EFIAPI
+N1xxWUMultiBoardDetect (
+ VOID
+ )
+{
+ N1xxWUBoardDetect ();
+ if (LibPcdGetSku () == BoardIdN1xxWU) {
+ RegisterBoardPreMemInit (&mN1xxWUBoardPreMemInitFunc);
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+PeiN1xxWUMultiBoardInitPreMemLibConstructor (
+ VOID
+ )
+{
+ return RegisterBoardDetect (&mN1xxWUBoardDetectFunc);
+}
\ No newline at end of file
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxWUDetect.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxWUDetect.c
new file mode 100644
index 0000000000..edda4da7a0
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxWUDetect.c
@@ -0,0 +1,72 @@
+/** @file
+ Clevo N1xxWU board detection.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <SaPolicyCommon.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PciLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/BoardInitLib.h>
+#include <PchAccess.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsSklLp.h>
+#include <GpioPinsSklH.h>
+#include <Library/GpioExpanderLib.h>
+#include <SioRegs.h>
+#include <Library/PchPcrLib.h>
+#include <Library/SiliconInitLib.h>
+
+#include "PeiN1xxWUInitLib.h"
+
+#include <ConfigBlock.h>
+#include <ConfigBlock/MemoryConfig.h>
+
+BOOLEAN
+IsN1xxWU (
+ VOID
+ )
+{
+ // TBD: Do detection - BoardIdN1xxWU v.s. BoardIdN1xxWU
+ return TRUE;
+}
+
+EFI_STATUS
+EFIAPI
+N1xxWUBoardDetect (
+ VOID
+ )
+{
+ if (LibPcdGetSku () != 0) {
+ return EFI_SUCCESS;
+ }
+
+ DEBUG ((EFI_D_INFO, "N1xxWUDetectionCallback\n"));
+
+ if (IsN1xxWU ()) {
+ LibPcdSetSku (BoardIdN1xxWU);
+
+ DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+ ASSERT (LibPcdGetSku() == BoardIdN1xxWU);
+ }
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxWUInitPostMemLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxWUInitPostMemLib.c
new file mode 100644
index 0000000000..5bd74035cb
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxWUInitPostMemLib.c
@@ -0,0 +1,215 @@
+/** @file
+ Clevo N1xxWU board post-memory initialization.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <SaPolicyCommon.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PciLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/BoardInitLib.h>
+#include <PchAccess.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsSklLp.h>
+#include <GpioPinsSklH.h>
+#include <Library/GpioExpanderLib.h>
+#include <SioRegs.h>
+#include <Library/PchPcrLib.h>
+#include <IoExpander.h>
+#include <Library/PcdLib.h>
+#include <Library/SiliconInitLib.h>
+
+#include "PeiN1xxWUInitLib.h"
+
+/**
+ N 1XX WU board configuration init function for PEI post memory phase.
+
+ PEI_BOARD_CONFIG_PCD_INIT
+
+ @param Content pointer to the buffer contain init information for board init.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_INVALID_PARAMETER The parameter is NULL.
+**/
+EFI_STATUS
+EFIAPI
+N1xxWUInit (
+ VOID
+ )
+{
+ PcdSet32S (PcdHdaVerbTable, (UINTN) &HdaVerbTableAlc286Rvp3);
+
+ //
+ // Assign the GPIO table with pin configs to be used for UCMC
+ //
+ PcdSet32S (PcdBoardUcmcGpioTable, (UINTN)mGpioTableN1xxWUUcmcDevice);
+ PcdSet16S (PcdBoardUcmcGpioTableSize, mGpioTableN1xxWUUcmcDeviceSize);
+
+ return EFI_SUCCESS;
+}
+
+#define EXPANDERS 2 // defines expander's quantity
+
+/**
+ Configures GPIO
+
+ @param[in] GpioTable Point to Platform Gpio table
+ @param[in] GpioTableCount Number of Gpio table entries
+
+**/
+VOID
+ConfigureGpio (
+ IN GPIO_INIT_CONFIG *GpioDefinition,
+ IN UINT16 GpioTableCount
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
+
+ Status = GpioConfigurePads (GpioTableCount, GpioDefinition);
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
+}
+
+VOID
+SetBit (
+ IN OUT UINT32 *Value,
+ IN UINT32 BitNumber,
+ IN BOOLEAN NewBitValue
+ )
+{
+ if (NewBitValue) {
+ *Value |= 1 << BitNumber;
+ } else {
+ *Value &= ~(1 << BitNumber);
+ }
+}
+
+/**
+ Configures IO Expander GPIO device
+
+ @param[in] IOExpGpioDefinition Point to IO Expander Gpio table
+ @param[in] IOExpGpioTableCount Number of Gpio table entries
+
+**/
+void
+ConfigureIoExpanderGpio (
+ IN IO_EXPANDER_GPIO_CONFIG *IoExpGpioDefinition,
+ IN UINT16 IoExpGpioTableCount
+ )
+{
+ UINT8 Index;
+ UINT32 Direction[EXPANDERS] = {0x00FFFFFF, 0x00FFFFFF};
+ UINT32 Level[EXPANDERS] = {0};
+ UINT32 Polarity[EXPANDERS] = {0};
+
+ // IoExpander {TCA6424A}
+ DEBUG ((DEBUG_INFO, "IO Expander Configuration Start\n"));
+ for (Index = 0; Index < IoExpGpioTableCount; Index++) { //Program IO Expander as per the table defined in PeiPlatformHooklib.c
+ SetBit(&Direction[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpGpioDefinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].GpioDirection);
+ SetBit(&Level[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpGpioDefinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].GpioLevel);
+ SetBit(&Polarity[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpGpioDefinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].GpioInversion);
+ }
+ for (Index = 0; Index < EXPANDERS; Index++) {
+ GpioExpBulkConfig(Index, Direction[Index], Polarity[Index], Level[Index]);
+ }
+ DEBUG ((DEBUG_INFO, "IO Expander Configuration End\n"));
+ return;
+}
+
+/**
+ Configure GPIO behind IoExpander.
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] NotifyDescriptor
+ @param[in] Interface
+
+ @retval EFI_SUCCESS Operation success.
+**/
+VOID
+ExpanderGpioInit (
+ VOID
+ )
+{
+ ConfigureIoExpanderGpio(mGpioTableIoExpander, mGpioTableIoExpanderSize);
+}
+
+/**
+ Configure single GPIO pad for touchpanel interrupt
+
+**/
+VOID
+TouchpanelGpioInit (
+ VOID
+ )
+{
+ GPIO_INIT_CONFIG* TouchpanelPad;
+ GPIO_PAD_OWN PadOwnVal;
+
+ PadOwnVal = 0;
+ TouchpanelPad = &mGpioTableN1xxWUTouchpanel;
+
+ GpioGetPadOwnership (TouchpanelPad->GpioPad, &PadOwnVal);
+ if (PadOwnVal == GpioPadOwnHost) {
+ GpioConfigurePads (1, TouchpanelPad);
+ }
+}
+
+
+/**
+ Configure GPIO
+
+**/
+VOID
+GpioInit (
+ VOID
+ )
+{
+ ConfigureGpio (mGpioTableN1xxWU, mGpioTableN1xxWUSize);
+
+ TouchpanelGpioInit();
+
+ return;
+}
+
+
+/**
+ Configure GPIO and SIO
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+EFIAPI
+N1xxWUBoardInitBeforeSiliconInit (
+ VOID
+ )
+{
+ N1xxWUInit ();
+
+ GpioInit ();
+ ExpanderGpioInit ();
+
+ ///
+ /// Do Late PCH init
+ ///
+ LateSiliconInit ();
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxWUInitPreMemLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxWUInitPreMemLib.c
new file mode 100644
index 0000000000..d9e2e659ab
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxWUInitPreMemLib.c
@@ -0,0 +1,236 @@
+/** @file
+ Clevo N1xxWU board pre-memory initialization.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <SaPolicyCommon.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PciLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/BoardInitLib.h>
+#include <PchAccess.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsSklLp.h>
+#include <GpioPinsSklH.h>
+#include <Library/GpioExpanderLib.h>
+#include <SioRegs.h>
+#include <Library/PchPcrLib.h>
+#include <Library/SiliconInitLib.h>
+
+#include "PeiN1xxWUInitLib.h"
+
+#include <ConfigBlock.h>
+#include <ConfigBlock/MemoryConfig.h>
+
+//
+// Reference RCOMP resistors on motherboard - for SKL RVP1
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp1[SA_MRC_MAX_RCOMP] = { 200, 81, 162 };
+//
+// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for SKL RVP1
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp1[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 40, 23, 40 };
+
+/**
+ N 1XX WU board configuration init function for PEI pre-memory phase.
+
+ PEI_BOARD_CONFIG_PCD_INIT
+
+ @param Content pointer to the buffer contain init information for board init.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_INVALID_PARAMETER The parameter is NULL.
+**/
+EFI_STATUS
+EFIAPI
+N1xxWUInitPreMem (
+ VOID
+ )
+{
+ PcdSet32S (PcdPcie0WakeGpioNo, 0);
+ PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
+ PcdSet32S (PcdPcie0HoldRstGpioNo, 8);
+ PcdSetBoolS (PcdPcie0HoldRstActive, TRUE);
+ PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
+ PcdSet32S (PcdPcie0PwrEnableGpioNo, 16);
+ PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
+
+ //
+ // HSIO PTSS Table
+ //
+ PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_Bx_N1xxWU);
+ PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_Bx_N1xxWU_Size);
+ PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_Cx_N1xxWU);
+ PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_Cx_N1xxWU_Size);
+
+ //
+ // DRAM related definition
+ //
+ PcdSet8S (PcdSaMiscUserBd, 5);
+
+ PcdSet8S (PcdMrcSpdAddressTable0, 0xA2);
+ PcdSet8S (PcdMrcSpdAddressTable1, 0xA0);
+ PcdSet8S (PcdMrcSpdAddressTable2, 0xA2);
+ PcdSet8S (PcdMrcSpdAddressTable3, 0xA0);
+
+ PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapSklRvp3);
+ PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapSklRvp3));
+ PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramSklRvp3);
+ PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramSklRvp3));
+ PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorSklRvp1);
+ PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetSklRvp1);
+
+ PcdSet32S (PcdMrcSpdData, (UINTN) mSkylakeRvp3Spd110);
+ PcdSet16S (PcdMrcSpdDataSize, mSkylakeRvp3Spd110Size);
+
+ PcdSetBoolS (PcdIoExpanderPresent, TRUE);
+
+ return EFI_SUCCESS;
+}
+
+#define SIO_RUNTIME_REG_BASE_ADDRESS 0x0680
+
+/**
+ Configures GPIO
+
+ @param[in] GpioTable Point to Platform Gpio table
+ @param[in] GpioTableCount Number of Gpio table entries
+
+**/
+VOID
+ConfigureGpio (
+ IN GPIO_INIT_CONFIG *GpioDefinition,
+ IN UINT16 GpioTableCount
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
+
+ Status = GpioConfigurePads (GpioTableCount, GpioDefinition);
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
+}
+
+/**
+ Configure GPIO Before Memory is not ready.
+
+**/
+VOID
+GpioInitPreMem (
+ VOID
+ )
+{
+ // ConfigureGpio ();
+}
+
+/**
+ Configure Super IO
+
+**/
+VOID
+SioInit (
+ VOID
+ )
+{
+ //
+ // Program and Enable Default Super IO Configuration Port Addresses and range
+ //
+ PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x10);
+
+ //
+ // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF;
+ //
+ PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS & (~0x7F), 0x10);
+
+ return;
+}
+
+/**
+ Configues the IC2 Controller on which GPIO Expander Communicates.
+ This Function is to enable the I2CGPIOExapanderLib to programm the Gpios
+ Complete intilization will be done in later Stage
+
+**/
+VOID
+EFIAPI
+I2CGpioExpanderInitPreMem(
+ VOID
+ )
+{
+ ConfigureSerialIoController (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden);
+ SerialIoI2cGpioInit (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden, PchSerialIoIs33V);
+}
+
+/**
+ Configure GPIO and SIO before memory ready
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+EFIAPI
+N1xxWUBoardInitBeforeMemoryInit (
+ VOID
+ )
+{
+ N1xxWUInitPreMem ();
+
+ //
+ // Configures the I2CGpioExpander
+ //
+ if (PcdGetBool (PcdIoExpanderPresent)) {
+ I2CGpioExpanderInitPreMem();
+ }
+
+ GpioInitPreMem ();
+ SioInit ();
+
+ ///
+ /// Do basic PCH init
+ ///
+ SiliconInit ();
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+N1xxWUBoardDebugInit (
+ VOID
+ )
+{
+ ///
+ /// Do Early PCH init
+ ///
+ EarlySiliconInit ();
+ return EFI_SUCCESS;
+}
+
+EFI_BOOT_MODE
+EFIAPI
+N1xxWUBoardBootModeDetect (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c
new file mode 100644
index 0000000000..56d2afd917
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c
@@ -0,0 +1,181 @@
+/** @file
+ DXE GOP policy initialization.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "DxeGopPolicyInit.h"
+#include <Protocol/GopPolicy.h>
+
+GLOBAL_REMOVE_IF_UNREFERENCED GOP_POLICY_PROTOCOL mGOPPolicy;
+GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mVbtSize = 0;
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mVbtAddress = 0;
+
+//
+// Function implementations
+//
+
+/**
+
+ @param[out] CurrentLidStatus
+
+ @retval EFI_SUCCESS
+ @retval EFI_UNSUPPORTED
+**/
+EFI_STATUS
+EFIAPI
+GetPlatformLidStatus (
+ OUT LID_STATUS *CurrentLidStatus
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+/**
+
+ @param[out] CurrentDockStatus
+
+ @retval EFI_SUCCESS
+ @retval EFI_UNSUPPORTED
+**/
+EFI_STATUS
+EFIAPI
+GetPlatformDockStatus (
+ OUT DOCK_STATUS CurrentDockStatus
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+
+/**
+
+ @param[out] VbtAddress
+ @param[out] VbtSize
+
+ @retval EFI_SUCCESS
+ @retval EFI_NOT_FOUND
+**/
+EFI_STATUS
+EFIAPI
+GetVbtData (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+ )
+{
+ EFI_STATUS Status;
+ UINTN FvProtocolCount;
+ EFI_HANDLE *FvHandles;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
+ UINTN Index;
+ UINT32 AuthenticationStatus;
+ UINT8 *Buffer;
+ UINTN VbtBufferSize;
+
+
+ Status = EFI_NOT_FOUND;
+ if ( mVbtAddress == 0) {
+ Fv = NULL;
+
+ Buffer = 0;
+ FvHandles = NULL;
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiFirmwareVolume2ProtocolGuid,
+ NULL,
+ &FvProtocolCount,
+ &FvHandles
+ );
+ if (!EFI_ERROR (Status)) {
+ for (Index = 0; Index < FvProtocolCount; Index++) {
+ Status = gBS->HandleProtocol (
+ FvHandles[Index],
+ &gEfiFirmwareVolume2ProtocolGuid,
+ (VOID **) &Fv
+ );
+ VbtBufferSize = 0;
+ Status = Fv->ReadSection (
+ Fv,
+ PcdGetPtr (PcdGraphicsVbtGuid),
+ EFI_SECTION_RAW,
+ 0,
+ (VOID **) &Buffer,
+ &VbtBufferSize,
+ &AuthenticationStatus
+ );
+ if (!EFI_ERROR (Status)) {
+ *VbtAddress = (EFI_PHYSICAL_ADDRESS)Buffer;
+ *VbtSize = (UINT32)VbtBufferSize;
+ mVbtAddress = *VbtAddress;
+ mVbtSize = *VbtSize;
+ Status = EFI_SUCCESS;
+ break;
+ }
+ }
+ } else {
+ Status = EFI_NOT_FOUND;
+ }
+
+ if (FvHandles != NULL) {
+ FreePool (FvHandles);
+ FvHandles = NULL;
+ }
+ } else {
+ *VbtAddress = mVbtAddress;
+ *VbtSize = mVbtSize;
+ Status = EFI_SUCCESS;
+ }
+
+ return Status;
+}
+
+
+
+/**
+Initialize GOP DXE Policy
+
+@param[in] ImageHandle Image handle of this driver.
+
+@retval EFI_SUCCESS Initialization complete.
+@retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+@retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+
+EFI_STATUS
+EFIAPI
+GopPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Initialize the EFI Driver Library
+ //
+ SetMem (&mGOPPolicy, sizeof (GOP_POLICY_PROTOCOL), 0);
+
+ mGOPPolicy.Revision = GOP_POLICY_PROTOCOL_REVISION_03;
+ mGOPPolicy.GetPlatformLidStatus = GetPlatformLidStatus;
+ mGOPPolicy.GetVbtData = GetVbtData;
+ mGOPPolicy.GetPlatformDockStatus = GetPlatformDockStatus;
+
+ //
+ // Install protocol to allow access to this Policy.
+ //
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &ImageHandle,
+ &gGopPolicyProtocolGuid,
+ &mGOPPolicy,
+ NULL
+ );
+
+ return Status;
+}
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c
new file mode 100644
index 0000000000..f7fb071e2b
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c
@@ -0,0 +1,71 @@
+/** @file
+ This file is the library for SA DXE Policy initialization.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "DxeSaPolicyInit.h"
+
+#define SA_VTD_RMRR_USB_LENGTH 0x20000
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mAddress;
+GLOBAL_REMOVE_IF_UNREFERENCED UINTN mSize;
+
+/**
+ Update RMRR Base and Limit Address for USB.
+
+**/
+VOID
+UpdateRmrrUsbAddress (
+ IN OUT SA_POLICY_PROTOCOL *SaPolicy
+ )
+{
+ EFI_STATUS Status;
+ MISC_DXE_CONFIG *MiscDxeConfig;
+
+ Status = GetConfigBlock ((VOID *)SaPolicy, &gMiscDxeConfigGuid, (VOID *)&MiscDxeConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ if (1) {
+ mSize = EFI_SIZE_TO_PAGES(SA_VTD_RMRR_USB_LENGTH);
+ mAddress = SIZE_4GB;
+
+ Status = (gBS->AllocatePages) (
+ AllocateMaxAddress,
+ EfiReservedMemoryType,
+ mSize,
+ &mAddress
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ MiscDxeConfig->RmrrUsbBaseAddress[0] = mAddress;
+ MiscDxeConfig->RmrrUsbBaseAddress[1] = mAddress + SA_VTD_RMRR_USB_LENGTH - 1;
+ }
+}
+
+/**
+ Get data for platform policy from setup options.
+
+ @param[in] SaPolicy The pointer to get SA Policy protocol instance
+
+ @retval EFI_SUCCESS Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxeSaPolicy (
+ IN OUT SA_POLICY_PROTOCOL *SaPolicy
+ )
+{
+ UpdateRmrrUsbAddress (SaPolicy);
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c
new file mode 100644
index 0000000000..a7ddfcc428
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c
@@ -0,0 +1,60 @@
+/** @file
+ DXE silicon policy update library.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/SiliconPolicyUpdateLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include "DxeSaPolicyInit.h"
+#include "DxeGopPolicyInit.h"
+
+/**
+ Performs silicon late policy update.
+
+ The meaning of Policy is defined by silicon code.
+ It could be the raw data, a handle, a Protocol, etc.
+
+ The input Policy must be returned by SiliconPolicyDoneLate().
+
+ In FSP or non-FSP path, the board may use additional way to get
+ the silicon policy data field based upon the input Policy.
+
+ @param[in, out] Policy Pointer to policy.
+
+ @return the updated policy.
+**/
+VOID *
+EFIAPI
+SiliconPolicyUpdateLate (
+ IN VOID *Policy
+ )
+{
+ SA_POLICY_PROTOCOL *SaPolicy;
+ EFI_STATUS Status;
+
+ SaPolicy = Policy;
+ UpdateDxeSaPolicy (SaPolicy);
+
+ if (PcdGetBool(PcdIntelGopEnable)) {
+ //
+ // GOP Dxe Policy Initialization
+ //
+ Status = GopPolicyInitDxe(gImageHandle);
+ DEBUG((DEBUG_INFO, "GOP Dxe Policy Initialization done\n"));
+ ASSERT_EFI_ERROR(Status);
+ }
+
+ return Policy;
+}
+
--
2.16.2.windows.1
next prev parent reply other threads:[~2019-01-31 6:12 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-31 6:11 [edk2-platforms/devel-MinPlatform][PATCH v4 0/7] Add initial ClevoOpenBoardPkg Michael Kubacki
2019-01-31 6:11 ` [edk2-platforms/devel-MinPlatform][PATCH v4 1/7] ClevoOpenBoardPkg: Add package and headers Michael Kubacki
2019-01-31 6:11 ` [edk2-platforms/devel-MinPlatform][PATCH v4 2/7] ClevoOpenBoardPkg/N1xxWU: Add headers Michael Kubacki
2019-01-31 6:11 ` [edk2-platforms/devel-MinPlatform][PATCH v4 3/7] ClevoOpenBoardPkg: Add library instances Michael Kubacki
2019-01-31 6:11 ` Michael Kubacki [this message]
2019-01-31 6:11 ` [edk2-platforms/devel-MinPlatform][PATCH v4 5/7] ClevoOpenBoardPkg: Add modules Michael Kubacki
2019-01-31 6:11 ` [edk2-platforms/devel-MinPlatform][PATCH v4 6/7] ClevoOpenBoardPkg/N1xxWU: Add DSC and build files Michael Kubacki
2019-01-31 6:11 ` [edk2-platforms/devel-MinPlatform][PATCH v4 7/7] ClevoOpenBoardPkg/N1xxWU: Update DEBUG print level macro usage Michael Kubacki
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