From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=141.146.126.79; helo=aserp2130.oracle.com; envelope-from=nikita.leshchenko@oracle.com; receiver=edk2-devel@lists.01.org Received: from aserp2130.oracle.com (aserp2130.oracle.com [141.146.126.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 83BF621CAD998 for ; Thu, 31 Jan 2019 02:08:18 -0800 (PST) Received: from pps.filterd (aserp2130.oracle.com [127.0.0.1]) by aserp2130.oracle.com (8.16.0.22/8.16.0.22) with SMTP id x0VA4Qo2154125 for ; Thu, 31 Jan 2019 10:08:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=corp-2018-07-02; bh=Axy7NwbR4pMOirgOTBKJG3v3oKF6UTVoQ37Yz2Fk3UQ=; b=Kpoa7BaGYYqHX4sc1IJ0SPbqqQeOHS1s/k86kT/Y8hMzZPsH7tqyRfJmvUAgPXdJ/n9C BDyiKyQZCkcmOBywlkW38u/fqPIZhFYODsB3l/fpyIqEZnbpNLv8oKGHJfMbouT3aVBM /E2UJr9CLqY/ie8yUWzuwUYuuLHPmF7IRxX1xDnnEFb6vm7qv8d2yhwD+crvYp5ATgJL vc0w4xedPKb7rB0xgKX2sSrkUakjsBQDgylpBz0SJQHKqxKntrkCbSEVeoNA8MLSw/6u QcQx3ExWQjlJ2SPF3Xv+YIvfYOrlk7x4MWPimDL/uD3B3g48m6i4C3OvcSNanZzXpdHq xQ== Received: from aserv0022.oracle.com (aserv0022.oracle.com [141.146.126.234]) by aserp2130.oracle.com with ESMTP id 2q8d2efvav-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Thu, 31 Jan 2019 10:08:17 +0000 Received: from userv0122.oracle.com (userv0122.oracle.com [156.151.31.75]) by aserv0022.oracle.com (8.14.4/8.14.4) with ESMTP id x0VA8GXe005044 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Thu, 31 Jan 2019 10:08:17 GMT Received: from abhmp0013.oracle.com (abhmp0013.oracle.com [141.146.116.19]) by userv0122.oracle.com (8.14.4/8.14.4) with ESMTP id x0VA8Gme019907 for ; Thu, 31 Jan 2019 10:08:16 GMT Received: from spark.ravello.local (/213.57.127.2) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Thu, 31 Jan 2019 02:08:16 -0800 From: Nikita Leshenko To: edk2-devel@lists.01.org Cc: liran.alon@oracle.com, Nikita Leshenko Date: Thu, 31 Jan 2019 12:07:21 +0200 Message-Id: <20190131100724.20907-12-nikita.leshchenko@oracle.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190131100724.20907-1-nikita.leshchenko@oracle.com> References: <20190131100724.20907-1-nikita.leshchenko@oracle.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=nai engine=5900 definitions=9152 signatures=668682 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901310080 Subject: [PATCH 11/14] OvmfPkg/MptScsiDxe: Initialize hardware X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Jan 2019 10:08:18 -0000 Content-Transfer-Encoding: 8bit Reset and send the IO controller initialization request. The reply is read back to complete the doorbell function but it isn't useful to us because it doesn't contain relevant data or status codes. See "LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller" technical manual for more information. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Nikita Leshenko Reviewed-by: Aaron Young Reviewed-by: Liran Alon --- OvmfPkg/MptScsiDxe/MptScsi.c | 234 +++++++++++++++++++++++++++++++++++ 1 file changed, 234 insertions(+) diff --git a/OvmfPkg/MptScsiDxe/MptScsi.c b/OvmfPkg/MptScsiDxe/MptScsi.c index 92c190499e..fbabeb22ca 100644 --- a/OvmfPkg/MptScsiDxe/MptScsi.c +++ b/OvmfPkg/MptScsiDxe/MptScsi.c @@ -33,10 +33,109 @@ #define LSI_SAS1068_PCI_DEVICE_ID 0x0054 #define LSI_SAS1068E_PCI_DEVICE_ID 0x0058 +#define MPT_REG_DOORBELL 0x00 +#define MPT_REG_WRITE_SEQ 0x04 +#define MPT_REG_HOST_DIAG 0x08 +#define MPT_REG_TEST 0x0c +#define MPT_REG_DIAG_DATA 0x10 +#define MPT_REG_DIAG_ADDR 0x14 +#define MPT_REG_ISTATUS 0x30 +#define MPT_REG_IMASK 0x34 +#define MPT_REG_REQ_Q 0x40 +#define MPT_REG_REP_Q 0x44 + +#define MPT_DOORBELL_RESET 0x40 +#define MPT_DOORBELL_HANDSHAKE 0x42 + +#define MPT_IMASK_DOORBELL 0x01 +#define MPT_IMASK_REPLY 0x08 + +#define MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST 0x00 +#define MPT_MESSAGE_HDR_FUNCTION_IOC_INIT 0x02 + +#define MPT_SG_ENTRY_TYPE_SIMPLE 0x01 + +#define MPT_IOC_WHOINIT_ROM_BIOS 0x02 + // // Runtime Structures // +typedef struct { + UINT8 WhoInit; + UINT8 Reserved1; + UINT8 ChainOffset; + UINT8 Function; + UINT8 Flags; + UINT8 MaxDevices; + UINT8 MaxBuses; + UINT8 MessageFlags; + UINT32 MessageContext; + UINT16 ReplyFrameSize; + UINT16 Reserved2; + UINT32 HostMfaHighAddr; + UINT32 SenseBufferHighAddr; +} __attribute__((aligned(8), packed)) MPT_IO_CONTROLLER_INIT_REQUEST; // Align required by HW +typedef struct { + UINT8 WhoInit; + UINT8 Reserved1; + UINT8 MessageLength; + UINT8 Function; + UINT8 Flags; + UINT8 MaxDevices; + UINT8 MaxBuses; + UINT8 MessageFlags; + UINT32 MessageContext; + UINT16 Reserved2; + UINT16 IOCStatus; + UINT32 IOCLogInfo; +} __attribute__((packed)) MPT_IO_CONTROLLER_INIT_REPLY; +typedef struct { + UINT8 TargetID; + UINT8 Bus; + UINT8 ChainOffset; + UINT8 Function; + UINT8 CDBLength; + UINT8 SenseBufferLength; + UINT8 Reserved; + UINT8 MessageFlags; + UINT32 MessageContext; + UINT8 LUN[8]; + UINT32 Control; + UINT8 CDB[16]; + UINT32 DataLength; + UINT32 SenseBufferLowAddress; +} __attribute__((packed)) MPT_SCSI_IO_REQUEST; +typedef struct { + UINT32 Length: 24; + UINT32 EndOfList: 1; + UINT32 Is64BitAddress: 1; + UINT32 BufferContainsData: 1; + UINT32 LocalAddress: 1; + UINT32 ElementType: 2; + UINT32 EndOfBuffer: 1; + UINT32 LastElement: 1; + UINT64 DataBufferAddress; +} __attribute__((packed)) MPT_SG_ENTRY_SIMPLE; +typedef struct { + UINT8 TargetID; + UINT8 Bus; + UINT8 MessageLength; + UINT8 Function; + UINT8 CDBLength; + UINT8 SenseBufferLength; + UINT8 Reserved; + UINT8 MessageFlags; + UINT32 MessageContext; + UINT8 SCSIStatus; + UINT8 SCSIState; + UINT16 IOCStatus; + UINT32 IOCLogInfo; + UINT32 TransferCount; + UINT32 SenseCount; + UINT32 ResponseInfo; +} __attribute__((aligned(8), packed)) MPT_SCSI_IO_ERROR_REPLY; // Align required by HW + #define MPT_SCSI_DEV_SIGNATURE SIGNATURE_32 ('M','P','T','S') typedef struct { UINT32 Signature; @@ -49,6 +148,134 @@ typedef struct { #define MPT_SCSI_FROM_PASS_THRU(PassThruPtr) \ CR (PassThruPtr, MPT_SCSI_DEV, PassThru, MPT_SCSI_DEV_SIGNATURE) +// +// Hardware functions +// + +STATIC +EFI_STATUS +Out32 ( + IN MPT_SCSI_DEV *Dev, + IN UINT32 Addr, + IN UINT32 Data + ) +{ + return Dev->PciIo->Io.Write ( + Dev->PciIo, + EfiPciIoWidthUint32, + 0, // BAR0 + Addr, 1, &Data); +} + +STATIC +EFI_STATUS +In32 ( + IN MPT_SCSI_DEV *Dev, + IN UINT32 Addr, + OUT UINT32 *Data + ) +{ + return Dev->PciIo->Io.Read ( + Dev->PciIo, + EfiPciIoWidthUint32, + 0, // BAR0 + Addr, 1, Data); +} + +STATIC +EFI_STATUS +MptDoorbell ( + IN MPT_SCSI_DEV *Dev, + IN UINT8 DoorbellFunc, + IN UINT8 DoorbellArg + ) +{ + return Out32 (Dev, MPT_REG_DOORBELL, (DoorbellFunc << 24) | (DoorbellArg << 16)); +} + +STATIC +EFI_STATUS +MptScsiReset ( + IN MPT_SCSI_DEV *Dev + ) +{ + EFI_STATUS Status; + + // Reset hardware + Status = MptDoorbell (Dev, MPT_DOORBELL_RESET, 0); + if (EFI_ERROR (Status)) { + return Status; + } + // Mask interrupts + Status = Out32 (Dev, MPT_REG_IMASK, MPT_IMASK_DOORBELL|MPT_IMASK_REPLY); + if (EFI_ERROR (Status)) { + return Status; + } + // Clear interrupt status + Status = Out32 (Dev, MPT_REG_ISTATUS, 0); + if (EFI_ERROR (Status)) { + return Status; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +MptScsiInit ( + IN MPT_SCSI_DEV *Dev + ) +{ + EFI_STATUS Status; + + Status = MptScsiReset (Dev); + if (EFI_ERROR (Status)) { + return Status; + } + + MPT_IO_CONTROLLER_INIT_REQUEST Req = { + .WhoInit = MPT_IOC_WHOINIT_ROM_BIOS, + .Function = MPT_MESSAGE_HDR_FUNCTION_IOC_INIT, + .MaxDevices = 1, + .MaxBuses = 1, + .ReplyFrameSize = sizeof (MPT_SCSI_IO_ERROR_REPLY), + }; + CONST UINT32 ReqSizeInDwords = sizeof (Req) / sizeof (UINT32); + MPT_IO_CONTROLLER_INIT_REPLY Reply = {0}; + + // Send controller init through doorbell + Status = MptDoorbell (Dev, MPT_DOORBELL_HANDSHAKE, ReqSizeInDwords); + if (EFI_ERROR (Status)) { + return Status; + } + Status = Dev->PciIo->Io.Write ( + Dev->PciIo, EfiPciIoWidthFifoUint32, 0, + MPT_REG_DOORBELL, ReqSizeInDwords, &Req); + if (EFI_ERROR (Status)) { + return Status; + } + + // Read reply through doorbell + // Each 32bit read produces 16bit of data + UINT16 *Reply16 = (UINT16 *) &Reply; + while (Reply16 != (UINT16 *) (&Reply + 1)) { + UINT32 Reply32; + Status = In32 (Dev, MPT_REG_DOORBELL, &Reply32); + if (EFI_ERROR (Status)) { + return Status; + } + *Reply16++ = (UINT16) Reply32; + } + + // Clear interrupts generated by doorbell reply + Status = Out32 (Dev, MPT_REG_ISTATUS, 0); + if (EFI_ERROR (Status)) { + return Status; + } + + return EFI_SUCCESS; +} + // // Ext SCSI Pass Thru // @@ -328,6 +555,11 @@ MptScsiControllerStart ( } PciAttributesChanged = TRUE; + Status = MptScsiInit (Dev); + if (EFI_ERROR (Status)) { + goto Done; + } + Dev->PassThruMode.AdapterId = MAX_UINT32; // Host adapter channel, doesn't exist Dev->PassThruMode.Attributes = EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_PHYSICAL @@ -407,6 +639,8 @@ MptScsiControllerStop ( &gEfiExtScsiPassThruProtocolGuid, &Dev->PassThru); + MptScsiReset (Dev); + Dev->PciIo->Attributes ( Dev->PciIo, EfiPciIoAttributeOperationEnable, -- 2.20.1