From: Ming Huang <ming.huang@linaro.org>
To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org,
edk2-devel@lists.01.org, graeme.gregory@linaro.org
Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com,
lersek@redhat.com, wanghuiqiang@huawei.com,
huangming23@huawei.com, zhangjinsong2@huawei.com,
huangdaode@hisilicon.com, john.garry@huawei.com,
xinliang.liu@linaro.org, zhangfeng56@huawei.com,
Ming Huang <ming.huang@linaro.org>
Subject: [PATCH edk2-platforms v1 11/16] Hisilicon/D06: Add Setup Item "Support DPC"
Date: Fri, 1 Feb 2019 21:34:31 +0800 [thread overview]
Message-ID: <20190201133436.10500-12-ming.huang@linaro.org> (raw)
In-Reply-To: <20190201133436.10500-1-ming.huang@linaro.org>
Add setup item "Support DPC" to enable or disable PCIe DPC
(Downstream Port Containment).
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
---
Silicon/Hisilicon/Include/Library/OemConfigData.h | 1 +
Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 2 -
Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 4 +
Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr | 197 +-------------------
Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni | 3 +-
5 files changed, 10 insertions(+), 197 deletions(-)
diff --git a/Silicon/Hisilicon/Include/Library/OemConfigData.h b/Silicon/Hisilicon/Include/Library/OemConfigData.h
index f120e3123c83..c0097d0829f0 100644
--- a/Silicon/Hisilicon/Include/Library/OemConfigData.h
+++ b/Silicon/Hisilicon/Include/Library/OemConfigData.h
@@ -49,6 +49,7 @@ typedef struct {
UINT8 OSWdtAction;
/*PCIe Config*/
UINT8 PcieSRIOVSupport;
+ UINT8 PcieDPCSupport;
UINT8 PciePort[PCIE_MAX_TOTAL_PORTS];
UINT8 PcieLinkSpeedPort[PCIE_MAX_TOTAL_PORTS];
UINT8 PcieLinkDeEmphasisPort[PCIE_MAX_TOTAL_PORTS];
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr
index 08236704fbfe..93ccb99bdc67 100644
--- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr
+++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr
@@ -62,11 +62,9 @@ formset
prompt = STRING_TOKEN(STR_IBMC_CONFIG_FORM_TITLE),
help = STRING_TOKEN(STR_IBMC_CONFIG_FORM_HELP);
- suppressif TRUE;
goto PCIE_CONFIG_FORM_ID,
prompt = STRING_TOKEN(STR_PCIE_CONFIG_FORM_TITLE),
help = STRING_TOKEN(STR_PCIE_CONFIG_FORM_HELP);
- endif;
goto MISC_CONFIG_FORM_ID,
prompt = STRING_TOKEN(STR_MISC_CONFIG_FORM_TITLE),
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c
index 6668103af027..be4ce8820f73 100644
--- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c
+++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c
@@ -290,6 +290,10 @@ OemConfigUiLibConstructor (
Configuration.OSWdtTimeout = 5;
Configuration.OSWdtAction = 1;
//
+ //Set the default value of the PCIe option
+ //
+ Configuration.PcieDPCSupport = 0;
+ //
//Set the default value of the Misc option
//
Configuration.EnableSmmu = 1;
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr
index 7cf7cdd29ba2..c65907fe846e 100644
--- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr
+++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr
@@ -17,203 +17,12 @@
form formid = PCIE_CONFIG_FORM_ID,
title = STRING_TOKEN (STR_PCIE_CONFIG_FORM_TITLE);
- goto VFR_FORMID_PCIE_SOCKET0,
- prompt = STRING_TOKEN (STR_PCIE_CPU_0_PROMPT),
- help = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP);
-
- goto VFR_FORMID_PCIE_SOCKET1,
- prompt = STRING_TOKEN (STR_PCIE_CPU_1_PROMPT),
- help = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP);
-
- oneof varid = OEM_CONFIG_DATA.PcieSRIOVSupport,
- prompt = STRING_TOKEN (STR_SRIOV_SUPPORT_PROMPT),
- help = STRING_TOKEN (STR_SRIOV_SUPPORT_HELP),
+ oneof varid = OEM_CONFIG_DATA.PcieDPCSupport,
+ prompt = STRING_TOKEN (STR_DPC_SUPPORT_PROMPT),
+ help = STRING_TOKEN (STR_DPC_SUPPORT_HELP),
option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
option text = STRING_TOKEN (STR_ENABLE), value = 1, flags = RESET_REQUIRED;
endoneof;
endform;
-form formid = VFR_FORMID_PCIE_SOCKET0,
- title = STRING_TOKEN(STR_PCIE_CPU_0_PROMPT);
-
- goto VFR_FORMID_PCIE_PORT2,
- prompt = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
-
- goto VFR_FORMID_PCIE_PORT4,
- prompt = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
-
- goto VFR_FORMID_PCIE_PORT5,
- prompt = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
-
- goto VFR_FORMID_PCIE_PORT6,
- prompt = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
-
- goto VFR_FORMID_PCIE_PORT7,
- prompt = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
-
-endform;
-
-form formid = VFR_FORMID_PCIE_SOCKET1,
- title = STRING_TOKEN(STR_PCIE_CPU_1_PROMPT);
- goto VFR_FORMID_PCIE_PORT10,
- prompt = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
-
- goto VFR_FORMID_PCIE_PORT12,
- prompt = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
-
- goto VFR_FORMID_PCIE_PORT13,
- prompt = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
-endform;
-
-form formid = VFR_FORMID_PCIE_PORT0,
- title = STRING_TOKEN(STR_PCIE_PORT_0_PROMPT);
- #undef INDEX
- #define INDEX 0
- #include "PciePortConfig.hfr"
-
-endform;
-
-form formid = VFR_FORMID_PCIE_PORT1,
- title = STRING_TOKEN(STR_PCIE_PORT_1_PROMPT);
-
- #undef INDEX
- #define INDEX 1
- #include "PciePortConfig.hfr"
-
-endform;
-
-form formid = VFR_FORMID_PCIE_PORT2,
- title = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT);
-
- #undef INDEX
- #define INDEX 2
- #include "PciePortConfig.hfr"
-
-endform;
-
-form formid = VFR_FORMID_PCIE_PORT3,
- title = STRING_TOKEN(STR_PCIE_PORT_3_PROMPT);
-
- #undef INDEX
- #define INDEX 3
- #include "PciePortConfig.hfr"
-
-endform;
-
-form formid = VFR_FORMID_PCIE_PORT4,
- title = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT);
-
- #undef INDEX
- #define INDEX 4
- #include "PciePortConfig.hfr"
-
-endform;
-
-form formid = VFR_FORMID_PCIE_PORT5,
- title = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT);
-
- #undef INDEX
- #define INDEX 5
- #include "PciePortConfig.hfr"
-
-endform;
-
-form formid = VFR_FORMID_PCIE_PORT6,
- title = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT);
-
- #undef INDEX
- #define INDEX 6
- #include "PciePortConfig.hfr"
-
-endform;
-
-form formid = VFR_FORMID_PCIE_PORT7,
- title = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT);
-
- #undef INDEX
- #define INDEX 7
- #include "PciePortConfig.hfr"
-
-endform;
-
-form formid = VFR_FORMID_PCIE_PORT8,
- title = STRING_TOKEN(STR_PCIE_PORT_8_PROMPT);
-
- #undef INDEX
- #define INDEX 8
- #include "PciePortConfig.hfr"
-
-endform;
-
-form formid = VFR_FORMID_PCIE_PORT9,
- title = STRING_TOKEN(STR_PCIE_PORT_9_PROMPT);
-
- #undef INDEX
- #define INDEX 9
- #include "PciePortConfig.hfr"
-
-endform;
-
-form formid = VFR_FORMID_PCIE_PORT10,
- title = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT);
-
- #undef INDEX
- #define INDEX 10
- #include "PciePortConfig.hfr"
-
-endform;
-
-form formid = VFR_FORMID_PCIE_PORT11,
- title = STRING_TOKEN(STR_PCIE_PORT_11_PROMPT);
-
- #undef INDEX
- #define INDEX 11
- #include "PciePortConfig.hfr"
-
-endform;
-
-form formid = VFR_FORMID_PCIE_PORT12,
- title = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT);
-
- #undef INDEX
- #define INDEX 12
- #include "PciePortConfig.hfr"
-
-endform;
-
-form formid = VFR_FORMID_PCIE_PORT13,
- title = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT);
-
- #undef INDEX
- #define INDEX 13
- #include "PciePortConfig.hfr"
-
-endform;
-
-form formid = VFR_FORMID_PCIE_PORT14,
- title = STRING_TOKEN(STR_PCIE_PORT_14_PROMPT);
-
- #undef INDEX
- #define INDEX 14
- #include "PciePortConfig.hfr"
-
-endform;
-
-form formid = VFR_FORMID_PCIE_PORT15,
- title = STRING_TOKEN(STR_PCIE_PORT_15_PROMPT);
-
- #undef INDEX
- #define INDEX 15
- #include "PciePortConfig.hfr"
-
-endform;
-
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni
index d87d30f975b8..0127ea952dee 100644
--- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni
+++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni
@@ -26,7 +26,8 @@
#string STR_PCIE_CPU_1_PROMPT #language en-US "CPU 1 PCIE Configuration"
#string STR_SRIOV_SUPPORT_PROMPT #language en-US "SRIOV"
#string STR_SRIOV_SUPPORT_HELP #language en-US "This option enables / disables the SRIOV function"
-
+#string STR_DPC_SUPPORT_PROMPT #language en-US "Support DPC"
+#string STR_DPC_SUPPORT_HELP #language en-US "This option enables / disables the DPC function"
#string STR_PCIE_PORT_PROMPT_HELP #language en-US "Press <Enter> to config this port."
#string STR_PCIE_PORT_0_NULL_PROMPT #language en-US ""
#string STR_PCIE_PORT_0_PROMPT #language en-US "CPU 0 Pcie - Port 0"
--
2.9.5
next prev parent reply other threads:[~2019-02-01 13:35 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-01 13:34 [PATCH edk2-platforms v1 00/16] Fix issues and improve D0x Ming Huang
2019-02-01 13:34 ` [PATCH edk2-platforms v1 01/16] Hisilicon/D0x: Remove SerdesLib Ming Huang
2019-02-11 15:05 ` Leif Lindholm
2019-02-13 6:36 ` Ming Huang
2019-02-13 9:42 ` Leif Lindholm
2019-02-13 11:39 ` Ming Huang
2019-02-14 10:51 ` Ming Huang
2019-02-01 13:34 ` [PATCH edk2-platforms v1 02/16] Hisilicon/D0x: Add DriverHealthManagerDxe Ming Huang
2019-02-11 15:20 ` Leif Lindholm
2019-02-01 13:34 ` [PATCH edk2-platforms v1 03/16] Hisilicon/D06: Optimize SAS driver for reducing boot time Ming Huang
2019-02-12 15:12 ` Leif Lindholm
2019-02-13 6:01 ` Ming Huang
2019-02-01 13:34 ` [PATCH edk2-platforms v1 04/16] Hisilicon/D06: Fix access variable fail issue Ming Huang
2019-02-12 15:17 ` Leif Lindholm
2019-02-13 2:21 ` Ming Huang
2019-02-01 13:34 ` [PATCH edk2-platforms v1 05/16] Hisilicon/D06: Add more PCIe port INT-x support Ming Huang
2019-02-11 17:05 ` Leif Lindholm
2019-02-12 12:27 ` Ming Huang
2019-02-01 13:34 ` [PATCH edk2-platforms v1 06/16] Hisilicon/D06: Add OemGetCpuFreq to encapsulate difference Ming Huang
2019-02-11 17:15 ` Leif Lindholm
2019-02-13 2:29 ` Ming Huang
2019-02-01 13:34 ` [PATCH edk2-platforms v1 07/16] Hisilicon/D0x: Rename StartupAp() function Ming Huang
2019-02-11 18:04 ` Leif Lindholm
2019-02-01 13:34 ` [PATCH edk2-platforms v1 08/16] Hisilicon/D06: Change HCCS speed from 30G to 26G Ming Huang
2019-02-11 18:36 ` Leif Lindholm
2019-02-12 14:45 ` Ming Huang
2019-02-12 14:59 ` Leif Lindholm
2019-02-01 13:34 ` [PATCH edk2-platforms v1 09/16] Hisilicon/D06: Add PCI_OSC_SUPPORT Ming Huang
2019-02-11 18:51 ` Leif Lindholm
2019-02-13 2:59 ` Ming Huang
2019-02-13 9:08 ` Leif Lindholm
2019-02-01 13:34 ` [PATCH edk2-platforms v1 10/16] Hisilicon/D06: Modify for M7 self-Adapte support Ming Huang
2019-02-11 19:28 ` Leif Lindholm
2019-02-12 15:14 ` Ming Huang
2019-02-12 15:46 ` Leif Lindholm
2019-02-13 4:38 ` Ming Huang
2019-02-01 13:34 ` Ming Huang [this message]
2019-02-11 19:46 ` [PATCH edk2-platforms v1 11/16] Hisilicon/D06: Add Setup Item "Support DPC" Leif Lindholm
2019-02-12 15:22 ` Ming Huang
2019-02-12 15:49 ` Leif Lindholm
2019-02-01 13:34 ` [PATCH edk2-platforms v1 12/16] Hisilicon/D06: Use new flash layout Ming Huang
2019-02-11 14:54 ` Leif Lindholm
2019-02-13 4:43 ` Ming Huang
2019-02-01 13:34 ` [PATCH edk2-platforms v1 13/16] Hisilicon/D06: Remove SECURE_BOOT_ENABLE definition Ming Huang
2019-02-11 19:47 ` Leif Lindholm
2019-02-01 13:34 ` [PATCH edk2-platforms v1 14/16] Hisilicon/D0x: Remove SP805 watchdog pcd Ming Huang
2019-02-11 19:48 ` Leif Lindholm
2019-02-15 14:18 ` [PATCH edk2-platforms v1 00/16] Fix issues and improve D0x Ming Huang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190201133436.10500-12-ming.huang@linaro.org \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox