From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::642; helo=mail-pl1-x642.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl1-x642.google.com (mail-pl1-x642.google.com [IPv6:2607:f8b0:4864:20::642]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5F042211C5729 for ; Fri, 1 Feb 2019 05:35:33 -0800 (PST) Received: by mail-pl1-x642.google.com with SMTP id z23so3249569plo.0 for ; Fri, 01 Feb 2019 05:35:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AXjRF9hRJEgJZKNG8641qCmPpPPHtjLeU9qsQkkhcAE=; b=HcyHRaH4fo7+fea9e6+Yk9S1cVh8pAvze3H9YgcIxAA9txlo1P1Yo1Qi/mF6n9s5L1 /dCCxiNPzduMeCafbOMxRbo+Y9vd/7K1NtzXYm8pSFGJ5lI6hFyZjkOi9u35AnQ9yhyr RKCd3U6IWilXREHaUMMebE2xoN/a+LSYJ/x3M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AXjRF9hRJEgJZKNG8641qCmPpPPHtjLeU9qsQkkhcAE=; b=YElYwJ9EGzZk3nuGc8erFf7S3KAfKsQOXhHNMS8KcpKaZ/Zjnw4mRiD+qtyekD/uJ2 q6W5V0kLpsmONLA3sDVCwQWrNcktkuUPCemyOT/BGVICxP/wZ3Yo8yPF2zlekwgejnCC mKYjwzgkSmrOGfwtipZ6z1YOnvxBS/KNFBZ5Qo4VSEQfqU7Txhts1prnqBz5+nvhdF5i HP+gnutlGCkA9v1F7I4LBIlYUFtB4xVeXbEndIeHrJLsbl6aw2R5HsX/okyEsWg4Ztwd lj01524CITYUhjCHWrjgwibUI6cgpzeU0h3+8DM8tTZ1yzD7VepJWDMP+enYEur5s+gy 76yg== X-Gm-Message-State: AJcUuke8FK/idjoSIcYHNJzT3hpmfrAhQBMjT/InlJOykmwg4zXPqGRI nCRWqHimb7oJT0aA1/KqO/1NKw== X-Google-Smtp-Source: ALg8bN4Ph3Gfs299n9i4yJwiKzHVfnhTgMonHNVeDueDCOzDcd9iG/k/JhOHNOyMMNiLDzqgm8K9RA== X-Received: by 2002:a17:902:583:: with SMTP id f3mr40586772plf.202.1549028133041; Fri, 01 Feb 2019 05:35:33 -0800 (PST) Received: from localhost.localdomain ([114.119.4.74]) by smtp.gmail.com with ESMTPSA id s21sm11134073pfk.133.2019.02.01.05.35.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 01 Feb 2019 05:35:32 -0800 (PST) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org, zhangfeng56@huawei.com, Ming Huang Date: Fri, 1 Feb 2019 21:34:25 +0800 Message-Id: <20190201133436.10500-6-ming.huang@linaro.org> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20190201133436.10500-1-ming.huang@linaro.org> References: <20190201133436.10500-1-ming.huang@linaro.org> Subject: [PATCH edk2-platforms v1 05/16] Hisilicon/D06: Add more PCIe port INT-x support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Feb 2019 13:35:33 -0000 From: Jason Zhang Since NVMe riser width is 6*X4, need add the related port's INT-x support to match OS driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 65 +++++++++++++++----- 1 file changed, 50 insertions(+), 15 deletions(-) diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl index 27fde2e09bfe..4d9d9d95be68 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl +++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl @@ -41,11 +41,21 @@ Scope(_SB) // adding RPx INTx configure deponds on hardware board topology, // if UEFI enables RPx, RPy, RPz... related INTx configure // should be added + Package () {0x2FFFF,0,0,640}, // INT_A + Package () {0x2FFFF,1,0,641}, // INT_B + Package () {0x2FFFF,2,0,642}, // INT_C + Package () {0x2FFFF,3,0,643}, // INT_D + Package () {0x4FFFF,0,0,640}, // INT_A Package () {0x4FFFF,1,0,641}, // INT_B Package () {0x4FFFF,2,0,642}, // INT_C Package () {0x4FFFF,3,0,643}, // INT_D + Package () {0x6FFFF,0,0,640}, // INT_A + Package () {0x6FFFF,1,0,641}, // INT_B + Package () {0x6FFFF,2,0,642}, // INT_C + Package () {0x6FFFF,3,0,643}, // INT_D + Package () {0x8FFFF,0,0,640}, // INT_A Package () {0x8FFFF,1,0,641}, // INT_B Package () {0x8FFFF,2,0,642}, // INT_C @@ -56,6 +66,11 @@ Scope(_SB) Package () {0xCFFFF,2,0,642}, // INT_C Package () {0xCFFFF,3,0,643}, // INT_D + Package () {0xEFFFF,0,0,640}, // INT_A + Package () {0xEFFFF,1,0,641}, // INT_B + Package () {0xEFFFF,2,0,642}, // INT_C + Package () {0xEFFFF,3,0,643}, // INT_D + Package () {0x10FFFF,0,0,640}, // INT_A Package () {0x10FFFF,1,0,641}, // INT_B Package () {0x10FFFF,2,0,642}, // INT_C @@ -759,26 +774,46 @@ Device (PCI6) // adding RPx INTx configure deponds on hardware board topology, // if UEFI enables RPx, RPy, RPz... related INTx configure // should be added - Package () {0x04FFFF,0,0,640}, // INT_A - Package () {0x04FFFF,1,0,641}, // INT_B - Package () {0x04FFFF,2,0,642}, // INT_C - Package () {0x04FFFF,3,0,643}, // INT_D - - Package () {0x08FFFF,0,0,640}, // INT_A - Package () {0x08FFFF,1,0,641}, // INT_B - Package () {0x08FFFF,2,0,642}, // INT_C - Package () {0x08FFFF,3,0,643}, // INT_D - - Package () {0x0CFFFF,0,0,640}, // INT_A - Package () {0x0CFFFF,1,0,641}, // INT_B - Package () {0x0CFFFF,2,0,642}, // INT_C - Package () {0x0CFFFF,3,0,643}, // INT_D + Package () {0x2FFFF,0,0,640}, // INT_A + Package () {0x2FFFF,1,0,641}, // INT_B + Package () {0x2FFFF,2,0,642}, // INT_C + Package () {0x2FFFF,3,0,643}, // INT_D + + Package () {0x4FFFF,0,0,640}, // INT_A + Package () {0x4FFFF,1,0,641}, // INT_B + Package () {0x4FFFF,2,0,642}, // INT_C + Package () {0x4FFFF,3,0,643}, // INT_D + + Package () {0x6FFFF,0,0,640}, // INT_A + Package () {0x6FFFF,1,0,641}, // INT_B + Package () {0x6FFFF,2,0,642}, // INT_C + Package () {0x6FFFF,3,0,643}, // INT_D + + Package () {0x8FFFF,0,0,640}, // INT_A + Package () {0x8FFFF,1,0,641}, // INT_B + Package () {0x8FFFF,2,0,642}, // INT_C + Package () {0x8FFFF,3,0,643}, // INT_D + + Package () {0xCFFFF,0,0,640}, // INT_A + Package () {0xCFFFF,1,0,641}, // INT_B + Package () {0xCFFFF,2,0,642}, // INT_C + Package () {0xCFFFF,3,0,643}, // INT_D + + Package () {0xEFFFF,0,0,640}, // INT_A + Package () {0xEFFFF,1,0,641}, // INT_B + Package () {0xEFFFF,2,0,642}, // INT_C + Package () {0xEFFFF,3,0,643}, // INT_D Package () {0x10FFFF,0,0,640}, // INT_A Package () {0x10FFFF,1,0,641}, // INT_B Package () {0x10FFFF,2,0,642}, // INT_C Package () {0x10FFFF,3,0,643}, // INT_D - }) + + Package () {0x12FFFF,0,0,640}, // INT_A + Package () {0x12FFFF,1,0,641}, // INT_B + Package () {0x12FFFF,2,0,642}, // INT_C + Package () {0x12FFFF,3,0,643}, // INT_D + }) Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource setting Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111, -- 2.9.5