From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::443; helo=mail-wr1-x443.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6F0CE208AEA1D for ; Mon, 11 Feb 2019 08:45:57 -0800 (PST) Received: by mail-wr1-x443.google.com with SMTP id x10so5468004wrs.8 for ; Mon, 11 Feb 2019 08:45:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=0IOdsIO/0HYR3mB68NxLf0dqw5oFtEwjo8EiaKPLpNs=; b=Pf/CwjFV9lYIcEiPFMYYeXB6dk91IoYVcuryUj4+DGNutgFwmOtz2HojSP0Jprhjpp M3pwYcdZNs/ma8gq79t2W81D3972G2NQ24AMOMrpq/GANWDK07mpTrpvvyPM7C/WWatp 5okFhbXOz7lgUn5Z+RCe1xIewK6rq13Vo6C5L2ceHKFOdKyZt0Q02Q2zEt67gpb6gCMh M+k7+e/SJcvvtMxpGx/jmL0TFeN7GDWSdiEUD1/Smdw/m1hkTwbqI1e4HVJxeOptSrWy VUBzHnC8BG2XX3r7YGyO/BB61NsDtYKbv1G2LMUeLs1rxB+kSzRJW9TR16nsfAi6BCAS 8mWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=0IOdsIO/0HYR3mB68NxLf0dqw5oFtEwjo8EiaKPLpNs=; b=sldBrNtXAsUJiF/9t1xaNKl5Gsb6uf2DIxLYPIHHTHLbEH2Er5OxRHtUQC2v3UVa8H 5JMHhXrwMZqQVeyb/a05ZbzKeI6bkG0LclGawI27NQjXayWrmZTenBLY5wXz+nNycZCE 4v7AYJoaUUDg5QvBn/AhupokNQQCONTCAMWU9hYuBYGniT1MuhUC++AeJiAWfupnuWmE U2jt4iTeSdA+4Bi3KyR30jlbRaoWx/uI/sqZ6LnyBJT+savly4mm8vSN2GIKqNlj7cQu H32Wy0j8LWyMzCMdPattse8osjTCa19RzRL01VimjMgOe6V6JvC1h7h9Ed0LNFh39xJf dmmg== X-Gm-Message-State: AHQUAuYeL3Nh6Ydv1AEzVjE1U16yk+u4FejX5042dvHNc7hnqO5e1QfX F0d1HHr7znxd6swfvhXDBbXpzAzMrcA= X-Google-Smtp-Source: AHgI3IbvgPwb92aPeLmdiHMLLekHj83TbF3JSk9+W1nKBEi+OLcOtS1Do7ljtf2dHYkEyRGj+q6RPA== X-Received: by 2002:adf:e34b:: with SMTP id n11mr26651929wrj.91.1549903555693; Mon, 11 Feb 2019 08:45:55 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id y1sm2300828wrh.65.2019.02.11.08.45.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 08:45:54 -0800 (PST) Date: Mon, 11 Feb 2019 16:45:53 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: "edk2-devel@lists.01.org" Message-ID: <20190211164553.nc7ho6kb2ri2adtl@bivouac.eciton.net> References: <20190114170205.9748-1-ard.biesheuvel@linaro.org> <20190114170205.9748-7-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 6/8] Silicon/SynQuacer/Stage2Tables: fix 32-bit build X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Feb 2019 16:45:57 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Jan 14, 2019 at 06:52:07PM +0100, Ard Biesheuvel wrote: > On Mon, 14 Jan 2019 at 18:02, Ard Biesheuvel wrote: > > > > The static stage2 page tables don't contain any code, but we are > > relying on the linker to resolve the references to the next level > > tables, so we can only use native word size quantities. So add a > > CPP macro to emit the same quantity in different ways. > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Ard Biesheuvel > > --- > > Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S | 12 +++++++++--- > > The 'elf64-little' in the .inf is now wrong as well, but it seems I > can just remove that and objcopy will detect the input format. Hmm. Actually, no. When cross-compiling: $ objcopy -O binary -j .rodata /work/git/tianocore/Build/DeveloperBox/DEBUG_GCC5/AARCH64/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables/OUTPUT/Stage2Tables.elf /work/git/tianocore/Build/DeveloperBox/DEBUG_GCC5/AARCH64/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables/OUTPUT/Stage2Tables.bin objcopy: Unable to recognise the format of the input file `/work/git/tianocore/Build/DeveloperBox/DEBUG_GCC5/AARCH64/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables/OUTPUT/Stage2Tables.elf' If I put -I elf64-little back, the command succeeds. If I explicitly call the cross-toolchain objcopy, the command succeeds without that addition. When building natively, this works fine without the flag. Why do we even end up running the build machine native objcopy here? / Leif > > 1 file changed, 9 insertions(+), 3 deletions(-) > > > > diff --git a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S > > index af55f27bca47..28c7a6ac970f 100644 > > --- a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S > > +++ b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S > > @@ -32,6 +32,12 @@ > > #define TT_S2_L3_PAGE (0x1 << 1) > > #define TT_S2_VALID (0x1 << 0) > > > > +#ifdef __aarch64__ > > +#define QWORD(x) .quad (x) > > +#else > > +#define QWORD(x) .long (x), 0 > > +#endif > > + > > .altmacro > > .macro for, start, count, do, arg2, arg3, arg4 > > .if \count == 1 > > @@ -69,7 +75,7 @@ > > .section ".rodata", "a", %progbits > > /* level 1 */ > > s2_mem_entry 0 /* 0x0000_0000 - 0x3fff_ffff */ > > - .quad 1f + TT_S2_TABLE /* 0x4000_0000 - 0x7fff_ffff */ > > + QWORD (1f + TT_S2_TABLE) /* 0x4000_0000 - 0x7fff_ffff */ > > for 2, 246, s2_mem_entry /* 0x8000_0000 - 0x3d_ffff_ffff */ > > for 248, 8, s2_dev_entry /* PCIe MMIO64 */ > > for 256, 768, s2_mem_entry /* 0x40_0000_0000 - 0xff_ffff_ffff */ > > @@ -77,12 +83,12 @@ > > /* level 2 */ > > 1:for 0, 256, s2_mem_entry, 21, 0x40000000, 1 > > > > - .quad 2f + TT_S2_TABLE /* 0x6000_0000 -> RC #0 bus 0 */ > > + QWORD (2f + TT_S2_TABLE) /* 0x6000_0000 -> RC #0 bus 0 */ > > for 1, 15, s2_mem_entry, 21, 0x60000000 > > for 0, 48, s2_mem_entry, 21, 0x62000000, 1 > > for 0, 64, s2_dev_entry, 21, 0x68000000, 1 /* PCIe MMIO32 */ > > > > - .quad 3f + TT_S2_TABLE /* 0x7000_0000 -> RC #1 bus 0 */ > > + QWORD (3f + TT_S2_TABLE) /* 0x7000_0000 -> RC #1 bus 0 */ > > for 1, 15, s2_mem_entry, 21, 0x70000000 > > for 0, 48, s2_mem_entry, 21, 0x72000000, 1 > > for 0, 64, s2_dev_entry, 21, 0x78000000, 1 /* PCIe MMIO32 */ > > -- > > 2.17.1 > >