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[2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id y22sm30032569wrd.45.2019.02.11.09.05.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 09:05:15 -0800 (PST) Date: Mon, 11 Feb 2019 17:05:14 +0000 From: Leif Lindholm To: Ming Huang Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, zhangfeng56@huawei.com Message-ID: <20190211170514.a6ixqcm4oz3i3kga@bivouac.eciton.net> References: <20190201133436.10500-1-ming.huang@linaro.org> <20190201133436.10500-6-ming.huang@linaro.org> MIME-Version: 1.0 In-Reply-To: <20190201133436.10500-6-ming.huang@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v1 05/16] Hisilicon/D06: Add more PCIe port INT-x support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Feb 2019 17:05:19 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Feb 01, 2019 at 09:34:25PM +0800, Ming Huang wrote: > From: Jason Zhang > > Since NVMe riser width is 6*X4, need add the related > port's INT-x support to match OS driver. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ming Huang > --- > Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 65 +++++++++++++++----- > 1 file changed, 50 insertions(+), 15 deletions(-) > > diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl > index 27fde2e09bfe..4d9d9d95be68 100644 > --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl > +++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl > @@ -41,11 +41,21 @@ Scope(_SB) > // adding RPx INTx configure deponds on hardware board topology, > // if UEFI enables RPx, RPy, RPz... related INTx configure > // should be added > + Package () {0x2FFFF,0,0,640}, // INT_A > + Package () {0x2FFFF,1,0,641}, // INT_B > + Package () {0x2FFFF,2,0,642}, // INT_C > + Package () {0x2FFFF,3,0,643}, // INT_D > + > Package () {0x4FFFF,0,0,640}, // INT_A > Package () {0x4FFFF,1,0,641}, // INT_B > Package () {0x4FFFF,2,0,642}, // INT_C > Package () {0x4FFFF,3,0,643}, // INT_D > > + Package () {0x6FFFF,0,0,640}, // INT_A > + Package () {0x6FFFF,1,0,641}, // INT_B > + Package () {0x6FFFF,2,0,642}, // INT_C > + Package () {0x6FFFF,3,0,643}, // INT_D > + > Package () {0x8FFFF,0,0,640}, // INT_A > Package () {0x8FFFF,1,0,641}, // INT_B > Package () {0x8FFFF,2,0,642}, // INT_C > @@ -56,6 +66,11 @@ Scope(_SB) > Package () {0xCFFFF,2,0,642}, // INT_C > Package () {0xCFFFF,3,0,643}, // INT_D > > + Package () {0xEFFFF,0,0,640}, // INT_A > + Package () {0xEFFFF,1,0,641}, // INT_B > + Package () {0xEFFFF,2,0,642}, // INT_C > + Package () {0xEFFFF,3,0,643}, // INT_D > + > Package () {0x10FFFF,0,0,640}, // INT_A > Package () {0x10FFFF,1,0,641}, // INT_B > Package () {0x10FFFF,2,0,642}, // INT_C > @@ -759,26 +774,46 @@ Device (PCI6) > // adding RPx INTx configure deponds on hardware board topology, > // if UEFI enables RPx, RPy, RPz... related INTx configure > // should be added > - Package () {0x04FFFF,0,0,640}, // INT_A > - Package () {0x04FFFF,1,0,641}, // INT_B > - Package () {0x04FFFF,2,0,642}, // INT_C > - Package () {0x04FFFF,3,0,643}, // INT_D > - > - Package () {0x08FFFF,0,0,640}, // INT_A > - Package () {0x08FFFF,1,0,641}, // INT_B > - Package () {0x08FFFF,2,0,642}, // INT_C > - Package () {0x08FFFF,3,0,643}, // INT_D > - > - Package () {0x0CFFFF,0,0,640}, // INT_A > - Package () {0x0CFFFF,1,0,641}, // INT_B > - Package () {0x0CFFFF,2,0,642}, // INT_C > - Package () {0x0CFFFF,3,0,643}, // INT_D Please don't include the non-functional change of dropping the leading 0 (0x0 -> 0x) here together with the functional change of adding new entries. Please submit as a separate patch. / Leif > + Package () {0x2FFFF,0,0,640}, // INT_A > + Package () {0x2FFFF,1,0,641}, // INT_B > + Package () {0x2FFFF,2,0,642}, // INT_C > + Package () {0x2FFFF,3,0,643}, // INT_D > + > + Package () {0x4FFFF,0,0,640}, // INT_A > + Package () {0x4FFFF,1,0,641}, // INT_B > + Package () {0x4FFFF,2,0,642}, // INT_C > + Package () {0x4FFFF,3,0,643}, // INT_D > + > + Package () {0x6FFFF,0,0,640}, // INT_A > + Package () {0x6FFFF,1,0,641}, // INT_B > + Package () {0x6FFFF,2,0,642}, // INT_C > + Package () {0x6FFFF,3,0,643}, // INT_D > + > + Package () {0x8FFFF,0,0,640}, // INT_A > + Package () {0x8FFFF,1,0,641}, // INT_B > + Package () {0x8FFFF,2,0,642}, // INT_C > + Package () {0x8FFFF,3,0,643}, // INT_D > + > + Package () {0xCFFFF,0,0,640}, // INT_A > + Package () {0xCFFFF,1,0,641}, // INT_B > + Package () {0xCFFFF,2,0,642}, // INT_C > + Package () {0xCFFFF,3,0,643}, // INT_D > + > + Package () {0xEFFFF,0,0,640}, // INT_A > + Package () {0xEFFFF,1,0,641}, // INT_B > + Package () {0xEFFFF,2,0,642}, // INT_C > + Package () {0xEFFFF,3,0,643}, // INT_D > > Package () {0x10FFFF,0,0,640}, // INT_A > Package () {0x10FFFF,1,0,641}, // INT_B > Package () {0x10FFFF,2,0,642}, // INT_C > Package () {0x10FFFF,3,0,643}, // INT_D > - }) > + > + Package () {0x12FFFF,0,0,640}, // INT_A > + Package () {0x12FFFF,1,0,641}, // INT_B > + Package () {0x12FFFF,2,0,642}, // INT_C > + Package () {0x12FFFF,3,0,643}, // INT_D > + }) > > Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource setting > Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111, > -- > 2.9.5 >