From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::444; helo=mail-wr1-x444.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6DFB6208D6134 for ; Mon, 11 Feb 2019 10:51:44 -0800 (PST) Received: by mail-wr1-x444.google.com with SMTP id r2so5875065wrv.10 for ; Mon, 11 Feb 2019 10:51:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=UTIowjUIBW2+2OMLgeZphE84ffWz4pWeDAF6GJgRbZY=; b=CxQElCUUUW6i4poab1NkKLlfVkDlwLYZDV4IrasbBxaMBlWOJ2R4F7f507s3j+87HN Wa6404o4clJabitFhSgGCAB8vd0dZTmQbit/dr2MKLW5s6X4P7daF0GMgVaecEs/bWyF 8JW0I80v87/XWvDpt84juGUsKOlAvPh2V35KqzhKZnBGTUjDznxAQL9PftFYn4mGgq6j FUfYmUlWnZmgqWSzTs345zigHJl8LH/Q6hT3Yf1/wkTCGZ4RTKqa9vNHeM8uNWtbmE/T tvCWAirNA3VCi8MBNXdnz0Njbu6B4sERJVA40Ltzfq15V3pbwF11uKwderbVG8YX95Ya YLFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=UTIowjUIBW2+2OMLgeZphE84ffWz4pWeDAF6GJgRbZY=; b=d1K3FWw4gZla+ZRFg4Y1rP1puLKnVEatQjPZhydamYak/dfRqaMUGSDyaaGiuSjepd 0DL/hzO5SQVTbUbcu8Wwa3u2+2WB65tMXaw3Gheujlaxw0xCrvdyb801LPhCAIxmJX9k Lx1Ql7re26AueqS7ot5K4crFTedjGC+EuHHQJYx3Z/9xRTMQvNeRupwgMerECz8yajDw aweOYJo2V76YLQwAszYCFNeIr3c6CQryrVTOXoEZx7quQIKm1JYuoe71iW2Muujvexwc x/TAaco2zKC9UVCUUIZSRtXSxR9M4gIxzeCs7xv8AQ7IJkdl1WoUqvcuHBJK32YH9N9L LI0Q== X-Gm-Message-State: AHQUAuZkuvtlY7Mar/J80Sh6HHlHqTtf9qjsOUCqFAZbZHy38tPYMAfK cuBU/Kpwzk/qmwGzc/8enKHNKA== X-Google-Smtp-Source: AHgI3IYvgFO9cMgLNKxQrFUsq3j1MtlucULw/GJOOcIjONHxExhPPmJYUKGARyM8VWBkBfQwaxSJNg== X-Received: by 2002:adf:fa51:: with SMTP id y17mr13571937wrr.233.1549911102741; Mon, 11 Feb 2019 10:51:42 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id u17sm6600720wrg.71.2019.02.11.10.51.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 10:51:41 -0800 (PST) Date: Mon, 11 Feb 2019 18:51:40 +0000 From: Leif Lindholm To: Ming Huang Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org, zhangfeng56@huawei.com Message-ID: <20190211185140.6vn7swtqtiencdak@bivouac.eciton.net> References: <20190201133436.10500-1-ming.huang@linaro.org> <20190201133436.10500-10-ming.huang@linaro.org> MIME-Version: 1.0 In-Reply-To: <20190201133436.10500-10-ming.huang@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v1 09/16] Hisilicon/D06: Add PCI_OSC_SUPPORT X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Feb 2019 18:51:44 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Feb 01, 2019 at 09:34:29PM +0800, Ming Huang wrote: > Add PCI_OSC_SUPPORT for remaining host bridges to remove fail > output in kernel: > [ 103.478893] acpi PNP0A08:01: _OSC failed (AE_NOT_FOUND); > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ming Huang > --- > Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 64 ++++++++++++++++++++ > 1 file changed, 64 insertions(+) > > diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl > index 4d9d9d95be68..86d8728b82f2 100644 > --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl > +++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl > @@ -17,6 +17,50 @@ > **/ > > //#include "ArmPlatform.h" > + > +/* > + See ACPI 6.1 Spec, 6.2.11, PCI Firmware Spec 3.0, 4.5 > +*/ > +#define PCI_OSC_SUPPORT() \ PCI0 and PCI6 already have _OSC entries. This macro ends up being used for 1-5 and 7-B. So calling it PCI_OSC_SUPPORT seems somewhat misleading. Then again, there is a lot of similarities between this macro and the existing entries. Could the same macro be used for 0 and 6? Or could the macro be split up into multiple parts and reused? / Leif > + Name(SUPP, Zero) /* PCI _OSC Support Field value */ \ > + Name(CTRL, Zero) /* PCI _OSC Control Field value */ \ > + Method(_OSC,4) { \ > + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \ > + /* Create DWord-adressable fields from the Capabilities Buffer */ \ > + CreateDWordField(Arg3,0,CDW1) \ > + CreateDWordField(Arg3,4,CDW2) \ > + CreateDWordField(Arg3,8,CDW3) \ > + /* Save Capabilities DWord2 & 3 */ \ > + Store(CDW2,SUPP) \ > + Store(CDW3,CTRL) \ > + /* Only allow native hot plug control if OS supports: */ \ > + /* ASPM */ \ > + /* Clock PM */ \ > + /* MSI/MSI-X */ \ > + If(LNotEqual(And(SUPP, 0x16), 0x16)) { \ > + And(CTRL,0x1E,CTRL) \ > + }\ > + \ > + /* Do not allow native PME, AER */ \ > + /* Never allow SHPC (no SHPC controller in this system)*/ \ > + And(CTRL,0x10,CTRL) \ > + If(LNotEqual(Arg1,One)) { /* Unknown revision */ \ > + Or(CDW1,0x08,CDW1) \ > + } \ > + \ > + If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \ > + Or(CDW1,0x10,CDW1) \ > + } \ > + \ > + /* Update DWORD3 in the buffer */ \ > + Store(CTRL,CDW3) \ > + Return(Arg3) \ > + } Else { \ > + Or(CDW1,4,CDW1) /* Unrecognized UUID */ \ > + Return(Arg3) \ > + } \ > + } // End _OSC > + > Scope(_SB) > { > Device (PCI0) > @@ -270,6 +314,8 @@ Device (PCI1) > Return (RBUF) > } // Method(_CRS), this method return RBUF! > > + PCI_OSC_SUPPORT () > + > Method (_STA, 0x0, NotSerialized) > { > Return (0xf) > @@ -333,6 +379,8 @@ Device (PCI2) > Return (RBUF) > } // Method(_CRS), this method return RBUF! > > + PCI_OSC_SUPPORT () > + > Method (_STA, 0x0, NotSerialized) > { > Return (0xf) > @@ -382,6 +430,8 @@ Device (PCI3) > Return (RBUF) > } // Method(_CRS), this method return RBUF! > > + PCI_OSC_SUPPORT () > + > Method (_STA, 0x0, NotSerialized) > { > Return (0xf) > @@ -431,6 +481,8 @@ Device (PCI4) > Return (RBUF) > } // Method(_CRS), this method return RBUF! > > + PCI_OSC_SUPPORT () > + > Method (_STA, 0x0, NotSerialized) > { > Return (0x0F) > @@ -505,6 +557,8 @@ Device (PCI5) > Return (RBUF) > } // Method(_CRS), this method return RBUF! > > + PCI_OSC_SUPPORT () > + > Method (_STA, 0x0, NotSerialized) > { > Return (0xf) > @@ -1002,6 +1056,8 @@ Device (PCI7) > Return (RBUF) > } // Method(_CRS), this method return RBUF! > > + PCI_OSC_SUPPORT () > + > Method (_STA, 0x0, NotSerialized) > { > Return (0xf) > @@ -1066,6 +1122,8 @@ Device (PCI8) > Return (RBUF) > } // Method(_CRS), this method return RBUF! > > + PCI_OSC_SUPPORT () > + > Method (_STA, 0x0, NotSerialized) > { > Return (0xf) > @@ -1115,6 +1173,8 @@ Device (PCI9) > Return (RBUF) > } // Method(_CRS), this method return RBUF! > > + PCI_OSC_SUPPORT () > + > Method (_STA, 0x0, NotSerialized) > { > Return (0xf) > @@ -1164,6 +1224,8 @@ Device (PCIA) > Return (RBUF) > } // Method(_CRS), this method return RBUF! > > + PCI_OSC_SUPPORT () > + > Method (_STA, 0x0, NotSerialized) > { > Return (0x0F) > @@ -1238,6 +1300,8 @@ Device (PCIB) > Return (RBUF) > } // Method(_CRS), this method return RBUF! > > + PCI_OSC_SUPPORT () > + > Method (_STA, 0x0, NotSerialized) > { > Return (0xf) > -- > 2.9.5 >