From: "Albecki, Mateusz" <mateusz.albecki@intel.com>
To: edk2-devel@lists.01.org
Cc: "Albecki, Mateusz" <mateusz.albecki@intel.com>,
Hao Wu <hao.a.wu@intel.com>
Subject: [PATCH 0/1] Correcting eMMC HS400 switch sequence
Date: Fri, 15 Feb 2019 15:44:57 +0100 [thread overview]
Message-ID: <20190215144458.1812-1-mateusz.albecki@intel.com> (raw)
SdMmcPchHcDxe used to execute SEND_STATUS with link running at incorrect
clock frequency while downgrading from HS200 to high speed during HS400 switch
sequence. Changing clock frequency before executing SEND_STATUS makes sure that
SEND_STATUS is executed with link at correct frequency. Since new frequency might
not be suitable for old bus timing this change is not sufficient for protecting
against failed bus timing change but seeing as the rest of the driver is unable to
mitigate failed bus timing change it is of no importance.
Cc: Hao Wu <hao.a.wu@intel.com>
Albecki, Mateusz (1):
MdeModulePkg/SdMmcPciHcDxe Fix eMMC HS400 switch sequence
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 37 +++++++++++++------------
1 file changed, 19 insertions(+), 18 deletions(-)
--
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next reply other threads:[~2019-02-15 14:45 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-15 14:44 Albecki, Mateusz [this message]
2019-02-15 14:44 ` [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe Fix eMMC HS400 switch sequence Albecki, Mateusz
2019-02-18 6:00 ` Wu, Hao A
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