From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.93; helo=mga11.intel.com; envelope-from=jordan.l.justen@intel.com; receiver=edk2-devel@lists.01.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C44FD2194EB70 for ; Mon, 18 Feb 2019 02:10:23 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Feb 2019 02:10:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,384,1544515200"; d="scan'208";a="135160741" Received: from mmdandap-mobl1.amr.corp.intel.com (HELO jljusten-skl.amr.corp.intel.com) ([10.254.8.66]) by orsmga002.jf.intel.com with ESMTP; 18 Feb 2019 02:10:21 -0800 From: Jordan Justen To: edk2-devel@lists.01.org Cc: Jordan Justen , Peter Fang , Maurice Ma , Laszlo Ersek , Ard Biesheuvel , Anthony Perard , Julien Grall Date: Mon, 18 Feb 2019 02:10:15 -0800 Message-Id: <20190218101015.23399-1-jordan.l.justen@intel.com> X-Mailer: git-send-email 2.20.0.rc1 MIME-Version: 1.0 Subject: [PATCH] OvmfPkg/Sec: Clear the Cache Disable flag in the CR0 register X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Feb 2019 10:10:24 -0000 Content-Transfer-Encoding: 8bit Clear the CD (Cache Disable) flag in the CR0 register. When the VM implements the CD flag, this can substantially decrease the time it takes to decompress the firmware volumes. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jordan Justen Tested-by: Peter Fang Cc: Peter Fang Cc: Maurice Ma Cc: Laszlo Ersek Cc: Ard Biesheuvel Cc: Anthony Perard Cc: Julien Grall --- OvmfPkg/Sec/Ia32/SecEntry.nasm | 8 +++++++- OvmfPkg/Sec/X64/SecEntry.nasm | 8 +++++++- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/OvmfPkg/Sec/Ia32/SecEntry.nasm b/OvmfPkg/Sec/Ia32/SecEntry.nasm index 03501969eb..fc7f47385a 100644 --- a/OvmfPkg/Sec/Ia32/SecEntry.nasm +++ b/OvmfPkg/Sec/Ia32/SecEntry.nasm @@ -40,6 +40,13 @@ extern ASM_PFX(SecCoreStartupWithStack) global ASM_PFX(_ModuleEntryPoint) ASM_PFX(_ModuleEntryPoint): + ; + ; Clear the CD (Cache Disable) flag in the CR0 register. + ; + mov eax, cr0 + and eax, ~(1 << 30) + mov cr0, eax + ; ; Fill the temporary RAM with the initial stack value. ; The loop below will seed the heap as well, but that's harmless. @@ -71,4 +78,3 @@ ASM_PFX(_ModuleEntryPoint): push eax push ebp call ASM_PFX(SecCoreStartupWithStack) - diff --git a/OvmfPkg/Sec/X64/SecEntry.nasm b/OvmfPkg/Sec/X64/SecEntry.nasm index d76adcffd8..7471b3a3e3 100644 --- a/OvmfPkg/Sec/X64/SecEntry.nasm +++ b/OvmfPkg/Sec/X64/SecEntry.nasm @@ -41,6 +41,13 @@ extern ASM_PFX(SecCoreStartupWithStack) global ASM_PFX(_ModuleEntryPoint) ASM_PFX(_ModuleEntryPoint): + ; + ; Clear the CD (Cache Disable) flag in the CR0 register. + ; + mov rax, cr0 + and eax, ~(1 << 30) + mov cr0, rax + ; ; Fill the temporary RAM with the initial stack value. ; The loop below will seed the heap as well, but that's harmless. @@ -72,4 +79,3 @@ ASM_PFX(_ModuleEntryPoint): mov rdx, rsp sub rsp, 0x20 call ASM_PFX(SecCoreStartupWithStack) - -- 2.20.1