* [PATCH edk2-non-osi v2 1/8] Hisilicon/D06: Remove PCI enumeration dependency from SAS driver
2019-02-20 7:25 [PATCH edk2-non-osi v2 0/8] Upload D0x binary modules Ming Huang
@ 2019-02-20 7:25 ` Ming Huang
2019-02-20 7:25 ` [PATCH edk2-non-osi v2 2/8] Hisilicon/D0x: Update PlatformSysCtrlLib binary Ming Huang
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Ming Huang @ 2019-02-20 7:25 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, michael.d.kinney, lersek, wanghuiqiang,
huangming23, zhangjinsong2, huangdaode, john.garry, zhangfeng56,
Ming Huang
SAS controller is always existed, so accessing SAS register don't
depend on PciBusDxe (pci enumeration). Modify SAS driver remove the
dependence on pci enumeration.
This patch is done to improve boot times.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
---
Platform/Hisilicon/D06/Drivers/Sas/SasDriverDxe.depex | Bin 216 -> 36 bytes
Platform/Hisilicon/D06/Drivers/Sas/SasDriverDxe.efi | Bin 221312 -> 220640 bytes
2 files changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Hisilicon/D06/Drivers/Sas/SasDriverDxe.depex b/Platform/Hisilicon/D06/Drivers/Sas/SasDriverDxe.depex
index 1a5bc1e..e076777 100644
Binary files a/Platform/Hisilicon/D06/Drivers/Sas/SasDriverDxe.depex and b/Platform/Hisilicon/D06/Drivers/Sas/SasDriverDxe.depex differ
diff --git a/Platform/Hisilicon/D06/Drivers/Sas/SasDriverDxe.efi b/Platform/Hisilicon/D06/Drivers/Sas/SasDriverDxe.efi
index ac6bae7..4a29e8c 100644
Binary files a/Platform/Hisilicon/D06/Drivers/Sas/SasDriverDxe.efi and b/Platform/Hisilicon/D06/Drivers/Sas/SasDriverDxe.efi differ
--
2.9.5
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH edk2-non-osi v2 2/8] Hisilicon/D0x: Update PlatformSysCtrlLib binary
2019-02-20 7:25 [PATCH edk2-non-osi v2 0/8] Upload D0x binary modules Ming Huang
2019-02-20 7:25 ` [PATCH edk2-non-osi v2 1/8] Hisilicon/D06: Remove PCI enumeration dependency from SAS driver Ming Huang
@ 2019-02-20 7:25 ` Ming Huang
2019-02-20 7:25 ` [PATCH edk2-non-osi v2 3/8] Hisilicon/D06: Update Mbigen and gic RAS register Ming Huang
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Ming Huang @ 2019-02-20 7:25 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, michael.d.kinney, lersek, wanghuiqiang,
huangming23, zhangjinsong2, huangdaode, john.garry, zhangfeng56,
Ming Huang
As suggestion of community, 'AP' is a bit unfortunate to use in EDK2
context. PI specifies 'BSP' for Boot-strap Processor, as the one
executing all of the EDK2 code. It then uses 'AP' to refer to
Additional Processors, which can be assigned tasks using the
EFI_MP_SERVICES_PROTOCOL. In a TianoCore context, this should be
'BSP'. So, Rename StartupAp() to StartUpBSP.
This patch applies to D0x PlatformSysCtrlLib.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
---
Silicon/Hisilicon/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib | Bin 297590 -> 229128 bytes
Silicon/Hisilicon/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.lib | Bin 344310 -> 275312 bytes
Silicon/Hisilicon/Hi1620/Library/PlatformSysCtrlLibHi1620/PlatformSysCtrlLibHi1620.lib | Bin 356032 -> 375916 bytes
3 files changed, 0 insertions(+), 0 deletions(-)
diff --git a/Silicon/Hisilicon/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib b/Silicon/Hisilicon/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib
index 68be770..4c63a26 100644
Binary files a/Silicon/Hisilicon/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib and b/Silicon/Hisilicon/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib differ
diff --git a/Silicon/Hisilicon/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.lib b/Silicon/Hisilicon/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.lib
index b3cc88e..cb2c652 100644
Binary files a/Silicon/Hisilicon/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.lib and b/Silicon/Hisilicon/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.lib differ
diff --git a/Silicon/Hisilicon/Hi1620/Library/PlatformSysCtrlLibHi1620/PlatformSysCtrlLibHi1620.lib b/Silicon/Hisilicon/Hi1620/Library/PlatformSysCtrlLibHi1620/PlatformSysCtrlLibHi1620.lib
index 50d453a..d643f7b 100644
Binary files a/Silicon/Hisilicon/Hi1620/Library/PlatformSysCtrlLibHi1620/PlatformSysCtrlLibHi1620.lib and b/Silicon/Hisilicon/Hi1620/Library/PlatformSysCtrlLibHi1620/PlatformSysCtrlLibHi1620.lib differ
--
2.9.5
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH edk2-non-osi v2 3/8] Hisilicon/D06: Update Mbigen and gic RAS register
2019-02-20 7:25 [PATCH edk2-non-osi v2 0/8] Upload D0x binary modules Ming Huang
2019-02-20 7:25 ` [PATCH edk2-non-osi v2 1/8] Hisilicon/D06: Remove PCI enumeration dependency from SAS driver Ming Huang
2019-02-20 7:25 ` [PATCH edk2-non-osi v2 2/8] Hisilicon/D0x: Update PlatformSysCtrlLib binary Ming Huang
@ 2019-02-20 7:25 ` Ming Huang
2019-02-20 7:25 ` [PATCH edk2-non-osi v2 4/8] Hisilicon/D06: Support PCIe local RAS Ming Huang
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Ming Huang @ 2019-02-20 7:25 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, michael.d.kinney, lersek, wanghuiqiang,
huangming23, zhangjinsong2, huangdaode, john.garry, zhangfeng56,
Ming Huang
As chip group suggestions, update Mbigen and gic RAS configuration
flow.
Add below flow:
1 Reset Mbigen;
2 Disable Mbigen clock;
3 Deassert reset Mbigen;
4 Enable Mbigen clock;
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
---
Platform/Hisilicon/D06/Drivers/RasInitDxe/RasInitDxe.efi | Bin 17984 -> 18720 bytes
1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Hisilicon/D06/Drivers/RasInitDxe/RasInitDxe.efi b/Platform/Hisilicon/D06/Drivers/RasInitDxe/RasInitDxe.efi
index 19adbc9..9ea21e9 100644
Binary files a/Platform/Hisilicon/D06/Drivers/RasInitDxe/RasInitDxe.efi and b/Platform/Hisilicon/D06/Drivers/RasInitDxe/RasInitDxe.efi differ
--
2.9.5
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH edk2-non-osi v2 4/8] Hisilicon/D06: Support PCIe local RAS
2019-02-20 7:25 [PATCH edk2-non-osi v2 0/8] Upload D0x binary modules Ming Huang
` (2 preceding siblings ...)
2019-02-20 7:25 ` [PATCH edk2-non-osi v2 3/8] Hisilicon/D06: Update Mbigen and gic RAS register Ming Huang
@ 2019-02-20 7:25 ` Ming Huang
2019-02-20 7:25 ` [PATCH edk2-non-osi v2 5/8] Hisilicon/D06: Use new flash layout Ming Huang
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Ming Huang @ 2019-02-20 7:25 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, michael.d.kinney, lersek, wanghuiqiang,
huangming23, zhangjinsong2, huangdaode, john.garry, zhangfeng56,
Ming Huang
Add some registers configuration in PcieRasInitDxe and add PCIe
local RAS interrupt handle in trusted firmware to support PCIe
local RAS.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/Hisilicon/D06/Drivers/PcieRasInitDxe/PcieRasInitDxe.efi | Bin 21248 -> 22048 bytes
Platform/Hisilicon/D06/bl1.bin | Bin 12432 -> 12432 bytes
Platform/Hisilicon/D06/fip.bin | Bin 113450 -> 121866 bytes
3 files changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Hisilicon/D06/Drivers/PcieRasInitDxe/PcieRasInitDxe.efi b/Platform/Hisilicon/D06/Drivers/PcieRasInitDxe/PcieRasInitDxe.efi
index 0e22237..f9ceff2 100644
Binary files a/Platform/Hisilicon/D06/Drivers/PcieRasInitDxe/PcieRasInitDxe.efi and b/Platform/Hisilicon/D06/Drivers/PcieRasInitDxe/PcieRasInitDxe.efi differ
diff --git a/Platform/Hisilicon/D06/bl1.bin b/Platform/Hisilicon/D06/bl1.bin
index 416535f..d0970e5 100644
Binary files a/Platform/Hisilicon/D06/bl1.bin and b/Platform/Hisilicon/D06/bl1.bin differ
diff --git a/Platform/Hisilicon/D06/fip.bin b/Platform/Hisilicon/D06/fip.bin
index c9b7ca0..795cfb5 100644
Binary files a/Platform/Hisilicon/D06/fip.bin and b/Platform/Hisilicon/D06/fip.bin differ
--
2.9.5
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH edk2-non-osi v2 5/8] Hisilicon/D06: Use new flash layout
2019-02-20 7:25 [PATCH edk2-non-osi v2 0/8] Upload D0x binary modules Ming Huang
` (3 preceding siblings ...)
2019-02-20 7:25 ` [PATCH edk2-non-osi v2 4/8] Hisilicon/D06: Support PCIe local RAS Ming Huang
@ 2019-02-20 7:25 ` Ming Huang
2019-02-20 7:25 ` [PATCH edk2-non-osi v2 6/8] Hisilicon/D06: Fix numa node wrong issue Ming Huang
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Ming Huang @ 2019-02-20 7:25 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, michael.d.kinney, lersek, wanghuiqiang,
huangming23, zhangjinsong2, huangdaode, john.garry, zhangfeng56,
Ming Huang
In new flash layout, BIOS fd change from offset 1M to 8M in 16M
spi flash.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
---
Platform/Hisilicon/D06/CustomData.Fv | Bin 0 -> 65536 bytes
Platform/Hisilicon/D06/Library/OemAddressMapD06/OemAddressMapD06.lib | Bin 61892 -> 31696 bytes
Platform/Hisilicon/D06/Sec/FVMAIN_SEC.Fv | Bin 1048576 -> 1048576 bytes
3 files changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Hisilicon/D06/CustomData.Fv b/Platform/Hisilicon/D06/CustomData.Fv
new file mode 100644
index 0000000..22ef62b
Binary files /dev/null and b/Platform/Hisilicon/D06/CustomData.Fv differ
diff --git a/Platform/Hisilicon/D06/Library/OemAddressMapD06/OemAddressMapD06.lib b/Platform/Hisilicon/D06/Library/OemAddressMapD06/OemAddressMapD06.lib
index 7e1f6b2..851c2c3 100644
Binary files a/Platform/Hisilicon/D06/Library/OemAddressMapD06/OemAddressMapD06.lib and b/Platform/Hisilicon/D06/Library/OemAddressMapD06/OemAddressMapD06.lib differ
diff --git a/Platform/Hisilicon/D06/Sec/FVMAIN_SEC.Fv b/Platform/Hisilicon/D06/Sec/FVMAIN_SEC.Fv
index 247e44e..7f75bc6 100644
Binary files a/Platform/Hisilicon/D06/Sec/FVMAIN_SEC.Fv and b/Platform/Hisilicon/D06/Sec/FVMAIN_SEC.Fv differ
--
2.9.5
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH edk2-non-osi v2 6/8] Hisilicon/D06: Fix numa node wrong issue
2019-02-20 7:25 [PATCH edk2-non-osi v2 0/8] Upload D0x binary modules Ming Huang
` (4 preceding siblings ...)
2019-02-20 7:25 ` [PATCH edk2-non-osi v2 5/8] Hisilicon/D06: Use new flash layout Ming Huang
@ 2019-02-20 7:25 ` Ming Huang
2019-02-20 7:26 ` [PATCH edk2-non-osi v2 7/8] Hisilicon/D06: Add Setup Item "Support DPC" Ming Huang
2019-02-20 7:26 ` [PATCH edk2-non-osi v2 8/8] Hisilicon/D0x: Add some header files Ming Huang
7 siblings, 0 replies; 9+ messages in thread
From: Ming Huang @ 2019-02-20 7:25 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, michael.d.kinney, lersek, wanghuiqiang,
huangming23, zhangjinsong2, huangdaode, john.garry, zhangfeng56,
Ming Huang
Numa informations are acquired from HOB that build from memory
initialization module. Correct numa informations to match booting
from TA(Totem A or super cpu cluster A).
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
---
Platform/Hisilicon/D06/MemoryInitPei/MemoryInit.efi | Bin 297696 -> 358656 bytes
1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Hisilicon/D06/MemoryInitPei/MemoryInit.efi b/Platform/Hisilicon/D06/MemoryInitPei/MemoryInit.efi
index 5fba353..fea1475 100644
Binary files a/Platform/Hisilicon/D06/MemoryInitPei/MemoryInit.efi and b/Platform/Hisilicon/D06/MemoryInitPei/MemoryInit.efi differ
--
2.9.5
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH edk2-non-osi v2 7/8] Hisilicon/D06: Add Setup Item "Support DPC"
2019-02-20 7:25 [PATCH edk2-non-osi v2 0/8] Upload D0x binary modules Ming Huang
` (5 preceding siblings ...)
2019-02-20 7:25 ` [PATCH edk2-non-osi v2 6/8] Hisilicon/D06: Fix numa node wrong issue Ming Huang
@ 2019-02-20 7:26 ` Ming Huang
2019-02-20 7:26 ` [PATCH edk2-non-osi v2 8/8] Hisilicon/D0x: Add some header files Ming Huang
7 siblings, 0 replies; 9+ messages in thread
From: Ming Huang @ 2019-02-20 7:26 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, michael.d.kinney, lersek, wanghuiqiang,
huangming23, zhangjinsong2, huangdaode, john.garry, zhangfeng56,
Ming Huang
Add setup item "Support DPC" to enable or disable PCIe DPC
(Downstream Port Containment).
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi | Bin 232832 -> 226784 bytes
1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi
index e32c056..4511f6b 100644
Binary files a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi and b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi differ
--
2.9.5
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH edk2-non-osi v2 8/8] Hisilicon/D0x: Add some header files
2019-02-20 7:25 [PATCH edk2-non-osi v2 0/8] Upload D0x binary modules Ming Huang
` (6 preceding siblings ...)
2019-02-20 7:26 ` [PATCH edk2-non-osi v2 7/8] Hisilicon/D06: Add Setup Item "Support DPC" Ming Huang
@ 2019-02-20 7:26 ` Ming Huang
7 siblings, 0 replies; 9+ messages in thread
From: Ming Huang @ 2019-02-20 7:26 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, michael.d.kinney, lersek, wanghuiqiang,
huangming23, zhangjinsong2, huangdaode, john.garry, zhangfeng56,
Ming Huang
As interfaces exposed only by implementations in edk2-non-osi,
so move some header files from edk2-platforms to edk2-non-osi.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
---
Silicon/Hisilicon/Include/Library/IpmiCmdLib.h | 110 +++++++++++++++++++
Silicon/Hisilicon/Include/Library/LpcLib.h | 113 ++++++++++++++++++++
Silicon/Hisilicon/Include/Library/OemAddressMapLib.h | 45 ++++++++
Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h | 112 +++++++++++++++++++
Silicon/Hisilicon/Include/Library/SerdesLib.h | 21 ++++
5 files changed, 401 insertions(+)
diff --git a/Silicon/Hisilicon/Include/Library/IpmiCmdLib.h b/Silicon/Hisilicon/Include/Library/IpmiCmdLib.h
new file mode 100644
index 0000000..b956ee6
--- /dev/null
+++ b/Silicon/Hisilicon/Include/Library/IpmiCmdLib.h
@@ -0,0 +1,110 @@
+/** @file
+*
+* Copyright (c) 2017, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2017, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _IPMI_CMD_LIB_H_
+#define _IPMI_CMD_LIB_H_
+
+#define BOOT_OPTION_BOOT_FLAG_VALID 1
+#define BOOT_OPTION_BOOT_FLAG_INVALID 0
+
+typedef enum {
+ EfiReserved,
+ EfiBiosFrb2,
+ EfiBiosPost,
+ EfiOsLoad,
+ EfiSmsOs,
+ EfiOem,
+ EfiFrbReserved1,
+ EfiFrbReserved2
+} EFI_WDT_USER_TYPE;
+
+typedef enum {
+ NoOverride = 0x0,
+ ForcePxe,
+ ForceDefaultHardDisk,
+ ForceDefaultHardDiskSafeMode,
+ ForceDefaultDiagnosticPartition,
+ ForceDefaultCD,
+ ForceSetupUtility,
+ ForceRemoteRemovableMedia,
+ ForceRemoteCD,
+ ForcePrimaryRemoteMedia,
+ ForceRemoteHardDisk = 0xB,
+ ForcePrimaryRemovableMedia = 0xF
+} BOOT_DEVICE_SELECTOR;
+
+//
+// Get System Boot Option data structure
+//
+typedef struct {
+ UINT8 ParameterVersion :4;
+ UINT8 Reserved1 :4;
+ UINT8 ParameterSelector :7;
+ UINT8 ParameterValid :1;
+ //
+ // Boot Flags Data 1
+ //
+ UINT8 Reserved2 :5;
+ UINT8 BiosBootType :1;
+ UINT8 Persistent :1;
+ UINT8 BootFlagsValid :1;
+ //
+ // Boot Flags Data 2
+ //
+ UINT8 LockResetBtn :1;
+ UINT8 ScreenBlank :1;
+ UINT8 BootDeviceSelector :4;
+ UINT8 LockKeyboard :1;
+ UINT8 ClearCmos :1;
+ //
+ // Boot Flags Data 3
+ //
+ UINT8 ConsoleRedirectionControl :2;
+ UINT8 LockSleepBtn :1;
+ UINT8 UserPasswordByPass :1;
+ UINT8 Reserved3 :1;
+ UINT8 FirmwareVerbosity :2;
+ UINT8 LockPowerBtn :1;
+ //
+ // Boot Flags Data 4
+ //
+ UINT8 MuxControlOverride :3;
+ UINT8 ShareModeOverride :1;
+ UINT8 Reserved4 :4;
+ //
+ // Boot Flags Data 5
+ //
+ UINT8 DeviceInstanceSelector :5;
+ UINT8 Reserved5 :3;
+} IPMI_GET_BOOT_OPTION;
+
+EFI_STATUS
+EFIAPI
+IpmiCmdSetSysBootOptions (
+ OUT IPMI_GET_BOOT_OPTION *BootOption
+ );
+
+EFI_STATUS
+EFIAPI
+IpmiCmdGetSysBootOptions (
+ IN IPMI_GET_BOOT_OPTION *BootOption
+ );
+
+EFI_STATUS
+IpmiCmdStopWatchdogTimer (
+ IN EFI_WDT_USER_TYPE UserType
+ );
+
+#endif
diff --git a/Silicon/Hisilicon/Include/Library/LpcLib.h b/Silicon/Hisilicon/Include/Library/LpcLib.h
new file mode 100755
index 0000000..236a52b
--- /dev/null
+++ b/Silicon/Hisilicon/Include/Library/LpcLib.h
@@ -0,0 +1,113 @@
+/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _LPC_LIB_H_
+#define _LPC_LIB_H_
+
+#include <Uefi.h>
+
+#define PCIE_SUBSYS_IO_MUX 0xA0170000
+#define PCIE_SUBSYS_IOMG033 (PCIE_SUBSYS_IO_MUX + 0x84)
+#define PCIE_SUBSYS_IOMG035 (PCIE_SUBSYS_IO_MUX + 0x8C)
+#define PCIE_SUBSYS_IOMG036 (PCIE_SUBSYS_IO_MUX + 0x90)
+#define PCIE_SUBSYS_IOMG045 (PCIE_SUBSYS_IO_MUX + 0xB4)
+#define PCIE_SUBSYS_IOMG046 (PCIE_SUBSYS_IO_MUX + 0xB8)
+#define PCIE_SUBSYS_IOMG047 (PCIE_SUBSYS_IO_MUX + 0xBC)
+#define PCIE_SUBSYS_IOMG048 (PCIE_SUBSYS_IO_MUX + 0xC0)
+#define PCIE_SUBSYS_IOMG049 (PCIE_SUBSYS_IO_MUX + 0xC4)
+#define PCIE_SUBSYS_IOMG050 (PCIE_SUBSYS_IO_MUX + 0xC8)
+
+#define IO_WRAP_CTRL_BASE 0xA0100000
+#define SC_LPC_CLK_EN_REG (IO_WRAP_CTRL_BASE + 0x03a0)
+#define SC_LPC_CLK_DIS_REG (IO_WRAP_CTRL_BASE + 0x03a4)
+#define SC_LPC_BUS_CLK_EN_REG (IO_WRAP_CTRL_BASE + 0x03a8)
+#define SC_LPC_BUS_CLK_DIS_REG (IO_WRAP_CTRL_BASE + 0x03ac)
+#define SC_LPC_RESET_REQ (IO_WRAP_CTRL_BASE + 0x0ad8)
+#define SC_LPC_RESET_DREQ (IO_WRAP_CTRL_BASE + 0x0adc)
+#define SC_LPC_BUS_RESET_REQ (IO_WRAP_CTRL_BASE + 0x0ae0)
+#define SC_LPC_BUS_RESET_DREQ (IO_WRAP_CTRL_BASE + 0x0ae4)
+#define SC_LPC_CTRL_REG (IO_WRAP_CTRL_BASE + 0x2028)
+
+
+#define LPC_BASE 0xA01B0000
+#define LPC_START_REG (LPC_BASE + 0x00)
+#define LPC_OP_STATUS_REG (LPC_BASE + 0x04)
+#define LPC_IRQ_ST_REG (LPC_BASE + 0x08)
+#define LPC_OP_LEN_REG (LPC_BASE + 0x10)
+#define LPC_CMD_REG (LPC_BASE + 0x14)
+#define LPC_FWH_ID_MSIZE_REG (LPC_BASE + 0x18)
+#define LPC_ADDR_REG (LPC_BASE + 0x20)
+#define LPC_WDATA_REG (LPC_BASE + 0x24)
+#define LPC_RDATA_REG (LPC_BASE + 0x28)
+#define LPC_LONG_CNT_REG (LPC_BASE + 0x30)
+#define LPC_TX_FIFO_ST_REG (LPC_BASE + 0x50)
+#define LPC_RX_FIFO_ST_REG (LPC_BASE + 0x54)
+#define LPC_TIME_OUT_REG (LPC_BASE + 0x58)
+#define LPC_SIRQ_CTRL0_REG (LPC_BASE + 0x80)
+#define LPC_SIRQ_CTRL1_REG (LPC_BASE + 0x84)
+#define LPC_SIRQ_INT_REG (LPC_BASE + 0x90)
+#define LPC_SIRQ_INT_MASK_REG (LPC_BASE + 0x94)
+#define LPC_SIRQ_STAT_REG (LPC_BASE + 0xA0)
+
+#define LPC_FIFO_LEN (16)
+
+typedef enum{
+ LPC_ADDR_MODE_INCREASE,
+ LPC_ADDR_MODE_SINGLE
+}LPC_ADDR_MODE;
+
+typedef enum{
+ LPC_TYPE_IO,
+ LPC_TYPE_MEM,
+ LPC_TYPE_FWH
+}LPC_TYPE;
+
+
+typedef union {
+ struct{
+ UINT32 lpc_wr:1;
+ UINT32 lpc_type:2;
+ UINT32 same_addr:1;
+ UINT32 resv:28;
+ }bits;
+ UINT32 u32;
+}LPC_CMD_STRUCT;
+
+typedef union {
+ struct{
+ UINT32 op_len:5;
+ UINT32 resv:27;
+ }bits;
+ UINT32 u32;
+}LPC_OP_LEN_STRUCT;
+
+
+VOID LpcInit(VOID);
+BOOLEAN LpcIdle(VOID);
+EFI_STATUS LpcByteWrite(
+ IN UINT32 Addr,
+ IN UINT8 Data);
+EFI_STATUS LpcByteRead(
+ IN UINT32 Addr,
+ IN OUT UINT8 *Data);
+
+EFI_STATUS LpcWrite(
+ IN UINT32 Addr,
+ IN UINT8 *Data,
+ IN UINT8 Len);
+
+#endif
+
+
diff --git a/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h b/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h
new file mode 100644
index 0000000..b5de34f
--- /dev/null
+++ b/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h
@@ -0,0 +1,45 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _OEM_ADDRESS_MAP_LIB_H_
+#define _OEM_ADDRESS_MAP_LIB_H_
+
+#include <PlatformArch.h>
+
+typedef struct _DDRC_BASE_ID{
+ UINTN Base;
+ UINTN Id;
+}DDRC_BASE_ID;
+
+// Invalid address, will cause exception when accessed by bug code
+#define ADDRESS_MAP_INVALID ((UINTN)(-1))
+
+UINTN OemGetPoeSubBase (UINT32 NodeId);
+UINTN OemGetPeriSubBase (UINT32 NodeId);
+UINTN OemGetAlgSubBase (UINT32 NodeId);
+UINTN OemGetCfgbusBase (UINT32 NodeId);
+UINTN OemGetGicSubBase (UINT32 NodeId);
+UINTN OemGetHACSubBase (UINT32 NodeId);
+UINTN OemGetIOMGMTSubBase (UINT32 NodeId);
+UINTN OemGetNetworkSubBase (UINT32 NodeId);
+UINTN OemGetM3SubBase (UINT32 NodeId);
+UINTN OemGetPCIeSubBase (UINT32 NodeId);
+
+VOID OemAddressMapInit(VOID);
+
+extern DDRC_BASE_ID DdrcBaseId[MAX_SOCKET][MAX_CHANNEL];
+
+#endif
+
diff --git a/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h b/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h
new file mode 100644
index 0000000..712b77c
--- /dev/null
+++ b/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h
@@ -0,0 +1,112 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _PLATFORM_SYS_CTRL_LIB_H_
+#define _PLATFORM_SYS_CTRL_LIB_H_
+
+#define PACKAGE_16CORE 0
+#define PACKAGE_32CORE 1
+#define PACKAGE_RESERVED 2
+#define PACKAGE_TYPE_NUM 3
+
+UINT32 PlatformGetPackageType (VOID);
+
+VOID DisplayCpuInfo (VOID);
+UINT32 CheckChipIsEc(VOID);
+
+UINTN PlatformGetPll (UINT32 NodeId, UINTN Pll);
+
+#define DJTAG_READ_INVALID_VALUE 0xFFFFFFFF
+#define DJTAG_CHAIN_ID_AA 1
+#define DJTAG_CHAIN_ID_LLC 4
+
+
+#define SC_DJTAG_MSTR_EN_OFFSET 0x6800
+#define SC_DJTAG_MSTR_START_EN_OFFSET 0x6804
+#define SC_DJTAG_SEC_ACC_EN_OFFSET 0x6808
+#define SC_DJTAG_DEBUG_MODULE_SEL_OFFSET 0x680C
+#define SC_DJTAG_MSTR_WR_OFFSET 0x6810
+#define SC_DJTAG_CHAIN_UNIT_CFG_EN_OFFSET 0x6814
+#define SC_DJTAG_MSTR_ADDR_OFFSET 0x6818
+#define SC_DJTAG_MSTR_DATA_OFFSET 0x681C
+#define SC_DJTAG_TMOUT_OFFSET 0x6820
+#define SC_TDRE_OP_ADDR_OFFSET 0x6824
+#define SC_TDRE_WDATA_OFFSET 0x6828
+#define SC_TDRE_REPAIR_EN_OFFSET 0x682C
+#define SC_DJTAG_RD_DATA0_OFFSET 0xE800
+#define SC_TDRE_RDATA0_OFFSET 0xE830
+
+
+UINTN PlatformGetI2cBase(UINT32 Socket,UINT8 Port);
+
+VOID PlatformAddressMapCleanUp (VOID);
+VOID PlatformDisableDdrWindow (VOID);
+
+VOID PlatformEnableArchTimer (VOID);
+
+EFI_STATUS
+DawFindFreeWindow (UINTN Socket, UINTN *DawIndex);
+
+VOID DawSetWindow (UINTN Socket, UINTN WindowIndex, UINT32 Value);
+
+VOID DJTAG_TDRE_WRITE(UINT32 Offset, UINT32 Value, UINT32 ChainID, UINT32 NodeId, BOOLEAN Repair);
+
+UINT32 DJTAG_TDRE_READ(UINT32 Offset, UINT32 ChainID, UINT32 NodeId, BOOLEAN Repair);
+
+VOID RemoveRoceReset(VOID);
+
+UINTN PlatformGetDdrChannel (VOID);
+
+VOID ITSCONFIG (VOID);
+
+VOID MN_CONFIG (VOID);
+
+VOID SmmuConfigForOS (VOID);
+VOID SmmuConfigForBios (VOID);
+
+VOID StartUpBSP (VOID);
+
+VOID LlcCleanInvalidate (VOID);
+
+UINTN PlatformGetCpuFreq (UINT8 Socket);
+VOID ClearInterruptStatus(VOID);
+
+UINTN PlatformGetCoreCount (VOID);
+VOID DAWConfigEn(UINT32 socket);
+
+VOID DResetUsb ();
+UINT32 PlatformGetEhciBase ();
+UINT32 PlatformGetOhciBase ();
+VOID PlatformPllInit();
+// PLL initialization for super IO clusters.
+VOID SiclPllInit(UINT32 SclId);
+VOID PlatformDeviceDReset();
+VOID PlatformGicdInit();
+VOID PlatformLpcInit();
+// Synchronize architecture timer counter between different super computing
+// clusters.
+VOID PlatformArchTimerSynchronize(VOID);
+VOID PlatformEventBroadcastConfig(VOID);
+UINTN GetDjtagRegBase(UINT32 NodeId);
+VOID LlcCleanInvalidateAsm(VOID);
+VOID PlatformMdioInit(VOID);
+VOID DisableClusterClock(UINTN CpuClusterBase);
+VOID EnableClusterClock(UINTN CpuClusterBase);
+VOID DisableSocketClock (UINT8 Skt);
+
+EFI_STATUS EFIAPI HandleI2CException (UINT32 Socket, UINT32 Port);
+EFI_STATUS EFIAPI HandleI2CExceptionBySocket (UINT32 Socket);
+
+#endif
diff --git a/Silicon/Hisilicon/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Include/Library/SerdesLib.h
new file mode 100644
index 0000000..e3fe9b7
--- /dev/null
+++ b/Silicon/Hisilicon/Include/Library/SerdesLib.h
@@ -0,0 +1,21 @@
+/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _SERDES_LIB_H_
+#define _SERDES_LIB_H_
+
+EFI_STATUS EfiSerdesInitWrap (VOID);
+
+#endif
--
2.9.5
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