From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::444; helo=mail-pf1-x444.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf1-x444.google.com (mail-pf1-x444.google.com [IPv6:2607:f8b0:4864:20::444]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 31EA2211CAF52 for ; Tue, 19 Feb 2019 23:29:11 -0800 (PST) Received: by mail-pf1-x444.google.com with SMTP id n125so4206022pfn.5 for ; Tue, 19 Feb 2019 23:29:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ab7zoCPUAckYvbGEHQgQ2OoONoXR45pa9pDts4Jv7Lw=; b=Hdbri/jr0r3p2pqasHvVhLqqKHpzacEhlB3TW6F3fg8Soe68qofAkkxKEFl6ELUOf9 JdFjfP59bGYe2Cj3Un2IZgfQKNUTIV7gfiIWJw3hJo+AJFf70S4PGipmqx2xL4vpK3Ri Bw9N7xUs5mUrlEy4CDV51p3pNes2oZTRJHF3akK2Ghz2yGwM8k1xd5JhrIZ0ZP0ahf3a abCU9bbJ3Xl4IREPv5yUfpb685lrqrQVYaQHX34ZlVqrMk5cPOHWJTLoHA4ckH9kTPH+ ueegEdzb3AlkuUPcF2GffDIb99IrtwPEO/mpilsIKM7vMqTVnTVITQeNDlRzlPKrBXrm uhTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ab7zoCPUAckYvbGEHQgQ2OoONoXR45pa9pDts4Jv7Lw=; b=kL2lOVwUb+jIDpS6cDByarddnQC319ihJIrGtdxkeoxjBANJa/whcdmDH4pS6oE1m5 FJuEylEZeOWc5HiCQeAnxRGeoHeUk/TMaGFR3xFcO47JYaLfYddfDiWpjl4wEvbjpQUY EA0/Z9YPAGxbGzET7alFZcZ///EQySrI8AldnjcAl51/4lx55ocnP0ghIhMbhUedLPQ5 RcQNur7ghGr4tsV8didLtyfHkfSHbrMA74Hy+5Zx6UcgqDInj4zgOgPQ2EjhU1Tvb6Il Rwmf+QtC+cJuqbsJkc8gIfqZtV78obVKCxS73SCkM16SzJ0EBRwXf/E9hv0kyxKKSwlH teAw== X-Gm-Message-State: AHQUAuYj9wViRygFpCv6sOOHVs/loyp8ioaIELToFcUCfpFiut/Rur64 ICox58x9HHUnwHnaWKMJiTbt7Q== X-Google-Smtp-Source: AHgI3IY8+msSkaMzbiNVvk1jJWEQdmgfm6NuoLzUUz6R3AnYer70ISE8ILky/+nPEL7upyKnqRe8zg== X-Received: by 2002:aa7:92da:: with SMTP id k26mr18771387pfa.216.1550647750936; Tue, 19 Feb 2019 23:29:10 -0800 (PST) Received: from localhost.localdomain ([203.160.91.226]) by smtp.gmail.com with ESMTPSA id 23sm19152969pft.187.2019.02.19.23.29.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Feb 2019 23:29:10 -0800 (PST) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, zhangfeng56@huawei.com, xiaojun2@hisilicon.com, Ming Huang Date: Wed, 20 Feb 2019 15:28:27 +0800 Message-Id: <20190220072837.35058-9-ming.huang@linaro.org> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20190220072837.35058-1-ming.huang@linaro.org> References: <20190220072837.35058-1-ming.huang@linaro.org> Subject: [PATCH edk2-platforms v2 08/18] Hisilicon/D06: Use HCCS speed with 2.6G X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Feb 2019 07:29:11 -0000 Follow chip team suggestion, HCCS(Huawei Cache-Coherent System) may be unstable while speed is 3.0G, so use 2.6G to avoid some unstable stress issue. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Silicon/Hisilicon/Include/Library/OemMiscLib.h | 10 ++++++++++ Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c | 8 ++++++++ 2 files changed, 18 insertions(+) diff --git a/Silicon/Hisilicon/Include/Library/OemMiscLib.h b/Silicon/Hisilicon/Include/Library/OemMiscLib.h index dfac87d635d9..ea95fe38d75c 100644 --- a/Silicon/Hisilicon/Include/Library/OemMiscLib.h +++ b/Silicon/Hisilicon/Include/Library/OemMiscLib.h @@ -22,6 +22,11 @@ #include #include +#define HCCS_PLL_VALUE_2600 0x52240681 +#define HCCS_PLL_VALUE_2800 0x52240701 +#define HCCS_PLL_VALUE_3000 0x52240781 + + #define PCIEDEVICE_REPORT_MAX 8 #define MAX_PROCESSOR_SOCKETS MAX_SOCKET #define MAX_MEMORY_CHANNELS MAX_CHANNEL @@ -55,4 +60,9 @@ extern EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM]; EFI_HII_HANDLE EFIAPI OemGetPackages (); UINTN OemGetCpuFreq (UINT8 Socket); +UINTN +OemGetHccsFreq ( + VOID + ); + #endif diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c index 624fa33d2e14..914387de7d63 100644 --- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c @@ -223,3 +223,11 @@ UINTN OemGetCpuFreq (UINT8 Socket) } } +UINTN +OemGetHccsFreq ( + VOID + ) +{ + return HCCS_PLL_VALUE_2600; +} + -- 2.9.5