From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.151; helo=mga17.intel.com; envelope-from=jiewen.yao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 26AA6211CCD5A for ; Thu, 21 Feb 2019 20:16:17 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Feb 2019 20:16:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,398,1544515200"; d="scan'208";a="116876454" Received: from jyao1-mobl2.ccr.corp.intel.com ([10.239.192.59]) by orsmga007.jf.intel.com with ESMTP; 21 Feb 2019 20:16:15 -0800 From: Jiewen Yao To: edk2-devel@lists.01.org Cc: Eric Dong , Ray Ni , Laszlo Ersek , Yao Jiewen Date: Fri, 22 Feb 2019 12:15:57 +0800 Message-Id: <20190222041558.25312-3-jiewen.yao@intel.com> X-Mailer: git-send-email 2.19.2.windows.1 In-Reply-To: <20190222041558.25312-1-jiewen.yao@intel.com> References: <20190222041558.25312-1-jiewen.yao@intel.com> MIME-Version: 1.0 Subject: [PATCH 2/3] UefiCpuPkg/ExceptionLib: Add CET support. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Feb 2019 04:16:17 -0000 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521 Add information dump for Control Protection exception. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yao Jiewen --- UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c | 7 ++++--- UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h | 3 ++- UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c | 5 +++-- UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c | 5 +++-- 4 files changed, 12 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c index 0576144a97..ca210d1de2 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c @@ -1,7 +1,7 @@ /** @file CPU Exception Handler Library common functions. - Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -20,7 +20,7 @@ // // 1 means an error code will be pushed, otherwise 0 // -CONST UINT32 mErrorCodeFlag = 0x00027d00; +CONST UINT32 mErrorCodeFlag = 0x00227d00; // // Define the maximum message length @@ -49,7 +49,8 @@ CONST CHAR8 *mExceptionNameStr[] = { "#AC - Alignment Check", "#MC - Machine-Check", "#XM - SIMD floating-point", - "#VE - Virtualization" + "#VE - Virtualization", + "#CP - Control Protection" }; #define EXCEPTION_KNOWN_NAME_NUM (sizeof (mExceptionNameStr) / sizeof (CHAR8 *)) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h index 83e55ab828..edf46cb60d 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h @@ -1,7 +1,7 @@ /** @file Common header file for CPU Exception Handler Library. - Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -39,6 +39,7 @@ #define IA32_PF_EC_RSVD BIT3 #define IA32_PF_EC_ID BIT4 #define IA32_PF_EC_PK BIT5 +#define IA32_PF_EC_SS BIT6 #define IA32_PF_EC_SGX BIT15 #include "ArchInterruptDefs.h" diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c index 531258610a..f3d993af75 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c @@ -1,7 +1,7 @@ /** @file IA32 CPU Exception Handler functons. - Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -326,13 +326,14 @@ DumpCpuContext ( ); if (ExceptionType == EXCEPT_IA32_PAGE_FAULT) { InternalPrintMessage ( - " I:%x R:%x U:%x W:%x P:%x PK:%x S:%x", + " I:%x R:%x U:%x W:%x P:%x PK:%x SS:%x SGX:%x", (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0, (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_RSVD) != 0, (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_US) != 0, (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_WR) != 0, (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_P) != 0, (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_PK) != 0, + (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_SS) != 0, (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_SGX) != 0 ); } diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c index d7e883d19a..0183239e59 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c @@ -1,7 +1,7 @@ /** @file x64 CPU Exception Handler. - Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -299,13 +299,14 @@ DumpCpuContext ( ); if (ExceptionType == EXCEPT_IA32_PAGE_FAULT) { InternalPrintMessage ( - " I:%x R:%x U:%x W:%x P:%x PK:%x S:%x", + " I:%x R:%x U:%x W:%x P:%x PK:%x SS:%x SGX:%x", (SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0, (SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_RSVD) != 0, (SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_US) != 0, (SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_WR) != 0, (SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_P) != 0, (SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_PK) != 0, + (SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_SS) != 0, (SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_SGX) != 0 ); } -- 2.19.2.windows.1