From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.106.50; helo=cam-smtp0.cambridge.arm.com; envelope-from=sami.mujawar@arm.com; receiver=edk2-devel@lists.01.org Received: from cam-smtp0.cambridge.arm.com (unknown [217.140.106.50]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8FF91202E5324 for ; Fri, 22 Feb 2019 11:43:42 -0800 (PST) Received: from E107187.Arm.com (e107187.arm.com [10.1.195.55]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id x1MJhXa3010669; Fri, 22 Feb 2019 19:43:33 GMT From: Sami Mujawar To: edk2-devel@lists.01.org Cc: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, Matteo.Carlini@arm.com, Stephanie.Hughes-Fitt@arm.com, carl@cog.systems, nd@arm.com Date: Fri, 22 Feb 2019 19:43:28 +0000 Message-Id: <20190222194328.36248-1-sami.mujawar@arm.com> X-Mailer: git-send-email 2.11.0.windows.3 Subject: [PATCH v1 1/1] ArmPkg: Fix writes to GICv3 GICD_IROUTER reg X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Feb 2019 19:43:43 -0000 According to ARM Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0, GICD_IROUTER is a 64-bit register. Fixed code to use 64 bit MMIO write operations so that the Aff3 value (bits [39:32]) is written to GICD_IROUTER. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sami Mujawar Reported-by: Carl van Schaik --- The changes can be seen at https://github.com/samimujawar/edk2/tree/352_fix_gicv3_GICD_IROUTERn_v1 ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c index 1558db31713a828f324a807583076b21dd3302d0..67c74f79654586f8b6e47795d3c7400b88172d6e 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2011-2017, ARM Limited. All rights reserved. +* Copyright (c) 2011-2018, ARM Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License @@ -467,7 +467,7 @@ GicV3DxeInitialize ( // Route the SPIs to the primary CPU. SPIs start at the INTID 32 for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) { - MmioWrite32 ( + MmioWrite64 ( mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), CpuTarget ); -- 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'