From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.151; helo=mga17.intel.com; envelope-from=hao.a.wu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4CFB9211CD639 for ; Mon, 4 Mar 2019 17:13:48 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Mar 2019 17:13:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,441,1544515200"; d="scan'208";a="138068637" Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.8]) by FMSMGA003.fm.intel.com with ESMTP; 04 Mar 2019 17:13:47 -0800 From: Hao Wu To: edk2-devel@lists.01.org Cc: "Cohen, Eugene" , Ard Biesheuvel , Ashish Singhal , Hao Wu Date: Tue, 5 Mar 2019 09:13:41 +0800 Message-Id: <20190305011341.10440-2-hao.a.wu@intel.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20190305011341.10440-1-hao.a.wu@intel.com> References: <20190305011341.10440-1-hao.a.wu@intel.com> Subject: [PATCH v2 1/1] MdeModulePkg/SdMmcPciHcDxe: Fix DMA on SDHC v3 64-bit systems X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Mar 2019 01:13:48 -0000 From: "Cohen, Eugene" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1583 The SdMmcPciHcDriverBindingStart function was checking two different capability bits in determining whether 64-bit DMA modes were supported, one mode is defined in the SDHC version 3 specification (using 96-bit descriptors) and another is defined in the SDHC version 4 specification (using 128-bit descriptors). Since the currently implementation of 64-bit ADMA2 only supports the SDHC version 4 implementation, it is incorrect to check the V3 64-bit capability bit since this will activate V4 ADMA2 on V3 controllers which then causes buffers to be allocated that cannot be DMAed. Cc: Ard Biesheuvel Cc: Ashish Singhal Cc: Hao Wu Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eugene Cohen Acked-by: Ard Biesheuvel Acked-by: Ashish Singhal Reviewed-by: Hao Wu --- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c index b474f8decd..5bc91c5337 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c @@ -666,8 +666,7 @@ SdMmcPciHcDriverBindingStart ( // If any of the slots does not support 64b system bus // do not enable 64b DMA in the PCI layer. // - if (Private->Capability[Slot].SysBus64V3 == 0 && - Private->Capability[Slot].SysBus64V4 == 0) { + if (Private->Capability[Slot].SysBus64V4 == 0) { Support64BitDma = FALSE; } -- 2.12.0.windows.1