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* [PATCH V2] UefiCpuPkg/CpuCommonFeaturesLib: Aesni.c uses BIT0 and BIT1 reversedly
@ 2019-03-14  4:24 Star Zeng
  2019-03-15  5:35 ` Dong, Eric
  0 siblings, 1 reply; 2+ messages in thread
From: Star Zeng @ 2019-03-14  4:24 UTC (permalink / raw)
  To: edk2-devel; +Cc: Star Zeng, Laszlo Ersek, Eric Dong, Ruiyu Ni, Chandana Kumar

V2:
Correct description "disable(0)/enable(1)" to "disable(1)/enable(0)".

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1621

According to Intel SDM as below, the BIT0 should be treated as
lock bit, and BIT1 should be treated as disable(1)/enable(0) bit.

"11b: AES instructions are not available until next
RESET.
Otherwise, AES instructions are available.
If the configuration is not 01b, AES
instructions can be mis-configured if a privileged agent
unintentionally writes 11b"

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Chandana Kumar <chandana.c.kumar@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
---
 UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
index 56b1b551d977..3f7c933e51f4 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
@@ -1,7 +1,7 @@
 /** @file
   AESNI feature.
 
-  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -123,7 +123,7 @@ AesniInitialize (
         MSR_SANDY_BRIDGE_FEATURE_CONFIG,
         MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER,
         Bits.AESConfiguration,
-        BIT1 | ((State) ? 0 : BIT0)
+        BIT0 | ((State) ? 0 : BIT1)
         );
     }
   }
-- 
2.21.0.windows.1



^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH V2] UefiCpuPkg/CpuCommonFeaturesLib: Aesni.c uses BIT0 and BIT1 reversedly
  2019-03-14  4:24 [PATCH V2] UefiCpuPkg/CpuCommonFeaturesLib: Aesni.c uses BIT0 and BIT1 reversedly Star Zeng
@ 2019-03-15  5:35 ` Dong, Eric
  0 siblings, 0 replies; 2+ messages in thread
From: Dong, Eric @ 2019-03-15  5:35 UTC (permalink / raw)
  To: Zeng, Star, edk2-devel@lists.01.org
  Cc: Laszlo Ersek, Ni, Ray, Kumar, Chandana C

Reviewed-by: Eric Dong <eric.dong@intel.com>

> -----Original Message-----
> From: Zeng, Star
> Sent: Thursday, March 14, 2019 12:24 PM
> To: edk2-devel@lists.01.org
> Cc: Zeng, Star <star.zeng@intel.com>; Laszlo Ersek <lersek@redhat.com>;
> Dong, Eric <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar,
> Chandana C <chandana.c.kumar@intel.com>
> Subject: [PATCH V2] UefiCpuPkg/CpuCommonFeaturesLib: Aesni.c uses BIT0
> and BIT1 reversedly
> 
> V2:
> Correct description "disable(0)/enable(1)" to "disable(1)/enable(0)".
> 
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1621
> 
> According to Intel SDM as below, the BIT0 should be treated as lock bit, and
> BIT1 should be treated as disable(1)/enable(0) bit.
> 
> "11b: AES instructions are not available until next RESET.
> Otherwise, AES instructions are available.
> If the configuration is not 01b, AES
> instructions can be mis-configured if a privileged agent unintentionally writes
> 11b"
> 
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Ruiyu Ni <ruiyu.ni@intel.com>
> Cc: Chandana Kumar <chandana.c.kumar@intel.com>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Star Zeng <star.zeng@intel.com>
> ---
>  UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
> b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
> index 56b1b551d977..3f7c933e51f4 100644
> --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
> +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
> @@ -1,7 +1,7 @@
>  /** @file
>    AESNI feature.
> 
> -  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +  Copyright (c) 2017 - 2019, Intel Corporation. All rights
> + reserved.<BR>
>    This program and the accompanying materials
>    are licensed and made available under the terms and conditions of the BSD
> License
>    which accompanies this distribution.  The full text of the license may be
> found at @@ -123,7 +123,7 @@ AesniInitialize (
>          MSR_SANDY_BRIDGE_FEATURE_CONFIG,
>          MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER,
>          Bits.AESConfiguration,
> -        BIT1 | ((State) ? 0 : BIT0)
> +        BIT0 | ((State) ? 0 : BIT1)
>          );
>      }
>    }
> --
> 2.21.0.windows.1



^ permalink raw reply	[flat|nested] 2+ messages in thread

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