From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=star.zeng@intel.com; receiver=edk2-devel@lists.01.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7B8BE211DC098 for ; Wed, 13 Mar 2019 21:24:21 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Mar 2019 21:24:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,477,1544515200"; d="scan'208";a="327148841" Received: from shwdeopenpsi068.ccr.corp.intel.com ([10.239.158.59]) by fmsmga006.fm.intel.com with ESMTP; 13 Mar 2019 21:24:19 -0700 From: Star Zeng To: edk2-devel@lists.01.org Cc: Star Zeng , Laszlo Ersek , Eric Dong , Ruiyu Ni , Chandana Kumar Date: Thu, 14 Mar 2019 12:24:17 +0800 Message-Id: <20190314042417.3696-1-star.zeng@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 MIME-Version: 1.0 Subject: [PATCH V2] UefiCpuPkg/CpuCommonFeaturesLib: Aesni.c uses BIT0 and BIT1 reversedly X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Mar 2019 04:24:21 -0000 Content-Transfer-Encoding: 8bit V2: Correct description "disable(0)/enable(1)" to "disable(1)/enable(0)". BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1621 According to Intel SDM as below, the BIT0 should be treated as lock bit, and BIT1 should be treated as disable(1)/enable(0) bit. "11b: AES instructions are not available until next RESET. Otherwise, AES instructions are available. If the configuration is not 01b, AES instructions can be mis-configured if a privileged agent unintentionally writes 11b" Cc: Laszlo Ersek Cc: Eric Dong Cc: Ruiyu Ni Cc: Chandana Kumar Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng --- UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c index 56b1b551d977..3f7c933e51f4 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c @@ -1,7 +1,7 @@ /** @file AESNI feature. - Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -123,7 +123,7 @@ AesniInitialize ( MSR_SANDY_BRIDGE_FEATURE_CONFIG, MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER, Bits.AESConfiguration, - BIT1 | ((State) ? 0 : BIT0) + BIT0 | ((State) ? 0 : BIT1) ); } } -- 2.21.0.windows.1