From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.100; helo=mga07.intel.com; envelope-from=zhichao.gao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F3D4921959CB2 for ; Tue, 19 Mar 2019 18:43:03 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Mar 2019 18:43:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,246,1549958400"; d="scan'208";a="308655028" Received: from gaozhic-mobl.ccr.corp.intel.com ([10.239.196.107]) by orsmga005.jf.intel.com with ESMTP; 19 Mar 2019 18:43:02 -0700 From: Zhichao Gao To: edk2-devel@lists.01.org Cc: Jian J Wang , Hao Wu , Ray Ni , Star Zeng , Liming Gao Date: Wed, 20 Mar 2019 09:42:55 +0800 Message-Id: <20190320014256.1224-2-zhichao.gao@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 In-Reply-To: <20190320014256.1224-1-zhichao.gao@intel.com> References: <20190320014256.1224-1-zhichao.gao@intel.com> Subject: [PATCH 1/2] MdeModulePkg/CapsuleRuntimeDxe: Merge changes form arm to all ARCH X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Mar 2019 01:43:04 -0000 BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1462 The arm ARCH has already to add a function CapsuleCacheWriteBack to flush the cache data to DRAM. That is also required in IA32 ARCH. So merge the changes. And this function do not support in runtime phase. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Zhichao Gao Cc: Jian J Wang Cc: Hao Wu Cc: Ray Ni Cc: Star Zeng Cc: Liming Gao --- .../Universal/CapsuleRuntimeDxe/CapsuleReset.c | 21 ++++++++++++++++ .../{Arm/CapsuleReset.c => CapsuleResetNull.c} | 29 +++------------------- .../CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf | 14 +++++------ 3 files changed, 30 insertions(+), 34 deletions(-) rename MdeModulePkg/Universal/CapsuleRuntimeDxe/{Arm/CapsuleReset.c => CapsuleResetNull.c} (51%) diff --git a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleReset.c b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleReset.c index 353f6f2090..8c45f6665e 100644 --- a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleReset.c +++ b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleReset.c @@ -16,6 +16,8 @@ #include "CapsuleService.h" +#include + /** Whether the platform supports capsules that persist across reset. Note that some platforms only support such capsules at boot time. @@ -46,4 +48,23 @@ CapsuleCacheWriteBack ( IN EFI_PHYSICAL_ADDRESS ScatterGatherList ) { + EFI_CAPSULE_BLOCK_DESCRIPTOR *Desc; + + if (!EfiAtRuntime()) { + Desc = (EFI_CAPSULE_BLOCK_DESCRIPTOR *)(UINTN)ScatterGatherList; + do { + WriteBackDataCacheRange (Desc, sizeof *Desc); + + if (Desc->Length > 0) { + WriteBackDataCacheRange ((VOID *)(UINTN)Desc->Union.DataBlock, + Desc->Length + ); + Desc++; + } else if (Desc->Union.ContinuationPointer > 0) { + Desc = (EFI_CAPSULE_BLOCK_DESCRIPTOR *)(UINTN)Desc->Union.ContinuationPointer; + } + } while (Desc->Length > 0 || Desc->Union.ContinuationPointer > 0); + + WriteBackDataCacheRange (Desc, sizeof *Desc); + } } diff --git a/MdeModulePkg/Universal/CapsuleRuntimeDxe/Arm/CapsuleReset.c b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleResetNull.c similarity index 51% rename from MdeModulePkg/Universal/CapsuleRuntimeDxe/Arm/CapsuleReset.c rename to MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleResetNull.c index d79d2fc693..3c5cfc1a16 100644 --- a/MdeModulePkg/Universal/CapsuleRuntimeDxe/Arm/CapsuleReset.c +++ b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleResetNull.c @@ -1,8 +1,9 @@ /** @file - ARM implementation of architecture specific routines related to + Default implementation of architecture specific routines related to PersistAcrossReset capsules Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+ Copyright (c) 2019, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this @@ -31,14 +32,7 @@ IsPersistAcrossResetCapsuleSupported ( VOID ) { - // - // ARM requires the capsule payload to be cleaned to the point of coherency - // (PoC), but only permits doing so using cache maintenance instructions that - // operate on virtual addresses. Since at runtime, we don't know the virtual - // addresses of the data structures that make up the scatter/gather list, we - // cannot perform the maintenance, and all we can do is give up. - // - return FeaturePcdGet (PcdSupportUpdateCapsuleReset) && !EfiAtRuntime (); + return FeaturePcdGet (PcdSupportUpdateCapsuleReset); } /** @@ -55,21 +49,4 @@ CapsuleCacheWriteBack ( IN EFI_PHYSICAL_ADDRESS ScatterGatherList ) { - EFI_CAPSULE_BLOCK_DESCRIPTOR *Desc; - - Desc = (EFI_CAPSULE_BLOCK_DESCRIPTOR *)(UINTN)ScatterGatherList; - do { - WriteBackDataCacheRange (Desc, sizeof *Desc); - - if (Desc->Length > 0) { - WriteBackDataCacheRange ((VOID *)(UINTN)Desc->Union.DataBlock, - Desc->Length - ); - Desc++; - } else if (Desc->Union.ContinuationPointer > 0) { - Desc = (EFI_CAPSULE_BLOCK_DESCRIPTOR *)(UINTN)Desc->Union.ContinuationPointer; - } - } while (Desc->Length > 0 || Desc->Union.ContinuationPointer > 0); - - WriteBackDataCacheRange (Desc, sizeof *Desc); } diff --git a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf index ad7af5fe62..c0bdf6db3d 100644 --- a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf +++ b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf @@ -36,15 +36,15 @@ [Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64] SaveLongModeContext.c + +[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64] CapsuleReset.c +[Sources.EBC] + CapsuleResetNull.c + [Sources.X64] X64/SaveLongModeContext.c - CapsuleReset.c - -[Sources.ARM, Sources.AARCH64] - SaveLongModeContext.c - Arm/CapsuleReset.c [Packages] MdePkg/MdePkg.dec @@ -61,14 +61,12 @@ BaseLib PrintLib BaseMemoryLib + CacheMaintenanceLib [LibraryClasses.X64] UefiLib BaseMemoryLib -[LibraryClasses.ARM, LibraryClasses.AARCH64] - CacheMaintenanceLib - [Guids] ## SOMETIMES_PRODUCES ## Variable:L"CapsuleUpdateData" # (Process across reset capsule image) for capsule updated data ## SOMETIMES_PRODUCES ## Variable:L"CapsuleLongModeBuffer" # The long mode buffer used by IA32 Capsule PEIM to call X64 CapsuleCoalesce code to handle >4GB capsule blocks -- 2.16.2.windows.1