From: Ming Huang <ming.huang@linaro.org>
To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org,
edk2-devel@lists.01.org, graeme.gregory@linaro.org
Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com,
lersek@redhat.com, wanghuiqiang@huawei.com,
huangming23@huawei.com, zhangjinsong2@huawei.com,
huangdaode@hisilicon.com, john.garry@huawei.com,
zhangfeng56@huawei.com, xiaojun2@hisilicon.com,
Ming Huang <ming.huang@linaro.org>
Subject: [PATCH edk2-platforms v3 11/18] Hisilicon/D06: Add PCI_OSC_SUPPORT
Date: Wed, 20 Mar 2019 16:08:22 +0800 [thread overview]
Message-ID: <20190320080829.52003-12-ming.huang@linaro.org> (raw)
In-Reply-To: <20190320080829.52003-1-ming.huang@linaro.org>
Add PCI_OSC_SUPPORT for remaining host bridges to remove fail
output in kernel:
[ 103.478893] acpi PNP0A08:01: _OSC failed (AE_NOT_FOUND);
Add PCI_OSC_SUPPORT_HOTPLUG to rewrite _OSC of PCI0 and PCI6.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
---
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 200 +++++++++++---------
1 file changed, 106 insertions(+), 94 deletions(-)
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl
index 4d9d9d95be68..6dc380f27fa2 100644
--- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl
@@ -17,6 +17,90 @@
**/
//#include "ArmPlatform.h"
+
+/*
+ See ACPI 6.1 Spec, 6.2.11, PCI Firmware Spec 3.0, 4.5
+*/
+#define PCI_OSC_SUPPORT() \
+ Name(SUPP, Zero) /* PCI _OSC Support Field value */ \
+ Name(CTRL, Zero) /* PCI _OSC Control Field value */ \
+ Method(_OSC,4) { \
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \
+ /* Create DWord-adressable fields from the Capabilities Buffer */ \
+ CreateDWordField(Arg3,0,CDW1) \
+ CreateDWordField(Arg3,4,CDW2) \
+ CreateDWordField(Arg3,8,CDW3) \
+ /* Save Capabilities DWord2 & 3 */ \
+ Store(CDW2,SUPP) \
+ Store(CDW3,CTRL) \
+ /* Only allow native hot plug control if OS supports: */ \
+ /* ASPM */ \
+ /* Clock PM */ \
+ /* MSI/MSI-X */ \
+ If(LNotEqual(And(SUPP, 0x16), 0x16)) { \
+ And(CTRL,0x1E,CTRL) \
+ }\
+ \
+ /* Do not allow native PME, AER */ \
+ /* Never allow SHPC (no SHPC controller in this system)*/ \
+ And(CTRL,0x10,CTRL) \
+ If(LNotEqual(Arg1,One)) { /* Unknown revision */ \
+ Or(CDW1,0x08,CDW1) \
+ } \
+ \
+ If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \
+ Or(CDW1,0x10,CDW1) \
+ } \
+ \
+ /* Update DWORD3 in the buffer */ \
+ Store(CTRL,CDW3) \
+ Return(Arg3) \
+ } Else { \
+ Or(CDW1,4,CDW1) /* Unrecognized UUID */ \
+ Return(Arg3) \
+ } \
+ } // End _OSC
+
+#define PCI_OSC_SUPPORT_HOTPLUG() \
+ Name(SUPP, Zero) /* PCI _OSC Support Field value */ \
+ Name(CTRL, Zero) /* PCI _OSC Control Field value */ \
+ Method(_OSC,4) { \
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \
+ /* Create DWord-adressable fields from the Capabilities Buffer */ \
+ CreateDWordField(Arg3,0,CDW1) \
+ CreateDWordField(Arg3,4,CDW2) \
+ CreateDWordField(Arg3,8,CDW3) \
+ /* Save Capabilities DWord2 & 3 */ \
+ Store(CDW2,SUPP) \
+ Store(CDW3,CTRL) \
+ /* Only allow native hot plug control if OS supports: */ \
+ /* ASPM */ \
+ /* Clock PM */ \
+ /* MSI/MSI-X */ \
+ If(LNotEqual(And(SUPP, 0x16), 0x16)) { \
+ And(CTRL,0x1E,CTRL) \
+ }\
+ \
+ /* Always allow native PME, AER (no dependencies) */ \
+ /* Never allow SHPC (no SHPC controller in this system)*/ \
+ And(CTRL,0x1D,CTRL) \
+ If(LNotEqual(Arg1,One)) { /* Unknown revision */ \
+ Or(CDW1,0x08,CDW1) \
+ } \
+ \
+ If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \
+ Or(CDW1,0x10,CDW1) \
+ } \
+ \
+ /* Update DWORD3 in the buffer */ \
+ Store(CTRL,CDW3) \
+ Return(Arg3) \
+ } Else { \
+ Or(CDW1,4,CDW1) /* Unrecognized UUID */ \
+ Return(Arg3) \
+ } \
+ } // End _OSC
+
Scope(_SB)
{
Device (PCI0)
@@ -139,53 +223,7 @@ Scope(_SB)
Return (RBUF)
} // Method(_CRS), this method return RBUF!
- //
- // OS Control Handoff
- //
- Name(SUPP, Zero) // PCI _OSC Support Field value
- Name(CTRL, Zero) // PCI _OSC Control Field value
-
- Method(_OSC,4) {
- // Check for proper UUID
- If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
- // Create DWord-adressable fields from the Capabilities Buffer
- CreateDWordField(Arg3,0,CDW1)
- CreateDWordField(Arg3,4,CDW2)
- CreateDWordField(Arg3,8,CDW3)
-
- // Save Capabilities DWord2 & 3
- Store(CDW2,SUPP)
- Store(CDW3,CTRL)
-
- // Only allow native hot plug control if OS supports:
- // ASPM
- // Clock PM
- // MSI/MSI-X
- If(LNotEqual(And(SUPP, 0x16), 0x16)) {
- And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
- }
-
- // Always allow native PME, AER (no dependencies)
-
- // Never allow SHPC (no SHPC controller in this system)
- And(CTRL,0x1D,CTRL)
-
- If(LNotEqual(Arg1,One)) { // Unknown revision
- Or(CDW1,0x08,CDW1)
- }
-
- If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
- Or(CDW1,0x10,CDW1)
- }
-
- // Update DWORD3 in the buffer
- Store(CTRL,CDW3)
- Return(Arg3)
- } Else {
- Or(CDW1,4,CDW1) // Unrecognized UUID
- Return(Arg3)
- }
- } // End _OSC
+ PCI_OSC_SUPPORT_HOTPLUG ()
Method (_HPX, 0) {
Return (Package(2) {
@@ -270,6 +308,8 @@ Device (PCI1)
Return (RBUF)
} // Method(_CRS), this method return RBUF!
+ PCI_OSC_SUPPORT ()
+
Method (_STA, 0x0, NotSerialized)
{
Return (0xf)
@@ -333,6 +373,8 @@ Device (PCI2)
Return (RBUF)
} // Method(_CRS), this method return RBUF!
+ PCI_OSC_SUPPORT ()
+
Method (_STA, 0x0, NotSerialized)
{
Return (0xf)
@@ -382,6 +424,8 @@ Device (PCI3)
Return (RBUF)
} // Method(_CRS), this method return RBUF!
+ PCI_OSC_SUPPORT ()
+
Method (_STA, 0x0, NotSerialized)
{
Return (0xf)
@@ -431,6 +475,8 @@ Device (PCI4)
Return (RBUF)
} // Method(_CRS), this method return RBUF!
+ PCI_OSC_SUPPORT ()
+
Method (_STA, 0x0, NotSerialized)
{
Return (0x0F)
@@ -505,6 +551,8 @@ Device (PCI5)
Return (RBUF)
} // Method(_CRS), this method return RBUF!
+ PCI_OSC_SUPPORT ()
+
Method (_STA, 0x0, NotSerialized)
{
Return (0xf)
@@ -870,53 +918,7 @@ Device (PCI6)
Return (RBUF)
} // Method(_CRS), this method return RBUF!
- //
- // OS Control Handoff
- //
- Name(SUPP, Zero) // PCI _OSC Support Field value
- Name(CTRL, Zero) // PCI _OSC Control Field value
-
- Method(_OSC,4) {
- // Check for proper UUID
- If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
- // Create DWord-adressable fields from the Capabilities Buffer
- CreateDWordField(Arg3,0,CDW1)
- CreateDWordField(Arg3,4,CDW2)
- CreateDWordField(Arg3,8,CDW3)
-
- // Save Capabilities DWord2 & 3
- Store(CDW2,SUPP)
- Store(CDW3,CTRL)
-
- // Only allow native hot plug control if OS supports:
- // ASPM
- // Clock PM
- // MSI/MSI-X
- If(LNotEqual(And(SUPP, 0x16), 0x16)) {
- And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
- }
-
- // Always allow native PME, AER (no dependencies)
-
- // Never allow SHPC (no SHPC controller in this system)
- And(CTRL,0x1D,CTRL)
-
- If(LNotEqual(Arg1,One)) { // Unknown revision
- Or(CDW1,0x08,CDW1)
- }
-
- If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
- Or(CDW1,0x10,CDW1)
- }
-
- // Update DWORD3 in the buffer
- Store(CTRL,CDW3)
- Return(Arg3)
- } Else {
- Or(CDW1,4,CDW1) // Unrecognized UUID
- Return(Arg3)
- }
- } // End _OSC
+ PCI_OSC_SUPPORT_HOTPLUG ()
Method (_HPX, 0) {
Return (Package(2) {
@@ -1002,6 +1004,8 @@ Device (PCI7)
Return (RBUF)
} // Method(_CRS), this method return RBUF!
+ PCI_OSC_SUPPORT ()
+
Method (_STA, 0x0, NotSerialized)
{
Return (0xf)
@@ -1066,6 +1070,8 @@ Device (PCI8)
Return (RBUF)
} // Method(_CRS), this method return RBUF!
+ PCI_OSC_SUPPORT ()
+
Method (_STA, 0x0, NotSerialized)
{
Return (0xf)
@@ -1115,6 +1121,8 @@ Device (PCI9)
Return (RBUF)
} // Method(_CRS), this method return RBUF!
+ PCI_OSC_SUPPORT ()
+
Method (_STA, 0x0, NotSerialized)
{
Return (0xf)
@@ -1164,6 +1172,8 @@ Device (PCIA)
Return (RBUF)
} // Method(_CRS), this method return RBUF!
+ PCI_OSC_SUPPORT ()
+
Method (_STA, 0x0, NotSerialized)
{
Return (0x0F)
@@ -1238,6 +1248,8 @@ Device (PCIB)
Return (RBUF)
} // Method(_CRS), this method return RBUF!
+ PCI_OSC_SUPPORT ()
+
Method (_STA, 0x0, NotSerialized)
{
Return (0xf)
--
2.9.5
next prev parent reply other threads:[~2019-03-20 8:09 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-20 8:08 [PATCH edk2-platforms v3 00/18] Fix issues and improve D0x Ming Huang
2019-03-20 8:08 ` [PATCH edk2-platforms v3 01/18] Hisilicon/D0x: Remove and tidy some codes about SerdesLib Ming Huang
2019-03-20 8:08 ` [PATCH edk2-platforms v3 02/18] Hisilicon/D0x: Delete some header files Ming Huang
2019-03-20 8:08 ` [PATCH edk2-platforms v3 03/18] Hisilicon/D0x: Add DriverHealthManagerDxe Ming Huang
2019-03-20 8:08 ` [PATCH edk2-platforms v3 04/18] Hisilicon/D06: Optimize SAS driver for reducing boot time Ming Huang
2019-03-20 8:08 ` [PATCH edk2-platforms v3 05/18] Hisilicon/D06: Fix access variable fail issue Ming Huang
2019-03-21 17:52 ` Leif Lindholm
2019-03-21 17:56 ` Leif Lindholm
2019-03-22 4:27 ` Ming Huang
2019-03-20 8:08 ` [PATCH edk2-platforms v3 06/18] Hisilicon/D06: Drop the leading 0 (0x0 -> 0x) Ming Huang
2019-03-20 8:08 ` [PATCH edk2-platforms v3 07/18] Hisilicon/D06: Add more PCIe port INT-x support Ming Huang
2019-03-20 8:08 ` [PATCH edk2-platforms v3 08/18] Hisilicon/D06: Add OemGetCpuFreq to encapsulate difference Ming Huang
2019-03-20 8:08 ` [PATCH edk2-platforms v3 09/18] Hisilicon/D0x: Rename StartupAp() function Ming Huang
2019-03-20 8:08 ` [PATCH edk2-platforms v3 10/18] Hisilicon/D06: Use HCCS speed with 2.6G Ming Huang
2019-03-20 8:08 ` Ming Huang [this message]
2019-03-20 8:08 ` [PATCH edk2-platforms v3 12/18] Hisilicon/D06: Modify for IMP self-Adapte support Ming Huang
2019-03-21 18:02 ` Leif Lindholm
2019-03-20 8:08 ` [PATCH edk2-platforms v3 13/18] Hisilicon/D06: Add Setup Item "Support DPC" and delete some PCIe menus Ming Huang
2019-03-21 12:32 ` Leif Lindholm
2019-03-22 4:28 ` Ming Huang
2019-03-20 8:08 ` [PATCH edk2-platforms v3 14/18] Hisilicon/D06: Use new flash layout Ming Huang
2019-03-20 8:08 ` [PATCH edk2-platforms v3 15/18] Hisilicon/D06: Remove SECURE_BOOT_ENABLE definition Ming Huang
2019-03-20 8:08 ` [PATCH edk2-platforms v3 16/18] Hisilicon/D0x: Remove SP805 watchdog pcd Ming Huang
2019-03-20 8:08 ` [PATCH edk2-platforms v3 17/18] Hisilicon/D06: Fix USB crash issue(4079) Ming Huang
2019-03-20 8:08 ` [PATCH edk2-platforms v3 18/18] Hisilicon/D0x: Modify version to 19.02 Ming Huang
2019-03-21 18:41 ` [PATCH edk2-platforms v3 00/18] Fix issues and improve D0x Leif Lindholm
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