From: Ming Huang <ming.huang@linaro.org>
To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org,
edk2-devel@lists.01.org, graeme.gregory@linaro.org
Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com,
lersek@redhat.com, wanghuiqiang@huawei.com,
huangming23@huawei.com, zhangjinsong2@huawei.com,
huangdaode@hisilicon.com, john.garry@huawei.com,
zhangfeng56@huawei.com, xiaojun2@hisilicon.com,
Ming Huang <ming.huang@linaro.org>
Subject: [PATCH edk2-non-osi v3 1/8] Hisilicon/D0x: Add some header files
Date: Wed, 20 Mar 2019 16:17:22 +0800 [thread overview]
Message-ID: <20190320081729.52806-2-ming.huang@linaro.org> (raw)
In-Reply-To: <20190320081729.52806-1-ming.huang@linaro.org>
As interfaces exposed only by implementations in edk2-non-osi,
so move some header files from edk2-platforms to edk2-non-osi.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
---
Silicon/Hisilicon/Include/Library/IpmiCmdLib.h | 110 +++++++++++++++++++
Silicon/Hisilicon/Include/Library/LpcLib.h | 113 ++++++++++++++++++++
Silicon/Hisilicon/Include/Library/OemAddressMapLib.h | 45 ++++++++
Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h | 112 +++++++++++++++++++
Silicon/Hisilicon/Include/Library/SerdesLib.h | 21 ++++
5 files changed, 401 insertions(+)
diff --git a/Silicon/Hisilicon/Include/Library/IpmiCmdLib.h b/Silicon/Hisilicon/Include/Library/IpmiCmdLib.h
new file mode 100644
index 0000000..b956ee6
--- /dev/null
+++ b/Silicon/Hisilicon/Include/Library/IpmiCmdLib.h
@@ -0,0 +1,110 @@
+/** @file
+*
+* Copyright (c) 2017, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2017, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _IPMI_CMD_LIB_H_
+#define _IPMI_CMD_LIB_H_
+
+#define BOOT_OPTION_BOOT_FLAG_VALID 1
+#define BOOT_OPTION_BOOT_FLAG_INVALID 0
+
+typedef enum {
+ EfiReserved,
+ EfiBiosFrb2,
+ EfiBiosPost,
+ EfiOsLoad,
+ EfiSmsOs,
+ EfiOem,
+ EfiFrbReserved1,
+ EfiFrbReserved2
+} EFI_WDT_USER_TYPE;
+
+typedef enum {
+ NoOverride = 0x0,
+ ForcePxe,
+ ForceDefaultHardDisk,
+ ForceDefaultHardDiskSafeMode,
+ ForceDefaultDiagnosticPartition,
+ ForceDefaultCD,
+ ForceSetupUtility,
+ ForceRemoteRemovableMedia,
+ ForceRemoteCD,
+ ForcePrimaryRemoteMedia,
+ ForceRemoteHardDisk = 0xB,
+ ForcePrimaryRemovableMedia = 0xF
+} BOOT_DEVICE_SELECTOR;
+
+//
+// Get System Boot Option data structure
+//
+typedef struct {
+ UINT8 ParameterVersion :4;
+ UINT8 Reserved1 :4;
+ UINT8 ParameterSelector :7;
+ UINT8 ParameterValid :1;
+ //
+ // Boot Flags Data 1
+ //
+ UINT8 Reserved2 :5;
+ UINT8 BiosBootType :1;
+ UINT8 Persistent :1;
+ UINT8 BootFlagsValid :1;
+ //
+ // Boot Flags Data 2
+ //
+ UINT8 LockResetBtn :1;
+ UINT8 ScreenBlank :1;
+ UINT8 BootDeviceSelector :4;
+ UINT8 LockKeyboard :1;
+ UINT8 ClearCmos :1;
+ //
+ // Boot Flags Data 3
+ //
+ UINT8 ConsoleRedirectionControl :2;
+ UINT8 LockSleepBtn :1;
+ UINT8 UserPasswordByPass :1;
+ UINT8 Reserved3 :1;
+ UINT8 FirmwareVerbosity :2;
+ UINT8 LockPowerBtn :1;
+ //
+ // Boot Flags Data 4
+ //
+ UINT8 MuxControlOverride :3;
+ UINT8 ShareModeOverride :1;
+ UINT8 Reserved4 :4;
+ //
+ // Boot Flags Data 5
+ //
+ UINT8 DeviceInstanceSelector :5;
+ UINT8 Reserved5 :3;
+} IPMI_GET_BOOT_OPTION;
+
+EFI_STATUS
+EFIAPI
+IpmiCmdSetSysBootOptions (
+ OUT IPMI_GET_BOOT_OPTION *BootOption
+ );
+
+EFI_STATUS
+EFIAPI
+IpmiCmdGetSysBootOptions (
+ IN IPMI_GET_BOOT_OPTION *BootOption
+ );
+
+EFI_STATUS
+IpmiCmdStopWatchdogTimer (
+ IN EFI_WDT_USER_TYPE UserType
+ );
+
+#endif
diff --git a/Silicon/Hisilicon/Include/Library/LpcLib.h b/Silicon/Hisilicon/Include/Library/LpcLib.h
new file mode 100755
index 0000000..236a52b
--- /dev/null
+++ b/Silicon/Hisilicon/Include/Library/LpcLib.h
@@ -0,0 +1,113 @@
+/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _LPC_LIB_H_
+#define _LPC_LIB_H_
+
+#include <Uefi.h>
+
+#define PCIE_SUBSYS_IO_MUX 0xA0170000
+#define PCIE_SUBSYS_IOMG033 (PCIE_SUBSYS_IO_MUX + 0x84)
+#define PCIE_SUBSYS_IOMG035 (PCIE_SUBSYS_IO_MUX + 0x8C)
+#define PCIE_SUBSYS_IOMG036 (PCIE_SUBSYS_IO_MUX + 0x90)
+#define PCIE_SUBSYS_IOMG045 (PCIE_SUBSYS_IO_MUX + 0xB4)
+#define PCIE_SUBSYS_IOMG046 (PCIE_SUBSYS_IO_MUX + 0xB8)
+#define PCIE_SUBSYS_IOMG047 (PCIE_SUBSYS_IO_MUX + 0xBC)
+#define PCIE_SUBSYS_IOMG048 (PCIE_SUBSYS_IO_MUX + 0xC0)
+#define PCIE_SUBSYS_IOMG049 (PCIE_SUBSYS_IO_MUX + 0xC4)
+#define PCIE_SUBSYS_IOMG050 (PCIE_SUBSYS_IO_MUX + 0xC8)
+
+#define IO_WRAP_CTRL_BASE 0xA0100000
+#define SC_LPC_CLK_EN_REG (IO_WRAP_CTRL_BASE + 0x03a0)
+#define SC_LPC_CLK_DIS_REG (IO_WRAP_CTRL_BASE + 0x03a4)
+#define SC_LPC_BUS_CLK_EN_REG (IO_WRAP_CTRL_BASE + 0x03a8)
+#define SC_LPC_BUS_CLK_DIS_REG (IO_WRAP_CTRL_BASE + 0x03ac)
+#define SC_LPC_RESET_REQ (IO_WRAP_CTRL_BASE + 0x0ad8)
+#define SC_LPC_RESET_DREQ (IO_WRAP_CTRL_BASE + 0x0adc)
+#define SC_LPC_BUS_RESET_REQ (IO_WRAP_CTRL_BASE + 0x0ae0)
+#define SC_LPC_BUS_RESET_DREQ (IO_WRAP_CTRL_BASE + 0x0ae4)
+#define SC_LPC_CTRL_REG (IO_WRAP_CTRL_BASE + 0x2028)
+
+
+#define LPC_BASE 0xA01B0000
+#define LPC_START_REG (LPC_BASE + 0x00)
+#define LPC_OP_STATUS_REG (LPC_BASE + 0x04)
+#define LPC_IRQ_ST_REG (LPC_BASE + 0x08)
+#define LPC_OP_LEN_REG (LPC_BASE + 0x10)
+#define LPC_CMD_REG (LPC_BASE + 0x14)
+#define LPC_FWH_ID_MSIZE_REG (LPC_BASE + 0x18)
+#define LPC_ADDR_REG (LPC_BASE + 0x20)
+#define LPC_WDATA_REG (LPC_BASE + 0x24)
+#define LPC_RDATA_REG (LPC_BASE + 0x28)
+#define LPC_LONG_CNT_REG (LPC_BASE + 0x30)
+#define LPC_TX_FIFO_ST_REG (LPC_BASE + 0x50)
+#define LPC_RX_FIFO_ST_REG (LPC_BASE + 0x54)
+#define LPC_TIME_OUT_REG (LPC_BASE + 0x58)
+#define LPC_SIRQ_CTRL0_REG (LPC_BASE + 0x80)
+#define LPC_SIRQ_CTRL1_REG (LPC_BASE + 0x84)
+#define LPC_SIRQ_INT_REG (LPC_BASE + 0x90)
+#define LPC_SIRQ_INT_MASK_REG (LPC_BASE + 0x94)
+#define LPC_SIRQ_STAT_REG (LPC_BASE + 0xA0)
+
+#define LPC_FIFO_LEN (16)
+
+typedef enum{
+ LPC_ADDR_MODE_INCREASE,
+ LPC_ADDR_MODE_SINGLE
+}LPC_ADDR_MODE;
+
+typedef enum{
+ LPC_TYPE_IO,
+ LPC_TYPE_MEM,
+ LPC_TYPE_FWH
+}LPC_TYPE;
+
+
+typedef union {
+ struct{
+ UINT32 lpc_wr:1;
+ UINT32 lpc_type:2;
+ UINT32 same_addr:1;
+ UINT32 resv:28;
+ }bits;
+ UINT32 u32;
+}LPC_CMD_STRUCT;
+
+typedef union {
+ struct{
+ UINT32 op_len:5;
+ UINT32 resv:27;
+ }bits;
+ UINT32 u32;
+}LPC_OP_LEN_STRUCT;
+
+
+VOID LpcInit(VOID);
+BOOLEAN LpcIdle(VOID);
+EFI_STATUS LpcByteWrite(
+ IN UINT32 Addr,
+ IN UINT8 Data);
+EFI_STATUS LpcByteRead(
+ IN UINT32 Addr,
+ IN OUT UINT8 *Data);
+
+EFI_STATUS LpcWrite(
+ IN UINT32 Addr,
+ IN UINT8 *Data,
+ IN UINT8 Len);
+
+#endif
+
+
diff --git a/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h b/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h
new file mode 100644
index 0000000..b5de34f
--- /dev/null
+++ b/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h
@@ -0,0 +1,45 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _OEM_ADDRESS_MAP_LIB_H_
+#define _OEM_ADDRESS_MAP_LIB_H_
+
+#include <PlatformArch.h>
+
+typedef struct _DDRC_BASE_ID{
+ UINTN Base;
+ UINTN Id;
+}DDRC_BASE_ID;
+
+// Invalid address, will cause exception when accessed by bug code
+#define ADDRESS_MAP_INVALID ((UINTN)(-1))
+
+UINTN OemGetPoeSubBase (UINT32 NodeId);
+UINTN OemGetPeriSubBase (UINT32 NodeId);
+UINTN OemGetAlgSubBase (UINT32 NodeId);
+UINTN OemGetCfgbusBase (UINT32 NodeId);
+UINTN OemGetGicSubBase (UINT32 NodeId);
+UINTN OemGetHACSubBase (UINT32 NodeId);
+UINTN OemGetIOMGMTSubBase (UINT32 NodeId);
+UINTN OemGetNetworkSubBase (UINT32 NodeId);
+UINTN OemGetM3SubBase (UINT32 NodeId);
+UINTN OemGetPCIeSubBase (UINT32 NodeId);
+
+VOID OemAddressMapInit(VOID);
+
+extern DDRC_BASE_ID DdrcBaseId[MAX_SOCKET][MAX_CHANNEL];
+
+#endif
+
diff --git a/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h b/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h
new file mode 100644
index 0000000..712b77c
--- /dev/null
+++ b/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h
@@ -0,0 +1,112 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _PLATFORM_SYS_CTRL_LIB_H_
+#define _PLATFORM_SYS_CTRL_LIB_H_
+
+#define PACKAGE_16CORE 0
+#define PACKAGE_32CORE 1
+#define PACKAGE_RESERVED 2
+#define PACKAGE_TYPE_NUM 3
+
+UINT32 PlatformGetPackageType (VOID);
+
+VOID DisplayCpuInfo (VOID);
+UINT32 CheckChipIsEc(VOID);
+
+UINTN PlatformGetPll (UINT32 NodeId, UINTN Pll);
+
+#define DJTAG_READ_INVALID_VALUE 0xFFFFFFFF
+#define DJTAG_CHAIN_ID_AA 1
+#define DJTAG_CHAIN_ID_LLC 4
+
+
+#define SC_DJTAG_MSTR_EN_OFFSET 0x6800
+#define SC_DJTAG_MSTR_START_EN_OFFSET 0x6804
+#define SC_DJTAG_SEC_ACC_EN_OFFSET 0x6808
+#define SC_DJTAG_DEBUG_MODULE_SEL_OFFSET 0x680C
+#define SC_DJTAG_MSTR_WR_OFFSET 0x6810
+#define SC_DJTAG_CHAIN_UNIT_CFG_EN_OFFSET 0x6814
+#define SC_DJTAG_MSTR_ADDR_OFFSET 0x6818
+#define SC_DJTAG_MSTR_DATA_OFFSET 0x681C
+#define SC_DJTAG_TMOUT_OFFSET 0x6820
+#define SC_TDRE_OP_ADDR_OFFSET 0x6824
+#define SC_TDRE_WDATA_OFFSET 0x6828
+#define SC_TDRE_REPAIR_EN_OFFSET 0x682C
+#define SC_DJTAG_RD_DATA0_OFFSET 0xE800
+#define SC_TDRE_RDATA0_OFFSET 0xE830
+
+
+UINTN PlatformGetI2cBase(UINT32 Socket,UINT8 Port);
+
+VOID PlatformAddressMapCleanUp (VOID);
+VOID PlatformDisableDdrWindow (VOID);
+
+VOID PlatformEnableArchTimer (VOID);
+
+EFI_STATUS
+DawFindFreeWindow (UINTN Socket, UINTN *DawIndex);
+
+VOID DawSetWindow (UINTN Socket, UINTN WindowIndex, UINT32 Value);
+
+VOID DJTAG_TDRE_WRITE(UINT32 Offset, UINT32 Value, UINT32 ChainID, UINT32 NodeId, BOOLEAN Repair);
+
+UINT32 DJTAG_TDRE_READ(UINT32 Offset, UINT32 ChainID, UINT32 NodeId, BOOLEAN Repair);
+
+VOID RemoveRoceReset(VOID);
+
+UINTN PlatformGetDdrChannel (VOID);
+
+VOID ITSCONFIG (VOID);
+
+VOID MN_CONFIG (VOID);
+
+VOID SmmuConfigForOS (VOID);
+VOID SmmuConfigForBios (VOID);
+
+VOID StartUpBSP (VOID);
+
+VOID LlcCleanInvalidate (VOID);
+
+UINTN PlatformGetCpuFreq (UINT8 Socket);
+VOID ClearInterruptStatus(VOID);
+
+UINTN PlatformGetCoreCount (VOID);
+VOID DAWConfigEn(UINT32 socket);
+
+VOID DResetUsb ();
+UINT32 PlatformGetEhciBase ();
+UINT32 PlatformGetOhciBase ();
+VOID PlatformPllInit();
+// PLL initialization for super IO clusters.
+VOID SiclPllInit(UINT32 SclId);
+VOID PlatformDeviceDReset();
+VOID PlatformGicdInit();
+VOID PlatformLpcInit();
+// Synchronize architecture timer counter between different super computing
+// clusters.
+VOID PlatformArchTimerSynchronize(VOID);
+VOID PlatformEventBroadcastConfig(VOID);
+UINTN GetDjtagRegBase(UINT32 NodeId);
+VOID LlcCleanInvalidateAsm(VOID);
+VOID PlatformMdioInit(VOID);
+VOID DisableClusterClock(UINTN CpuClusterBase);
+VOID EnableClusterClock(UINTN CpuClusterBase);
+VOID DisableSocketClock (UINT8 Skt);
+
+EFI_STATUS EFIAPI HandleI2CException (UINT32 Socket, UINT32 Port);
+EFI_STATUS EFIAPI HandleI2CExceptionBySocket (UINT32 Socket);
+
+#endif
diff --git a/Silicon/Hisilicon/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Include/Library/SerdesLib.h
new file mode 100644
index 0000000..e3fe9b7
--- /dev/null
+++ b/Silicon/Hisilicon/Include/Library/SerdesLib.h
@@ -0,0 +1,21 @@
+/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _SERDES_LIB_H_
+#define _SERDES_LIB_H_
+
+EFI_STATUS EfiSerdesInitWrap (VOID);
+
+#endif
--
2.9.5
next prev parent reply other threads:[~2019-03-20 8:17 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-20 8:17 [PATCH edk2-non-osi v3 0/8] Upload D0x binary modules Ming Huang
2019-03-20 8:17 ` Ming Huang [this message]
2019-03-20 8:17 ` [PATCH edk2-non-osi v3 2/8] Hisilicon/D06: Remove PCI enumeration dependency from SAS driver Ming Huang
2019-03-20 8:17 ` [PATCH edk2-non-osi v3 3/8] Hisilicon/D0x: Update PlatformSysCtrlLib binary Ming Huang
2019-03-20 8:17 ` [PATCH edk2-non-osi v3 4/8] Hisilicon/D06: Update Mbigen and gic RAS register Ming Huang
2019-03-20 8:17 ` [PATCH edk2-non-osi v3 5/8] Hisilicon/D06: Support PCIe local RAS Ming Huang
2019-03-20 8:17 ` [PATCH edk2-non-osi v3 6/8] Hisilicon/D06: Use new flash layout Ming Huang
2019-03-20 8:17 ` [PATCH edk2-non-osi v3 7/8] Hisilicon/D06: Fix numa node wrong issue Ming Huang
2019-03-20 8:17 ` [PATCH edk2-non-osi v3 8/8] Hisilicon/D06: Add Setup Item "Support DPC" Ming Huang
2019-03-21 18:33 ` Leif Lindholm
2019-03-21 18:41 ` [PATCH edk2-non-osi v3 0/8] Upload D0x binary modules Leif Lindholm
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190320081729.52806-2-ming.huang@linaro.org \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox