From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.126; helo=mga18.intel.com; envelope-from=narendra.k.vanguput@intel.com; receiver=edk2-devel@lists.01.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3F31A211E82F9 for ; Fri, 22 Mar 2019 11:50:09 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Mar 2019 11:50:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,256,1549958400"; d="scan'208";a="154891603" Received: from nkvangup-desk4.gar.corp.intel.com ([10.223.18.132]) by fmsmga004.fm.intel.com with ESMTP; 22 Mar 2019 11:50:02 -0700 From: nkvangup To: edk2-devel@lists.01.org Cc: Vanguput Narendra K , Eric Dong , Ray Ni , Laszlo Ersek , Yao Jiewen Date: Sat, 23 Mar 2019 00:19:56 +0530 Message-Id: <20190322184956.2928-1-narendra.k.vanguput@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 Subject: [PATCH v5] UefiCpuPkg\CpuSmm: Save & restore CR2 on-demand paging in SMM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Mar 2019 18:50:09 -0000 BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1593 For every SMI occurrence, save and restore CR2 register only when SMM on-demand paging support is enabled in 64 bit operation mode. This is not a bug but to have better improvement of code. Patch5 is updated with separate functions for Save and Restore of CR2 based on review feedback. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vanguput Narendra K Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Yao Jiewen --- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 22 ++++++++++++++++++++++ UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 9 +++++---- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 16 ++++++++++++++++ UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 28 ++++++++++++++++++++++++++++ 4 files changed, 71 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c index b734a1ea8c..3750332ca8 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c @@ -316,3 +316,25 @@ SetPageTableAttributes ( return ; } + +/** + This function returns with no action for 32 bit. +**/ +VOID +SaveCr2 ( + VOID + ) +{ +// Do Nothing +} + +/** + This function returns with no action for 32 bit. +**/ +VOID +RestoreCr2 ( + VOID + ) +{ +// Do Nothing +} diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c index 3b0b3b52ac..6a5736a3eb 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -1107,14 +1107,14 @@ SmiRendezvous ( BOOLEAN IsBsp; BOOLEAN BspInProgress; UINTN Index; - UINTN Cr2; ASSERT(CpuIndex < mMaxNumberOfCpus); // - // Save Cr2 because Page Fault exception in SMM may override its value + // Save Cr2 because Page Fault exception in SMM may override its value, + // when using on-demand paging for above 4G memory. // - Cr2 = AsmReadCr2 (); + SaveCr2 (); // // Perform CPU specific entry hooks @@ -1253,10 +1253,11 @@ SmiRendezvous ( Exit: SmmCpuFeaturesRendezvousExit (CpuIndex); + // // Restore Cr2 // - AsmWriteCr2 (Cr2); + RestoreCr2 (); } /** diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h index 84efb22981..71a8c13960 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -1243,4 +1243,20 @@ EFIAPI PiSmmCpuSmiEntryFixupAddress ( ); +/** + This function saves CR2 register for 64 bit and no action for 32 bit. +**/ +VOID +SaveCr2 ( + VOID + ); + +/** + This function restores CR2 register for 64 bit and no action for 32 bit. +**/ +VOID +RestoreCr2 ( + VOID + ); + #endif diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c index 2c77cb47a4..76a30de171 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -22,6 +22,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. LIST_ENTRY mPagePool = INITIALIZE_LIST_HEAD_VARIABLE (mPagePool); BOOLEAN m1GPageTableSupport = FALSE; BOOLEAN mCpuSmmStaticPageTable; +UINTN Cr2 = 0; /** Disable CET. @@ -1053,3 +1054,30 @@ SetPageTableAttributes ( return ; } + +/** + This function saves CR2 register. +**/ +VOID +SaveCr2 ( + VOID + ) +{ + if (!mCpuSmmStaticPageTable) { + Cr2 = AsmReadCr2 (); + } +} + +/** + This function restores CR2 register. +**/ +VOID +RestoreCr2 ( + VOID + ) +{ + if ((!mCpuSmmStaticPageTable) && (Cr2 != 0)) { + AsmWriteCr2 (Cr2); + Cr2 = 0; + } +} -- 2.16.2.windows.1