From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::641; helo=mail-pl1-x641.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl1-x641.google.com (mail-pl1-x641.google.com [IPv6:2607:f8b0:4864:20::641]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 08C62211E742F for ; Mon, 25 Mar 2019 08:08:48 -0700 (PDT) Received: by mail-pl1-x641.google.com with SMTP id b65so88101plb.6 for ; Mon, 25 Mar 2019 08:08:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=U0oprTdprmy3XXFEDBq+vuudG9pSL7tA5BqvjSvlKhw=; b=E99mrsUd+e5xf7C4eqX4TXt5qcgEgv5a32AjkVVo51RHXGCZUj2Z5UPaqe+9fT/RR0 mPH//FIxHs8/CXOVQDF7I7feP3QWs2hpa0RLRGD8I9+thqfOMDwyCRWhSN6S0hOCcq6g xf9gZUFbad321ViJjvxKAMLPClpcWQEWeJqKC2vqUGrWLjFOrUwhUHVuyvgu4fv4jIc6 TV1o5HjSlSUaIeVXwYk/EJdFk+g1+qc5WqD6TP0cLqYqOTLWhRY/0ZTSQAZKaryYX1WY /GvCnVADhxF0Z0YFNUGaJ0bzX/9iV9GRm9XgRRUsBy+AQExq0VGzk7w4M5dleRTRgJNA yFzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=U0oprTdprmy3XXFEDBq+vuudG9pSL7tA5BqvjSvlKhw=; b=t3RKUx7b8eEQfXTVycNgyEkZR6NS73zAGXz6+gHrVsfvEEXUTqaF2obgVDYTFBcHbn 2kGi70BzoOeIjBDciTV3os6RuaW+mzuSryM2YMYM6H2o232Ac0oJ/aMRwgY6282wOXMj BDf6u/s/bTRD8Gs/g1wr1jY2Q/HsQg0d0BJfdTagNzzLYpN0/ec9YBi2mlPnMrhyyCeE JrpxyT4gf5Dio+2BhDf1ZqHu/ibJVFL1cUNC6E52cCRcrhTmxBf0jUjjohrJeSwodAQ9 ROcFEWtx1GvMLEujBoo9aw7SHnlSXXLz/ZfTusgEseWuXKiyq8BhnxFQBDyZ/WC9yzG5 rYAw== X-Gm-Message-State: APjAAAUDoqtEdsDZduQC0RMHZSe4ZF0z1Kgmqo1tUp1zlqhZbIF0S+JA 7iTwcKgMugvasS3pE8d/8Clgmw== X-Google-Smtp-Source: APXvYqzdHqTHtRiMrgiSpIJRK0P+VDG69DmHUNoq1dC4GuhKUjwEEJmQr7GgeWwmW+TtMsuI8TdYig== X-Received: by 2002:a17:902:2e83:: with SMTP id r3mr8197910plb.153.1553526528227; Mon, 25 Mar 2019 08:08:48 -0700 (PDT) Received: from localhost.localdomain ([203.160.91.226]) by smtp.gmail.com with ESMTPSA id j14sm21083283pfe.12.2019.03.25.08.08.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 25 Mar 2019 08:08:47 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, zhangfeng56@huawei.com, xiaojun2@hisilicon.com, Ming Huang Date: Mon, 25 Mar 2019 23:08:29 +0800 Message-Id: <20190325150829.24520-4-ming.huang@linaro.org> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20190325150829.24520-1-ming.huang@linaro.org> References: <20190325150829.24520-1-ming.huang@linaro.org> Subject: [PATCH edk2-platforms v4 3/3] Hisilicon/D06: Add Setup Item "Support DPC" X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 25 Mar 2019 15:08:49 -0000 Add setup item "Support DPC" to enable or disable PCIe DPC (Downstream Port Containment). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Silicon/Hisilicon/Include/Library/OemConfigData.h | 1 + Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 2 -- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 4 ++++ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr | 3 +++ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni | 3 ++- 5 files changed, 10 insertions(+), 3 deletions(-) diff --git a/Silicon/Hisilicon/Include/Library/OemConfigData.h b/Silicon/Hisilicon/Include/Library/OemConfigData.h index f120e3123c83..c0097d0829f0 100644 --- a/Silicon/Hisilicon/Include/Library/OemConfigData.h +++ b/Silicon/Hisilicon/Include/Library/OemConfigData.h @@ -49,6 +49,7 @@ typedef struct { UINT8 OSWdtAction; /*PCIe Config*/ UINT8 PcieSRIOVSupport; + UINT8 PcieDPCSupport; UINT8 PciePort[PCIE_MAX_TOTAL_PORTS]; UINT8 PcieLinkSpeedPort[PCIE_MAX_TOTAL_PORTS]; UINT8 PcieLinkDeEmphasisPort[PCIE_MAX_TOTAL_PORTS]; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr index 08236704fbfe..93ccb99bdc67 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr @@ -62,11 +62,9 @@ formset prompt = STRING_TOKEN(STR_IBMC_CONFIG_FORM_TITLE), help = STRING_TOKEN(STR_IBMC_CONFIG_FORM_HELP); - suppressif TRUE; goto PCIE_CONFIG_FORM_ID, prompt = STRING_TOKEN(STR_PCIE_CONFIG_FORM_TITLE), help = STRING_TOKEN(STR_PCIE_CONFIG_FORM_HELP); - endif; goto MISC_CONFIG_FORM_ID, prompt = STRING_TOKEN(STR_MISC_CONFIG_FORM_TITLE), diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c index 6668103af027..be4ce8820f73 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c @@ -290,6 +290,10 @@ OemConfigUiLibConstructor ( Configuration.OSWdtTimeout = 5; Configuration.OSWdtAction = 1; // + //Set the default value of the PCIe option + // + Configuration.PcieDPCSupport = 0; + // //Set the default value of the Misc option // Configuration.EnableSmmu = 1; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr index f700699b093b..c65907fe846e 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr @@ -17,6 +17,9 @@ form formid = PCIE_CONFIG_FORM_ID, title = STRING_TOKEN (STR_PCIE_CONFIG_FORM_TITLE); + oneof varid = OEM_CONFIG_DATA.PcieDPCSupport, + prompt = STRING_TOKEN (STR_DPC_SUPPORT_PROMPT), + help = STRING_TOKEN (STR_DPC_SUPPORT_HELP), option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; option text = STRING_TOKEN (STR_ENABLE), value = 1, flags = RESET_REQUIRED; endoneof; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni index d87d30f975b8..0127ea952dee 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni @@ -26,7 +26,8 @@ #string STR_PCIE_CPU_1_PROMPT #language en-US "CPU 1 PCIE Configuration" #string STR_SRIOV_SUPPORT_PROMPT #language en-US "SRIOV" #string STR_SRIOV_SUPPORT_HELP #language en-US "This option enables / disables the SRIOV function" - +#string STR_DPC_SUPPORT_PROMPT #language en-US "Support DPC" +#string STR_DPC_SUPPORT_HELP #language en-US "This option enables / disables the DPC function" #string STR_PCIE_PORT_PROMPT_HELP #language en-US "Press to config this port." #string STR_PCIE_PORT_0_NULL_PROMPT #language en-US "" #string STR_PCIE_PORT_0_PROMPT #language en-US "CPU 0 Pcie - Port 0" -- 2.9.5