From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.100; helo=mga07.intel.com; envelope-from=michael.a.kubacki@intel.com; receiver=edk2-devel@lists.01.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 075BF211EE6AD for ; Mon, 1 Apr 2019 15:48:29 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Apr 2019 15:48:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,298,1549958400"; d="scan'208";a="130602340" Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.144]) by orsmga008.jf.intel.com with ESMTP; 01 Apr 2019 15:48:28 -0700 From: Michael Kubacki To: edk2-devel@lists.01.org Cc: Ankit Sinha , Nate DeSimone , Chasel Chiu , Liming Gao , Michael D Kinney Date: Mon, 1 Apr 2019 15:48:02 -0700 Message-Id: <20190401224803.8388-3-michael.a.kubacki@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 In-Reply-To: <20190401224803.8388-1-michael.a.kubacki@intel.com> References: <20190401224803.8388-1-michael.a.kubacki@intel.com> Subject: [edk2-platforms/devel-MinPlatform][PATCH v2 2/3] ClevoOpenBoardPkg/N1xxWU: Flash map update X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 01 Apr 2019 22:48:29 -0000 Updates the total BIOS flash image size to 0x5E0000. This size matches the BIOS region size already configured in the SPI flash descriptor. To write an image produced from the N1xxWU board build, write the N1XXWU.fd file (~6 MB) to the beginning of the BIOS region in the SPI flash (currently 0x220000). Always back up the original SPI flash image. These offsets and sizes are subject to change over time. Cc: Ankit Sinha Cc: Nate DeSimone Cc: Chasel Chiu Cc: Liming Gao Cc: Michael D Kinney Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kubacki --- .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc | 2 +- .../N1xxWU/Include/Fdf/FlashMapInclude.fdf | 44 +++++++++++----------- .../Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat | 4 +- 3 files changed, 26 insertions(+), 24 deletions(-) diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc index 81487ed58d..2116c48fc0 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc @@ -55,7 +55,7 @@ # # Default value for OpenBoardPkg.fdf use # - DEFINE BIOS_SIZE_OPTION = SIZE_70 + DEFINE BIOS_SIZE_OPTION = SIZE_60 ################################################################################ # diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude.fdf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude.fdf index a727eb3b83..423c6b18f5 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude.fdf +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude.fdf @@ -14,39 +14,41 @@ ## #=================================================================================# -# 8 M BIOS - for FSP wrapper +# 6 M BIOS - for FSP wrapper #=================================================================================# -DEFINE FLASH_BASE = 0xFF800000 # -DEFINE FLASH_SIZE = 0x00800000 # +DEFINE FLASH_BASE = 0xFFA20000 # +DEFINE FLASH_SIZE = 0x005E0000 # DEFINE FLASH_BLOCK_SIZE = 0x00010000 # -DEFINE FLASH_NUM_BLOCKS = 0x00000080 # +DEFINE FLASH_NUM_BLOCKS = 0x0000005E # #=================================================================================# -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = 0x00000000 # Flash addr (0xFF800000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = 0x00000000 # Flash addr (0xFFA20000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize = 0x00040000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = 0x00000000 # Flash addr (0xFF800000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = 0x00000000 # Flash addr (0xFFA20000) SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0x0001E000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = 0x0001E000 # Flash addr (0xFF81E000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = 0x0001E000 # Flash addr (0xFFA3E000) SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = 0x00002000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = 0x00020000 # Flash addr (0xFF820000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = 0x00020000 # Flash addr (0xFFA40000) SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = 0x00020000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00040000 # Flash addr (0xFF840000) +SET gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset = 0x00040000 # Flash addr (0xFFA60000) +SET gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize = 0x00010000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00050000 # Flash addr (0xFFA70000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = 0x00060000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = 0x000A0000 # Flash addr (0xFF8A0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = 0x000B0000 # Flash addr (0xFFAD0000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00070000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = 0x00110000 # Flash addr (0xFF910000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = 0x00120000 # Flash addr (0xFFB40000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00090000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = 0x001A0000 # Flash addr (0xFF9A0000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x001E0000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = 0x00380000 # Flash addr (0xFFB80000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00180000 # -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = 0x00500000 # Flash addr (0xFFD00000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = 0x001B0000 # Flash addr (0xFFBD0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x00140000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = 0x002F0000 # Flash addr (0xFFD10000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x000B0000 # +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = 0x003A0000 # Flash addr (0xFFDC0000) SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = 0x000A0000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = 0x005A0000 # Flash addr (0xFFDA0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = 0x00440000 # Flash addr (0xFFE60000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = 0x00060000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = 0x00600000 # Flash addr (0xFFE00000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = 0x004A0000 # Flash addr (0xFFEC0000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize = 0x000BC000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = 0x006BC000 # Flash addr (0xFFEBC000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = 0x0055C000 # Flash addr (0xFFF7C000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize = 0x00004000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = 0x006C0000 # Flash addr (0xFFEC0000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = 0x00140000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = 0x00560000 # Flash addr (0xFFF80000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = 0x00080000 # diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat index c09d2d5b16..c3360403f1 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat @@ -202,8 +202,8 @@ cl @set BIOS_SIZE_OPTION= -@REM default size option is 7M -@set BIOS_SIZE_OPTION=-DBIOS_SIZE_OPTION=SIZE_70 +@REM default size option is 6M +@set BIOS_SIZE_OPTION=-DBIOS_SIZE_OPTION=SIZE_60 :BiosSizeDone @echo BIOS_SIZE_OPTION=%BIOS_SIZE_OPTION% -- 2.16.2.windows.1