* [edk2-platforms/devel-MinPlatform][PATCH v3 0/3] Enable SPI flash debug messages
@ 2019-04-02 1:23 Michael Kubacki
2019-04-02 1:23 ` [edk2-platforms/devel-MinPlatform][PATCH v3 1/3] KabylakeSiliconPkg: Add SPI write support in PEI Michael Kubacki
` (2 more replies)
0 siblings, 3 replies; 11+ messages in thread
From: Michael Kubacki @ 2019-04-02 1:23 UTC (permalink / raw)
To: edk2-devel
Cc: Ankit Sinha, Nate DeSimone, Chasel Chiu, Ray Ni, Liming Gao,
Michael D Kinney
Adds support to the N1xxWU board series in the ClevoOpenBoardPkg
to write debug messages to a dedicated area on SPI flash. This
supports simple closed chassis debug. At this time, only a PEI
library instance is added since it is anticipated an alternative
mechanism will be available in DXE such as USB debug.
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Michael Kubacki (3):
KabylakeSiliconPkg: Add SPI write support in PEI
ClevoOpenBoardPkg/N1xxWU: Flash map update
ClevoOpenBoardPkg/N1xxWU: Write PEI debug messages to SPI flash
Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec | 5 +
.../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc | 22 +-
Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc | 3 +-
.../N1xxWU/Include/Fdf/FlashMapInclude.fdf | 44 +--
.../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf | 4 +
.../PeiSerialPortLibSpiFlash.inf | 56 ++++
.../Pch/Library/PeiSpiLib/PeiSpiLib.inf | 50 ++++
.../Pch/Include/Library/SpiLib.h | 32 ++
.../PeiSerialPortLibSpiFlash.c | 326 +++++++++++++++++++++
.../Pch/Library/PeiSpiLib/PeiSpiLib.c | 221 ++++++++++++++
.../LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c | 5 +-
.../Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat | 4 +-
12 files changed, 740 insertions(+), 32 deletions(-)
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.inf
create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf
create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiLib.h
create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.c
create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c
--
2.16.2.windows.1
^ permalink raw reply [flat|nested] 11+ messages in thread* [edk2-platforms/devel-MinPlatform][PATCH v3 1/3] KabylakeSiliconPkg: Add SPI write support in PEI 2019-04-02 1:23 [edk2-platforms/devel-MinPlatform][PATCH v3 0/3] Enable SPI flash debug messages Michael Kubacki @ 2019-04-02 1:23 ` Michael Kubacki 2019-04-02 2:28 ` Chiu, Chasel 2019-04-02 2:31 ` Desimone, Nathaniel L 2019-04-02 1:23 ` [edk2-platforms/devel-MinPlatform][PATCH v3 2/3] ClevoOpenBoardPkg/N1xxWU: Flash map update Michael Kubacki 2019-04-02 1:23 ` [edk2-platforms/devel-MinPlatform][PATCH v3 3/3] ClevoOpenBoardPkg/N1xxWU: Write PEI debug messages to SPI flash Michael Kubacki 2 siblings, 2 replies; 11+ messages in thread From: Michael Kubacki @ 2019-04-02 1:23 UTC (permalink / raw) To: edk2-devel; +Cc: Nate DeSimone, Chasel Chiu, Liming Gao, Michael D Kinney Adds a new library PeiSpiLib to perform the initialization necessary to perform SPI write cycles in PEI. After initialization, it installs an instance of the PCH_SPI_PPI. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com> --- Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc | 3 +- .../Pch/Library/PeiSpiLib/PeiSpiLib.inf | 50 +++++ .../Pch/Include/Library/SpiLib.h | 32 +++ .../Pch/Library/PeiSpiLib/PeiSpiLib.c | 221 +++++++++++++++++++++ .../LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c | 5 +- 5 files changed, 307 insertions(+), 4 deletions(-) create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc b/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc index b81a736486..bb95ce3888 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc @@ -1,7 +1,7 @@ ## @file # Component description file for the SkyLake SiPkg PEI libraries. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> # # This program and the accompanying materials are licensed and made available under # the terms and conditions of the BSD License which accompanies this distribution. @@ -30,6 +30,7 @@ !endif ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiResetSystemLib/PeiResetSystemLib.inf PchResetLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiPchResetLib/PeiPchResetLib.inf + SpiLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiSpiLib/PeiSpiLib.inf # # Cpu diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf new file mode 100644 index 0000000000..9240b6ef06 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf @@ -0,0 +1,50 @@ +## @file +# Component description file for PEI PCH SPI Initialization +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PeiSpiLib + FILE_GUID = 4998447D-7948-448F-AB75-96E24E18FF23 + VERSION_STRING = 1.0 + MODULE_TYPE = PEIM + LIBRARY_CLASS = SpiLib|PEIM PEI_CORE + # + # The following information is for reference only and not required by the build tools. + # + # VALID_ARCHITECTURES = IA32 X64 IPF + # + +[LibraryClasses] + DebugLib + MemoryAllocationLib + PcdLib + PchCycleDecodingLib + PchSpiCommonLib + PciSegmentLib + PeiServicesLib + PeiServicesTablePointerLib + +[Packages] + MdePkg/MdePkg.dec + KabylakeSiliconPkg/SiPkg.dec + +[Sources] + PeiSpiLib.c + +[Pcd] + gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES + +[Ppis] + gPchSpiPpiGuid ## PRODUCES diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiLib.h new file mode 100644 index 0000000000..6af66f8869 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiLib.h @@ -0,0 +1,32 @@ +/** @file + Library to initialize SPI services for future SPI accesses. + +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SPI_LIB_H_ +#define _SPI_LIB_H_ + +/** + Initializes SPI for access from future services. + + @retval EFI_SUCCESS The SPI service was initialized successfully. + @retval EFI_OUT_OF_RESOUCES Insufficient memory available to allocate structures required for initialization. + @retval Others An error occurred initializing SPI services. + +**/ +EFI_STATUS +EFIAPI +SpiServiceInit ( + VOID + ); + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c new file mode 100644 index 0000000000..954317cd40 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c @@ -0,0 +1,221 @@ +/** @file + PCH SPI PEI Library implements the SPI Host Controller Interface. + +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <PchReservedResources.h> +#include <IndustryStandard/Pci30.h> +#include <Ppi/Spi.h> +#include <Register/PchRegsLpc.h> +#include <Register/PchRegsSpi.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PcdLib.h> +#include <Library/PchCycleDecodingLib.h> +#include <Library/PchSpiCommonLib.h> +#include <Library/PciSegmentLib.h> +#include <Library/PeiServicesLib.h> + +typedef struct { + EFI_PEI_PPI_DESCRIPTOR PpiDescriptor; + SPI_INSTANCE SpiInstance; +} PEI_SPI_INSTANCE; + +/** + Initializes the SPI BAR0 value to a default value and enables memory space decoding. + + The SPI BAR0 will be assigned later in PCI enumeration. + +**/ +VOID +InitSpiBar0 ( + VOID + ) +{ + UINT64 PchSpiBase; + PchSpiBase = PCI_SEGMENT_LIB_ADDRESS ( + 0, + 0, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + 0 + ); + PciSegmentWrite32 (PchSpiBase + R_PCH_SPI_BAR0, PCH_SPI_BASE_ADDRESS); + PciSegmentOr32 (PchSpiBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE); +} + +/** + Initializes SPI for access from future services. + + @retval EFI_SUCCESS The SPI service was initialized successfully. + @retval EFI_OUT_OF_RESOUCES Insufficient memory available to allocate structures required for initialization. + @retval Others An error occurred initializing SPI services. + +**/ +EFI_STATUS +EFIAPI +SpiServiceInit ( + VOID + ) +{ + EFI_STATUS Status; + PEI_SPI_INSTANCE *PeiSpiInstance; + SPI_INSTANCE *SpiInstance; + PCH_SPI_PPI *SpiPpi; + UINT16 AcpiBase; + + AcpiBase = 0; + + Status = PeiServicesLocatePpi ( + &gPchSpiPpiGuid, + 0, + NULL, + (VOID **) &SpiPpi + ); + + if (Status != EFI_SUCCESS) { + PchAcpiBaseGet (&AcpiBase); + if (AcpiBase == 0) { + PchAcpiBaseSet (PcdGet16 (PcdAcpiBaseAddress)); + } + + // + // Prior to PCI enumeration, initialize SPI BAR0 to a default value + // and also enable memory space decoding for SPI + // + InitSpiBar0 (); + + PeiSpiInstance = (PEI_SPI_INSTANCE *) AllocateZeroPool (sizeof (PEI_SPI_INSTANCE)); + if (NULL == PeiSpiInstance) { + return EFI_OUT_OF_RESOURCES; + } + + SpiInstance = &(PeiSpiInstance->SpiInstance); + SpiProtocolConstructor (SpiInstance); + + PeiSpiInstance->PpiDescriptor.Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + PeiSpiInstance->PpiDescriptor.Guid = &gPchSpiPpiGuid; + PeiSpiInstance->PpiDescriptor.Ppi = &(SpiInstance->SpiProtocol); + + Status = PeiServicesInstallPpi (&PeiSpiInstance->PpiDescriptor); + } + return Status; +} + +/** + Acquires the PCH SPI BAR0 MMIO address. + + @param[in] SpiInstance Pointer to SpiInstance to initialize + + @retval UINTN The SPIO BAR0 MMIO address + +**/ +UINTN +AcquireSpiBar0 ( + IN SPI_INSTANCE *SpiInstance + ) +{ + return MmioRead32 (SpiInstance->PchSpiBase + R_PCH_SPI_BAR0) & ~(B_PCH_SPI_BAR0_MASK); +} + +/** + Release the PCH SPI BAR0 MMIO address. + + @param[in] SpiInstance Pointer to SpiInstance to initialize + + @retval None +**/ +VOID +ReleaseSpiBar0 ( + IN SPI_INSTANCE *SpiInstance + ) +{ + return; +} + +/** + Disables BIOS Write Protect + + @retval EFI_SUCCESS BIOS Write Protect was disabled successfully + +**/ +EFI_STATUS +EFIAPI +DisableBiosWriteProtect ( + VOID + ) +{ + UINT64 SpiBaseAddress; + + SpiBaseAddress = PCI_SEGMENT_LIB_ADDRESS ( + 0, + 0, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + 0 + ); + // + // Clear EISS bit to allow for SPI use + // + PciSegmentAnd8 (SpiBaseAddress + R_PCH_SPI_BC, (UINT8) ~B_PCH_SPI_BC_EISS); + + // + // Write clear BC_SYNC_SS prior to change WPD from 0 to 1. + // + PciSegmentOr8 ( + SpiBaseAddress + R_PCH_SPI_BC + 1, + (B_PCH_SPI_BC_SYNC_SS >> 8) + ); + + // + // Set BIOSWE bit (SPI PCI Offset DCh [0]) = 1b + // Enable the access to the BIOS space for both read and write cycles + // + PciSegmentOr8 ( + SpiBaseAddress + R_PCH_SPI_BC, + B_PCH_SPI_BC_WPD + ); + + ASSERT ((PciSegmentRead8 (SpiBaseAddress + R_PCH_SPI_BC) & B_PCH_SPI_BC_EISS) != 0); + + return EFI_SUCCESS; +} + +/** + Enables BIOS Write Protect + +**/ +VOID +EFIAPI +EnableBiosWriteProtect ( + VOID + ) +{ + UINT64 SpiBaseAddress; + + SpiBaseAddress = PCI_SEGMENT_LIB_ADDRESS ( + 0, + 0, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + 0 + ); + + // + // Disable the access to the BIOS space for write cycles + // + PciSegmentAnd8 ( + SpiBaseAddress + R_PCH_SPI_BC, + (UINT8) (~B_PCH_SPI_BC_WPD) + ); +} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c b/Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c index 46184d4994..0b708d4aad 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c @@ -1,7 +1,7 @@ /** @file PCH SPI Common Driver implements the SPI Host Controller Compatibility Interface. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at @@ -760,9 +760,8 @@ SendSpiCmd ( Status = EFI_SUCCESS; SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This); SpiBaseAddress = SpiInstance->PchSpiBase; - PchSpiBar0 = AcquireSpiBar0 (SpiInstance); - SpiBaseAddress = SpiInstance->PchSpiBase; ABase = SpiInstance->PchAcpiBase; + PchSpiBar0 = AcquireSpiBar0 (SpiInstance); // // Disable SMIs to make sure normal mode flash access is not interrupted by an SMI -- 2.16.2.windows.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [edk2-platforms/devel-MinPlatform][PATCH v3 1/3] KabylakeSiliconPkg: Add SPI write support in PEI 2019-04-02 1:23 ` [edk2-platforms/devel-MinPlatform][PATCH v3 1/3] KabylakeSiliconPkg: Add SPI write support in PEI Michael Kubacki @ 2019-04-02 2:28 ` Chiu, Chasel 2019-04-02 2:48 ` Kubacki, Michael A 2019-04-02 2:31 ` Desimone, Nathaniel L 1 sibling, 1 reply; 11+ messages in thread From: Chiu, Chasel @ 2019-04-02 2:28 UTC (permalink / raw) To: Kubacki, Michael A, edk2-devel@lists.01.org Cc: Desimone, Nathaniel L, Gao, Liming, Kinney, Michael D Hi Michael, Please see below inline. Thanks! Chasel > -----Original Message----- > From: Kubacki, Michael A > Sent: Tuesday, April 2, 2019 9:23 AM > To: edk2-devel@lists.01.org > Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chiu, Chasel > <chasel.chiu@intel.com>; Gao, Liming <liming.gao@intel.com>; Kinney, Michael > D <michael.d.kinney@intel.com> > Subject: [edk2-platforms/devel-MinPlatform][PATCH v3 1/3] KabylakeSiliconPkg: > Add SPI write support in PEI > > Adds a new library PeiSpiLib to perform the initialization necessary to perform > SPI write cycles in PEI. After initialization, it installs an instance of the > PCH_SPI_PPI. > > Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> > Cc: Chasel Chiu <chasel.chiu@intel.com> > Cc: Liming Gao <liming.gao@intel.com> > Cc: Michael D Kinney <michael.d.kinney@intel.com> > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com> > --- > Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc | 3 +- > .../Pch/Library/PeiSpiLib/PeiSpiLib.inf | 50 +++++ > .../Pch/Include/Library/SpiLib.h | 32 +++ > .../Pch/Library/PeiSpiLib/PeiSpiLib.c | 221 +++++++++++++++++++++ > .../LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c | 5 +- > 5 files changed, 307 insertions(+), 4 deletions(-) create mode 100644 > Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf > create mode 100644 > Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiLib.h > create mode 100644 > Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c > > diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc > b/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc > index b81a736486..bb95ce3888 100644 > --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc > +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc > @@ -1,7 +1,7 @@ > ## @file > # Component description file for the SkyLake SiPkg PEI libraries. > # > -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > +reserved.<BR> > # > # This program and the accompanying materials are licensed and made available > under # the terms and conditions of the BSD License which accompanies this > distribution. > @@ -30,6 +30,7 @@ > !endif > > ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiResetSystemLib/P > eiResetSystemLib.inf > > PchResetLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiPchResetLib/PeiPchR > esetLib.inf > + SpiLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiSpiLib/PeiSpiLib.inf > > # > # Cpu > diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf > b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf > new file mode 100644 > index 0000000000..9240b6ef06 > --- /dev/null > +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.i > +++ nf > @@ -0,0 +1,50 @@ > +## @file > +# Component description file for PEI PCH SPI Initialization # # > +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> # # > +This program and the accompanying materials are licensed and made > +available under # the terms and conditions of the BSD License which > accompanies this distribution. > +# The full text of the license may be found at # > +http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER > EXPRESS OR IMPLIED. > +# > +## > + > +[Defines] > + INF_VERSION = 0x00010017 > + BASE_NAME = PeiSpiLib > + FILE_GUID = 4998447D-7948-448F-AB75-96E24E18FF23 > + VERSION_STRING = 1.0 > + MODULE_TYPE = PEIM > + LIBRARY_CLASS = SpiLib|PEIM PEI_CORE > + # > + # The following information is for reference only and not required by the build > tools. > + # > + # VALID_ARCHITECTURES = IA32 X64 IPF > + # > + > +[LibraryClasses] > + DebugLib > + MemoryAllocationLib > + PcdLib > + PchCycleDecodingLib > + PchSpiCommonLib > + PciSegmentLib > + PeiServicesLib > + PeiServicesTablePointerLib > + > +[Packages] > + MdePkg/MdePkg.dec > + KabylakeSiliconPkg/SiPkg.dec > + > +[Sources] > + PeiSpiLib.c > + > +[Pcd] > + gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES > + > +[Ppis] > + gPchSpiPpiGuid ## PRODUCES > diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiLib.h > b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiLib.h > new file mode 100644 > index 0000000000..6af66f8869 > --- /dev/null > +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiLib.h > @@ -0,0 +1,32 @@ > +/** @file > + Library to initialize SPI services for future SPI accesses. > + > +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> This > +program and the accompanying materials are licensed and made available > +under the terms and conditions of the BSD License that accompanies this > distribution. > +The full text of the license may be found at > +http://opensource.org/licenses/bsd-license.php. > + > +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS > OR IMPLIED. > + > +**/ > + > +#ifndef _SPI_LIB_H_ > +#define _SPI_LIB_H_ > + > +/** > + Initializes SPI for access from future services. > + > + @retval EFI_SUCCESS The SPI service was initialized successfully. > + @retval EFI_OUT_OF_RESOUCES Insufficient memory available to allocate > structures required for initialization. > + @retval Others An error occurred initializing SPI services. > + > +**/ > +EFI_STATUS > +EFIAPI > +SpiServiceInit ( > + VOID > + ); > + > +#endif > diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c > b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c > new file mode 100644 > index 0000000000..954317cd40 > --- /dev/null > +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c > @@ -0,0 +1,221 @@ > +/** @file > + PCH SPI PEI Library implements the SPI Host Controller Interface. > + > +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> This > +program and the accompanying materials are licensed and made available > +under the terms and conditions of the BSD License that accompanies this > distribution. > +The full text of the license may be found at > +http://opensource.org/licenses/bsd-license.php. > + > +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS > OR IMPLIED. > + > +**/ > + > +#include <PchReservedResources.h> > +#include <IndustryStandard/Pci30.h> > +#include <Ppi/Spi.h> > +#include <Register/PchRegsLpc.h> > +#include <Register/PchRegsSpi.h> > +#include <Library/DebugLib.h> > +#include <Library/IoLib.h> > +#include <Library/MemoryAllocationLib.h> #include <Library/PcdLib.h> > +#include <Library/PchCycleDecodingLib.h> #include > +<Library/PchSpiCommonLib.h> #include <Library/PciSegmentLib.h> #include > +<Library/PeiServicesLib.h> > + > +typedef struct { > + EFI_PEI_PPI_DESCRIPTOR PpiDescriptor; > + SPI_INSTANCE SpiInstance; > +} PEI_SPI_INSTANCE; > + > +/** > + Initializes the SPI BAR0 value to a default value and enables memory space > decoding. > + > + The SPI BAR0 will be assigned later in PCI enumeration. > + > +**/ > +VOID > +InitSpiBar0 ( > + VOID > + ) > +{ > + UINT64 PchSpiBase; > + PchSpiBase = PCI_SEGMENT_LIB_ADDRESS ( > + 0, > + 0, > + PCI_DEVICE_NUMBER_PCH_SPI, > + PCI_FUNCTION_NUMBER_PCH_SPI, > + 0 > + ); > + PciSegmentWrite32 (PchSpiBase + R_PCH_SPI_BAR0, > +PCH_SPI_BASE_ADDRESS); > + PciSegmentOr32 (PchSpiBase + PCI_COMMAND_OFFSET, > +EFI_PCI_COMMAND_MEMORY_SPACE); } > + > +/** > + Initializes SPI for access from future services. > + > + @retval EFI_SUCCESS The SPI service was initialized successfully. > + @retval EFI_OUT_OF_RESOUCES Insufficient memory available to allocate > structures required for initialization. > + @retval Others An error occurred initializing SPI services. > + > +**/ > +EFI_STATUS > +EFIAPI > +SpiServiceInit ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + PEI_SPI_INSTANCE *PeiSpiInstance; > + SPI_INSTANCE *SpiInstance; > + PCH_SPI_PPI *SpiPpi; > + UINT16 AcpiBase; > + > + AcpiBase = 0; > + > + Status = PeiServicesLocatePpi ( > + &gPchSpiPpiGuid, > + 0, > + NULL, > + (VOID **) &SpiPpi > + ); > + > + if (Status != EFI_SUCCESS) { Would you please add comments to explain why we must initialize ACPI BASE as part of the SpiServiceInit()? > + PchAcpiBaseGet (&AcpiBase); > + if (AcpiBase == 0) { > + PchAcpiBaseSet (PcdGet16 (PcdAcpiBaseAddress)); > + } > + > + // > + // Prior to PCI enumeration, initialize SPI BAR0 to a default value > + // and also enable memory space decoding for SPI > + // > + InitSpiBar0 (); > + > + PeiSpiInstance = (PEI_SPI_INSTANCE *) AllocateZeroPool (sizeof > (PEI_SPI_INSTANCE)); > + if (NULL == PeiSpiInstance) { > + return EFI_OUT_OF_RESOURCES; > + } > + > + SpiInstance = &(PeiSpiInstance->SpiInstance); > + SpiProtocolConstructor (SpiInstance); > + > + PeiSpiInstance->PpiDescriptor.Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | > EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; > + PeiSpiInstance->PpiDescriptor.Guid = &gPchSpiPpiGuid; > + PeiSpiInstance->PpiDescriptor.Ppi = &(SpiInstance->SpiProtocol); > + > + Status = PeiServicesInstallPpi (&PeiSpiInstance->PpiDescriptor); > + } > + return Status; > +} > + > +/** > + Acquires the PCH SPI BAR0 MMIO address. > + > + @param[in] SpiInstance Pointer to SpiInstance to initialize > + > + @retval UINTN The SPIO BAR0 MMIO address > + > +**/ > +UINTN > +AcquireSpiBar0 ( > + IN SPI_INSTANCE *SpiInstance > + ) > +{ > + return MmioRead32 (SpiInstance->PchSpiBase + R_PCH_SPI_BAR0) & > +~(B_PCH_SPI_BAR0_MASK); } > + > +/** > + Release the PCH SPI BAR0 MMIO address. > + > + @param[in] SpiInstance Pointer to SpiInstance to initialize > + > + @retval None > +**/ > +VOID > +ReleaseSpiBar0 ( > + IN SPI_INSTANCE *SpiInstance > + ) > +{ > + return; > +} > + > +/** > + Disables BIOS Write Protect > + > + @retval EFI_SUCCESS BIOS Write Protect was disabled successfully > + > +**/ > +EFI_STATUS > +EFIAPI > +DisableBiosWriteProtect ( > + VOID > + ) > +{ > + UINT64 SpiBaseAddress; > + > + SpiBaseAddress = PCI_SEGMENT_LIB_ADDRESS ( > + 0, > + 0, > + PCI_DEVICE_NUMBER_PCH_SPI, > + PCI_FUNCTION_NUMBER_PCH_SPI, > + 0 > + ); > + // > + // Clear EISS bit to allow for SPI use // > + PciSegmentAnd8 (SpiBaseAddress + R_PCH_SPI_BC, (UINT8) > + ~B_PCH_SPI_BC_EISS); > + > + // > + // Write clear BC_SYNC_SS prior to change WPD from 0 to 1. > + // > + PciSegmentOr8 ( > + SpiBaseAddress + R_PCH_SPI_BC + 1, > + (B_PCH_SPI_BC_SYNC_SS >> 8) > + ); > + > + // > + // Set BIOSWE bit (SPI PCI Offset DCh [0]) = 1b // Enable the access > + to the BIOS space for both read and write cycles // > + PciSegmentOr8 ( > + SpiBaseAddress + R_PCH_SPI_BC, > + B_PCH_SPI_BC_WPD > + ); > + > + ASSERT ((PciSegmentRead8 (SpiBaseAddress + R_PCH_SPI_BC) & > + B_PCH_SPI_BC_EISS) != 0); > + > + return EFI_SUCCESS; > +} > + > +/** > + Enables BIOS Write Protect > + > +**/ > +VOID > +EFIAPI > +EnableBiosWriteProtect ( > + VOID > + ) > +{ > + UINT64 SpiBaseAddress; > + > + SpiBaseAddress = PCI_SEGMENT_LIB_ADDRESS ( > + 0, > + 0, > + PCI_DEVICE_NUMBER_PCH_SPI, > + PCI_FUNCTION_NUMBER_PCH_SPI, > + 0 > + ); > + > + // > + // Disable the access to the BIOS space for write cycles > + // > + PciSegmentAnd8 ( > + SpiBaseAddress + R_PCH_SPI_BC, > + (UINT8) (~B_PCH_SPI_BC_WPD) > + ); > +} > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/BasePchSpiCommonLib/ > SpiCommon.c > b/Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/BasePchSpiCommonLib/ > SpiCommon.c > index 46184d4994..0b708d4aad 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/BasePchSpiCommonLib/ > SpiCommon.c > +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/BasePchSpiComm > +++ onLib/SpiCommon.c > @@ -1,7 +1,7 @@ > /** @file > PCH SPI Common Driver implements the SPI Host Controller Compatibility > Interface. > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> > This program and the accompanying materials are licensed and made available > under the terms and conditions of the BSD License that accompanies this > distribution. > The full text of the license may be found at @@ -760,9 +760,8 @@ SendSpiCmd > ( > Status = EFI_SUCCESS; > SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This); > SpiBaseAddress = SpiInstance->PchSpiBase; > - PchSpiBar0 = AcquireSpiBar0 (SpiInstance); > - SpiBaseAddress = SpiInstance->PchSpiBase; > ABase = SpiInstance->PchAcpiBase; > + PchSpiBar0 = AcquireSpiBar0 (SpiInstance); > > // > // Disable SMIs to make sure normal mode flash access is not interrupted by an > SMI > -- > 2.16.2.windows.1 ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [edk2-platforms/devel-MinPlatform][PATCH v3 1/3] KabylakeSiliconPkg: Add SPI write support in PEI 2019-04-02 2:28 ` Chiu, Chasel @ 2019-04-02 2:48 ` Kubacki, Michael A 0 siblings, 0 replies; 11+ messages in thread From: Kubacki, Michael A @ 2019-04-02 2:48 UTC (permalink / raw) To: Chiu, Chasel, edk2-devel@lists.01.org Cc: Desimone, Nathaniel L, Gao, Liming, Kinney, Michael D Comment added in v4 > -----Original Message----- > From: Chiu, Chasel > Sent: Monday, April 1, 2019 7:29 PM > To: Kubacki, Michael A <michael.a.kubacki@intel.com>; edk2- > devel@lists.01.org > Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Gao, Liming > <liming.gao@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com> > Subject: RE: [edk2-platforms/devel-MinPlatform][PATCH v3 1/3] > KabylakeSiliconPkg: Add SPI write support in PEI > > > Hi Michael, > > Please see below inline. > > Thanks! > Chasel > > > > -----Original Message----- > > From: Kubacki, Michael A > > Sent: Tuesday, April 2, 2019 9:23 AM > > To: edk2-devel@lists.01.org > > Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chiu, > > Chasel <chasel.chiu@intel.com>; Gao, Liming <liming.gao@intel.com>; > > Kinney, Michael D <michael.d.kinney@intel.com> > > Subject: [edk2-platforms/devel-MinPlatform][PATCH v3 1/3] > KabylakeSiliconPkg: > > Add SPI write support in PEI > > > > Adds a new library PeiSpiLib to perform the initialization necessary > > to perform SPI write cycles in PEI. After initialization, it installs > > an instance of the PCH_SPI_PPI. > > > > Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> > > Cc: Chasel Chiu <chasel.chiu@intel.com> > > Cc: Liming Gao <liming.gao@intel.com> > > Cc: Michael D Kinney <michael.d.kinney@intel.com> > > Contributed-under: TianoCore Contribution Agreement 1.0 > > Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com> > > --- > > Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc | 3 +- > > .../Pch/Library/PeiSpiLib/PeiSpiLib.inf | 50 +++++ > > .../Pch/Include/Library/SpiLib.h | 32 +++ > > .../Pch/Library/PeiSpiLib/PeiSpiLib.c | 221 +++++++++++++++++++++ > > .../LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c | 5 +- > > 5 files changed, 307 insertions(+), 4 deletions(-) create mode > > 100644 > > Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf > > create mode 100644 > > Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiLib.h > > create mode 100644 > > Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c > > > > diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc > > b/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc > > index b81a736486..bb95ce3888 100644 > > --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc > > +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc > > @@ -1,7 +1,7 @@ > > ## @file > > # Component description file for the SkyLake SiPkg PEI libraries. > > # > > -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > > +reserved.<BR> > > # > > # This program and the accompanying materials are licensed and made > > available under # the terms and conditions of the BSD License which > > accompanies this distribution. > > @@ -30,6 +30,7 @@ > > !endif > > > > > ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiResetSystemLib/P > > eiResetSystemLib.inf > > > > PchResetLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiPchResetLib/PeiPchR > > esetLib.inf > > + SpiLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiSpiLib/PeiSpiLib.inf > > > > # > > # Cpu > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf > > b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf > > new file mode 100644 > > index 0000000000..9240b6ef06 > > --- /dev/null > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib > > +++ .i > > +++ nf > > @@ -0,0 +1,50 @@ > > +## @file > > +# Component description file for PEI PCH SPI Initialization # # > > +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> # # > > +This program and the accompanying materials are licensed and made > > +available under # the terms and conditions of the BSD License which > > accompanies this distribution. > > +# The full text of the license may be found at # > > +http://opensource.org/licenses/bsd-license.php > > +# > > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" > > +BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, > EITHER > > EXPRESS OR IMPLIED. > > +# > > +## > > + > > +[Defines] > > + INF_VERSION = 0x00010017 > > + BASE_NAME = PeiSpiLib > > + FILE_GUID = 4998447D-7948-448F-AB75-96E24E18FF23 > > + VERSION_STRING = 1.0 > > + MODULE_TYPE = PEIM > > + LIBRARY_CLASS = SpiLib|PEIM PEI_CORE > > + # > > + # The following information is for reference only and not required > > +by the build > > tools. > > + # > > + # VALID_ARCHITECTURES = IA32 X64 IPF # > > + > > +[LibraryClasses] > > + DebugLib > > + MemoryAllocationLib > > + PcdLib > > + PchCycleDecodingLib > > + PchSpiCommonLib > > + PciSegmentLib > > + PeiServicesLib > > + PeiServicesTablePointerLib > > + > > +[Packages] > > + MdePkg/MdePkg.dec > > + KabylakeSiliconPkg/SiPkg.dec > > + > > +[Sources] > > + PeiSpiLib.c > > + > > +[Pcd] > > + gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES > > + > > +[Ppis] > > + gPchSpiPpiGuid ## PRODUCES > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiLib.h > > b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiLib.h > > new file mode 100644 > > index 0000000000..6af66f8869 > > --- /dev/null > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiLib.h > > @@ -0,0 +1,32 @@ > > +/** @file > > + Library to initialize SPI services for future SPI accesses. > > + > > +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> This > > +program and the accompanying materials are licensed and made > > +available under the terms and conditions of the BSD License that > > +accompanies this > > distribution. > > +The full text of the license may be found at > > +http://opensource.org/licenses/bsd-license.php. > > + > > +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" > BASIS, > > +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER > EXPRESS > > OR IMPLIED. > > + > > +**/ > > + > > +#ifndef _SPI_LIB_H_ > > +#define _SPI_LIB_H_ > > + > > +/** > > + Initializes SPI for access from future services. > > + > > + @retval EFI_SUCCESS The SPI service was initialized successfully. > > + @retval EFI_OUT_OF_RESOUCES Insufficient memory available to > > + allocate > > structures required for initialization. > > + @retval Others An error occurred initializing SPI services. > > + > > +**/ > > +EFI_STATUS > > +EFIAPI > > +SpiServiceInit ( > > + VOID > > + ); > > + > > +#endif > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c > > b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c > > new file mode 100644 > > index 0000000000..954317cd40 > > --- /dev/null > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib > > +++ .c > > @@ -0,0 +1,221 @@ > > +/** @file > > + PCH SPI PEI Library implements the SPI Host Controller Interface. > > + > > +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> This > > +program and the accompanying materials are licensed and made > > +available under the terms and conditions of the BSD License that > > +accompanies this > > distribution. > > +The full text of the license may be found at > > +http://opensource.org/licenses/bsd-license.php. > > + > > +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" > BASIS, > > +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER > EXPRESS > > OR IMPLIED. > > + > > +**/ > > + > > +#include <PchReservedResources.h> > > +#include <IndustryStandard/Pci30.h> > > +#include <Ppi/Spi.h> > > +#include <Register/PchRegsLpc.h> > > +#include <Register/PchRegsSpi.h> > > +#include <Library/DebugLib.h> > > +#include <Library/IoLib.h> > > +#include <Library/MemoryAllocationLib.h> #include <Library/PcdLib.h> > > +#include <Library/PchCycleDecodingLib.h> #include > > +<Library/PchSpiCommonLib.h> #include <Library/PciSegmentLib.h> > > +#include <Library/PeiServicesLib.h> > > + > > +typedef struct { > > + EFI_PEI_PPI_DESCRIPTOR PpiDescriptor; > > + SPI_INSTANCE SpiInstance; > > +} PEI_SPI_INSTANCE; > > + > > +/** > > + Initializes the SPI BAR0 value to a default value and enables > > +memory space > > decoding. > > + > > + The SPI BAR0 will be assigned later in PCI enumeration. > > + > > +**/ > > +VOID > > +InitSpiBar0 ( > > + VOID > > + ) > > +{ > > + UINT64 PchSpiBase; > > + PchSpiBase = PCI_SEGMENT_LIB_ADDRESS ( > > + 0, > > + 0, > > + PCI_DEVICE_NUMBER_PCH_SPI, > > + PCI_FUNCTION_NUMBER_PCH_SPI, > > + 0 > > + ); > > + PciSegmentWrite32 (PchSpiBase + R_PCH_SPI_BAR0, > > +PCH_SPI_BASE_ADDRESS); > > + PciSegmentOr32 (PchSpiBase + PCI_COMMAND_OFFSET, > > +EFI_PCI_COMMAND_MEMORY_SPACE); } > > + > > +/** > > + Initializes SPI for access from future services. > > + > > + @retval EFI_SUCCESS The SPI service was initialized successfully. > > + @retval EFI_OUT_OF_RESOUCES Insufficient memory available to > > + allocate > > structures required for initialization. > > + @retval Others An error occurred initializing SPI services. > > + > > +**/ > > +EFI_STATUS > > +EFIAPI > > +SpiServiceInit ( > > + VOID > > + ) > > +{ > > + EFI_STATUS Status; > > + PEI_SPI_INSTANCE *PeiSpiInstance; > > + SPI_INSTANCE *SpiInstance; > > + PCH_SPI_PPI *SpiPpi; > > + UINT16 AcpiBase; > > + > > + AcpiBase = 0; > > + > > + Status = PeiServicesLocatePpi ( > > + &gPchSpiPpiGuid, > > + 0, > > + NULL, > > + (VOID **) &SpiPpi > > + ); > > + > > + if (Status != EFI_SUCCESS) { > > Would you please add comments to explain why we must initialize ACPI BASE > as part of the SpiServiceInit()? > > > + PchAcpiBaseGet (&AcpiBase); > > + if (AcpiBase == 0) { > > + PchAcpiBaseSet (PcdGet16 (PcdAcpiBaseAddress)); > > + } > > + > > + // > > + // Prior to PCI enumeration, initialize SPI BAR0 to a default value > > + // and also enable memory space decoding for SPI > > + // > > + InitSpiBar0 (); > > + > > + PeiSpiInstance = (PEI_SPI_INSTANCE *) AllocateZeroPool (sizeof > > (PEI_SPI_INSTANCE)); > > + if (NULL == PeiSpiInstance) { > > + return EFI_OUT_OF_RESOURCES; > > + } > > + > > + SpiInstance = &(PeiSpiInstance->SpiInstance); > > + SpiProtocolConstructor (SpiInstance); > > + > > + PeiSpiInstance->PpiDescriptor.Flags = EFI_PEI_PPI_DESCRIPTOR_PPI > > + | > > EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; > > + PeiSpiInstance->PpiDescriptor.Guid = &gPchSpiPpiGuid; > > + PeiSpiInstance->PpiDescriptor.Ppi = &(SpiInstance->SpiProtocol); > > + > > + Status = PeiServicesInstallPpi (&PeiSpiInstance->PpiDescriptor); > > + } > > + return Status; > > +} > > + > > +/** > > + Acquires the PCH SPI BAR0 MMIO address. > > + > > + @param[in] SpiInstance Pointer to SpiInstance to initialize > > + > > + @retval UINTN The SPIO BAR0 MMIO address > > + > > +**/ > > +UINTN > > +AcquireSpiBar0 ( > > + IN SPI_INSTANCE *SpiInstance > > + ) > > +{ > > + return MmioRead32 (SpiInstance->PchSpiBase + R_PCH_SPI_BAR0) & > > +~(B_PCH_SPI_BAR0_MASK); } > > + > > +/** > > + Release the PCH SPI BAR0 MMIO address. > > + > > + @param[in] SpiInstance Pointer to SpiInstance to initialize > > + > > + @retval None > > +**/ > > +VOID > > +ReleaseSpiBar0 ( > > + IN SPI_INSTANCE *SpiInstance > > + ) > > +{ > > + return; > > +} > > + > > +/** > > + Disables BIOS Write Protect > > + > > + @retval EFI_SUCCESS BIOS Write Protect was disabled successfully > > + > > +**/ > > +EFI_STATUS > > +EFIAPI > > +DisableBiosWriteProtect ( > > + VOID > > + ) > > +{ > > + UINT64 SpiBaseAddress; > > + > > + SpiBaseAddress = PCI_SEGMENT_LIB_ADDRESS ( > > + 0, > > + 0, > > + PCI_DEVICE_NUMBER_PCH_SPI, > > + PCI_FUNCTION_NUMBER_PCH_SPI, > > + 0 > > + ); > > + // > > + // Clear EISS bit to allow for SPI use // > > + PciSegmentAnd8 (SpiBaseAddress + R_PCH_SPI_BC, (UINT8) > > + ~B_PCH_SPI_BC_EISS); > > + > > + // > > + // Write clear BC_SYNC_SS prior to change WPD from 0 to 1. > > + // > > + PciSegmentOr8 ( > > + SpiBaseAddress + R_PCH_SPI_BC + 1, > > + (B_PCH_SPI_BC_SYNC_SS >> 8) > > + ); > > + > > + // > > + // Set BIOSWE bit (SPI PCI Offset DCh [0]) = 1b // Enable the > > + access to the BIOS space for both read and write cycles // > > + PciSegmentOr8 ( > > + SpiBaseAddress + R_PCH_SPI_BC, > > + B_PCH_SPI_BC_WPD > > + ); > > + > > + ASSERT ((PciSegmentRead8 (SpiBaseAddress + R_PCH_SPI_BC) & > > + B_PCH_SPI_BC_EISS) != 0); > > + > > + return EFI_SUCCESS; > > +} > > + > > +/** > > + Enables BIOS Write Protect > > + > > +**/ > > +VOID > > +EFIAPI > > +EnableBiosWriteProtect ( > > + VOID > > + ) > > +{ > > + UINT64 SpiBaseAddress; > > + > > + SpiBaseAddress = PCI_SEGMENT_LIB_ADDRESS ( > > + 0, > > + 0, > > + PCI_DEVICE_NUMBER_PCH_SPI, > > + PCI_FUNCTION_NUMBER_PCH_SPI, > > + 0 > > + ); > > + > > + // > > + // Disable the access to the BIOS space for write cycles > > + // > > + PciSegmentAnd8 ( > > + SpiBaseAddress + R_PCH_SPI_BC, > > + (UINT8) (~B_PCH_SPI_BC_WPD) > > + ); > > +} > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/BasePchSpiCommon > > Lib/ > > SpiCommon.c > > b/Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/BasePchSpiCommon > > Lib/ > > SpiCommon.c > > index 46184d4994..0b708d4aad 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/BasePchSpiCommon > > Lib/ > > SpiCommon.c > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/BasePchSpiCo > > +++ mm > > +++ onLib/SpiCommon.c > > @@ -1,7 +1,7 @@ > > /** @file > > PCH SPI Common Driver implements the SPI Host Controller > > Compatibility Interface. > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > > +Copyright (c) 2017 - 2019, Intel Corporation. All rights > > +reserved.<BR> > > This program and the accompanying materials are licensed and made > > available under the terms and conditions of the BSD License that > > accompanies this distribution. > > The full text of the license may be found at @@ -760,9 +760,8 @@ > > SendSpiCmd ( > > Status = EFI_SUCCESS; > > SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This); > > SpiBaseAddress = SpiInstance->PchSpiBase; > > - PchSpiBar0 = AcquireSpiBar0 (SpiInstance); > > - SpiBaseAddress = SpiInstance->PchSpiBase; > > ABase = SpiInstance->PchAcpiBase; > > + PchSpiBar0 = AcquireSpiBar0 (SpiInstance); > > > > // > > // Disable SMIs to make sure normal mode flash access is not > > interrupted by an SMI > > -- > > 2.16.2.windows.1 ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [edk2-platforms/devel-MinPlatform][PATCH v3 1/3] KabylakeSiliconPkg: Add SPI write support in PEI 2019-04-02 1:23 ` [edk2-platforms/devel-MinPlatform][PATCH v3 1/3] KabylakeSiliconPkg: Add SPI write support in PEI Michael Kubacki 2019-04-02 2:28 ` Chiu, Chasel @ 2019-04-02 2:31 ` Desimone, Nathaniel L 1 sibling, 0 replies; 11+ messages in thread From: Desimone, Nathaniel L @ 2019-04-02 2:31 UTC (permalink / raw) To: Kubacki, Michael A, edk2-devel@lists.01.org Cc: Chiu, Chasel, Gao, Liming, Kinney, Michael D Look's good! Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> -----Original Message----- From: Kubacki, Michael A Sent: Monday, April 1, 2019 6:23 PM To: edk2-devel@lists.01.org Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>; Gao, Liming <liming.gao@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com> Subject: [edk2-platforms/devel-MinPlatform][PATCH v3 1/3] KabylakeSiliconPkg: Add SPI write support in PEI Adds a new library PeiSpiLib to perform the initialization necessary to perform SPI write cycles in PEI. After initialization, it installs an instance of the PCH_SPI_PPI. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com> --- Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc | 3 +- .../Pch/Library/PeiSpiLib/PeiSpiLib.inf | 50 +++++ .../Pch/Include/Library/SpiLib.h | 32 +++ .../Pch/Library/PeiSpiLib/PeiSpiLib.c | 221 +++++++++++++++++++++ .../LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c | 5 +- 5 files changed, 307 insertions(+), 4 deletions(-) create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc b/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc index b81a736486..bb95ce3888 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc @@ -1,7 +1,7 @@ ## @file # Component description file for the SkyLake SiPkg PEI libraries. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights +reserved.<BR> # # This program and the accompanying materials are licensed and made available under # the terms and conditions of the BSD License which accompanies this distribution. @@ -30,6 +30,7 @@ !endif ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiResetSystemLib/PeiResetSystemLib.inf PchResetLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiPchResetLib/PeiPchResetLib.inf + SpiLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiSpiLib/PeiSpiLib.inf # # Cpu diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf new file mode 100644 index 0000000000..9240b6ef06 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.i +++ nf @@ -0,0 +1,50 @@ +## @file +# Component description file for PEI PCH SPI Initialization # # +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> # # +This program and the accompanying materials are licensed and made +available under # the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at # +http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PeiSpiLib + FILE_GUID = 4998447D-7948-448F-AB75-96E24E18FF23 + VERSION_STRING = 1.0 + MODULE_TYPE = PEIM + LIBRARY_CLASS = SpiLib|PEIM PEI_CORE + # + # The following information is for reference only and not required by the build tools. + # + # VALID_ARCHITECTURES = IA32 X64 IPF + # + +[LibraryClasses] + DebugLib + MemoryAllocationLib + PcdLib + PchCycleDecodingLib + PchSpiCommonLib + PciSegmentLib + PeiServicesLib + PeiServicesTablePointerLib + +[Packages] + MdePkg/MdePkg.dec + KabylakeSiliconPkg/SiPkg.dec + +[Sources] + PeiSpiLib.c + +[Pcd] + gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES + +[Ppis] + gPchSpiPpiGuid ## PRODUCES diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiLib.h new file mode 100644 index 0000000000..6af66f8869 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiLib.h @@ -0,0 +1,32 @@ +/** @file + Library to initialize SPI services for future SPI accesses. + +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> This +program and the accompanying materials are licensed and made available +under the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SPI_LIB_H_ +#define _SPI_LIB_H_ + +/** + Initializes SPI for access from future services. + + @retval EFI_SUCCESS The SPI service was initialized successfully. + @retval EFI_OUT_OF_RESOUCES Insufficient memory available to allocate structures required for initialization. + @retval Others An error occurred initializing SPI services. + +**/ +EFI_STATUS +EFIAPI +SpiServiceInit ( + VOID + ); + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c new file mode 100644 index 0000000000..954317cd40 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c @@ -0,0 +1,221 @@ +/** @file + PCH SPI PEI Library implements the SPI Host Controller Interface. + +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> This +program and the accompanying materials are licensed and made available +under the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <PchReservedResources.h> +#include <IndustryStandard/Pci30.h> +#include <Ppi/Spi.h> +#include <Register/PchRegsLpc.h> +#include <Register/PchRegsSpi.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/MemoryAllocationLib.h> #include <Library/PcdLib.h> +#include <Library/PchCycleDecodingLib.h> #include +<Library/PchSpiCommonLib.h> #include <Library/PciSegmentLib.h> #include +<Library/PeiServicesLib.h> + +typedef struct { + EFI_PEI_PPI_DESCRIPTOR PpiDescriptor; + SPI_INSTANCE SpiInstance; +} PEI_SPI_INSTANCE; + +/** + Initializes the SPI BAR0 value to a default value and enables memory space decoding. + + The SPI BAR0 will be assigned later in PCI enumeration. + +**/ +VOID +InitSpiBar0 ( + VOID + ) +{ + UINT64 PchSpiBase; + PchSpiBase = PCI_SEGMENT_LIB_ADDRESS ( + 0, + 0, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + 0 + ); + PciSegmentWrite32 (PchSpiBase + R_PCH_SPI_BAR0, +PCH_SPI_BASE_ADDRESS); + PciSegmentOr32 (PchSpiBase + PCI_COMMAND_OFFSET, +EFI_PCI_COMMAND_MEMORY_SPACE); } + +/** + Initializes SPI for access from future services. + + @retval EFI_SUCCESS The SPI service was initialized successfully. + @retval EFI_OUT_OF_RESOUCES Insufficient memory available to allocate structures required for initialization. + @retval Others An error occurred initializing SPI services. + +**/ +EFI_STATUS +EFIAPI +SpiServiceInit ( + VOID + ) +{ + EFI_STATUS Status; + PEI_SPI_INSTANCE *PeiSpiInstance; + SPI_INSTANCE *SpiInstance; + PCH_SPI_PPI *SpiPpi; + UINT16 AcpiBase; + + AcpiBase = 0; + + Status = PeiServicesLocatePpi ( + &gPchSpiPpiGuid, + 0, + NULL, + (VOID **) &SpiPpi + ); + + if (Status != EFI_SUCCESS) { + PchAcpiBaseGet (&AcpiBase); + if (AcpiBase == 0) { + PchAcpiBaseSet (PcdGet16 (PcdAcpiBaseAddress)); + } + + // + // Prior to PCI enumeration, initialize SPI BAR0 to a default value + // and also enable memory space decoding for SPI + // + InitSpiBar0 (); + + PeiSpiInstance = (PEI_SPI_INSTANCE *) AllocateZeroPool (sizeof (PEI_SPI_INSTANCE)); + if (NULL == PeiSpiInstance) { + return EFI_OUT_OF_RESOURCES; + } + + SpiInstance = &(PeiSpiInstance->SpiInstance); + SpiProtocolConstructor (SpiInstance); + + PeiSpiInstance->PpiDescriptor.Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + PeiSpiInstance->PpiDescriptor.Guid = &gPchSpiPpiGuid; + PeiSpiInstance->PpiDescriptor.Ppi = &(SpiInstance->SpiProtocol); + + Status = PeiServicesInstallPpi (&PeiSpiInstance->PpiDescriptor); + } + return Status; +} + +/** + Acquires the PCH SPI BAR0 MMIO address. + + @param[in] SpiInstance Pointer to SpiInstance to initialize + + @retval UINTN The SPIO BAR0 MMIO address + +**/ +UINTN +AcquireSpiBar0 ( + IN SPI_INSTANCE *SpiInstance + ) +{ + return MmioRead32 (SpiInstance->PchSpiBase + R_PCH_SPI_BAR0) & +~(B_PCH_SPI_BAR0_MASK); } + +/** + Release the PCH SPI BAR0 MMIO address. + + @param[in] SpiInstance Pointer to SpiInstance to initialize + + @retval None +**/ +VOID +ReleaseSpiBar0 ( + IN SPI_INSTANCE *SpiInstance + ) +{ + return; +} + +/** + Disables BIOS Write Protect + + @retval EFI_SUCCESS BIOS Write Protect was disabled successfully + +**/ +EFI_STATUS +EFIAPI +DisableBiosWriteProtect ( + VOID + ) +{ + UINT64 SpiBaseAddress; + + SpiBaseAddress = PCI_SEGMENT_LIB_ADDRESS ( + 0, + 0, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + 0 + ); + // + // Clear EISS bit to allow for SPI use // + PciSegmentAnd8 (SpiBaseAddress + R_PCH_SPI_BC, (UINT8) + ~B_PCH_SPI_BC_EISS); + + // + // Write clear BC_SYNC_SS prior to change WPD from 0 to 1. + // + PciSegmentOr8 ( + SpiBaseAddress + R_PCH_SPI_BC + 1, + (B_PCH_SPI_BC_SYNC_SS >> 8) + ); + + // + // Set BIOSWE bit (SPI PCI Offset DCh [0]) = 1b // Enable the access + to the BIOS space for both read and write cycles // + PciSegmentOr8 ( + SpiBaseAddress + R_PCH_SPI_BC, + B_PCH_SPI_BC_WPD + ); + + ASSERT ((PciSegmentRead8 (SpiBaseAddress + R_PCH_SPI_BC) & + B_PCH_SPI_BC_EISS) != 0); + + return EFI_SUCCESS; +} + +/** + Enables BIOS Write Protect + +**/ +VOID +EFIAPI +EnableBiosWriteProtect ( + VOID + ) +{ + UINT64 SpiBaseAddress; + + SpiBaseAddress = PCI_SEGMENT_LIB_ADDRESS ( + 0, + 0, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + 0 + ); + + // + // Disable the access to the BIOS space for write cycles + // + PciSegmentAnd8 ( + SpiBaseAddress + R_PCH_SPI_BC, + (UINT8) (~B_PCH_SPI_BC_WPD) + ); +} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c b/Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c index 46184d4994..0b708d4aad 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/BasePchSpiComm +++ onLib/SpiCommon.c @@ -1,7 +1,7 @@ /** @file PCH SPI Common Driver implements the SPI Host Controller Compatibility Interface. -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at @@ -760,9 +760,8 @@ SendSpiCmd ( Status = EFI_SUCCESS; SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This); SpiBaseAddress = SpiInstance->PchSpiBase; - PchSpiBar0 = AcquireSpiBar0 (SpiInstance); - SpiBaseAddress = SpiInstance->PchSpiBase; ABase = SpiInstance->PchAcpiBase; + PchSpiBar0 = AcquireSpiBar0 (SpiInstance); // // Disable SMIs to make sure normal mode flash access is not interrupted by an SMI -- 2.16.2.windows.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [edk2-platforms/devel-MinPlatform][PATCH v3 2/3] ClevoOpenBoardPkg/N1xxWU: Flash map update 2019-04-02 1:23 [edk2-platforms/devel-MinPlatform][PATCH v3 0/3] Enable SPI flash debug messages Michael Kubacki 2019-04-02 1:23 ` [edk2-platforms/devel-MinPlatform][PATCH v3 1/3] KabylakeSiliconPkg: Add SPI write support in PEI Michael Kubacki @ 2019-04-02 1:23 ` Michael Kubacki 2019-04-02 2:31 ` Desimone, Nathaniel L 2019-04-02 2:36 ` Chiu, Chasel 2019-04-02 1:23 ` [edk2-platforms/devel-MinPlatform][PATCH v3 3/3] ClevoOpenBoardPkg/N1xxWU: Write PEI debug messages to SPI flash Michael Kubacki 2 siblings, 2 replies; 11+ messages in thread From: Michael Kubacki @ 2019-04-02 1:23 UTC (permalink / raw) To: edk2-devel Cc: Ankit Sinha, Nate DeSimone, Chasel Chiu, Liming Gao, Michael D Kinney Updates the total BIOS flash image size to 0x5E0000. This size matches the BIOS region size already configured in the SPI flash descriptor. To write an image produced from the N1xxWU board build, write the N1XXWU.fd file (~6 MB) to the beginning of the BIOS region in the SPI flash (currently 0x220000). Always back up the original SPI flash image. These offsets and sizes are subject to change over time. Cc: Ankit Sinha <ankit.sinha@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com> --- .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc | 2 +- .../N1xxWU/Include/Fdf/FlashMapInclude.fdf | 44 +++++++++++----------- .../Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat | 4 +- 3 files changed, 26 insertions(+), 24 deletions(-) diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc index 81487ed58d..2116c48fc0 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc @@ -55,7 +55,7 @@ # # Default value for OpenBoardPkg.fdf use # - DEFINE BIOS_SIZE_OPTION = SIZE_70 + DEFINE BIOS_SIZE_OPTION = SIZE_60 ################################################################################ # diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude.fdf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude.fdf index a727eb3b83..423c6b18f5 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude.fdf +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude.fdf @@ -14,39 +14,41 @@ ## #=================================================================================# -# 8 M BIOS - for FSP wrapper +# 6 M BIOS - for FSP wrapper #=================================================================================# -DEFINE FLASH_BASE = 0xFF800000 # -DEFINE FLASH_SIZE = 0x00800000 # +DEFINE FLASH_BASE = 0xFFA20000 # +DEFINE FLASH_SIZE = 0x005E0000 # DEFINE FLASH_BLOCK_SIZE = 0x00010000 # -DEFINE FLASH_NUM_BLOCKS = 0x00000080 # +DEFINE FLASH_NUM_BLOCKS = 0x0000005E # #=================================================================================# -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = 0x00000000 # Flash addr (0xFF800000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = 0x00000000 # Flash addr (0xFFA20000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize = 0x00040000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = 0x00000000 # Flash addr (0xFF800000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = 0x00000000 # Flash addr (0xFFA20000) SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0x0001E000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = 0x0001E000 # Flash addr (0xFF81E000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = 0x0001E000 # Flash addr (0xFFA3E000) SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = 0x00002000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = 0x00020000 # Flash addr (0xFF820000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = 0x00020000 # Flash addr (0xFFA40000) SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = 0x00020000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00040000 # Flash addr (0xFF840000) +SET gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset = 0x00040000 # Flash addr (0xFFA60000) +SET gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize = 0x00010000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00050000 # Flash addr (0xFFA70000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = 0x00060000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = 0x000A0000 # Flash addr (0xFF8A0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = 0x000B0000 # Flash addr (0xFFAD0000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00070000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = 0x00110000 # Flash addr (0xFF910000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = 0x00120000 # Flash addr (0xFFB40000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00090000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = 0x001A0000 # Flash addr (0xFF9A0000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x001E0000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = 0x00380000 # Flash addr (0xFFB80000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00180000 # -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = 0x00500000 # Flash addr (0xFFD00000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = 0x001B0000 # Flash addr (0xFFBD0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x00140000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = 0x002F0000 # Flash addr (0xFFD10000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x000B0000 # +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = 0x003A0000 # Flash addr (0xFFDC0000) SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = 0x000A0000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = 0x005A0000 # Flash addr (0xFFDA0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = 0x00440000 # Flash addr (0xFFE60000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = 0x00060000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = 0x00600000 # Flash addr (0xFFE00000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = 0x004A0000 # Flash addr (0xFFEC0000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize = 0x000BC000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = 0x006BC000 # Flash addr (0xFFEBC000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = 0x0055C000 # Flash addr (0xFFF7C000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize = 0x00004000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = 0x006C0000 # Flash addr (0xFFEC0000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = 0x00140000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = 0x00560000 # Flash addr (0xFFF80000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = 0x00080000 # diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat index c09d2d5b16..c3360403f1 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat @@ -202,8 +202,8 @@ cl @set BIOS_SIZE_OPTION= -@REM default size option is 7M -@set BIOS_SIZE_OPTION=-DBIOS_SIZE_OPTION=SIZE_70 +@REM default size option is 6M +@set BIOS_SIZE_OPTION=-DBIOS_SIZE_OPTION=SIZE_60 :BiosSizeDone @echo BIOS_SIZE_OPTION=%BIOS_SIZE_OPTION% -- 2.16.2.windows.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [edk2-platforms/devel-MinPlatform][PATCH v3 2/3] ClevoOpenBoardPkg/N1xxWU: Flash map update 2019-04-02 1:23 ` [edk2-platforms/devel-MinPlatform][PATCH v3 2/3] ClevoOpenBoardPkg/N1xxWU: Flash map update Michael Kubacki @ 2019-04-02 2:31 ` Desimone, Nathaniel L 2019-04-02 2:36 ` Chiu, Chasel 1 sibling, 0 replies; 11+ messages in thread From: Desimone, Nathaniel L @ 2019-04-02 2:31 UTC (permalink / raw) To: Kubacki, Michael A, edk2-devel@lists.01.org Cc: Sinha, Ankit, Chiu, Chasel, Gao, Liming, Kinney, Michael D No change from V1 or V2. Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> -----Original Message----- From: Kubacki, Michael A Sent: Monday, April 1, 2019 6:23 PM To: edk2-devel@lists.01.org Cc: Sinha, Ankit <ankit.sinha@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>; Gao, Liming <liming.gao@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com> Subject: [edk2-platforms/devel-MinPlatform][PATCH v3 2/3] ClevoOpenBoardPkg/N1xxWU: Flash map update Updates the total BIOS flash image size to 0x5E0000. This size matches the BIOS region size already configured in the SPI flash descriptor. To write an image produced from the N1xxWU board build, write the N1XXWU.fd file (~6 MB) to the beginning of the BIOS region in the SPI flash (currently 0x220000). Always back up the original SPI flash image. These offsets and sizes are subject to change over time. Cc: Ankit Sinha <ankit.sinha@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com> --- .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc | 2 +- .../N1xxWU/Include/Fdf/FlashMapInclude.fdf | 44 +++++++++++----------- .../Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat | 4 +- 3 files changed, 26 insertions(+), 24 deletions(-) diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc index 81487ed58d..2116c48fc0 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc @@ -55,7 +55,7 @@ # # Default value for OpenBoardPkg.fdf use # - DEFINE BIOS_SIZE_OPTION = SIZE_70 + DEFINE BIOS_SIZE_OPTION = SIZE_60 ################################################################################ # diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude.fdf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude.fdf index a727eb3b83..423c6b18f5 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude.fdf +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclud +++ e.fdf @@ -14,39 +14,41 @@ ## #=================================================================================# -# 8 M BIOS - for FSP wrapper +# 6 M BIOS - for FSP wrapper #=================================================================================# -DEFINE FLASH_BASE = 0xFF800000 # -DEFINE FLASH_SIZE = 0x00800000 # +DEFINE FLASH_BASE = 0xFFA20000 # +DEFINE FLASH_SIZE = 0x005E0000 # DEFINE FLASH_BLOCK_SIZE = 0x00010000 # -DEFINE FLASH_NUM_BLOCKS = 0x00000080 # +DEFINE FLASH_NUM_BLOCKS = 0x0000005E # #=================================================================================# -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = 0x00000000 # Flash addr (0xFF800000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = 0x00000000 # Flash addr (0xFFA20000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize = 0x00040000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = 0x00000000 # Flash addr (0xFF800000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = 0x00000000 # Flash addr (0xFFA20000) SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0x0001E000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = 0x0001E000 # Flash addr (0xFF81E000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = +0x0001E000 # Flash addr (0xFFA3E000) SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = 0x00002000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = 0x00020000 # Flash addr (0xFF820000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = 0x00020000 # Flash addr (0xFFA40000) SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = 0x00020000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00040000 # Flash addr (0xFF840000) +SET gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset = 0x00040000 # Flash addr (0xFFA60000) +SET gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize = 0x00010000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00050000 # Flash addr (0xFFA70000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = 0x00060000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = 0x000A0000 # Flash addr (0xFF8A0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = 0x000B0000 # Flash addr (0xFFAD0000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00070000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = 0x00110000 # Flash addr (0xFF910000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = 0x00120000 # Flash addr (0xFFB40000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00090000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = 0x001A0000 # Flash addr (0xFF9A0000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x001E0000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = 0x00380000 # Flash addr (0xFFB80000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00180000 # -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = 0x00500000 # Flash addr (0xFFD00000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = 0x001B0000 # Flash addr (0xFFBD0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x00140000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = 0x002F0000 # Flash addr (0xFFD10000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x000B0000 # +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = 0x003A0000 # Flash addr (0xFFDC0000) SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = 0x000A0000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = 0x005A0000 # Flash addr (0xFFDA0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = 0x00440000 # Flash addr (0xFFE60000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = 0x00060000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = 0x00600000 # Flash addr (0xFFE00000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = 0x004A0000 # Flash addr (0xFFEC0000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize = 0x000BC000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = 0x006BC000 # Flash addr (0xFFEBC000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = 0x0055C000 # Flash addr (0xFFF7C000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize = 0x00004000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = 0x006C0000 # Flash addr (0xFFEC0000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = 0x00140000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = 0x00560000 # Flash addr (0xFFF80000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = 0x00080000 # diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat index c09d2d5b16..c3360403f1 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat @@ -202,8 +202,8 @@ cl @set BIOS_SIZE_OPTION= -@REM default size option is 7M -@set BIOS_SIZE_OPTION=-DBIOS_SIZE_OPTION=SIZE_70 +@REM default size option is 6M +@set BIOS_SIZE_OPTION=-DBIOS_SIZE_OPTION=SIZE_60 :BiosSizeDone @echo BIOS_SIZE_OPTION=%BIOS_SIZE_OPTION% -- 2.16.2.windows.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [edk2-platforms/devel-MinPlatform][PATCH v3 2/3] ClevoOpenBoardPkg/N1xxWU: Flash map update 2019-04-02 1:23 ` [edk2-platforms/devel-MinPlatform][PATCH v3 2/3] ClevoOpenBoardPkg/N1xxWU: Flash map update Michael Kubacki 2019-04-02 2:31 ` Desimone, Nathaniel L @ 2019-04-02 2:36 ` Chiu, Chasel 1 sibling, 0 replies; 11+ messages in thread From: Chiu, Chasel @ 2019-04-02 2:36 UTC (permalink / raw) To: Kubacki, Michael A, edk2-devel@lists.01.org Cc: Sinha, Ankit, Desimone, Nathaniel L, Gao, Liming, Kinney, Michael D Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> > -----Original Message----- > From: Kubacki, Michael A > Sent: Tuesday, April 2, 2019 9:23 AM > To: edk2-devel@lists.01.org > Cc: Sinha, Ankit <ankit.sinha@intel.com>; Desimone, Nathaniel L > <nathaniel.l.desimone@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>; Gao, > Liming <liming.gao@intel.com>; Kinney, Michael D > <michael.d.kinney@intel.com> > Subject: [edk2-platforms/devel-MinPlatform][PATCH v3 2/3] > ClevoOpenBoardPkg/N1xxWU: Flash map update > > Updates the total BIOS flash image size to 0x5E0000. This size matches the BIOS > region size already configured in the SPI flash descriptor. > > To write an image produced from the N1xxWU board build, write the N1XXWU.fd > file (~6 MB) to the beginning of the BIOS region in the SPI flash (currently > 0x220000). > > Always back up the original SPI flash image. These offsets and sizes are subject to > change over time. > > Cc: Ankit Sinha <ankit.sinha@intel.com> > Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> > Cc: Chasel Chiu <chasel.chiu@intel.com> > Cc: Liming Gao <liming.gao@intel.com> > Cc: Michael D Kinney <michael.d.kinney@intel.com> > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com> > --- > .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc | 2 +- > .../N1xxWU/Include/Fdf/FlashMapInclude.fdf | 44 > +++++++++++----------- > .../Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat | 4 +- > 3 files changed, 26 insertions(+), 24 deletions(-) > > diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc > b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc > index 81487ed58d..2116c48fc0 100644 > --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc > +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc > @@ -55,7 +55,7 @@ > # > # Default value for OpenBoardPkg.fdf use > # > - DEFINE BIOS_SIZE_OPTION = SIZE_70 > + DEFINE BIOS_SIZE_OPTION = SIZE_60 > > > ################################################################ > ################ > # > diff --git > a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude. > fdf > b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude. > fdf > index a727eb3b83..423c6b18f5 100644 > --- > a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude. > fdf > +++ > b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclud > +++ e.fdf > @@ -14,39 +14,41 @@ > ## > > > #=============================================================== > ==================# > -# 8 M BIOS - for FSP wrapper > +# 6 M BIOS - for FSP wrapper > > #=============================================================== > ==================# > -DEFINE FLASH_BASE = 0xFF800000 # > -DEFINE FLASH_SIZE = 0x00800000 # > +DEFINE FLASH_BASE = 0xFFA20000 # > +DEFINE FLASH_SIZE = 0x005E0000 # > DEFINE FLASH_BLOCK_SIZE = 0x00010000 > # > -DEFINE FLASH_NUM_BLOCKS = > 0x00000080 # > +DEFINE FLASH_NUM_BLOCKS = > 0x0000005E # > > #=============================================================== > ==================# > > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = > 0x00000000 # Flash addr (0xFF800000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = > 0x00000000 # Flash addr (0xFFA20000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize = > 0x00040000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = > 0x00000000 # Flash addr (0xFF800000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = > 0x00000000 # Flash addr (0xFFA20000) > SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = > 0x0001E000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = > 0x0001E000 # Flash addr (0xFF81E000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = > +0x0001E000 # Flash addr (0xFFA3E000) > SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize > = 0x00002000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = > 0x00020000 # Flash addr (0xFF820000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = > 0x00020000 # Flash addr (0xFFA40000) > SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = > 0x00020000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = > 0x00040000 # Flash addr (0xFF840000) > +SET gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset = > 0x00040000 # Flash addr (0xFFA60000) > +SET gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize = > 0x00010000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = > 0x00050000 # Flash addr (0xFFA70000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = > 0x00060000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = > 0x000A0000 # Flash addr (0xFF8A0000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = > 0x000B0000 # Flash addr (0xFFAD0000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = > 0x00070000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = > 0x00110000 # Flash addr (0xFF910000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = > 0x00120000 # Flash addr (0xFFB40000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = > 0x00090000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = > 0x001A0000 # Flash addr (0xFF9A0000) > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = > 0x001E0000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = > 0x00380000 # Flash addr (0xFFB80000) > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = > 0x00180000 # > -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = > 0x00500000 # Flash addr (0xFFD00000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = > 0x001B0000 # Flash addr (0xFFBD0000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = > 0x00140000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = > 0x002F0000 # Flash addr (0xFFD10000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = > 0x000B0000 # > +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = > 0x003A0000 # Flash addr (0xFFDC0000) > SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = > 0x000A0000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = > 0x005A0000 # Flash addr (0xFFDA0000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = > 0x00440000 # Flash addr (0xFFE60000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = > 0x00060000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = > 0x00600000 # Flash addr (0xFFE00000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = > 0x004A0000 # Flash addr (0xFFEC0000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize = > 0x000BC000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = > 0x006BC000 # Flash addr (0xFFEBC000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = > 0x0055C000 # Flash addr (0xFFF7C000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize = > 0x00004000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = > 0x006C0000 # Flash addr (0xFFEC0000) > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = > 0x00140000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = > 0x00560000 # Flash addr (0xFFF80000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = > 0x00080000 # > diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat > b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat > index c09d2d5b16..c3360403f1 100644 > --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat > +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat > @@ -202,8 +202,8 @@ cl > > @set BIOS_SIZE_OPTION= > > -@REM default size option is 7M > -@set BIOS_SIZE_OPTION=-DBIOS_SIZE_OPTION=SIZE_70 > +@REM default size option is 6M > +@set BIOS_SIZE_OPTION=-DBIOS_SIZE_OPTION=SIZE_60 > > :BiosSizeDone > @echo BIOS_SIZE_OPTION=%BIOS_SIZE_OPTION% > -- > 2.16.2.windows.1 ^ permalink raw reply [flat|nested] 11+ messages in thread
* [edk2-platforms/devel-MinPlatform][PATCH v3 3/3] ClevoOpenBoardPkg/N1xxWU: Write PEI debug messages to SPI flash 2019-04-02 1:23 [edk2-platforms/devel-MinPlatform][PATCH v3 0/3] Enable SPI flash debug messages Michael Kubacki 2019-04-02 1:23 ` [edk2-platforms/devel-MinPlatform][PATCH v3 1/3] KabylakeSiliconPkg: Add SPI write support in PEI Michael Kubacki 2019-04-02 1:23 ` [edk2-platforms/devel-MinPlatform][PATCH v3 2/3] ClevoOpenBoardPkg/N1xxWU: Flash map update Michael Kubacki @ 2019-04-02 1:23 ` Michael Kubacki 2019-04-02 2:31 ` Desimone, Nathaniel L 2019-04-02 2:35 ` Chiu, Chasel 2 siblings, 2 replies; 11+ messages in thread From: Michael Kubacki @ 2019-04-02 1:23 UTC (permalink / raw) To: edk2-devel Cc: Ankit Sinha, Nate DeSimone, Chasel Chiu, Liming Gao, Michael D Kinney Adds a new SerialPortLib instance to the ClevoOpenBoardPkg to support writing debug messages to a dedicated area on SPI flash. This is to enable closed chassis debug support on the system. DXE and later phases after memory initialization are expected to use USB debug. Cc: Ankit Sinha <ankit.sinha@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com> --- Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec | 5 + .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc | 20 +- .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf | 4 + .../PeiSerialPortLibSpiFlash.inf | 56 ++++ .../PeiSerialPortLibSpiFlash.c | 326 +++++++++++++++++++++ 5 files changed, 407 insertions(+), 4 deletions(-) create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.inf create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.c diff --git a/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec b/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec index 87bbfb2240..aa457e64db 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec +++ b/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec @@ -30,6 +30,7 @@ Features\Tbt\Include [Guids] gBoardModuleTokenSpaceGuid = {0x72d1fff7, 0xa42a, 0x4219, {0xb9, 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4, 0x2a}} gTianoLogoGuid = {0x7BB28B99, 0x61BB, 0x11D5, {0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}} +gSpiFlashDebugHobGuid = {0xcaaaf418, 0x38a5, 0x4d49, {0xbe, 0x74, 0xe6, 0x06, 0xe4, 0x02, 0x6d, 0x25}} gTbtInfoHobGuid = {0x74a81eaa, 0x033c, 0x4783, {0xbe, 0x2b, 0x84, 0x85, 0x74, 0xa6, 0x97, 0xb7}} gPlatformModuleTokenSpaceGuid = {0x69d13bf0, 0xaf91, 0x4d96, {0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}} @@ -64,6 +65,10 @@ gBoardModuleTokenSpaceGuid.PcdSwSmiDTbtEnumerate|0xF7|UINT8|0x000000110 gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition|0x01|UINT8|0x90000015 +gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageBase|0x00000000|UINT32|0x90000030 +gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize|0x00000000|UINT32|0x90000031 +gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset|0x00000000|UINT32|0x90000032 + [PcdsDynamic] # Board GPIO Table diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc index 2116c48fc0..c43a30de34 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc @@ -116,10 +116,18 @@ # !include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc +[LibraryClasses.IA32.SEC] + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SecTestPointCheckLib.inf + SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLibNull/SecBoardInitLibNull.inf + [LibraryClasses.IA32] # # PEI phase common # + SerialPortLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.inf + DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf !if $(TARGET) == DEBUG TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf @@ -138,10 +146,6 @@ # !include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc -[LibraryClasses.IA32.SEC] - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SecTestPointCheckLib.inf - SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLibNull/SecBoardInitLibNull.inf - [LibraryClasses.X64] # # DXE phase common @@ -185,6 +189,14 @@ # !include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc + # + # Core + # + MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf { + <LibraryClasses> + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + } + # # FSP wrapper SEC Core # diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf index 95c1758ff3..7f3e965c75 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf @@ -136,6 +136,10 @@ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTo gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize #NV_FTW_SPARE +gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset|gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize +gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageBase|gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize +#DEBUG_MESSAGE_AREA + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize FV = FvAdvanced diff --git a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.inf b/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.inf new file mode 100644 index 0000000000..c22201e033 --- /dev/null +++ b/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.inf @@ -0,0 +1,56 @@ +### @file +# Component description file for Serial I/O Port library to write to SPI flash. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiSerialPortLibFlash + FILE_GUID = 35A3BA89-04BE-409C-A3CA-DEF6B510F80F + VERSION_STRING = 1.1 + MODULE_TYPE = PEIM + LIBRARY_CLASS = SerialPortLib|PEIM PEI_CORE +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF +# + +[LibraryClasses] + BaseLib + BaseMemoryLib + HobLib + PcdLib + PeiServicesLib + SpiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + KabylakeSiliconPkg/SiPkg.dec + ClevoOpenBoardPkg/OpenBoardPkg.dec + +[Sources] + PeiSerialPortLibSpiFlash.c + +[Ppis] + gPchSpiPpiGuid + +[Guids] + gSpiFlashDebugHobGuid + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageBase ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize ## CONSUMES diff --git a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.c b/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.c new file mode 100644 index 0000000000..e36ff8bff8 --- /dev/null +++ b/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.c @@ -0,0 +1,326 @@ +/** @file + Serial I/O Port library implementation for output to SPI flash + +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Base.h> +#include <Ppi/Spi.h> +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/HobLib.h> +#include <Library/PcdLib.h> +#include <Library/PeiServicesLib.h> +#include <Library/SerialPortLib.h> +#include <Library/SpiLib.h> + +typedef struct { + PCH_SPI_PPI *PchSpiPpi; + UINT32 CurrentWriteOffset; +} SPI_FLASH_DEBUG_CONTEXT; + +/** + Update reference to the most recent PCH SPI PPI installed + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation + @param NotifyDescriptor Address of the notification descriptor data structure. + @param Ppi Address of the PPI that was installed. + + @retval EFI_SUCCESS Successfully update the PCH SPI PPI reference + @retval EFI_NOT_FOUND An error occurred locating a required interface + @retval EFI_NOT_SUPPORTED + +**/ +EFI_STATUS +EFIAPI +SpiPpiNotifyCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + PCH_SPI_PPI *PchSpiPpi; + SPI_FLASH_DEBUG_CONTEXT *Context; + + GuidHob = GetFirstGuidHob (&gSpiFlashDebugHobGuid); + if (GuidHob == NULL) { + return EFI_NOT_FOUND; + } + Context = GET_GUID_HOB_DATA (GuidHob); + + Status = PeiServicesLocatePpi ( + &gPchSpiPpiGuid, + 0, + NULL, + (VOID **) &PchSpiPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Context->PchSpiPpi = PchSpiPpi; + + return EFI_SUCCESS; +} + +EFI_PEI_NOTIFY_DESCRIPTOR mSpiPpiNotifyList[] = { + { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gPchSpiPpiGuid, + SpiPpiNotifyCallback + } +}; + +/** + Common function to write trace data to a chosen debug interface like + UART Serial device, USB Serial device or Trace Hub device + + @param Buffer Point of data buffer which need to be writed. + @param NumberOfBytes Number of output bytes which are cached in Buffer. + +**/ +UINTN +EFIAPI +SerialPortWrite ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + SPI_FLASH_DEBUG_CONTEXT *Context; + UINT32 BytesWritten; + UINT32 SourceBufferOffset; + UINT32 NvMessageAreaSize; + UINT32 LinearOffset; + + BytesWritten = NumberOfBytes; + SourceBufferOffset = 0; + + NvMessageAreaSize = (UINT32) FixedPcdGet32 (PcdFlashNvDebugMessageSize); + + if (NumberOfBytes == 0 || NvMessageAreaSize == 0) { + return 0; + } + GuidHob = GetFirstGuidHob (&gSpiFlashDebugHobGuid); + if (GuidHob == NULL) { + return 0; + } + Context = GET_GUID_HOB_DATA (GuidHob); + if (Context == NULL || Context->PchSpiPpi == NULL || Context->CurrentWriteOffset >= NvMessageAreaSize) { + return 0; + } + + if ((Context->CurrentWriteOffset + NumberOfBytes) / NvMessageAreaSize > 0) { + LinearOffset = (UINT32) (FixedPcdGet32 (PcdFlashNvDebugMessageBase) - FixedPcdGet32 (PcdFlashAreaBaseAddress)); + Status = Context->PchSpiPpi->FlashErase ( + Context->PchSpiPpi, + FlashRegionBios, + LinearOffset, + NvMessageAreaSize + ); + if (!EFI_ERROR (Status)) { + Context->CurrentWriteOffset = 0; + } else { + return 0; + } + } + + if (NumberOfBytes > NvMessageAreaSize) { + BytesWritten = NvMessageAreaSize; + SourceBufferOffset = NumberOfBytes - NvMessageAreaSize; + } + + LinearOffset = (FixedPcdGet32 (PcdFlashNvDebugMessageBase) + Context->CurrentWriteOffset) - FixedPcdGet32 (PcdFlashAreaBaseAddress); + + Status = Context->PchSpiPpi->FlashWrite ( + Context->PchSpiPpi, + FlashRegionBios, + LinearOffset, + BytesWritten, + (UINT8 *) &Buffer[SourceBufferOffset] + ); + if (!EFI_ERROR (Status)) { + Context->CurrentWriteOffset += BytesWritten; + return BytesWritten; + } + + return 0; +} + +/** + Common function to Read data from UART serial device, USB serial device and save the datas in buffer. + + @param Buffer Point of data buffer which need to be writed. + @param NumberOfBytes Number of output bytes which are cached in Buffer. + + @retval 0 Read data failed, no data is to be read. + @retval >0 Actual number of bytes read from debug device. + +**/ +UINTN +EFIAPI +SerialPortRead ( + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes +) +{ + return 0; +} + +/** + Polls a serial device to see if there is any data waiting to be read. + + Polls a serial device to see if there is any data waiting to be read. + If there is data waiting to be read from the serial device, then TRUE is returned. + If there is no data waiting to be read from the serial device, then FALSE is returned. + + @retval TRUE Data is waiting to be read from the serial device. + @retval FALSE There is no data waiting to be read from the serial device. + +**/ +BOOLEAN +EFIAPI +SerialPortPoll ( + VOID + ) +{ + return FALSE; +} + +/** + Sets the control bits on a serial device. + + @param Control Sets the bits of Control that are settable. + + @retval RETURN_SUCCESS The new control bits were set on the serial device. + @retval RETURN_UNSUPPORTED The serial device does not support this operation. + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetControl ( + IN UINT32 Control + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Retrieve the status of the control bits on a serial device. + + @param Control A pointer to return the current control signals from the serial device. + + @retval RETURN_SUCCESS The control bits were read from the serial device. + @retval RETURN_UNSUPPORTED The serial device does not support this operation. + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortGetControl ( + OUT UINT32 *Control + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Sets the baud rate, receive FIFO depth, transmit/receice time out, parity, + data bits, and stop bits on a serial device. + + @param BaudRate The requested baud rate. A BaudRate value of 0 will use the + device's default interface speed. + On output, the value actually set. + @param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the + serial interface. A ReceiveFifoDepth value of 0 will use + the device's default FIFO depth. + On output, the value actually set. + @param Timeout The requested time out for a single character in microseconds. + This timeout applies to both the transmit and receive side of the + interface. A Timeout value of 0 will use the device's default time + out value. + On output, the value actually set. + @param Parity The type of parity to use on this serial device. A Parity value of + DefaultParity will use the device's default parity value. + On output, the value actually set. + @param DataBits The number of data bits to use on the serial device. A DataBits + vaule of 0 will use the device's default data bit setting. + On output, the value actually set. + @param StopBits The number of stop bits to use on this serial device. A StopBits + value of DefaultStopBits will use the device's default number of + stop bits. + On output, the value actually set. + + @retval RETURN_SUCCESS The new attributes were set on the serial device. + @retval RETURN_UNSUPPORTED The serial device does not support this operation. + @retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value. + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetAttributes ( + IN OUT UINT64 *BaudRate, + IN OUT UINT32 *ReceiveFifoDepth, + IN OUT UINT32 *Timeout, + IN OUT EFI_PARITY_TYPE *Parity, + IN OUT UINT8 *DataBits, + IN OUT EFI_STOP_BITS_TYPE *StopBits + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Initialize the serial device hardware. + + If no initialization is required, then return RETURN_SUCCESS. + If the serial device was successfully initialized, then return RETURN_SUCCESS. + If the serial device could not be initialized, then return RETURN_DEVICE_ERROR. + + @retval RETURN_SUCCESS The serial device was initialized. + @retval RETURN_DEVICE_ERROR The serial device could not be initialized. + +**/ +RETURN_STATUS +EFIAPI +SerialPortInitialize ( + VOID + ) +{ + EFI_STATUS Status; + SPI_FLASH_DEBUG_CONTEXT *Context; + + Context = (SPI_FLASH_DEBUG_CONTEXT *) BuildGuidHob (&gSpiFlashDebugHobGuid, sizeof (SPI_FLASH_DEBUG_CONTEXT)); + if (Context == NULL) { + return EFI_DEVICE_ERROR; + } + ZeroMem ((VOID *) Context, sizeof (SPI_FLASH_DEBUG_CONTEXT)); + + Status = PeiServicesNotifyPpi (&mSpiPpiNotifyList[0]); + if (EFI_ERROR (Status)) { + return EFI_DEVICE_ERROR; + } + + // + // Perform silicon specific initialization required to enable write to SPI flash. + // + Status = SpiServiceInit (); + if (EFI_ERROR (Status)) { + Status = EFI_DEVICE_ERROR; + } + + return Status; +} -- 2.16.2.windows.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [edk2-platforms/devel-MinPlatform][PATCH v3 3/3] ClevoOpenBoardPkg/N1xxWU: Write PEI debug messages to SPI flash 2019-04-02 1:23 ` [edk2-platforms/devel-MinPlatform][PATCH v3 3/3] ClevoOpenBoardPkg/N1xxWU: Write PEI debug messages to SPI flash Michael Kubacki @ 2019-04-02 2:31 ` Desimone, Nathaniel L 2019-04-02 2:35 ` Chiu, Chasel 1 sibling, 0 replies; 11+ messages in thread From: Desimone, Nathaniel L @ 2019-04-02 2:31 UTC (permalink / raw) To: Kubacki, Michael A, edk2-devel@lists.01.org Cc: Sinha, Ankit, Chiu, Chasel, Gao, Liming, Kinney, Michael D No change from V1 or V2. Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> -----Original Message----- From: Kubacki, Michael A Sent: Monday, April 1, 2019 6:23 PM To: edk2-devel@lists.01.org Cc: Sinha, Ankit <ankit.sinha@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>; Gao, Liming <liming.gao@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com> Subject: [edk2-platforms/devel-MinPlatform][PATCH v3 3/3] ClevoOpenBoardPkg/N1xxWU: Write PEI debug messages to SPI flash Adds a new SerialPortLib instance to the ClevoOpenBoardPkg to support writing debug messages to a dedicated area on SPI flash. This is to enable closed chassis debug support on the system. DXE and later phases after memory initialization are expected to use USB debug. Cc: Ankit Sinha <ankit.sinha@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com> --- Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec | 5 + .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc | 20 +- .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf | 4 + .../PeiSerialPortLibSpiFlash.inf | 56 ++++ .../PeiSerialPortLibSpiFlash.c | 326 +++++++++++++++++++++ 5 files changed, 407 insertions(+), 4 deletions(-) create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.inf create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.c diff --git a/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec b/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec index 87bbfb2240..aa457e64db 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec +++ b/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec @@ -30,6 +30,7 @@ Features\Tbt\Include [Guids] gBoardModuleTokenSpaceGuid = {0x72d1fff7, 0xa42a, 0x4219, {0xb9, 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4, 0x2a}} gTianoLogoGuid = {0x7BB28B99, 0x61BB, 0x11D5, {0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}} +gSpiFlashDebugHobGuid = {0xcaaaf418, 0x38a5, 0x4d49, {0xbe, 0x74, 0xe6, 0x06, 0xe4, 0x02, 0x6d, 0x25}} gTbtInfoHobGuid = {0x74a81eaa, 0x033c, 0x4783, {0xbe, 0x2b, 0x84, 0x85, 0x74, 0xa6, 0x97, 0xb7}} gPlatformModuleTokenSpaceGuid = {0x69d13bf0, 0xaf91, 0x4d96, {0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}} @@ -64,6 +65,10 @@ gBoardModuleTokenSpaceGuid.PcdSwSmiDTbtEnumerate|0xF7|UINT8|0x000000110 gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition|0x01|UINT8|0x90000015 +gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageBase|0x00000000|UINT32 +|0x90000030 +gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize|0x00000000|UINT32 +|0x90000031 +gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset|0x00000000|UINT +32|0x90000032 + [PcdsDynamic] # Board GPIO Table diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc index 2116c48fc0..c43a30de34 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc @@ -116,10 +116,18 @@ # !include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc +[LibraryClasses.IA32.SEC] + +SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNul +l.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + +TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Se +cTestPointCheckLib.inf + +SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLi +bNull/SecBoardInitLibNull.inf + [LibraryClasses.IA32] # # PEI phase common # + + SerialPortLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiSerialPortLibSpiFla + sh/PeiSerialPortLibSpiFlash.inf + DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDeb + ugLibReportStatusCode.inf FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf !if $(TARGET) == DEBUG TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf @@ -138,10 +146,6 @@ # !include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc -[LibraryClasses.IA32.SEC] - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SecTestPointCheckLib.inf - SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLibNull/SecBoardInitLibNull.inf - [LibraryClasses.X64] # # DXE phase common @@ -185,6 +189,14 @@ # !include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc + # + # Core + # + MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf { + <LibraryClasses> + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + } + # # FSP wrapper SEC Core # diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf index 95c1758ff3..7f3e965c75 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf @@ -136,6 +136,10 @@ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTo gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize #NV_FTW_SPARE +gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset|gBoardModuleTok +enSpaceGuid.PcdFlashNvDebugMessageSize +gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageBase|gBoardModuleToken +SpaceGuid.PcdFlashNvDebugMessageSize +#DEBUG_MESSAGE_AREA + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize FV = FvAdvanced diff --git a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.inf b/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.inf new file mode 100644 index 0000000000..c22201e033 --- /dev/null +++ b/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/ +++ PeiSerialPortLibSpiFlash.inf @@ -0,0 +1,56 @@ +### @file +# Component description file for Serial I/O Port library to write to SPI flash. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> # # +This program and the accompanying materials are licensed and made +available under # the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at # +http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiSerialPortLibFlash + FILE_GUID = 35A3BA89-04BE-409C-A3CA-DEF6B510F80F + VERSION_STRING = 1.1 + MODULE_TYPE = PEIM + LIBRARY_CLASS = SerialPortLib|PEIM PEI_CORE +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF +# + +[LibraryClasses] + BaseLib + BaseMemoryLib + HobLib + PcdLib + PeiServicesLib + SpiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + KabylakeSiliconPkg/SiPkg.dec + ClevoOpenBoardPkg/OpenBoardPkg.dec + +[Sources] + PeiSerialPortLibSpiFlash.c + +[Ppis] + gPchSpiPpiGuid + +[Guids] + gSpiFlashDebugHobGuid + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageBase ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize ## CONSUMES diff --git a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.c b/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.c new file mode 100644 index 0000000000..e36ff8bff8 --- /dev/null +++ b/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/ +++ PeiSerialPortLibSpiFlash.c @@ -0,0 +1,326 @@ +/** @file + Serial I/O Port library implementation for output to SPI flash + +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> This +program and the accompanying materials are licensed and made available +under the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Base.h> +#include <Ppi/Spi.h> +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/HobLib.h> +#include <Library/PcdLib.h> +#include <Library/PeiServicesLib.h> +#include <Library/SerialPortLib.h> +#include <Library/SpiLib.h> + +typedef struct { + PCH_SPI_PPI *PchSpiPpi; + UINT32 CurrentWriteOffset; +} SPI_FLASH_DEBUG_CONTEXT; + +/** + Update reference to the most recent PCH SPI PPI installed + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation + @param NotifyDescriptor Address of the notification descriptor data structure. + @param Ppi Address of the PPI that was installed. + + @retval EFI_SUCCESS Successfully update the PCH SPI PPI reference + @retval EFI_NOT_FOUND An error occurred locating a required interface + @retval EFI_NOT_SUPPORTED + +**/ +EFI_STATUS +EFIAPI +SpiPpiNotifyCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + PCH_SPI_PPI *PchSpiPpi; + SPI_FLASH_DEBUG_CONTEXT *Context; + + GuidHob = GetFirstGuidHob (&gSpiFlashDebugHobGuid); if (GuidHob == + NULL) { + return EFI_NOT_FOUND; + } + Context = GET_GUID_HOB_DATA (GuidHob); + + Status = PeiServicesLocatePpi ( + &gPchSpiPpiGuid, + 0, + NULL, + (VOID **) &PchSpiPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Context->PchSpiPpi = PchSpiPpi; + + return EFI_SUCCESS; +} + +EFI_PEI_NOTIFY_DESCRIPTOR mSpiPpiNotifyList[] = { + { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gPchSpiPpiGuid, + SpiPpiNotifyCallback + } +}; + +/** + Common function to write trace data to a chosen debug interface like + UART Serial device, USB Serial device or Trace Hub device + + @param Buffer Point of data buffer which need to be writed. + @param NumberOfBytes Number of output bytes which are cached in Buffer. + +**/ +UINTN +EFIAPI +SerialPortWrite ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + SPI_FLASH_DEBUG_CONTEXT *Context; + UINT32 BytesWritten; + UINT32 SourceBufferOffset; + UINT32 NvMessageAreaSize; + UINT32 LinearOffset; + + BytesWritten = NumberOfBytes; + SourceBufferOffset = 0; + + NvMessageAreaSize = (UINT32) FixedPcdGet32 + (PcdFlashNvDebugMessageSize); + + if (NumberOfBytes == 0 || NvMessageAreaSize == 0) { + return 0; + } + GuidHob = GetFirstGuidHob (&gSpiFlashDebugHobGuid); if (GuidHob == + NULL) { + return 0; + } + Context = GET_GUID_HOB_DATA (GuidHob); if (Context == NULL || + Context->PchSpiPpi == NULL || Context->CurrentWriteOffset >= NvMessageAreaSize) { + return 0; + } + + if ((Context->CurrentWriteOffset + NumberOfBytes) / NvMessageAreaSize > 0) { + LinearOffset = (UINT32) (FixedPcdGet32 (PcdFlashNvDebugMessageBase) - FixedPcdGet32 (PcdFlashAreaBaseAddress)); + Status = Context->PchSpiPpi->FlashErase ( + Context->PchSpiPpi, + FlashRegionBios, + LinearOffset, + NvMessageAreaSize + ); + if (!EFI_ERROR (Status)) { + Context->CurrentWriteOffset = 0; + } else { + return 0; + } + } + + if (NumberOfBytes > NvMessageAreaSize) { + BytesWritten = NvMessageAreaSize; + SourceBufferOffset = NumberOfBytes - NvMessageAreaSize; } + + LinearOffset = (FixedPcdGet32 (PcdFlashNvDebugMessageBase) + + Context->CurrentWriteOffset) - FixedPcdGet32 + (PcdFlashAreaBaseAddress); + + Status = Context->PchSpiPpi->FlashWrite ( + Context->PchSpiPpi, + FlashRegionBios, + LinearOffset, + BytesWritten, + (UINT8 *) &Buffer[SourceBufferOffset] + ); + if (!EFI_ERROR (Status)) { + Context->CurrentWriteOffset += BytesWritten; + return BytesWritten; + } + + return 0; +} + +/** + Common function to Read data from UART serial device, USB serial device and save the datas in buffer. + + @param Buffer Point of data buffer which need to be writed. + @param NumberOfBytes Number of output bytes which are cached in Buffer. + + @retval 0 Read data failed, no data is to be read. + @retval >0 Actual number of bytes read from debug device. + +**/ +UINTN +EFIAPI +SerialPortRead ( + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes +) +{ + return 0; +} + +/** + Polls a serial device to see if there is any data waiting to be read. + + Polls a serial device to see if there is any data waiting to be read. + If there is data waiting to be read from the serial device, then TRUE is returned. + If there is no data waiting to be read from the serial device, then FALSE is returned. + + @retval TRUE Data is waiting to be read from the serial device. + @retval FALSE There is no data waiting to be read from the serial device. + +**/ +BOOLEAN +EFIAPI +SerialPortPoll ( + VOID + ) +{ + return FALSE; +} + +/** + Sets the control bits on a serial device. + + @param Control Sets the bits of Control that are settable. + + @retval RETURN_SUCCESS The new control bits were set on the serial device. + @retval RETURN_UNSUPPORTED The serial device does not support this operation. + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetControl ( + IN UINT32 Control + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Retrieve the status of the control bits on a serial device. + + @param Control A pointer to return the current control signals from the serial device. + + @retval RETURN_SUCCESS The control bits were read from the serial device. + @retval RETURN_UNSUPPORTED The serial device does not support this operation. + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortGetControl ( + OUT UINT32 *Control + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Sets the baud rate, receive FIFO depth, transmit/receice time out, +parity, + data bits, and stop bits on a serial device. + + @param BaudRate The requested baud rate. A BaudRate value of 0 will use the + device's default interface speed. + On output, the value actually set. + @param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the + serial interface. A ReceiveFifoDepth value of 0 will use + the device's default FIFO depth. + On output, the value actually set. + @param Timeout The requested time out for a single character in microseconds. + This timeout applies to both the transmit and receive side of the + interface. A Timeout value of 0 will use the device's default time + out value. + On output, the value actually set. + @param Parity The type of parity to use on this serial device. A Parity value of + DefaultParity will use the device's default parity value. + On output, the value actually set. + @param DataBits The number of data bits to use on the serial device. A DataBits + vaule of 0 will use the device's default data bit setting. + On output, the value actually set. + @param StopBits The number of stop bits to use on this serial device. A StopBits + value of DefaultStopBits will use the device's default number of + stop bits. + On output, the value actually set. + + @retval RETURN_SUCCESS The new attributes were set on the serial device. + @retval RETURN_UNSUPPORTED The serial device does not support this operation. + @retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value. + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetAttributes ( + IN OUT UINT64 *BaudRate, + IN OUT UINT32 *ReceiveFifoDepth, + IN OUT UINT32 *Timeout, + IN OUT EFI_PARITY_TYPE *Parity, + IN OUT UINT8 *DataBits, + IN OUT EFI_STOP_BITS_TYPE *StopBits + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Initialize the serial device hardware. + + If no initialization is required, then return RETURN_SUCCESS. + If the serial device was successfully initialized, then return RETURN_SUCCESS. + If the serial device could not be initialized, then return RETURN_DEVICE_ERROR. + + @retval RETURN_SUCCESS The serial device was initialized. + @retval RETURN_DEVICE_ERROR The serial device could not be initialized. + +**/ +RETURN_STATUS +EFIAPI +SerialPortInitialize ( + VOID + ) +{ + EFI_STATUS Status; + SPI_FLASH_DEBUG_CONTEXT *Context; + + Context = (SPI_FLASH_DEBUG_CONTEXT *) BuildGuidHob + (&gSpiFlashDebugHobGuid, sizeof (SPI_FLASH_DEBUG_CONTEXT)); if (Context == NULL) { + return EFI_DEVICE_ERROR; + } + ZeroMem ((VOID *) Context, sizeof (SPI_FLASH_DEBUG_CONTEXT)); + + Status = PeiServicesNotifyPpi (&mSpiPpiNotifyList[0]); if (EFI_ERROR + (Status)) { + return EFI_DEVICE_ERROR; + } + + // + // Perform silicon specific initialization required to enable write to SPI flash. + // + Status = SpiServiceInit (); + if (EFI_ERROR (Status)) { + Status = EFI_DEVICE_ERROR; + } + + return Status; +} -- 2.16.2.windows.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [edk2-platforms/devel-MinPlatform][PATCH v3 3/3] ClevoOpenBoardPkg/N1xxWU: Write PEI debug messages to SPI flash 2019-04-02 1:23 ` [edk2-platforms/devel-MinPlatform][PATCH v3 3/3] ClevoOpenBoardPkg/N1xxWU: Write PEI debug messages to SPI flash Michael Kubacki 2019-04-02 2:31 ` Desimone, Nathaniel L @ 2019-04-02 2:35 ` Chiu, Chasel 1 sibling, 0 replies; 11+ messages in thread From: Chiu, Chasel @ 2019-04-02 2:35 UTC (permalink / raw) To: Kubacki, Michael A, edk2-devel@lists.01.org Cc: Sinha, Ankit, Desimone, Nathaniel L, Gao, Liming, Kinney, Michael D Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> > -----Original Message----- > From: Kubacki, Michael A > Sent: Tuesday, April 2, 2019 9:23 AM > To: edk2-devel@lists.01.org > Cc: Sinha, Ankit <ankit.sinha@intel.com>; Desimone, Nathaniel L > <nathaniel.l.desimone@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>; Gao, > Liming <liming.gao@intel.com>; Kinney, Michael D > <michael.d.kinney@intel.com> > Subject: [edk2-platforms/devel-MinPlatform][PATCH v3 3/3] > ClevoOpenBoardPkg/N1xxWU: Write PEI debug messages to SPI flash > > Adds a new SerialPortLib instance to the ClevoOpenBoardPkg to support writing > debug messages to a dedicated area on SPI flash. This is to enable closed chassis > debug support on the system. > > DXE and later phases after memory initialization are expected to use USB debug. > > Cc: Ankit Sinha <ankit.sinha@intel.com> > Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> > Cc: Chasel Chiu <chasel.chiu@intel.com> > Cc: Liming Gao <liming.gao@intel.com> > Cc: Michael D Kinney <michael.d.kinney@intel.com> > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com> > --- > Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec | 5 + > .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc | 20 +- > .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf | 4 + > .../PeiSerialPortLibSpiFlash.inf | 56 ++++ > .../PeiSerialPortLibSpiFlash.c | 326 +++++++++++++++++++++ > 5 files changed, 407 insertions(+), 4 deletions(-) create mode 100644 > Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSerialP > ortLibSpiFlash.inf > create mode 100644 > Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSerialP > ortLibSpiFlash.c > > diff --git a/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec > b/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec > index 87bbfb2240..aa457e64db 100644 > --- a/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec > +++ b/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec > @@ -30,6 +30,7 @@ Features\Tbt\Include > [Guids] > gBoardModuleTokenSpaceGuid = {0x72d1fff7, 0xa42a, 0x4219, > {0xb9, 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4, 0x2a}} > gTianoLogoGuid = {0x7BB28B99, 0x61BB, 0x11D5, {0x9A, > 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}} > +gSpiFlashDebugHobGuid = {0xcaaaf418, 0x38a5, 0x4d49, {0xbe, > 0x74, 0xe6, 0x06, 0xe4, 0x02, 0x6d, 0x25}} > gTbtInfoHobGuid = {0x74a81eaa, 0x033c, 0x4783, {0xbe, > 0x2b, 0x84, 0x85, 0x74, 0xa6, 0x97, 0xb7}} > gPlatformModuleTokenSpaceGuid = {0x69d13bf0, 0xaf91, 0x4d96, > {0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}} > > @@ -64,6 +65,10 @@ > gBoardModuleTokenSpaceGuid.PcdSwSmiDTbtEnumerate|0xF7|UINT8|0x000 > 000110 > > > gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition|0x01|UINT8|0x9000 > 0015 > > +gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageBase|0x00000000 > |UINT32 > +|0x90000030 > +gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize|0x00000000| > UINT32 > +|0x90000031 > +gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset|0x0000000 > 0|UINT > +32|0x90000032 > + > [PcdsDynamic] > > # Board GPIO Table > diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc > b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc > index 2116c48fc0..c43a30de34 100644 > --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc > +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc > @@ -116,10 +116,18 @@ > # > !include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc > > +[LibraryClasses.IA32.SEC] > + > +SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNul > +l.inf > + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf > + > +TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/ > Se > +cTestPointCheckLib.inf > + > +SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLi > +bNull/SecBoardInitLibNull.inf > + > [LibraryClasses.IA32] > # > # PEI phase common > # > + > + SerialPortLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiSerialPortLibSpiFla > + sh/PeiSerialPortLibSpiFlash.inf > + > DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxe > Deb > + ugLibReportStatusCode.inf > > FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFsp > WrapperPlatformLib/PeiFspWrapperPlatformLib.inf > !if $(TARGET) == DEBUG > > TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/P > eiTestPointCheckLib.inf > @@ -138,10 +146,6 @@ > # > !include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc > > -[LibraryClasses.IA32.SEC] > - > TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/S > ecTestPointCheckLib.inf > - > SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLib > Null/SecBoardInitLibNull.inf > - > [LibraryClasses.X64] > # > # DXE phase common > @@ -185,6 +189,14 @@ > # > !include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc > > + # > + # Core > + # > + > MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf { > + <LibraryClasses> > + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf > + } > + > # > # FSP wrapper SEC Core > # > diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf > b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf > index 95c1758ff3..7f3e965c75 100644 > --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf > +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf > @@ -136,6 +136,10 @@ > gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMde > ModulePkgTo > > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMd > eModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > #NV_FTW_SPARE > > +gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset|gBoardMo > duleTok > +enSpaceGuid.PcdFlashNvDebugMessageSize > +gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageBase|gBoardMod > uleToken > +SpaceGuid.PcdFlashNvDebugMessageSize > +#DEBUG_MESSAGE_AREA > + > > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformP > kgTokenSpaceGuid.PcdFlashFvAdvancedSize > > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkg > TokenSpaceGuid.PcdFlashFvAdvancedSize > FV = FvAdvanced > diff --git > a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSeri > alPortLibSpiFlash.inf > b/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSeri > alPortLibSpiFlash.inf > new file mode 100644 > index 0000000000..c22201e033 > --- /dev/null > +++ b/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/ > +++ PeiSerialPortLibSpiFlash.inf > @@ -0,0 +1,56 @@ > +### @file > +# Component description file for Serial I/O Port library to write to SPI flash. > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> # # > +This program and the accompanying materials are licensed and made > +available under # the terms and conditions of the BSD License which > accompanies this distribution. > +# The full text of the license may be found at # > +http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER > EXPRESS OR IMPLIED. > +# > +## > + > +[Defines] > + INF_VERSION = 0x00010005 > + BASE_NAME = PeiSerialPortLibFlash > + FILE_GUID = 35A3BA89-04BE-409C-A3CA-DEF6B510F80F > + VERSION_STRING = 1.1 > + MODULE_TYPE = PEIM > + LIBRARY_CLASS = SerialPortLib|PEIM PEI_CORE > +# > +# The following information is for reference only and not required by the build > tools. > +# > +# VALID_ARCHITECTURES = IA32 X64 IPF > +# > + > +[LibraryClasses] > + BaseLib > + BaseMemoryLib > + HobLib > + PcdLib > + PeiServicesLib > + SpiLib > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MinPlatformPkg/MinPlatformPkg.dec > + KabylakeSiliconPkg/SiPkg.dec > + ClevoOpenBoardPkg/OpenBoardPkg.dec > + > +[Sources] > + PeiSerialPortLibSpiFlash.c > + > +[Ppis] > + gPchSpiPpiGuid > + > +[Guids] > + gSpiFlashDebugHobGuid > + > +[Pcd] > + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageBase ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize ## > CONSUMES > diff --git > a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSeri > alPortLibSpiFlash.c > b/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSeri > alPortLibSpiFlash.c > new file mode 100644 > index 0000000000..e36ff8bff8 > --- /dev/null > +++ b/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/ > +++ PeiSerialPortLibSpiFlash.c > @@ -0,0 +1,326 @@ > +/** @file > + Serial I/O Port library implementation for output to SPI flash > + > +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> This > +program and the accompanying materials are licensed and made available > +under the terms and conditions of the BSD License that accompanies this > distribution. > +The full text of the license may be found at > +http://opensource.org/licenses/bsd-license.php. > + > +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS > OR IMPLIED. > + > +**/ > + > +#include <Base.h> > +#include <Ppi/Spi.h> > +#include <Library/BaseLib.h> > +#include <Library/BaseMemoryLib.h> > +#include <Library/HobLib.h> > +#include <Library/PcdLib.h> > +#include <Library/PeiServicesLib.h> > +#include <Library/SerialPortLib.h> > +#include <Library/SpiLib.h> > + > +typedef struct { > + PCH_SPI_PPI *PchSpiPpi; > + UINT32 CurrentWriteOffset; > +} SPI_FLASH_DEBUG_CONTEXT; > + > +/** > + Update reference to the most recent PCH SPI PPI installed > + > + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table > published by the PEI Foundation > + @param NotifyDescriptor Address of the notification descriptor data > structure. > + @param Ppi Address of the PPI that was installed. > + > + @retval EFI_SUCCESS Successfully update the PCH SPI PPI reference > + @retval EFI_NOT_FOUND An error occurred locating a required interface > + @retval EFI_NOT_SUPPORTED > + > +**/ > +EFI_STATUS > +EFIAPI > +SpiPpiNotifyCallback ( > + IN EFI_PEI_SERVICES **PeiServices, > + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, > + IN VOID *Ppi > + ) > +{ > + EFI_STATUS Status; > + EFI_HOB_GUID_TYPE *GuidHob; > + PCH_SPI_PPI *PchSpiPpi; > + SPI_FLASH_DEBUG_CONTEXT *Context; > + > + GuidHob = GetFirstGuidHob (&gSpiFlashDebugHobGuid); if (GuidHob == > + NULL) { > + return EFI_NOT_FOUND; > + } > + Context = GET_GUID_HOB_DATA (GuidHob); > + > + Status = PeiServicesLocatePpi ( > + &gPchSpiPpiGuid, > + 0, > + NULL, > + (VOID **) &PchSpiPpi > + ); > + if (EFI_ERROR (Status)) { > + return EFI_NOT_FOUND; > + } > + > + Context->PchSpiPpi = PchSpiPpi; > + > + return EFI_SUCCESS; > +} > + > +EFI_PEI_NOTIFY_DESCRIPTOR mSpiPpiNotifyList[] = { > + { > + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | > EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), > + &gPchSpiPpiGuid, > + SpiPpiNotifyCallback > + } > +}; > + > +/** > + Common function to write trace data to a chosen debug interface like > + UART Serial device, USB Serial device or Trace Hub device > + > + @param Buffer Point of data buffer which need to be writed. > + @param NumberOfBytes Number of output bytes which are cached in > Buffer. > + > +**/ > +UINTN > +EFIAPI > +SerialPortWrite ( > + IN UINT8 *Buffer, > + IN UINTN NumberOfBytes > + ) > +{ > + EFI_STATUS Status; > + EFI_HOB_GUID_TYPE *GuidHob; > + SPI_FLASH_DEBUG_CONTEXT *Context; > + UINT32 BytesWritten; > + UINT32 SourceBufferOffset; > + UINT32 NvMessageAreaSize; > + UINT32 LinearOffset; > + > + BytesWritten = NumberOfBytes; > + SourceBufferOffset = 0; > + > + NvMessageAreaSize = (UINT32) FixedPcdGet32 > + (PcdFlashNvDebugMessageSize); > + > + if (NumberOfBytes == 0 || NvMessageAreaSize == 0) { > + return 0; > + } > + GuidHob = GetFirstGuidHob (&gSpiFlashDebugHobGuid); if (GuidHob == > + NULL) { > + return 0; > + } > + Context = GET_GUID_HOB_DATA (GuidHob); if (Context == NULL || > + Context->PchSpiPpi == NULL || Context->CurrentWriteOffset >= > NvMessageAreaSize) { > + return 0; > + } > + > + if ((Context->CurrentWriteOffset + NumberOfBytes) / NvMessageAreaSize > > 0) { > + LinearOffset = (UINT32) (FixedPcdGet32 (PcdFlashNvDebugMessageBase) - > FixedPcdGet32 (PcdFlashAreaBaseAddress)); > + Status = Context->PchSpiPpi->FlashErase ( > + Context->PchSpiPpi, > + FlashRegionBios, > + LinearOffset, > + NvMessageAreaSize > + ); > + if (!EFI_ERROR (Status)) { > + Context->CurrentWriteOffset = 0; > + } else { > + return 0; > + } > + } > + > + if (NumberOfBytes > NvMessageAreaSize) { > + BytesWritten = NvMessageAreaSize; > + SourceBufferOffset = NumberOfBytes - NvMessageAreaSize; } > + > + LinearOffset = (FixedPcdGet32 (PcdFlashNvDebugMessageBase) + > + Context->CurrentWriteOffset) - FixedPcdGet32 > + (PcdFlashAreaBaseAddress); > + > + Status = Context->PchSpiPpi->FlashWrite ( > + Context->PchSpiPpi, > + FlashRegionBios, > + LinearOffset, > + BytesWritten, > + (UINT8 *) &Buffer[SourceBufferOffset] > + ); > + if (!EFI_ERROR (Status)) { > + Context->CurrentWriteOffset += BytesWritten; > + return BytesWritten; > + } > + > + return 0; > +} > + > +/** > + Common function to Read data from UART serial device, USB serial device and > save the datas in buffer. > + > + @param Buffer Point of data buffer which need to be writed. > + @param NumberOfBytes Number of output bytes which are cached in > Buffer. > + > + @retval 0 Read data failed, no data is to be read. > + @retval >0 Actual number of bytes read from debug device. > + > +**/ > +UINTN > +EFIAPI > +SerialPortRead ( > + OUT UINT8 *Buffer, > + IN UINTN NumberOfBytes > +) > +{ > + return 0; > +} > + > +/** > + Polls a serial device to see if there is any data waiting to be read. > + > + Polls a serial device to see if there is any data waiting to be read. > + If there is data waiting to be read from the serial device, then TRUE is > returned. > + If there is no data waiting to be read from the serial device, then FALSE is > returned. > + > + @retval TRUE Data is waiting to be read from the serial device. > + @retval FALSE There is no data waiting to be read from the serial > device. > + > +**/ > +BOOLEAN > +EFIAPI > +SerialPortPoll ( > + VOID > + ) > +{ > + return FALSE; > +} > + > +/** > + Sets the control bits on a serial device. > + > + @param Control Sets the bits of Control that are settable. > + > + @retval RETURN_SUCCESS The new control bits were set on the serial > device. > + @retval RETURN_UNSUPPORTED The serial device does not support this > operation. > + @retval RETURN_DEVICE_ERROR The serial device is not functioning > correctly. > + > +**/ > +RETURN_STATUS > +EFIAPI > +SerialPortSetControl ( > + IN UINT32 Control > + ) > +{ > + return EFI_UNSUPPORTED; > +} > + > +/** > + Retrieve the status of the control bits on a serial device. > + > + @param Control A pointer to return the current control signals > from the serial device. > + > + @retval RETURN_SUCCESS The control bits were read from the serial > device. > + @retval RETURN_UNSUPPORTED The serial device does not support this > operation. > + @retval RETURN_DEVICE_ERROR The serial device is not functioning > correctly. > + > +**/ > +RETURN_STATUS > +EFIAPI > +SerialPortGetControl ( > + OUT UINT32 *Control > + ) > +{ > + return EFI_UNSUPPORTED; > +} > + > +/** > + Sets the baud rate, receive FIFO depth, transmit/receice time out, > +parity, > + data bits, and stop bits on a serial device. > + > + @param BaudRate The requested baud rate. A BaudRate value of 0 > will use the > + device's default interface speed. > + On output, the value actually set. > + @param ReveiveFifoDepth The requested depth of the FIFO on the receive > side of the > + serial interface. A ReceiveFifoDepth value of 0 will use > + the device's default FIFO depth. > + On output, the value actually set. > + @param Timeout The requested time out for a single character in > microseconds. > + This timeout applies to both the transmit and receive > side of the > + interface. A Timeout value of 0 will use the device's > default time > + out value. > + On output, the value actually set. > + @param Parity The type of parity to use on this serial device. A > Parity value of > + DefaultParity will use the device's default parity value. > + On output, the value actually set. > + @param DataBits The number of data bits to use on the serial device. > A DataBits > + vaule of 0 will use the device's default data bit setting. > + On output, the value actually set. > + @param StopBits The number of stop bits to use on this serial device. > A StopBits > + value of DefaultStopBits will use the device's default > number of > + stop bits. > + On output, the value actually set. > + > + @retval RETURN_SUCCESS The new attributes were set on the serial > device. > + @retval RETURN_UNSUPPORTED The serial device does not support > this operation. > + @retval RETURN_INVALID_PARAMETER One or more of the attributes has > an unsupported value. > + @retval RETURN_DEVICE_ERROR The serial device is not functioning > correctly. > + > +**/ > +RETURN_STATUS > +EFIAPI > +SerialPortSetAttributes ( > + IN OUT UINT64 *BaudRate, > + IN OUT UINT32 *ReceiveFifoDepth, > + IN OUT UINT32 *Timeout, > + IN OUT EFI_PARITY_TYPE *Parity, > + IN OUT UINT8 *DataBits, > + IN OUT EFI_STOP_BITS_TYPE *StopBits > + ) > +{ > + return EFI_UNSUPPORTED; > +} > + > +/** > + Initialize the serial device hardware. > + > + If no initialization is required, then return RETURN_SUCCESS. > + If the serial device was successfully initialized, then return RETURN_SUCCESS. > + If the serial device could not be initialized, then return > RETURN_DEVICE_ERROR. > + > + @retval RETURN_SUCCESS The serial device was initialized. > + @retval RETURN_DEVICE_ERROR The serial device could not be initialized. > + > +**/ > +RETURN_STATUS > +EFIAPI > +SerialPortInitialize ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + SPI_FLASH_DEBUG_CONTEXT *Context; > + > + Context = (SPI_FLASH_DEBUG_CONTEXT *) BuildGuidHob > + (&gSpiFlashDebugHobGuid, sizeof (SPI_FLASH_DEBUG_CONTEXT)); if > (Context == NULL) { > + return EFI_DEVICE_ERROR; > + } > + ZeroMem ((VOID *) Context, sizeof (SPI_FLASH_DEBUG_CONTEXT)); > + > + Status = PeiServicesNotifyPpi (&mSpiPpiNotifyList[0]); if (EFI_ERROR > + (Status)) { > + return EFI_DEVICE_ERROR; > + } > + > + // > + // Perform silicon specific initialization required to enable write to SPI flash. > + // > + Status = SpiServiceInit (); > + if (EFI_ERROR (Status)) { > + Status = EFI_DEVICE_ERROR; > + } > + > + return Status; > +} > -- > 2.16.2.windows.1 ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2019-04-02 2:48 UTC | newest] Thread overview: 11+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-04-02 1:23 [edk2-platforms/devel-MinPlatform][PATCH v3 0/3] Enable SPI flash debug messages Michael Kubacki 2019-04-02 1:23 ` [edk2-platforms/devel-MinPlatform][PATCH v3 1/3] KabylakeSiliconPkg: Add SPI write support in PEI Michael Kubacki 2019-04-02 2:28 ` Chiu, Chasel 2019-04-02 2:48 ` Kubacki, Michael A 2019-04-02 2:31 ` Desimone, Nathaniel L 2019-04-02 1:23 ` [edk2-platforms/devel-MinPlatform][PATCH v3 2/3] ClevoOpenBoardPkg/N1xxWU: Flash map update Michael Kubacki 2019-04-02 2:31 ` Desimone, Nathaniel L 2019-04-02 2:36 ` Chiu, Chasel 2019-04-02 1:23 ` [edk2-platforms/devel-MinPlatform][PATCH v3 3/3] ClevoOpenBoardPkg/N1xxWU: Write PEI debug messages to SPI flash Michael Kubacki 2019-04-02 2:31 ` Desimone, Nathaniel L 2019-04-02 2:35 ` Chiu, Chasel
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