From: "Ni, Ray" <ray.ni@intel.com>
To: devel@edk2.groups.io
Cc: Eric Dong <eric.dong@intel.com>
Subject: [PATCH v2] UefiCpuPkg/Cpuid.h: Update CPUID.7H.ECX structure for 5-level paging
Date: Mon, 8 Apr 2019 17:11:24 +0800 [thread overview]
Message-ID: <20190408091124.115416-1-ray.ni@intel.com> (raw)
Reserved6 is changed to Reserved7 because the bit width is changed.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
---
UefiCpuPkg/Include/Register/Cpuid.h | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Cpuid.h b/UefiCpuPkg/Include/Register/Cpuid.h
index e0f4f968f4..a67f2a1dff 100644
--- a/UefiCpuPkg/Include/Register/Cpuid.h
+++ b/UefiCpuPkg/Include/Register/Cpuid.h
@@ -1506,8 +1506,11 @@ typedef union {
/// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.).
///
UINT32 AVX512_VPOPCNTDQ:1;
- UINT32 Reserved6:2;
-
+ UINT32 Reserved7:1;
+ ///
+ /// [Bits 16] Supports 5-level paging if 1.
+ ///
+ UINT32 FiveLevelPage:1;
///
/// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions
/// in 64-bit mode.
--
2.21.0.windows.1
next reply other threads:[~2019-04-08 9:08 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-08 9:11 Ni, Ray [this message]
2019-04-09 0:10 ` [PATCH v2] UefiCpuPkg/Cpuid.h: Update CPUID.7H.ECX structure for 5-level paging Dong, Eric
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