From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: ray.ni@intel.com) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by groups.io with SMTP; Mon, 08 Apr 2019 02:08:14 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Apr 2019 02:08:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,324,1549958400"; d="scan'208";a="314019717" Received: from ray-dev.ccr.corp.intel.com ([10.239.9.36]) by orsmga005.jf.intel.com with ESMTP; 08 Apr 2019 02:08:12 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong Subject: [PATCH v2] UefiCpuPkg/Cpuid.h: Update CPUID.7H.ECX structure for 5-level paging Date: Mon, 8 Apr 2019 17:11:24 +0800 Message-Id: <20190408091124.115416-1-ray.ni@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Reserved6 is changed to Reserved7 because the bit width is changed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ray Ni Cc: Eric Dong --- UefiCpuPkg/Include/Register/Cpuid.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Include/Register/Cpuid.h b/UefiCpuPkg/Include/Register/Cpuid.h index e0f4f968f4..a67f2a1dff 100644 --- a/UefiCpuPkg/Include/Register/Cpuid.h +++ b/UefiCpuPkg/Include/Register/Cpuid.h @@ -1506,8 +1506,11 @@ typedef union { /// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.). /// UINT32 AVX512_VPOPCNTDQ:1; - UINT32 Reserved6:2; - + UINT32 Reserved7:1; + /// + /// [Bits 16] Supports 5-level paging if 1. + /// + UINT32 FiveLevelPage:1; /// /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions /// in 64-bit mode. -- 2.21.0.windows.1