From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=KZbUvrD+; spf=pass (domain: linaro.org, ip: 209.85.221.42, mailfrom: ard.biesheuvel@linaro.org) Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) by groups.io with SMTP; Thu, 25 Apr 2019 03:51:35 -0700 Received: by mail-wr1-f42.google.com with SMTP id g3so29617377wrx.9 for ; Thu, 25 Apr 2019 03:51:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=XRdEGIHvBdyPjk5tyJFonrsinuo/YS1/dbfxeITOlBM=; b=KZbUvrD+um+DeHeXBuaNRGNAGo79d0WRlPPMKEMq7gjvCpOgFI+zS25PFagKmDGqG9 C8BbzasBslDoWO0N785Geik9OiEV2w8uEuACWp4VSNaqV894X1rgesL42qnm2HlFGCpp +ZxFCGwJRu4y01ZiDbyFvzs2uboZy5YDflYwbxyKIyeB2a5wS4tY/+JTAy7HKEgTdKox bFEtpoKUVflQ+st768qfcoqhAUgwtVclh/LZdqIswYB7+sa2JziSCs79YRwO5Qn3Bgx2 3izCac0uiVgIm0xgPZWbDm0QF5w/7DkzNcLaNNjaHtQIbJrIhE2TwCHr3PpXhlVRNlmt Ms/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=XRdEGIHvBdyPjk5tyJFonrsinuo/YS1/dbfxeITOlBM=; b=SVQo+vhyxT9WUnnyiL+AjgUgunYPM2UUQRb391Psxk7k7IGLEJxvKYYj/neqTB0SIH wWjdnO76q32FRM4uHEj59ya/D5H56Z6ci0UWcKpieIoE9FJFDS01hOm81E82KKGmXGGZ LKOFZo3AyzKcUWsFHAM0K+dlZ/IhakjSaUGoQbrjP7f9aRYriLb8m0jTgqrgTDPDnnoe DpqVyXrMWjuoBwnRH2NZWWtZp7ECtxumHhfrBehFP0CY44Qi6V37jaSlej3TzRsO0M+T GS96WvnZMGkwF2k7I2N3N25VgKcucQyYnIZBswGEOig+yccPDInqjTmniplUqHGQqwaZ gMFA== X-Gm-Message-State: APjAAAVogLmvOk7zWL36oTijMjdnrF/MrNligJPgH3euF4GhtuWmbA+l Vi/9gozMg0Vmb1PVuT7g0wrK4px9TV65/w== X-Google-Smtp-Source: APXvYqyunjQXecMPlK6HaKmsUBGy4R/4z7PuB4GBHNQ/hjZRixw6Ay8aMGhYUzHu5jFeM/8HBmFDuA== X-Received: by 2002:a5d:670b:: with SMTP id o11mr24411612wru.125.1556189493730; Thu, 25 Apr 2019 03:51:33 -0700 (PDT) Return-Path: Received: from sudo.home ([2a01:cb1d:112:6f00:95f:9014:5be9:5288]) by smtp.gmail.com with ESMTPSA id n17sm18449197wrw.77.2019.04.25.03.51.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 03:51:32 -0700 (PDT) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, graeme.gregory@linaro.org, masahisa.kojima@linaro.org, Ard Biesheuvel Subject: [PATCH edk2-platforms] Silicon/SynQuacer: add ACPI description of GPIO controller and power button Date: Thu, 25 Apr 2019 12:51:27 +0200 Message-Id: <20190425105127.26429-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add ACPI descriptions of the GPIO and external interrupt (EXIU) controllers as well as the power button. Note that on rev 0.3 boards, the power button appears to reset the system (this was not the case on rev 0.1 boards), so it is included for reference primarily. The same GPIO event mechanism will be used in the future for reporting hardware errors to the OS. Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 52 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 4 ++ 2 files changed, 56 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl index aab4fbf0e6b4..acb77739ded6 100644 --- a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl @@ -201,5 +201,57 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", "SYNQUACR", } }) } + + Device (GPIO) { + Name (_HID, "SCX0007") + Name (_UID, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, SYNQUACER_GPIO_BASE, SYNQUACER_GPIO_SIZE) + Memory32Fixed (ReadWrite, SYNQUACER_EXIU_BASE, SYNQUACER_EXIU_SIZE) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 144 } + }) + Name (_DSD, + Package () // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () { "socionext,spi-base", 112 }, + Package () + { + "gpio-line-names", + Package () + { + "DSW3-PIN1", "DSW3-PIN2", "DSW3-PIN3", "DSW3-PIN4", + "DSW3-PIN5", "DSW3-PIN6", "DSW3-PIN7", "DSW3-PIN8", + "PSIN#", "PWROFF#", "GPIO-A", "GPIO-B", + "GPIO-C", "GPIO-D", "PCIE1EXTINT", "PCIE0EXTINT", + "PHY2-INT#", "PHY1-INT#", "GPIO-E", "GPIO-F", + "GPIO-G", "GPIO-H", "GPIO-I", "GPIO-J", + "GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD27", + "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31" + } + } + } + } + ) + Name (_AEI, ResourceTemplate () { + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullDefault,, "\\_SB.GPIO") + { + 0x08 + } + }) + Method (_E08, 0x0, NotSerialized) { + Notify (\_SB.PWRB, 0x80) + } + } + + Device (PWRB) { + Name (_HID, "PNP0C0C") + Name (_UID, Zero) + Method (_STA, 0x0, NotSerialized) { + Return (0xF) + } + } } // Scope (_SB) } diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h index b0fcc306c1ae..cff981c4f8ae 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h @@ -42,6 +42,10 @@ #define SYNQUACER_GPIO_BASE 0x51000000 #define SYNQUACER_GPIO_SIZE SIZE_4KB +// EXIU interrupt controller +#define SYNQUACER_EXIU_BASE 0x510c0000 +#define SYNQUACER_EXIU_SIZE 0x20 + // I2C0 block #define SYNQUACER_I2C0_BASE 0x51200000 #define SYNQUACER_I2C0_SIZE SIZE_4KB -- 2.20.1