From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: michael.d.kinney@intel.com) Received: from mga06.intel.com (mga06.intel.com []) by groups.io with SMTP; Thu, 25 Apr 2019 10:53:40 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Apr 2019 10:53:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,394,1549958400"; d="scan'208";a="134369330" Received: from unknown (HELO mdkinney-MOBL2.amr.corp.intel.com) ([10.241.111.154]) by orsmga007.jf.intel.com with ESMTP; 25 Apr 2019 10:53:38 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Liming Gao Subject: [Patch 1/4] MdePkg/BaseLib: Verify SSE2 support in IA32 AsmLfence() Date: Thu, 25 Apr 2019 10:53:31 -0700 Message-Id: <20190425175334.5944-2-michael.d.kinney@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20190425175334.5944-1-michael.d.kinney@intel.com> References: <20190425175334.5944-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Use CPUID in IA32 implementation of AsmLfence() to verify that SSE2 is supported before using the LFENCE instruction. Cc: Liming Gao Signed-off-by: Michael D Kinney --- MdePkg/Library/BaseLib/Ia32/Lfence.nasm | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/MdePkg/Library/BaseLib/Ia32/Lfence.nasm b/MdePkg/Library/BaseLib/Ia32/Lfence.nasm index 44478be35f..0a60ae1d57 100644 --- a/MdePkg/Library/BaseLib/Ia32/Lfence.nasm +++ b/MdePkg/Library/BaseLib/Ia32/Lfence.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2018, Intel Corporation. All rights reserved.
+; Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -26,5 +26,17 @@ ;------------------------------------------------------------------------------ global ASM_PFX(AsmLfence) ASM_PFX(AsmLfence): + ; + ; Use CPUID instruction (CPUID.01H:EDX.SSE2[bit 26] = 1) to test whether the + ; processor supports SSE2 instruction. Save/restore non-volatile register + ; EBX that is modified by CPUID + ; + push ebx + mov eax, 1 + cpuid + bt edx, 26 + jnc Done lfence +Done: + pop ebx ret -- 2.21.0.windows.1