From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=UU/eYkVD; spf=pass (domain: linaro.org, ip: 209.85.128.65, mailfrom: leif.lindholm@linaro.org) Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by groups.io with SMTP; Fri, 26 Apr 2019 03:58:17 -0700 Received: by mail-wm1-f65.google.com with SMTP id c1so3264217wml.4 for ; Fri, 26 Apr 2019 03:58:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=8IOS2m6zPtoxK+xLQ6L7+cr6mfVg8C83Z6x1j4THmmE=; b=UU/eYkVDJ71qGjbsBOSSIWahfbrb9DVuvz6p2T4KPkeCZ6oQgxAadmrF6oI4SQgnCS 7JJZ5voQjXsDoVGt6bkRODZn9zYg2y7NYlqIOYtYohkSoSkvdVGE0T9nZw1EC4umhSr0 8/g1zH7eBU/w7/p/mixMLvLZqWL8PVoiPfXGhTFJVB32tsHbKIarlhiDyTmHWCSHmHSS hSzf+KtGsG5tYq5rKm9Ao9rC+rXA5oW5XN2/91+15oQo52wN9C4P8dZt4AxHCXpkuGwj +mqyh1AAh2QjptD88HM9RH7FmElLEz5YYVaFe3jPNKfZ46enZQuwK5f5kW9m6NWuhvQs itWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=8IOS2m6zPtoxK+xLQ6L7+cr6mfVg8C83Z6x1j4THmmE=; b=VDHqZWmZlGNSK0UV6NhU/LT7SrB+aWJoPAR9S5CP/p0d/Y9VggQv2w90/fIHUnl74i VMUFPQh4BjOdeBqjxb5djr2bcUlJYOj/U/D9N5POj8YCCsP9vqxwaqMqv2cSEeq61Zid UyP/WcKdXUpwnQjtewkRZ5kh4t1sDA8zf/PZ7u/asEupNq/OAd+5hnn8QHFpuYZc9Sov SZTp5KXr1dA+haI0ZCCFHfKzdkYY5g/MHb3YhQq6tHVWI2V5p8Gs2c3reGGc+Zr880+C qK+SlrFZBxe/AWg9gE8JdXtnRJlUrxAT8aWjExTUxvtlFAKxrTCOKTwmx28qAM5cX2Qk O4Ag== X-Gm-Message-State: APjAAAX2adSMtjYo5CkKHwRyToXjrG7yxswk2tBvEQqUXzuthDtdyWSn 1LYarUVirs+s04BViFStkbg9eA== X-Google-Smtp-Source: APXvYqz2+Yw5bYbudDxkCfKIBkWCdL1l8tSGuHjIqPTh7xMyXTK1hzardzsKbuwt39GX+Os+mLPRkA== X-Received: by 2002:a7b:cb58:: with SMTP id v24mr5951355wmj.107.1556276295349; Fri, 26 Apr 2019 03:58:15 -0700 (PDT) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id z17sm24386849wmc.7.2019.04.26.03.58.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Apr 2019 03:58:14 -0700 (PDT) Date: Fri, 26 Apr 2019 11:58:13 +0100 From: "Leif Lindholm" To: Ard Biesheuvel Cc: devel@edk2.groups.io, graeme.gregory@linaro.org, masahisa.kojima@linaro.org Subject: Re: [PATCH edk2-platforms] Silicon/SynQuacer: add ACPI description of GPIO controller and power button Message-ID: <20190426105812.gff7q3ybeanh4c2f@bivouac.eciton.net> References: <20190425105127.26429-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20190425105127.26429-1-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Apr 25, 2019 at 12:51:27PM +0200, Ard Biesheuvel wrote: > Add ACPI descriptions of the GPIO and external interrupt (EXIU) > controllers as well as the power button. Note that on rev 0.3 > boards, the power button appears to reset the system (this was > not the case on rev 0.1 boards), so it is included for reference > primarily. The same GPIO event mechanism will be used in the future > for reporting hardware errors to the OS. > > Signed-off-by: Ard Biesheuvel With a contibuted-under: Reviewed-by: Leif Lindholm > --- > Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 52 ++++++++++++++++++++ > Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 4 ++ > 2 files changed, 56 insertions(+) > > diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > index aab4fbf0e6b4..acb77739ded6 100644 > --- a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > @@ -201,5 +201,57 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", "SYNQUACR", > } > }) > } > + > + Device (GPIO) { > + Name (_HID, "SCX0007") > + Name (_UID, Zero) > + Name (_CRS, ResourceTemplate () { > + Memory32Fixed (ReadWrite, SYNQUACER_GPIO_BASE, SYNQUACER_GPIO_SIZE) > + Memory32Fixed (ReadWrite, SYNQUACER_EXIU_BASE, SYNQUACER_EXIU_SIZE) > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 144 } > + }) > + Name (_DSD, > + Package () // _DSD: Device-Specific Data > + { > + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), > + Package () > + { > + Package () { "socionext,spi-base", 112 }, > + Package () > + { > + "gpio-line-names", > + Package () > + { > + "DSW3-PIN1", "DSW3-PIN2", "DSW3-PIN3", "DSW3-PIN4", > + "DSW3-PIN5", "DSW3-PIN6", "DSW3-PIN7", "DSW3-PIN8", > + "PSIN#", "PWROFF#", "GPIO-A", "GPIO-B", > + "GPIO-C", "GPIO-D", "PCIE1EXTINT", "PCIE0EXTINT", > + "PHY2-INT#", "PHY1-INT#", "GPIO-E", "GPIO-F", > + "GPIO-G", "GPIO-H", "GPIO-I", "GPIO-J", > + "GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD27", > + "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31" > + } > + } > + } > + } > + ) > + Name (_AEI, ResourceTemplate () { > + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullDefault,, "\\_SB.GPIO") > + { > + 0x08 > + } > + }) > + Method (_E08, 0x0, NotSerialized) { > + Notify (\_SB.PWRB, 0x80) > + } > + } > + > + Device (PWRB) { > + Name (_HID, "PNP0C0C") > + Name (_UID, Zero) > + Method (_STA, 0x0, NotSerialized) { > + Return (0xF) > + } > + } > } // Scope (_SB) > } > diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h > index b0fcc306c1ae..cff981c4f8ae 100644 > --- a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h > +++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h > @@ -42,6 +42,10 @@ > #define SYNQUACER_GPIO_BASE 0x51000000 > #define SYNQUACER_GPIO_SIZE SIZE_4KB > > +// EXIU interrupt controller > +#define SYNQUACER_EXIU_BASE 0x510c0000 > +#define SYNQUACER_EXIU_SIZE 0x20 > + > // I2C0 block > #define SYNQUACER_I2C0_BASE 0x51200000 > #define SYNQUACER_I2C0_SIZE SIZE_4KB > -- > 2.20.1 >