From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=s18uyASG; spf=pass (domain: linaro.org, ip: 209.85.128.65, mailfrom: ard.biesheuvel@linaro.org) Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by groups.io with SMTP; Thu, 02 May 2019 02:48:34 -0700 Received: by mail-wm1-f65.google.com with SMTP id n25so1738580wmk.4 for ; Thu, 02 May 2019 02:48:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=DQr81GQG0q8ZYaZQVwAqNQXJ/0VSPkrUvfyDe9jURXM=; b=s18uyASGPBwxNb2Oz43ewpP7A9GPhoLGIaPypJJjYwRHBs2OMWZ2HeYJ6cox2/JalP YhMt2sS+x4nHS6jqIcJEcnf1iJ6uRPPZpvpBnefL7LG9Id7uqDnVX2uhBYq/eU991eWq lSiwI1EieIRRHrDz4qlv6sBGzjKHekYKulor/GKAfIcKJpQLJ5MnohpgLeZ5zy+foiUP L1hu8qTzW1JU2VGhN18/TbCJjAN+gO1Lz6NpOAI3NEyBGqCx7Hl3fOtxHYOtUs+wNttc U6Shgdy7VxCiVPnDvUZTPKaWMRoObyvmrFLTmzI5HJcjGSMXm7IDlmF8QUFWmh8fFEpn G1Vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=DQr81GQG0q8ZYaZQVwAqNQXJ/0VSPkrUvfyDe9jURXM=; b=ec4+B4blhnnULHiOw6F9m18WYI+/H+viqxwrLtW1ZIM31LCbjOTeSO0o0bfxsqxXmR ceo8jAX+4qs3hwku5kp7ApvvlJSlrIACuwsPAfgJeXdGUYZUtzSl0FbUNPF9aBHp09/1 4OofL7O8aPTDro68wbs5CpZHfZcF4C1twoY8V69PDXeRMKIhyHMVbkEMvUMLabn+NCbt 9QZsebkI1IL0RL3xu3h+BuLUtuOAS+a9W5Rp+W/UV6NwqeoqbDp288bMggwuWFVEFk/6 eFZaytvQla8yztxlWOqRHDk+VnoXoXbLeDWlfa5mKZYyVIM0o3Y8S9PJ4HZqLVBQ0fVu tE5A== X-Gm-Message-State: APjAAAUfGcG1iUfeckV/vJbEaNvW7p5qC315dEuj8Orf1deIZu6+tklO 17UDKn2tbWlQGPZPIL2rVYtNjPWLJK/J9A== X-Google-Smtp-Source: APXvYqxy92d6HRhKu85ZNUXiXnpOCaMDmGTPBijsiZF0nFFC/nO/PGEpJY0qlmw4RJ73vz80neCAgA== X-Received: by 2002:a7b:c954:: with SMTP id i20mr1629970wml.59.1556790511932; Thu, 02 May 2019 02:48:31 -0700 (PDT) Return-Path: Received: from sudo.home ([2a01:cb1d:112:6f00:2dc9:bac0:dc74:9979]) by smtp.gmail.com with ESMTPSA id h123sm9819231wme.6.2019.05.02.02.48.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 02 May 2019 02:48:30 -0700 (PDT) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, graeme.gregory@linaro.org, Ard Biesheuvel Subject: [PATCH edk2-platforms v2] Silicon/SynQuacer: add ACPI description of GPIO controller and power button Date: Thu, 2 May 2019 11:48:26 +0200 Message-Id: <20190502094826.6550-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add ACPI descriptions of the GPIO and external interrupt (EXIU) controllers as well as the power button. Note that on rev 0.3 boards, the power button appears to reset the system (this was not the case on rev 0.1 boards), so it is included for reference primarily. The same GPIO event mechanism will be used in the future for reporting hardware errors to the OS. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- v2: split EXIU interrupt controller and GPIO controller into separate devices, and mirror the incoming GPIO interrupt with a interrupt resource pointing to the EXIU - this is a more accurate depiction of the situation, given that not all EXIU interrupt lines are connected to GPIO lines Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 56 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 4 ++ 2 files changed, 60 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl index aab4fbf0e6b4..44cdf6568991 100644 --- a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl @@ -201,5 +201,61 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", "SYNQUACR", } }) } + + Device (EXIU) { + Name (_HID, "SCX0008") + Name (_UID, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, SYNQUACER_EXIU_BASE, SYNQUACER_EXIU_SIZE) + }) + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "socionext,spi-base", 112 }, + } + }) + } + + Device (GPIO) { + Name (_HID, "SCX0007") + Name (_UID, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, SYNQUACER_GPIO_BASE, SYNQUACER_GPIO_SIZE) + Interrupt (ResourceConsumer, Edge, ActiveLow, ExclusiveAndWake, 0, "\\_SB.EXIU") { + 8, + } + }) + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { + "gpio-line-names", + Package () { + "DSW3-PIN1", "DSW3-PIN2", "DSW3-PIN3", "DSW3-PIN4", + "DSW3-PIN5", "DSW3-PIN6", "DSW3-PIN7", "DSW3-PIN8", + "PSIN#", "PWROFF#", "GPIO-A", "GPIO-B", + "GPIO-C", "GPIO-D", "PCIE1EXTINT", "PCIE0EXTINT", + "PHY2-INT#", "PHY1-INT#", "GPIO-E", "GPIO-F", + "GPIO-G", "GPIO-H", "GPIO-I", "GPIO-J", + "GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD27", + "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31" + }, + } + } + }) + Name (_AEI, ResourceTemplate () { + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullDefault, 0, "\\_SB.GPIO") + { + 8 + } + }) + Method (_E08) { + Notify (\_SB.PWRB, 0x80) + } + } + + Device (PWRB) { + Name (_HID, "PNP0C0C") + } } // Scope (_SB) } diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h index b0fcc306c1ae..cff981c4f8ae 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h @@ -42,6 +42,10 @@ #define SYNQUACER_GPIO_BASE 0x51000000 #define SYNQUACER_GPIO_SIZE SIZE_4KB +// EXIU interrupt controller +#define SYNQUACER_EXIU_BASE 0x510c0000 +#define SYNQUACER_EXIU_SIZE 0x20 + // I2C0 block #define SYNQUACER_I2C0_BASE 0x51200000 #define SYNQUACER_I2C0_SIZE SIZE_4KB -- 2.20.1