From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=o5rzp50t; spf=pass (domain: linaro.org, ip: 209.85.128.43, mailfrom: ard.biesheuvel@linaro.org) Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) by groups.io with SMTP; Thu, 02 May 2019 02:59:04 -0700 Received: by mail-wm1-f43.google.com with SMTP id q15so1919988wmf.3 for ; Thu, 02 May 2019 02:59:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OxMubmpHHtVg46plIQUYlxQveEuWTEt/LPiOn12OVs4=; b=o5rzp50t/L185OhbXT9msPSodhbD8lOwo8o9abn+DU7E1Q1G4qT8MKUkc6Ww0MdYXJ oywU8I2DrZkSuqtU2PaLVtWCaUihmMLv8pmGwinTvuFP9pT+46lzak0oR7jHS8PckhTd yYtQbG2Q6BjcfLtQ3Pu5oJ/xrO4m5xXicMNUcuZAzrUS8M8kTQPd8M6vLwkO//NZkYsa bQr0rJbIrb+gjvczrKONRvKMOeOSfVv+AF/oXbg+IB7ck4OAltN83ST3UWbDdpDcOk41 7mDXTjoh85axnwmftnjkifdw/I6KB2xcLjKGsHkqnE2SKRffY6f4nCvd4bu8bfNmF5pN 8aPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OxMubmpHHtVg46plIQUYlxQveEuWTEt/LPiOn12OVs4=; b=NR7cLuwG65LyHCF2mA1UjYMrd7u6vLfsZQKhTMv/x1ai7CvzWd9DH6q6B7bKpKb5r+ U0+7UZmVB44JAPp97SmpzwpDzwKid+Cnx8694B9DekglLLYysY5RijLSZYkaO47hAr61 J0SqYQ6uz96o7uckEN3Ud9QSVxd3APaVQCqWpGJWMC0RG/oxfZQI8Onc3DN+Fkkmzcag 9RSl+IGntPk/Lu+TRC3ASBKqfe45Pjf8cGGdq1rgAfzZABYQTD3dNNINRzdGMt8q53YG NHg9DZy+hdCJMUoFTNi8+z0ejhDyaOPePoCrcOsnmUkIoq4qnr7sVEkVUUr2yjsHnMIO O31g== X-Gm-Message-State: APjAAAVm69JsY2c4n7XuS8ExAijEd4XxUSzcFhwEv5EbDIOuNccfM6ak EUaRiesY8gbmwLy1STc2iNq9yurYB3FtDA== X-Google-Smtp-Source: APXvYqxVc8b3fiTEBC+D3NESwV2e0rBwhIm7krDT3a0HzV6qhpoqE/5xZoSM6dJ37Hajf1BDWkJ9aQ== X-Received: by 2002:a7b:c25a:: with SMTP id b26mr1599176wmj.123.1556791141790; Thu, 02 May 2019 02:59:01 -0700 (PDT) Return-Path: Received: from sudo.home ([2a01:cb1d:112:6f00:2dc9:bac0:dc74:9979]) by smtp.gmail.com with ESMTPSA id j3sm10681740wrg.72.2019.05.02.02.59.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 02 May 2019 02:59:00 -0700 (PDT) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, graeme.gregory@linaro.org, Ard Biesheuvel Subject: [PATCH edk2-platforms v2 2/2] Platform/Secure96Dxe: add ACPI description of the LEDs and I2C peripherals Date: Thu, 2 May 2019 11:58:54 +0200 Message-Id: <20190502095854.6989-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190502095854.6989-1-ard.biesheuvel@linaro.org> References: <20190502095854.6989-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Wire up the new 96boards mezzanine SSDT loading support, and use it to describe the four GPIO LEDs on the Secure96 mezzanine board, as well as the two ATmel crypto accelerators residing on the I2C bus. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/96Boards/Secure96Dxe/Secure96.asl | 116 ++++++++++++++++++++ Platform/96Boards/Secure96Dxe/Secure96.h | 8 ++ Platform/96Boards/Secure96Dxe/Secure96Dxe.c | 59 +++++++++- Platform/96Boards/Secure96Dxe/Secure96Dxe.inf | 1 + 4 files changed, 179 insertions(+), 5 deletions(-) diff --git a/Platform/96Boards/Secure96Dxe/Secure96.asl b/Platform/96Boards/Secure96Dxe/Secure96.asl new file mode 100644 index 000000000000..f458929fffb6 --- /dev/null +++ b/Platform/96Boards/Secure96Dxe/Secure96.asl @@ -0,0 +1,116 @@ +/** @file + * Copyright (c) 2019, Linaro Limited. All rights reserved. + * + * This program and the accompanying materials are licensed and made + * available under the terms and conditions of the BSD License which + * accompanies this distribution. The full text of the license may be + * found at http://opensource.org/licenses/bsd-license.php + * + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR + * IMPLIED. + */ + +#include "Secure96.h" + +DefinitionBlock ("Secure96.aml", "SSDT", 2, "96BRDS", "SECURE96", 1) +{ + Scope (_SB) + { + Device (LD96) + { + Name (_HID, "LNRO9601") + Name (_UID, 0x0) + Name (_CID, "PRP0001") + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { Package () { "compatible", "gpio-leds" }, } + }) + Name (_CRS, ResourceTemplate() { + GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, SECURE96_ACPI_GPIO) + { + FixedPcdGet32 (PcdGpioPinG), + FixedPcdGet32 (PcdGpioPinF), + FixedPcdGet32 (PcdGpioPinI), + FixedPcdGet32 (PcdGpioPinH), + } + }) + + Device (LDU1) + { + Name (_ADR, 0x1) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "label", "secure96-u1" }, + Package () { "gpios", Package () { ^^LD96, 0, 0, 0 }, }, + } + }) + } + + Device (LDU2) + { + Name (_ADR, 0x2) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "label", "secure96-u2" }, + Package () { "gpios", Package () { ^^LD96, 0, 1, 0 }, }, + } + }) + } + + Device (LDU3) + { + Name (_ADR, 0x3) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "label", "secure96-u3" }, + Package () { "gpios", Package () { ^^LD96, 0, 2, 0 }, }, + } + }) + } + + Device (LDU4) + { + Name (_ADR, 0x4) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "label", "secure96-u4" }, + Package () { "gpios", Package () { ^^LD96, 0, 3, 0 }, }, + } + }) + } + } + + Device (SH96) + { + Name (_HID, "LNRO9602") + Name (_UID, 0x0) + Name (_CID, "PRP0001") + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { Package () { "compatible", "atmel,atsha204a" }, } + }) + Name (_CRS, ResourceTemplate() { + I2CSerialBus (ATSHA204A_SLAVE_ADDRESS,, 100000,, SECURE96_ACPI_I2C0,,,,) + }) + } + + Device (EC96) + { + Name (_HID, "LNRO9603") + Name (_UID, 0x0) + Name (_CID, "PRP0001") + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { Package () { "compatible", "atmel,atecc508a" }, } + }) + Name (_CRS, ResourceTemplate() { + I2CSerialBus (ATECC508A_SLAVE_ADDRESS,, 100000,, SECURE96_ACPI_I2C0,,,,) + }) + } + } +} diff --git a/Platform/96Boards/Secure96Dxe/Secure96.h b/Platform/96Boards/Secure96Dxe/Secure96.h index 84b8aed13d1e..a44dc4804f92 100644 --- a/Platform/96Boards/Secure96Dxe/Secure96.h +++ b/Platform/96Boards/Secure96Dxe/Secure96.h @@ -23,4 +23,12 @@ #define INFINEON_SLB9670_SPI_CS 0x0 #define INFINEON_SLB9670_DT_NODENAME tpm@0 +#ifndef SECURE96_ACPI_GPIO +#define SECURE96_ACPI_GPIO "\\_SB.GPIO" +#endif + +#ifndef SECURE96_ACPI_I2C0 +#define SECURE96_ACPI_I2C0 "\\_SB.I2C0" +#endif + #endif // _SECURE96_H_ diff --git a/Platform/96Boards/Secure96Dxe/Secure96Dxe.c b/Platform/96Boards/Secure96Dxe/Secure96Dxe.c index 6c48d7c0b024..68f8ec812b52 100644 --- a/Platform/96Boards/Secure96Dxe/Secure96Dxe.c +++ b/Platform/96Boards/Secure96Dxe/Secure96Dxe.c @@ -24,6 +24,8 @@ #include "Secure96.h" +#define SECURE96_SSDT_OEM_TABLE_ID SIGNATURE_64('S','E','C','U','R','E','9','6') + STATIC CONST UINT32 mI2cAtmelSha204aSlaveAddress[] = { ATSHA204A_SLAVE_ADDRESS, @@ -148,15 +150,20 @@ ApplyDeviceTreeOverlay ( UINTN OverlaySize; EFI_STATUS Status; INT32 Err; + UINTN Index; // // Load the raw overlay DTB image from the raw section of this FFS file. // - Status = GetSectionFromFv (&gEfiCallerIdGuid, - EFI_SECTION_RAW, 0, &Overlay, &OverlaySize); - ASSERT_EFI_ERROR (Status); - if (EFI_ERROR (Status)) { - return EFI_NOT_FOUND; + for (Index = 0;; Index++) { + Status = GetSectionFromFv (&gEfiCallerIdGuid, + EFI_SECTION_RAW, Index, &Overlay, &OverlaySize); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + if (!fdt_check_header (Overlay)) { + break; + } } // @@ -177,8 +184,50 @@ ApplyDeviceTreeOverlay ( return EFI_SUCCESS; } +/** + Install the mezzanine's SSDT table + + @param[in] This Pointer to the MEZZANINE_PROTOCOL instance. + @param[in] Dtb Pointer to the device tree blob + + @return EFI_SUCCESS Operation succeeded. + @return other An error has occurred. +**/ +STATIC +EFI_STATUS +EFIAPI +InstallSsdtTable ( + IN MEZZANINE_PROTOCOL *This, + IN EFI_ACPI_TABLE_PROTOCOL *AcpiProtocol + ) +{ + EFI_ACPI_DESCRIPTION_HEADER *Ssdt; + UINTN SsdtSize; + EFI_STATUS Status; + UINTN Index; + UINTN TableKey; + + // + // Load SSDT table from the raw section of this FFS file. + // + for (Index = 0;; Index++) { + Status = GetSectionFromFv (&gEfiCallerIdGuid, EFI_SECTION_RAW, Index, + (VOID **)&Ssdt, &SsdtSize); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + if (SsdtSize >= sizeof (EFI_ACPI_DESCRIPTION_HEADER) && + Ssdt->OemTableId == SECURE96_SSDT_OEM_TABLE_ID) { + break; + } + } + return AcpiProtocol->InstallAcpiTable (AcpiProtocol, Ssdt, SsdtSize, + &TableKey); +} + STATIC MEZZANINE_PROTOCOL mMezzanine = { ApplyDeviceTreeOverlay, + InstallSsdtTable, ARRAY_SIZE (mI2c0Devices), 0, mI2c0Devices, diff --git a/Platform/96Boards/Secure96Dxe/Secure96Dxe.inf b/Platform/96Boards/Secure96Dxe/Secure96Dxe.inf index 72dbf1314c15..ce4c8b5f8fa5 100644 --- a/Platform/96Boards/Secure96Dxe/Secure96Dxe.inf +++ b/Platform/96Boards/Secure96Dxe/Secure96Dxe.inf @@ -21,6 +21,7 @@ [Defines] ENTRY_POINT = Secure96DxeEntryPoint [Sources] + Secure96.asl Secure96.dts Secure96.h Secure96Dxe.c -- 2.20.1