From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=xBmsbekF; spf=pass (domain: linaro.org, ip: 209.85.128.68, mailfrom: leif.lindholm@linaro.org) Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) by groups.io with SMTP; Fri, 03 May 2019 04:28:15 -0700 Received: by mail-wm1-f68.google.com with SMTP id y197so6321717wmd.0 for ; Fri, 03 May 2019 04:28:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=2rPLssSNd6ppsOtjha8zfhinrZnvAi78b7OhGGKjMgg=; b=xBmsbekF5F+6JFDRLCWE02kwqXAwsKd7ystd++A0OqjhGlxIbC1tarvsA+/FUPt9Bl 77x7pZIyxbs+fYguzsEP3MuFQviT9Ov2laSt5tL0cvwYDZdkc6q8rBaSlcpmHRUj9scf 505S/PYNvf54rBhnqxq03QzFDGEgg3T9gC7kvOvcsNcwO82SKlU/dZDXxYqH97ktu5D0 N8LzbUG8FAGF4VSk80vcQjikW07FKvImS4nPmvmOVANHnMNTove9YgNoQmaQPTk+O1FC nkQccAeAkMHmiMXpcUQv3+bVS+4xH8oPbAKJMHeGKzuEdowe235RzLNtlWVaRg75Zhpf wkNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=2rPLssSNd6ppsOtjha8zfhinrZnvAi78b7OhGGKjMgg=; b=XRrEBao91Yw3QUvTohdSFce/yXXoCciK7YCy0LbmCVWzW7+qBwkA/OsoERMLeV4u4i YFVtLRGRGBnOP9cy2Qn3aRCn9R5igpHFsQlH25FEBVzWQU5bFDPQya5MlyTOgbqFafej 7z112lKP28epHjUqoItv/MWBJHk/GICcBDmnpMxfuDNAc8lnq2B7Tb6sBYccly6293Ok uEryrsK18/Vzb6qcGGaCvW2LbIAPQUOVvQUkM69PeIPA2OLdTFSa6wru4OLscquLADPF jl425dbh9C+8TXPBM8vAVgDY28rOVUjsCqzHd7tB/T38876E7Qyx8P8ULA/1mPuzz1S5 M7TA== X-Gm-Message-State: APjAAAVvibJKeHJM4iJv0vNxdHHXrmm0Bu64bXnDzRkohDF0omPjTSfX yli+hZuOavbyZVKPCucLNJYTwQ== X-Google-Smtp-Source: APXvYqyvc4+VFMHYsGgjcw0ODMFaYlgVN/YR1RpjR/xueHW+/kcnqsCAmjqJiETUKpYd5cHt1LnPKQ== X-Received: by 2002:a1c:a00f:: with SMTP id j15mr5715662wme.148.1556882893498; Fri, 03 May 2019 04:28:13 -0700 (PDT) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id o130sm1951953wmo.43.2019.05.03.04.28.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 May 2019 04:28:12 -0700 (PDT) Date: Fri, 3 May 2019 12:28:11 +0100 From: "Leif Lindholm" To: Ard Biesheuvel Cc: devel@edk2.groups.io, graeme.gregory@linaro.org Subject: Re: [PATCH edk2-platforms v2] Silicon/SynQuacer: add ACPI description of GPIO controller and power button Message-ID: <20190503112811.2imhvyablmx7xm77@bivouac.eciton.net> References: <20190502094826.6550-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20190502094826.6550-1-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, May 02, 2019 at 11:48:26AM +0200, Ard Biesheuvel wrote: > Add ACPI descriptions of the GPIO and external interrupt (EXIU) > controllers as well as the power button. Note that on rev 0.3 > boards, the power button appears to reset the system (this was > not the case on rev 0.1 boards), so it is included for reference > primarily. The same GPIO event mechanism will be used in the future > for reporting hardware errors to the OS. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel Acked-by: Leif Lindholm > --- > v2: split EXIU interrupt controller and GPIO controller into separate devices, > and mirror the incoming GPIO interrupt with a interrupt resource pointing > to the EXIU - this is a more accurate depiction of the situation, given > that not all EXIU interrupt lines are connected to GPIO lines > > Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 56 ++++++++++++++++++++ > Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 4 ++ > 2 files changed, 60 insertions(+) > > diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > index aab4fbf0e6b4..44cdf6568991 100644 > --- a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > @@ -201,5 +201,61 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", "SYNQUACR", > } > }) > } > + > + Device (EXIU) { > + Name (_HID, "SCX0008") > + Name (_UID, Zero) > + Name (_CRS, ResourceTemplate () { > + Memory32Fixed (ReadWrite, SYNQUACER_EXIU_BASE, SYNQUACER_EXIU_SIZE) > + }) > + Name (_DSD, Package () { > + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), > + Package () { > + Package () { "socionext,spi-base", 112 }, > + } > + }) > + } > + > + Device (GPIO) { > + Name (_HID, "SCX0007") > + Name (_UID, Zero) > + Name (_CRS, ResourceTemplate () { > + Memory32Fixed (ReadWrite, SYNQUACER_GPIO_BASE, SYNQUACER_GPIO_SIZE) > + Interrupt (ResourceConsumer, Edge, ActiveLow, ExclusiveAndWake, 0, "\\_SB.EXIU") { > + 8, > + } > + }) > + Name (_DSD, Package () { > + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), > + Package () { > + Package () { > + "gpio-line-names", > + Package () { > + "DSW3-PIN1", "DSW3-PIN2", "DSW3-PIN3", "DSW3-PIN4", > + "DSW3-PIN5", "DSW3-PIN6", "DSW3-PIN7", "DSW3-PIN8", > + "PSIN#", "PWROFF#", "GPIO-A", "GPIO-B", > + "GPIO-C", "GPIO-D", "PCIE1EXTINT", "PCIE0EXTINT", > + "PHY2-INT#", "PHY1-INT#", "GPIO-E", "GPIO-F", > + "GPIO-G", "GPIO-H", "GPIO-I", "GPIO-J", > + "GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD27", > + "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31" > + }, > + } > + } > + }) > + Name (_AEI, ResourceTemplate () { > + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullDefault, 0, "\\_SB.GPIO") > + { > + 8 > + } > + }) > + Method (_E08) { > + Notify (\_SB.PWRB, 0x80) > + } > + } > + > + Device (PWRB) { > + Name (_HID, "PNP0C0C") > + } > } // Scope (_SB) > } > diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h > index b0fcc306c1ae..cff981c4f8ae 100644 > --- a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h > +++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h > @@ -42,6 +42,10 @@ > #define SYNQUACER_GPIO_BASE 0x51000000 > #define SYNQUACER_GPIO_SIZE SIZE_4KB > > +// EXIU interrupt controller > +#define SYNQUACER_EXIU_BASE 0x510c0000 > +#define SYNQUACER_EXIU_SIZE 0x20 > + > // I2C0 block > #define SYNQUACER_I2C0_BASE 0x51200000 > #define SYNQUACER_I2C0_SIZE SIZE_4KB > -- > 2.20.1 >