From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: michael.d.kinney@intel.com) Received: from mga07.intel.com (mga07.intel.com []) by groups.io with SMTP; Thu, 09 May 2019 20:34:48 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 May 2019 20:34:47 -0700 X-ExtLoop1: 1 Received: from unknown (HELO mdkinney-MOBL2.amr.corp.intel.com) ([10.241.98.74]) by orsmga002.jf.intel.com with ESMTP; 09 May 2019 20:34:42 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Kelly Steele , Michael Kubacki , Leif Lindholm , Ard Biesheuvel Subject: [edk2-platforms: Patch 4/8] Platform/QuarkPlatformPkg: Import QuarkPlatformPkg from edk2 Date: Thu, 9 May 2019 20:34:31 -0700 Message-Id: <20190510033435.24112-5-michael.d.kinney@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20190510033435.24112-1-michael.d.kinney@intel.com> References: <20190510033435.24112-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit https://bugzilla.tianocore.org/show_bug.cgi?id=1374 Import QuarkPlatformPkg from edk2/master. Cc: Kelly Steele Cc: Michael Kubacki Cc: Leif Lindholm Cc: Ard Biesheuvel Signed-off-by: Michael D Kinney --- .../Acpi/AcpiTables/AcpiTables.inf | 42 + .../Acpi/AcpiTables/Cpu0Cst/Cpu0Cst.asl | 399 ++++ .../Acpi/AcpiTables/Cpu0Ist/Cpu0Ist.asl | 159 ++ .../Acpi/AcpiTables/Cpu0Tst/Cpu0Tst.asl | 133 ++ .../Acpi/AcpiTables/CpuPm/CpuPm.asl | 73 + .../Acpi/AcpiTables/Dsdt/AD7298.asi | 38 + .../Acpi/AcpiTables/Dsdt/ADC108S102.asi | 33 + .../Acpi/AcpiTables/Dsdt/CAT24C08.asi | 34 + .../Acpi/AcpiTables/Dsdt/CY8C9540A.asi | 47 + .../Acpi/AcpiTables/Dsdt/GpioClient.asi | 89 + .../Acpi/AcpiTables/Dsdt/LpcDev.asi | 248 ++ .../Acpi/AcpiTables/Dsdt/PCA9685.asi | 34 + .../Acpi/AcpiTables/Dsdt/PCAL9555A.asi | 90 + .../Acpi/AcpiTables/Dsdt/PciHostBridge.asi | 195 ++ .../Acpi/AcpiTables/Dsdt/PciIrq.asi | 552 +++++ .../Acpi/AcpiTables/Dsdt/PcieExpansionPrt.asi | 127 + .../Acpi/AcpiTables/Dsdt/Platform.asl | 347 +++ .../Acpi/AcpiTables/Dsdt/QNC.asi | 49 + .../Acpi/AcpiTables/Dsdt/QNCApic.asi | 32 + .../Acpi/AcpiTables/Dsdt/QNCLpc.asi | 23 + .../AcpiTables/Dsdt/QuarkSouthCluster.asi | 110 + .../Acpi/AcpiTables/Dsdt/Tpm.asi | 45 + .../Acpi/AcpiTables/Facs/Facs.aslc | 74 + .../Acpi/AcpiTables/Facs/Facs.h | 29 + .../Acpi/AcpiTables/Fadt/Fadt.h | 102 + .../Acpi/AcpiTables/Fadt/Fadt1.0.aslc | 76 + .../Acpi/AcpiTables/Fadt/Fadt2.0.aslc | 157 ++ .../Acpi/AcpiTables/Hpet/Hpet.aslc | 68 + .../Acpi/AcpiTables/Hpet/Hpet.h | 45 + .../Acpi/AcpiTables/Mcfg/Mcfg.aslc | 75 + .../Acpi/AcpiTables/Mcfg/Mcfg.h | 56 + .../Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.c | 1402 +++++++++++ .../Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.h | 316 +++ .../Acpi/Dxe/AcpiPlatform/AcpiPlatform.c | 805 +++++++ .../Acpi/Dxe/AcpiPlatform/AcpiPlatform.h | 120 + .../Acpi/Dxe/AcpiPlatform/AcpiPlatform.inf | 196 ++ .../Acpi/Dxe/AcpiPlatform/Madt.h | 207 ++ .../Acpi/Dxe/AcpiPlatform/MadtPlatform.c | 300 +++ .../BootScriptExecutorDxe.inf | 77 + .../Dxe/BootScriptExecutorDxe/IA32/S3Asm.S | 44 + .../Dxe/BootScriptExecutorDxe/IA32/S3Asm.asm | 51 + .../BootScriptExecutorDxe/IA32/SetIdtEntry.c | 57 + .../Dxe/BootScriptExecutorDxe/ScriptExecute.c | 379 +++ .../Dxe/BootScriptExecutorDxe/ScriptExecute.h | 70 + .../Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.c | 1011 ++++++++ .../Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.h | 167 ++ .../Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.inf | 78 + .../Acpi/DxeSmm/SmmPowerManagement/Ppm.c | 372 +++ .../Acpi/DxeSmm/SmmPowerManagement/Ppm.h | 150 ++ .../SmmPowerManagement/SmmPowerManagement.c | 113 + .../SmmPowerManagement/SmmPowerManagement.h | 52 + .../SmmPowerManagement/SmmPowerManagement.inf | 74 + .../Application/ForceRecovery/ForceRecovery.c | 47 + .../ForceRecovery/ForceRecovery.inf | 34 + .../PlatformFlashAccessLibDxe.c | 262 +++ .../PlatformFlashAccessLibDxe.inf | 47 + .../PlatformFlashAccessLib/SpiFlashDevice.c | 330 +++ .../PlatformFlashAccessLib/SpiFlashDevice.h | 180 ++ .../SystemFirmwareDescriptor.aslc | 83 + .../SystemFirmwareDescriptor.inf | 40 + .../SystemFirmwareDescriptorPei.c | 60 + .../SystemFirmwareUpdateConfig.ini | 57 + .../Include/Guid/CapsuleOnDataCD.h | 23 + .../Include/Guid/CapsuleOnFatFloppyDisk.h | 23 + .../Include/Guid/CapsuleOnFatIdeDisk.h | 24 + .../Include/Guid/CapsuleOnFatUsbDisk.h | 24 + .../Include/Guid/MemoryConfigData.h | 23 + .../Include/Guid/QuarkCapsuleGuid.h | 46 + .../Include/Guid/QuarkVariableLock.h | 23 + .../Include/Guid/SystemNvDataHobGuid.h | 29 + .../Include/Library/PlatformHelperLib.h | 266 +++ .../Include/Library/PlatformPcieHelperLib.h | 56 + .../Intel/QuarkPlatformPkg/Include/Pcal9555.h | 24 + .../Intel/QuarkPlatformPkg/Include/Platform.h | 119 + .../QuarkPlatformPkg/Include/PlatformBoards.h | 166 ++ .../Include/Protocol/GlobalNvsArea.h | 82 + .../Include/Protocol/PlatformSmmSpiReady.h | 23 + .../PlatformBootManager.c | 472 ++++ .../PlatformBootManager.h | 49 + .../PlatformBootManagerLib.inf | 83 + .../PlatformBootManagerLib/PlatformData.c | 275 +++ .../Library/PlatformHelperLib/CommonHeader.h | 51 + .../DxePlatformHelperLib.inf | 70 + .../PeiPlatformHelperLib.inf | 45 + .../PlatformHelperLib/PlatformHelperDxe.c | 337 +++ .../PlatformHelperLib/PlatformHelperLib.c | 481 ++++ .../PlatformHelperLib/PlatformHelperPei.c | 159 ++ .../Library/PlatformHelperLib/PlatformLeds.c | 146 ++ .../PlatformPcieHelperLib/CommonHeader.h | 55 + .../PlatformPcieHelperLib.c | 114 + .../PlatformPcieHelperLib.inf | 41 + .../Library/PlatformPcieHelperLib/SocUnit.c | 125 + .../Library/PlatformSecLib/Ia32/Flat32.S | 796 +++++++ .../Library/PlatformSecLib/Ia32/Flat32.asm | 685 ++++++ .../Library/PlatformSecLib/Ia32/Platform.inc | 134 ++ .../Library/PlatformSecLib/PlatformSecLib.c | 207 ++ .../Library/PlatformSecLib/PlatformSecLib.inf | 54 + .../PlatformSecLib/PlatformSecLibModStrs.uni | 18 + .../PlatformSecureLib/PlatformSecureLib.c | 164 ++ .../PlatformSecureLib/PlatformSecureLib.inf | 41 + .../Library/Tpm12DeviceLibAtmelI2c/TisPc.c | 408 ++++ .../Tpm12DeviceLibAtmelI2c.inf | 39 + .../Tpm12DeviceLibAtmelI2c.uni | 16 + .../Library/Tpm12DeviceLibInfineonI2c/TisPc.c | 612 +++++ .../Tpm12DeviceLibInfineonI2c.inf | 39 + .../Tpm12DeviceLibInfineonI2c.uni | 16 + .../Pci/Dxe/PciHostBridge/PciHostBridge.c | 1397 +++++++++++ .../Pci/Dxe/PciHostBridge/PciHostBridge.h | 389 ++++ .../Pci/Dxe/PciHostBridge/PciHostBridge.inf | 61 + .../Dxe/PciHostBridge/PciHostBridgeSupport.c | 140 ++ .../Pci/Dxe/PciHostBridge/PciHostResource.h | 60 + .../Pci/Dxe/PciHostBridge/PciRootBridge.h | 693 ++++++ .../Pci/Dxe/PciHostBridge/PciRootBridgeIo.c | 1610 +++++++++++++ .../Pci/Dxe/PciPlatform/CommonHeader.h | 31 + .../Pci/Dxe/PciPlatform/PciPlatform.c | 194 ++ .../Pci/Dxe/PciPlatform/PciPlatform.h | 82 + .../Pci/Dxe/PciPlatform/PciPlatform.inf | 54 + .../Dxe/MemorySubClass/MemorySubClass.c | 435 ++++ .../Dxe/MemorySubClass/MemorySubClass.h | 65 + .../Dxe/MemorySubClass/MemorySubClass.inf | 60 + .../MemorySubClass/MemorySubClassStrings.uni | 29 + .../Dxe/PlatformInit/PlatformConfig.c | 443 ++++ .../Dxe/PlatformInit/PlatformInitDxe.c | 87 + .../Dxe/PlatformInit/PlatformInitDxe.h | 58 + .../Dxe/PlatformInit/PlatformInitDxe.inf | 56 + .../Dxe/SaveMemoryConfig/SaveMemoryConfig.c | 118 + .../Dxe/SaveMemoryConfig/SaveMemoryConfig.inf | 44 + .../Platform/Dxe/Setup/CommonHeader.h | 55 + .../Platform/Dxe/Setup/DxePlatform.inf | 76 + .../Platform/Dxe/Setup/KeyboardLayout.c | 262 +++ .../Platform/Dxe/Setup/QNCRegTable.c | 80 + .../Platform/Dxe/Setup/SetupPlatform.c | 97 + .../Platform/Dxe/Setup/SetupPlatform.h | 71 + .../Platform/Dxe/Setup/Strings.uni | 47 + .../Platform/Dxe/Setup/processor.c | 40 + .../Platform/Dxe/SmbiosMiscDxe/CommonHeader.h | 34 + .../MiscBaseBoardManufacturer.uni | 19 + .../MiscBaseBoardManufacturerData.c | 45 + .../MiscBaseBoardManufacturerFunction.c | 181 ++ .../Dxe/SmbiosMiscDxe/MiscBiosVendor.uni | 18 + .../Dxe/SmbiosMiscDxe/MiscBiosVendorData.c | 92 + .../SmbiosMiscDxe/MiscBiosVendorFunction.c | 222 ++ .../SmbiosMiscDxe/MiscBootInformationData.c | 24 + .../MiscBootInformationFunction.c | 71 + .../SmbiosMiscDxe/MiscChassisManufacturer.uni | 17 + .../MiscChassisManufacturerData.c | 36 + .../MiscChassisManufacturerFunction.c | 168 ++ .../Dxe/SmbiosMiscDxe/MiscDevicePath.h | 42 + .../MiscNumberOfInstallableLanguagesData.c | 28 + ...MiscNumberOfInstallableLanguagesFunction.c | 240 ++ .../Dxe/SmbiosMiscDxe/MiscOemString.uni | 12 + .../Dxe/SmbiosMiscDxe/MiscOemStringData.c | 20 + .../Dxe/SmbiosMiscDxe/MiscOemStringFunction.c | 78 + .../Dxe/SmbiosMiscDxe/MiscOnboardDevice.uni | 18 + .../Dxe/SmbiosMiscDxe/MiscOnboardDeviceData.c | 49 + .../SmbiosMiscDxe/MiscOnboardDeviceFunction.c | 105 + .../MiscPortInternalConnectorDesignator.uni | 53 + .../MiscPortInternalConnectorDesignatorData.c | 184 ++ ...cPortInternalConnectorDesignatorFunction.c | 292 +++ .../SmbiosMiscDxe/MiscSystemManufacturer.uni | 20 + .../MiscSystemManufacturerData.c | 32 + .../MiscSystemManufacturerFunction.c | 198 ++ .../SmbiosMiscDxe/MiscSystemOptionString.uni | 14 + .../MiscSystemOptionStringData.c | 23 + .../MiscSystemOptionStringFunction.c | 81 + .../MiscSystemSlotDesignation.uni | 27 + .../MiscSystemSlotDesignationData.c | 357 +++ .../MiscSystemSlotDesignationFunction.c | 285 +++ .../MiscSystemSlotOnboardDevices.uni | 23 + .../Platform/Dxe/SmbiosMiscDxe/SmbiosMisc.h | 137 ++ .../Dxe/SmbiosMiscDxe/SmbiosMiscDataTable.c | 109 + .../Dxe/SmbiosMiscDxe/SmbiosMiscDxe.inf | 308 +++ .../Dxe/SmbiosMiscDxe/SmbiosMiscEntryPoint.c | 82 + .../Dxe/SmbiosMiscDxe/SmbiosMiscStrings.uni | 26 + .../Pei/PlatformConfig/PlatformConfigPei.c | 81 + .../Pei/PlatformConfig/PlatformConfigPei.inf | 45 + .../Platform/Pei/PlatformInit/BootMode.c | 218 ++ .../Platform/Pei/PlatformInit/CommonHeader.h | 81 + .../Pei/PlatformInit/Generic/Recovery.c | 467 ++++ .../Pei/PlatformInit/MemoryCallback.c | 279 +++ .../Platform/Pei/PlatformInit/MrcWrapper.c | 1565 +++++++++++++ .../Platform/Pei/PlatformInit/MrcWrapper.h | 225 ++ .../Platform/Pei/PlatformInit/PeiFvSecurity.c | 111 + .../Platform/Pei/PlatformInit/PeiFvSecurity.h | 67 + .../Pei/PlatformInit/PlatformEarlyInit.c | 1227 ++++++++++ .../Pei/PlatformInit/PlatformEarlyInit.h | 301 +++ .../Pei/PlatformInit/PlatformEarlyInit.inf | 193 ++ .../Pei/PlatformInit/PlatformErratas.c | 178 ++ .../Platform/SpiFvbServices/FvbInfo.c | 332 +++ .../Platform/SpiFvbServices/FwBlockService.c | 2053 +++++++++++++++++ .../Platform/SpiFvbServices/FwBlockService.h | 308 +++ .../Platform/SpiFvbServices/PlatformSmmSpi.c | 31 + .../SpiFvbServices/PlatformSmmSpi.inf | 80 + .../Platform/SpiFvbServices/PlatformSpi.inf | 79 + .../Platform/SpiFvbServices/SpiFlashDevice.c | 331 +++ .../Platform/SpiFvbServices/SpiFlashDevice.h | 181 ++ Platform/Intel/QuarkPlatformPkg/Quark.dsc | 948 ++++++++ Platform/Intel/QuarkPlatformPkg/Quark.fdf | 907 ++++++++ Platform/Intel/QuarkPlatformPkg/QuarkMin.dsc | 648 ++++++ Platform/Intel/QuarkPlatformPkg/QuarkMin.fdf | 608 +++++ .../QuarkPlatformPkg/QuarkPlatformPkg.dec | 933 ++++++++ Platform/Intel/QuarkPlatformPkg/Readme.md | 685 ++++++ 202 files changed, 41211 insertions(+) create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/AcpiTables.inf create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Cst/Cpu0Cst.asl create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Ist/Cpu0Ist.asl create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Tst/Cpu0Tst.asl create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/CpuPm/CpuPm.asl create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/AD7298.asi create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/ADC108S102.asi create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CAT24C08.asi create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CY8C9540A.asi create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/GpioClient.asi create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/LpcDev.asi create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCA9685.asi create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCAL9555A.asi create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciHostBridge.asi create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciIrq.asi create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PcieExpansionPrt.asi create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Platform.asl create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNC.asi create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCApic.asi create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCLpc.asi create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QuarkSouthCluster.asi create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Tpm.asi create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Facs/Facs.aslc create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Facs/Facs.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt1.0.aslc create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt2.0.aslc create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Hpet/Hpet.aslc create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Hpet/Hpet.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Mcfg/Mcfg.aslc create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Mcfg/Mcfg.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.inf create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/Madt.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/MadtPlatform.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/BootScriptExecutorDxe.inf create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/S3Asm.S create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/S3Asm.asm create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/SetIdtEntry.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/ScriptExecute.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/ScriptExecute.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.inf create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/Ppm.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/Ppm.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.inf create mode 100644 Platform/Intel/QuarkPlatformPkg/Application/ForceRecovery/ForceRecovery.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Application/ForceRecovery/ForceRecovery.inf create mode 100644 Platform/Intel/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf create mode 100644 Platform/Intel/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Feature/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc create mode 100644 Platform/Intel/QuarkPlatformPkg/Feature/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf create mode 100644 Platform/Intel/QuarkPlatformPkg/Feature/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Feature/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini create mode 100644 Platform/Intel/QuarkPlatformPkg/Include/Guid/CapsuleOnDataCD.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Include/Guid/CapsuleOnFatFloppyDisk.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Include/Guid/CapsuleOnFatIdeDisk.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Include/Guid/CapsuleOnFatUsbDisk.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Include/Guid/MemoryConfigData.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Include/Guid/QuarkCapsuleGuid.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Include/Guid/QuarkVariableLock.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Include/Guid/SystemNvDataHobGuid.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Include/Library/PlatformHelperLib.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Include/Library/PlatformPcieHelperLib.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Include/Pcal9555.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Include/Platform.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Include/PlatformBoards.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Include/Protocol/GlobalNvsArea.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Include/Protocol/PlatformSmmSpiReady.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformData.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/CommonHeader.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/DxePlatformHelperLib.inf create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/PeiPlatformHelperLib.inf create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperDxe.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperLib.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperPei.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformLeds.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformPcieHelperLib/CommonHeader.h create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.inf create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformPcieHelperLib/SocUnit.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/Ia32/Flat32.S create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/Ia32/Flat32.asm create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/Ia32/Platform.inc create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/PlatformSecLib.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/PlatformSecLib.inf create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/PlatformSecLibModStrs.uni create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformSecureLib/PlatformSecureLib.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/PlatformSecureLib/PlatformSecureLib.inf create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/Tpm12DeviceLibAtmelI2c/TisPc.c create mode 100644 Platform/Intel/QuarkPlatformPkg/Library/Tpm12DeviceLibAtmelI2c/Tpm12DeviceLibAtmelI2c.inf create mode 100644 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b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000000..73c26c2532 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/AcpiTables.inf @@ -0,0 +1,42 @@ +## @file +# Component description file for PlatformAcpiTable module. +# +# Build acpi table data required by system boot. +# All .asi files tagged with "ToolCode="DUMMY"" in following +# file list are device description and are included by top +# level ASL file which will be dealed with by asl.exe application. +# +# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 EBC +# + +[Sources] + Facs/Facs.aslc + Fadt/Fadt2.0.aslc + Hpet/Hpet.aslc + Mcfg/Mcfg.aslc + Dsdt/Platform.asl + CpuPm/CpuPm.asl + Cpu0Cst/Cpu0Cst.asl + Cpu0Ist/Cpu0Ist.asl + Cpu0Tst/Cpu0Tst.asl + +[Packages] + MdePkg/MdePkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + QuarkSocPkg/QuarkSocPkg.dec diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Cst/Cpu0Cst.asl b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Cst/Cpu0Cst.asl new file mode 100644 index 0000000000..444f1ac988 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Cst/Cpu0Cst.asl @@ -0,0 +1,399 @@ +/** @file +CPU C State control methods + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +DefinitionBlock ( + "Cpu0Cst.aml", + "SSDT", + 0x01, + "SsgPmm", + "Cpu0Cst", + 0x0011 + ) +{ + External(\_PR.CPU0, DeviceObj) + External (PDC0, IntObj) + External (CFGD, FieldUnitObj) + + Scope(\_PR.CPU0) + { + Method (_CST, 0) + { + // If CMP is supported, and OSPM is not capable of independent C1, P, T state + // support for each processor for multi-processor configuration, we will just report + // C1 halt + // + // PDCx[4] = Indicates whether OSPM is not capable of independent C1, P, T state + // support for each processor for multi-processor configuration. + // + If(LAnd(And(CFGD,0x01000000), LNot(And(PDC0,0x10)))) + { + Return(Package() { + 1, + Package() + { // C1 halt + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + 1, + 157, + 1000 + } + }) + } + + // + // If MWAIT extensions is supported and OSPM is capable of performing + // native C state instructions for the C2/C3 in multi-processor configuration, + // we report every c state with MWAIT extensions. + // + // PDCx[9] = Indicates whether OSPM is capable of performing native C state instructions + // for the C2/C3 in multi-processor configuration + // + If(LAnd(And(CFGD, 0x200000), And(PDC0,0x200))) + { + // + // If C6 is supported, we report MWAIT C1,C2,C4,C6 + // + If(And(CFGD,0x200)) + { + Return( Package() + { + 4, + Package() + { // MWAIT C1, hardware coordinated with no bus master avoidance + ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)}, + 1, + 1, + 1000 + }, + Package() + { // MWAIT C2, hardware coordinated with no bus master avoidance + ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)}, + 2, + 20, + 500 + }, + Package() + { // MWAIT C4, hardware coordinated with bus master avoidance enabled + ResourceTemplate(){Register(FFixedHW, 1, 2, 0x30, 3)}, + 3, + 100, + 100 + }, + Package() + { // MWAIT C6, hardware coordinated with bus master avoidance enabled + ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 3)}, + 3, + 140, + 10 + } + }) + } + // + // If C4 is supported, we report MWAIT C1,C2,C4 + // + If(And(CFGD,0x080)) + { + Return( Package() + { + 3, + Package() + { // MWAIT C1, hardware coordinated with no bus master avoidance + ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)}, + 1, + 1, + 1000 + }, + Package() + { // MWAIT C2, hardware coordinated with no bus master avoidance + ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)}, + 2, + 20, + 500 + }, + Package() + { // MWAIT C4, hardware coordinated with bus master avoidance enabled + ResourceTemplate(){Register(FFixedHW, 1, 2, 0x30, 3)}, + 3, + 100, + 100 + } + }) + } + // + // If C2 is supported, we report MWAIT C1,C2 + // + If(And(CFGD,0x020)) + { + Return( Package() + { + 2, + Package() + { // MWAIT C1, hardware coordinated with no bus master avoidance + ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)}, + 1, + 1, + 1000 + }, + Package() + { // MWAIT C2, hardware coordinated with no bus master avoidance + ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)}, + 2, + 20, + 500 + } + }) + } + // + // Else we only report MWAIT C1. + // + Return(Package() + { + 1, + Package() + { // MWAIT C1, hardware coordinated with no bus master avoidance + ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)}, + 1, + 1, + 1000 + } + }) + } + + // If OSPM is only capable of performing native C state instructions for + // the C1 in multi-processor configuration, we report C1 with MWAIT, other + // C states with IO method. + // + // PDCx[8] = Indicates whether OSPM is capable of performing native C state instructions + // for the C1 in multi-processor configuration + // + If(LAnd(And(CFGD, 0x200000), And(PDC0,0x100))) + { + // + // If C6 is supported, we report MWAIT C1, IO C2,C4,C6 + // + If(And(CFGD,0x200)) + { + Return( Package() + { + 4, + Package() + { // MWAIT C1, hardware coordinated with no bus master avoidance + ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)}, + 1, + 1, + 1000 + }, + Package() + { // IO C2 ("PMBALVL2" will be updated at runtime) + ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)}, + 2, + 20, + 500 + }, + Package() + { // IO C4 ("PMBALVL4" will be updated at runtime) + ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)}, + 3, + 100, + 100 + }, + Package() + { // IO C6 ("PMBALVL6" will be updated at runtime) + ResourceTemplate () {Register(SystemIO, 8, 0, 0x364C564C41424D50)}, + 3, + 140, + 10 + } + }) + } + // + // If C4 is supported, we report MWAIT C1, IO C2,C4 + // + If(And(CFGD,0x080)) + { + Return( Package() + { + 3, + Package() + { // MWAIT C1, hardware coordinated with no bus master avoidance + ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)}, + 1, + 1, + 1000 + }, + Package() + { // IO C2 ("PMBALVL2" will be updated at runtime) + ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)}, + 2, + 20, + 500 + }, + Package() + { // IO C4 ("PMBALVL4" will be updated at runtime) + ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)}, + 3, + 100, + 100 + } + }) + } + // + // If C2 is supported, we report MWAIT C1, IO C2 + // + If(And(CFGD,0x020)) + { + Return( Package() + { + 2, + Package() + { // MWAIT C1, hardware coordinated with no bus master avoidance + ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)}, + 1, + 1, + 1000 + }, + Package() + { // IO C2 ("PMBALVL2" will be updated at runtime) + ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)}, + 2, + 20, + 500 + } + }) + } + // + // Else we only report MWAIT C1. + // + Return(Package() + { + 1, + Package() + { // MWAIT C1, hardware coordinated with no bus master avoidance + ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)}, + 1, + 1, + 1000 + } + }) + } + + // + // If MWAIT is not supported, we report all the c states with IO method + // + + // + // If C6 is supported, we report C1 halt, IO C2,C4,C6 + // + If(And(CFGD,0x200)) + { + Return(Package() + { + 4, + Package() + { // C1 Halt + ResourceTemplate () {Register(FFixedHW, 0, 0, 0)}, + 1, + 1, + 1000 + }, + Package() + { // IO C2 ("PMBALVL2" will be updated at runtime) + ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)}, + 2, + 20, + 500 + }, + Package() + { // IO C4 ("PMBALVL4" will be updated at runtime) + ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)}, + 3, + 100, + 100 + }, + Package() + { // IO C6 ("PMBALVL6" will be updated at runtime) + ResourceTemplate () {Register(SystemIO, 8, 0, 0x364C564C41424D50)}, + 3, + 140, + 10 + } + }) + } + // + // If C4 is supported, we report C1 halt, IO C2,C4 + // + If(And(CFGD,0x080)) + { + Return(Package() + { + 3, + Package() + { // C1 halt + ResourceTemplate () {Register(FFixedHW, 0, 0, 0)}, + 1, + 1, + 1000 + }, + Package() + { // IO C2 ("PMBALVL2" will be updated at runtime) + ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)}, + 2, + 20, + 500 + }, + Package() + { // IO C4 ("PMBALVL4" will be updated at runtime) + ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)}, + 3, + 100, + 100 + } + }) + } + + // + // If C2 is supported, we report C1 halt, IO C2 + // + If(And(CFGD,0x020)) + { + Return(Package() + { + 2, + Package() + { // C1 halt + ResourceTemplate () {Register(FFixedHW, 0, 0, 0)}, + 1, + 1, + 1000 + }, + Package() + { // IO C2 ("PMBALVL2" will be updated at runtime) + ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)}, + 2, + 20, + 500 + } + }) + } + // + // Else we only report C1 halt. + // + Return(Package() + { + 1, + Package() + { // C1 halt + ResourceTemplate () {Register(FFixedHW, 0, 0, 0)}, + 1, + 1, + 1000 + } + }) + } + } +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Ist/Cpu0Ist.asl b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Ist/Cpu0Ist.asl new file mode 100644 index 0000000000..68f2e7cccb --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Ist/Cpu0Ist.asl @@ -0,0 +1,159 @@ +/** @file +CPU EIST control methods + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +DefinitionBlock ( + "CPU0IST.aml", + "SSDT", + 0x01, + "SsgPmm", + "Cpu0Ist", + 0x0012 + ) +{ + External (PDC0, IntObj) + External (CFGD, FieldUnitObj) + External(\_PR.CPU0, DeviceObj) + + Scope(\_PR.CPU0) + { + Method(_PPC,0) + { + Return(ZERO) // Return All States Available. + } + + Method(_PCT,0) + { + // + // If GV3 is supported and OSPM is capable of direct access to + // performance state MSR, we use MSR method + // + // + // PDCx[0] = Indicates whether OSPM is capable of direct access to + // performance state MSR. + // + If(LAnd(And(CFGD,0x0001), And(PDC0,0x0001))) + { + Return(Package() // MSR Method + { + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + } + + // + // Otherwise, we use smi method + // + Return(Package() // SMI Method + { + ResourceTemplate(){Register(SystemIO,16,0,0xB2)}, + ResourceTemplate(){Register(SystemIO, 8,0,0xB3)} + }) + } + + Method(_PSS,0) + { + // + // If OSPM is capable of direct access to performance state MSR, + // we report NPSS, otherwise, we report SPSS. + If (And(PDC0,0x0001)) + { + Return(NPSS) + } + + Return(SPSS) + } + + Name(SPSS,Package() + { + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000} + }) + + Name(NPSS,Package() + { + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000} + }) + + Method(_PSD,0) + { + // + // If CMP is suppored, we report the dependency with two processors + // + If(And(CFGD,0x1000000)) + { + // + // If OSPM is capable of hardware coordination of P-states, we report + // the dependency with hardware coordination. + // + // PDCx[11] = Indicates whether OSPM is capable of hardware coordination of P-states + // + If(And(PDC0,0x0800)) + { + Return(Package(){ + Package(){ + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFE, // Coord Type- HW_ALL. + 2 // # processors. + } + }) + } + + // + // Otherwise, the dependency with OSPM coordination + // + Return(Package(){ + Package(){ + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFC, // Coord Type- SW_ALL. + 2 // # processors. + } + }) + } + + // + // Otherwise, we report the dependency with one processor + // + Return(Package(){ + Package(){ + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFC, // Coord Type- SW_ALL. + 1 // # processors. + } + }) + } + } +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Tst/Cpu0Tst.asl b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Tst/Cpu0Tst.asl new file mode 100644 index 0000000000..9af10a1c60 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Tst/Cpu0Tst.asl @@ -0,0 +1,133 @@ +/** @file +CPU T-state control methods + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +DefinitionBlock ( + "CPU0TST.aml", + "SSDT", + 0x01, + "SsgPmm", + "Cpu0Tst", + 0x0013 + ) +{ + External (PDC0, IntObj) + External (CFGD, FieldUnitObj) + External(\_PR.CPU0, DeviceObj) + External(_PSS) + + Scope(\_PR.CPU0) + { + Method(_TPC,0) + { + Return(ZERO) // Return All States Available. + } + + Name(TPTC, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0, 0, FIX1) // IO APIC + }) + + // + // If OSPM is capable of direct access to on demand throttling MSR, + // we use MSR method;otherwise we use IO method. + // + // + // PDCx[2] = Indicates whether OSPM is capable of direct access to + // on demand throttling MSR. + // + Method(_PTC, 0) + { + If(And(PDC0, 0x0004)) + { + Return(Package() // MSR Method + { + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + } + ) + } + Return(Package() // IO Method + { + // + // PM IO base ("PMBALVL0" will be updated at runtime) + // + ResourceTemplate(){Register(SystemIO, 4, 1, 0x304C564C41424D50)}, + ResourceTemplate(){Register(SystemIO, 4, 1, 0x304C564C41424D50)} + } + ) + } + + // + // _TSS returned package for IO Method + // + Name(TSSI, Package() + { + Package(){100, 1000, 0, 0x00, 0} + } + ) + // + // _TSS returned package for MSR Method + // + Name(TSSM, Package() + { + Package(){100, 1000, 0, 0x00, 0} + } + ) + + Method(_TSS, 0) + { + // + // If OSPM is capable of direct access to on demand throttling MSR, + // we report TSSM;otherwise report TSSI. + // + If(And(PDC0, 0x0004)) + { + Return(TSSM) + } + Return(TSSI) + } + + Method(_TSD, 0) + { + // + // If CMP is suppored, we report the dependency with two processors + // + If(LAnd(And(CFGD, 0x1000000), LNot(And(PDC0, 4)))) + { + Return(Package() + { + Package() + { + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFD, // Coord Type- SW_ANY + 2 // # processors. + } + } + ) + } + // + // Otherwise, we report the dependency with one processor + // + Return(Package() + { + Package() + { + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFC, // Coord Type- SW_ALL + 1 // # processors. + } + } + ) + } + } +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/CpuPm/CpuPm.asl b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/CpuPm/CpuPm.asl new file mode 100644 index 0000000000..7cecb8311c --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/CpuPm/CpuPm.asl @@ -0,0 +1,73 @@ +/** @file +CPU power management control methods + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +DefinitionBlock ( + "CPUPM.aml", + "SSDT", + 0x01, + "SsgPmm", + "CpuPm", + 0x0010 + ) +{ + External(\_PR.CPU0, DeviceObj) + External(CFGD, FieldUnitObj) + + Scope(\) + { + // Config DWord, modified during POST + // Bit definitions are the same as PPMFlags: + // CFGD[0] = PPM_GV3 = GV3 + // CFGD[1] = PPM_TURBO = Turbo Mode + // CFGD[2] = PPM_SUPER_LFM = N/2 Ratio + // CFGD[4] = PPM_C1 = C1 Capable, Enabled + // CFGD[5] = PPM_C2 = C2 Capable, Enabled + // CFGD[6] = PPM_C3 = C3 Capable, Enabled + // CFGD[7] = PPM_C4 = C4 Capable, Enabled + // CFGD[8] = PPM_C5 = C5/Deep C4 Capable, Enabled + // CFGD[9] = PPM_C6 = C6 Capable, Enabled + // CFGD[10] = PPM_C1E = C1E Enabled + // CFGD[11] = PPM_C2E = C2E Enabled + // CFGD[12] = PPM_C3E = C3E Enabled + // CFGD[13] = PPM_C4E = C4E Enabled + // CFGD[14] = PPM_HARD_C4E = Hard C4E Capable, Enabled + // CFGD[16] = PPM_TM1 = Thermal Monitor 1 + // CFGD[17] = PPM_TM2 = Thermal Monitor 2 + // CFGD[19] = PPM_PHOT = Bi-directional ProcHot + // CFGD[21] = PPM_MWAIT_EXT = MWAIT extensions supported + // CFGD[24] = PPM_CMP = CMP supported, Enabled + // CFGD[28] = PPM_TSTATE = CPU T states supported + // + // Name(CFGD, 0x80000000) + // External Defined in GNVS + + Name(PDC0,0x80000000) // CPU0 _PDC Flags. + + // We load it in AcpiPlatform + //Name(SSDT,Package() + //{ + // "CPU0IST ", 0x80000000, 0x80000000, + // "CPU1IST ", 0x80000000, 0x80000000, + // "CPU0CST ", 0x80000000, 0x80000000, + // "CPU1CST ", 0x80000000, 0x80000000, + //}) + } + Scope(\_PR.CPU0) + { + Method(_PDC, 1) + { + // + // Store result of PDC. + // + CreateDWordField(Arg0,8,CAP0) // Point to 3rd DWORD. + Store(CAP0,PDC0) // Store It in PDC0. + } + } + +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/AD7298.asi b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/AD7298.asi new file mode 100644 index 0000000000..ea59fb0860 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/AD7298.asi @@ -0,0 +1,38 @@ +/** @file +Analog devices AD7298 ADC. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Device(ADC1) +{ + Name(_HID, "INT3494") // Galileo Version 1 Low-Speed ADC. + Name(_CID, "INT3494") + Name(RBUF, ResourceTemplate() + { + // SPI0: mode 2, 4Mhz, 16-bit data length + SpiSerialBus (0x0000, PolarityLow, FourWireMode, 16, ControllerInitiated, 4000000, ClockPolarityHigh, ClockPhaseFirst, "\\_SB_.PCI0.SPI0",0x00, ResourceConsumer, ,) + + // GPIO<0> is SPI0_CS_N + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {QUARK_GPIO0_MAPPING} + }) + Method(_CRS, 0x0, NotSerialized) + { + Return(RBUF) + } + Method(_STA, 0x0, NotSerialized) + { + // + // Only Galileo platform has this device. + // EFI_PLATFORM_TYPE enum value Galileo = 6. + // + If(LNotEqual(PTYP, 6)) + { + return (0) + } + Return(0xf) + } +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/ADC108S102.asi b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/ADC108S102.asi new file mode 100644 index 0000000000..de651576b8 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/ADC108S102.asi @@ -0,0 +1,33 @@ +/** @file +TI ADC108S102 ADC. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Device(ADC2) +{ + Name(_HID, "INT3495") // GalileoGen2 Low-Speed ADC. + Name(_CID, "INT3495") + Name(RBUF, ResourceTemplate() + { + SPISerialBus(0x0000, PolarityLow, ThreeWireMode, 0x10, ControllerInitiated, 0x1E8480, ClockPolarityLow, ClockPhaseFirst, "\\_SB.PCI0.SPI0", 0x00, ResourceConsumer, ,) + }) + Method(_CRS, 0x0, NotSerialized) + { + Return(RBUF) + } + Method(_STA, 0x0, NotSerialized) + { + // + // Only Platform Type / Id 8 has this device. + // + If(LNotEqual(PTYP, 8)) + { + return (0) + } + Return(0xf) + } +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CAT24C08.asi b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CAT24C08.asi new file mode 100644 index 0000000000..ac6df50ae5 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CAT24C08.asi @@ -0,0 +1,34 @@ +/** @file +ONSEMI CAT24C08 I2C 8KB EEPROM. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Device(EEP2) +{ + Name(_HID, "INT3499") // ONSEMI CAT24C08 I2C 8KB EEPROM. + Name(_CID, "INT3499") + + Name(RBUF, ResourceTemplate() + { + I2CSerialBus(0x54, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , ) + }) + Method(_CRS, 0x0, NotSerialized) + { + Return(RBUF) + } + Method(_STA, 0x0, NotSerialized) + { + // + // Only Platform Type / Id 8 has this device. + // + If(LNotEqual(PTYP, 8)) + { + return (0) + } + Return(0xf) + } +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CY8C9540A.asi b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CY8C9540A.asi new file mode 100644 index 0000000000..b5a5f3b680 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CY8C9540A.asi @@ -0,0 +1,47 @@ +/** @file + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +CY8C9540A 40 Bit I/O Expander with EEPROM. + +**/ + +Device(CY8C) +{ + Name(_HID, "INT3490") // Cypress CY8C9540A Io Expander Function. + Name(_CID, "INT3490") + + Name(RBUF, ResourceTemplate() + { + I2CSerialBus(0x20, ControllerInitiated, 100000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , ) + GpioInt (Level, ActiveLow, Exclusive, PullDefault, , "\\_SB.PCI0.GIP0.GPO", 0, ResourceConsumer, , ) {QUARK_GPIO5_MAPPING} /* GPIO<5> is INT_S0 */ + }) + Method(_CRS, 0x0, NotSerialized) + { + CreateByteField(RBUF, 16, OB1) + if (LEqual (ALTS, 0)) + { + Store(0x20, OB1) + } + Else + { + Store(0x21, OB1) + } + Return(RBUF) + } + Method(_STA, 0x0, NotSerialized) + { + // + // Only Galileo platform has this device. + // EFI_PLATFORM_TYPE enum value Galileo = 6. + // + If(LNotEqual(PTYP, 6)) + { + return (0) + } + Return(0xf) + } +} + diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/GpioClient.asi b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/GpioClient.asi new file mode 100644 index 0000000000..9a5812d068 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/GpioClient.asi @@ -0,0 +1,89 @@ +/** @file +Expose GPIO resources to usermode through client driver. + +Copyright (c) 2013-2019 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Device(GPOT) +{ + Name(_HID, "INT349A") + Name(_CID, "INT349A") + Method(_CRS, 0x0, Serialized) + { + Name(RBUF, ResourceTemplate() + { + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x1} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x2} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x3} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x4} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x5} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x6} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x7} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x8} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x9} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xa} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xb} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xc} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xd} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xe} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xf} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x2} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x3} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x4} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x5} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x6} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x7} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x8} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x9} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xa} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xb} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xc} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xd} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xe} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xf} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x10} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x11} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x12} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x13} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x14} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x15} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x16} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x17} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x18} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x19} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1a} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1b} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1c} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1d} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1e} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1f} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x20} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x21} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x22} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x23} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x24} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x25} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x26} + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x27} + }) + Return(RBUF) + } + Method(_STA, 0x0, NotSerialized) + { + // + // Only Galileo platform has this device. + // EFI_PLATFORM_TYPE enum value Galileo = 6. + // + If(LNotEqual(PTYP, 6)) + { + return (0) + } + Return(0xf) + } +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/LpcDev.asi b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/LpcDev.asi new file mode 100644 index 0000000000..8df07a70a3 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/LpcDev.asi @@ -0,0 +1,248 @@ +/** @file +Legacy resource template + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef LPC_DEV_ASI +#define LPC_DEV_ASI + +Device(RTC) +{ + Name(_HID,EISAID("PNP0B00")) + Name(BUF0,ResourceTemplate() { + IO(Decode16,0x70,0x70,0x01,0x04) + IO(Decode16,0x74,0x74,0x01,0x04) + }) + Name(BUF1,ResourceTemplate() { + IO(Decode16,0x70,0x70,0x01,0x04) + IO(Decode16,0x74,0x74,0x01,0x04) + IRQNoFlags(){8} + }) + Method(_CRS,0,Serialized) + { + If (HPEA) + { + return (BUF0) + } + Else + { + return (BUF1) + } + } +} + +Device(PIC) +{ + Name(_HID,EISAID("PNP0000")) + + Name(_CRS,ResourceTemplate() { + IO(Decode16,0x20,0x20,0x01,0x1E) // length of 1Eh includes all aliases + IO(Decode16,0xA0,0xA0,0x01,0x1E) + IO(Decode16,0x4D0,0x4D0,0x01,0x02) + }) +} + +Device(TMR) +{ + Name(_HID,EISAID("PNP0100")) + + Name(BUF0,ResourceTemplate() { + IO(Decode16,0x40,0x40,0x01,0x04) + IO(Decode16,0x50,0x50,0x01,0x04) // alias + }) + Name(BUF1,ResourceTemplate() { + IO(Decode16,0x40,0x40,0x01,0x04) + IO(Decode16,0x50,0x50,0x01,0x04) // alias + IRQNoFlags(){0} + }) + Method(_CRS,0,Serialized) + { + If (HPEA) + { + return (BUF0) + } + Else + { + return (BUF1) + } + } +} + +Device(SPKR) +{ + Name(_HID,EISAID("PNP0800")) + + Name(_CRS,ResourceTemplate() { + IO(Decode16,0x61,0x61,0x01,0x01) + }) +} + +Device(XTRA) // all "PNP0C02" devices- pieces that don't fit anywhere else +{ + Name(_HID,EISAID("PNP0C02")) // Generic motherboard devices + + Name(CRS, + ResourceTemplate() + { + IO(Decode16,0x2E,0x2E,0x01,0x02) + IO(Decode16,0x4E,0x2E,0x01,0x02) + IO(Decode16,0x63,0x61,0x01,0x01) + IO(Decode16,0x65,0x61,0x01,0x01) + IO(Decode16,0x67,0x61,0x01,0x01) + IO(Decode16,0x80,0x80,0x01,0x01) + IO(Decode16,0x84,0x84,0x01,0x04) + IO(Decode16,0x88,0x88,0x01,0x01) + IO(Decode16,0x8c,0x8c,0x01,0x03) + IO(Decode16,0x92,0x92,0x01,0x01) + + IO( + Decode16, + 0, + 0, + 0x01, + 0x10, + FIX1 + ) + + IO( + Decode16, + 0, + 0, + 0x01, + 0x10, + FIX2 + ) + + IO( + Decode16, + 0, + 0, + 0x01, + 0x40, + FIX3 + ) + + IO( + Decode16, + 0, + 0, + 0x01, + 0x40, + FIX5 + ) + + IO( + Decode16, + 0, + 0, + 0x01, + 0x40, + FIX6 + ) + + } + ) + + Method (_CRS, 0, NotSerialized) { + CreateWordField (CRS, ^FIX1._MIN, MBR0) + Store(\P1BB, MBR0) + CreateWordField (CRS, ^FIX1._MAX, MBR1) + Store(\P1BB, MBR1) + CreateWordField (CRS, ^FIX2._MIN, MBR2) + Store(\PBAB, MBR2) + CreateWordField (CRS, ^FIX2._MAX, MBR3) + Store(\PBAB, MBR3) + CreateWordField (CRS, ^FIX3._MIN, MBR4) + Store(\GP0B, MBR4) + CreateWordField (CRS, ^FIX3._MAX, MBR5) + Store(\GP0B, MBR5) + CreateWordField (CRS, ^FIX5._MIN, MBR8) + Store(\SMBB, MBR8) + CreateWordField (CRS, ^FIX5._MAX, MBR9) + Store(\SMBB, MBR9) + CreateWordField (CRS, ^FIX6._MIN, MBRA) + Store(\WDTB, MBRA) + CreateWordField (CRS, ^FIX6._MAX, MBRB) + Store(\WDTB, MBRB) + return (CRS) + } +} + +Device(LGIO) // Legacy GPIO. +{ + Name(_HID, "INT3488") + Name(_CID, "INT3488") + + Name(CRS, + ResourceTemplate() + { + IO( + Decode16, + 0, + 0, + 0x01, + 0x48, + FIX4 + ) + } + ) + + Method (_CRS, 0, NotSerialized) { + CreateWordField (CRS, ^FIX4._MIN, MBR6) + Store(\GPAB, MBR6) + CreateWordField (CRS, ^FIX4._MAX, MBR7) + Store(\GPAB, MBR7) + return (CRS) + } +} + +Device(HPET) // High Performance Event Timer +{ + Name(_HID,EISAID("PNP0103")) + + Name(BUF0,ResourceTemplate() + { + IRQNoFlags() {0} + IRQNoFlags() {8} + Memory32Fixed(ReadOnly, 0, 0, FIX1) + }) + + Method(_STA,0) + { + // Show this Device only if the OS is WINXP or beyond. + + If(LGreaterEqual(OSTP,WINDOWS_XP)) + { + If(HPEA) + { + Return(0x000F) // Enabled, do Display. + } + } + Else + { + // OS = WIN98, WINME, or WIN2000. + + If(HPEA) + { + Return(0x000B) // Enabled, don't Display. + } + } + + Return(0x0000) // Return Nothing. + } + + Method(_CRS,0,Serialized) + { + CreateDWordField (BUF0, ^FIX1._BAS, MBR0) + Store(\HPTB, MBR0) + CreateDWordField (BUF0, ^FIX1._LEN, MBR1) + Store(\HPTS, MBR1) + Return(BUF0) + } +} + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCA9685.asi b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCA9685.asi new file mode 100644 index 0000000000..44fafbe999 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCA9685.asi @@ -0,0 +1,34 @@ +/** @file +NXP PCA9685 i2c-accessible PWM/LED controller. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Device(PWM1) +{ + Name(_HID, "INT3492") // NXP PCA9685 i2c-accessible PWM/LED controller. + Name(_CID, "INT3492") + + Name(RBUF, ResourceTemplate() + { + I2CSerialBus(0x47, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , ) + }) + Method(_CRS, 0x0, NotSerialized) + { + Return(RBUF) + } + Method(_STA, 0x0, NotSerialized) + { + // + // Only Platform Type / Id 8 has this device. + // + If(LNotEqual(PTYP, 8)) + { + return (0) + } + Return(0xf) + } +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCAL9555A.asi b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCAL9555A.asi new file mode 100644 index 0000000000..06517a7804 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCAL9555A.asi @@ -0,0 +1,90 @@ +/** @file +NXP PCAL9555A i2c-accessible I/O expander. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Device(NIO1) +{ + Name(_HID, "INT3491") // NXP PCAL9555A i2c-accessible I/O expander. + Name(_CID, "INT3491") + Name(_UID, 1) + + Name(RBUF, ResourceTemplate() + { + I2CSerialBus(0x25, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , ) + }) + Method(_CRS, 0x0, NotSerialized) + { + Return(RBUF) + } + Method(_STA, 0x0, NotSerialized) + { + // + // Only Platform Type / Id 8 has this device. + // + If(LNotEqual(PTYP, 8)) + { + return (0) + } + Return(0xf) + } +} + +Device(NIO2) +{ + Name(_HID, "INT3491") // NXP PCAL9555A i2c-accessible I/O expander. + Name(_CID, "INT3491") + Name(_UID, 2) + + Name(RBUF, ResourceTemplate() + { + I2CSerialBus(0x26, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , ) + }) + Method(_CRS, 0x0, NotSerialized) + { + Return(RBUF) + } + Method(_STA, 0x0, NotSerialized) + { + // + // Only Platform Type / Id 8 has this device. + // + If(LNotEqual(PTYP, 8)) + { + return (0) + } + Return(0xf) + } +} + +Device(NIO3) +{ + Name(_HID, "INT3491") // NXP PCAL9555A i2c-accessible I/O expander. + Name(_CID, "INT3491") + Name(_UID, 3) + + Name(RBUF, ResourceTemplate() + { + I2CSerialBus(0x27, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , ) + GpioInt (Level, ActiveLow, Exclusive, PullDefault, , "\\_SB.PCI0.GIP0.GPO", 0, ResourceConsumer, , ) {QUARK_GPIO1_MAPPING} /* GPIO<1> is EXP2_INT */ + }) + Method(_CRS, 0x0, NotSerialized) + { + Return(RBUF) + } + Method(_STA, 0x0, NotSerialized) + { + // + // Only Platform Type / Id 8 has this device. + // + If(LNotEqual(PTYP, 8)) + { + return (0) + } + Return(0xf) + } +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciHostBridge.asi b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciHostBridge.asi new file mode 100644 index 0000000000..0535d479e5 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciHostBridge.asi @@ -0,0 +1,195 @@ +/** @file +PCI Host Bridge Definitions + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +Name(PBRS, ResourceTemplate() { + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity + 0x0000, // Min + 0x001f, // Max + 0x0000, // Translation + 0x0020 // Range Length = Max-Min+1 + ) + + WORDIO( //Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity + 0x0000, // Min + 0x0cf7, // Max + 0x0000, // Translation + 0x0cf8 // Range Length + ) + + IO( //Consumed resource (CF8-CFF) + Decode16, + 0x0cf8, + 0xcf8, + 1, + 8 + ) + + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity + 0x0d00, // Min + 0xffff, // Max + 0x0000, // Translation + 0xf300 // Range Length + ) + + DWORDMEMORY( // descriptor for dos area(0->0xa0000) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x000a0000, // Min + 0x000bffff, // Max + 0x00000000, // Translation + 0x00020000 // Range Length + ) + + DWORDMemory( // Consumed-and-produced resource for pci memory mapped memory + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Min (calculated dynamically) + + 0xfebfffff, // Max = IO Apic base address - 1 + 0x00000000, // Translation + 0xfec00000, // Range Length (calculated dynamically) + , // Optional field left blank + , // Optional field left blank + MEM1 // Name declaration for this descriptor + ) + +}) // end of CRES Buffer + + +Method(_CRS, 0x0, NotSerialized) +{ + CreateDWordField(PBRS, \_SB.PCI0.MEM1._MIN, MMIN) + CreateDWordField(PBRS, \_SB.PCI0.MEM1._MAX, MMAX) + CreateDWordField(PBRS, \_SB.PCI0.MEM1._LEN, MLEN) + + // HMBOUND is PCI memory base + And(MNRD(0x03, 0x08), 0xFFFFF000, MMIN) + Add(Subtract(MMAX, MMIN), 1, MLEN) + + Return(PBRS) +} + +// Message Nework Registers +OperationRegion(MNR, PCI_Config, 0xD0, 0x10) +Field(MNR, DWordAcc, NoLock, Preserve) +{ + MCR, 32, // Message Control Register + MDR, 32 // Message Data Register +} + +// Message Nework Read Method +// Arg0 = Port +// Arg1 = RegAddress +// return 32 bit register value +Method(MNRD, 2, Serialized) +{ + Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0) + Or(Local0, 0x100000F0, Local0) + Store(Local0, MCR) + Return(MDR) +} + +// Message Nework Write Method +// Arg0 = Port +// Arg1 = RegAddress +// Arg2 = 32 bit write value +Method(MNWR, 3, Serialized) +{ + Store(Arg2, MDR) + Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0) + Or(Local0, 0x110000F0, Local0) + Store(Local0, MCR) +} + +Method(_PRT, 0, NotSerialized) +{ + If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing + { + Return ( + Package() + { + // Bus 0, Device 20 - IOSFAHB Bridge + Package() {0x0014ffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // INTA + Package() {0x0014ffff, 1, \_SB.PCI0.LPC.LNKB, 0}, // INTB + Package() {0x0014ffff, 2, \_SB.PCI0.LPC.LNKC, 0}, // INTC + Package() {0x0014ffff, 3, \_SB.PCI0.LPC.LNKD, 0}, // INTD + + // Bus 0, Device 21 - IOSFAHB Bridge + Package() {0x0015ffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // INTA + Package() {0x0015ffff, 1, \_SB.PCI0.LPC.LNKB, 0}, // INTB + Package() {0x0015ffff, 2, \_SB.PCI0.LPC.LNKC, 0}, // INTC + Package() {0x0015ffff, 3, \_SB.PCI0.LPC.LNKD, 0}, // INTD + + // Bus 0, Device 23 - PCIe port 0 + Package() {0x0017ffff, 0, \_SB.PCI0.LPC.LNKE, 0}, // INTA + Package() {0x0017ffff, 1, \_SB.PCI0.LPC.LNKF, 0}, // INTB + Package() {0x0017ffff, 2, \_SB.PCI0.LPC.LNKG, 0}, // INTC + Package() {0x0017ffff, 3, \_SB.PCI0.LPC.LNKH, 0}, // INTD + + // Bus 0, Device 31 + Package() {0x001fffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // LPC Bridge + } + ) + } + else { + Return ( + Package() + { + // Bus 0, Device 20 - IOSFAHB Bridge + Package() {0x0014ffff, 0, 0, 16}, // INTA + Package() {0x0014ffff, 1, 0, 17}, // INTB + Package() {0x0014ffff, 2, 0, 18}, // INTC + Package() {0x0014ffff, 3, 0, 19}, // INTD + + // Bus 0, Device 21 - IOSFAHB Bridge + Package() {0x0015ffff, 0, 0, 16}, // INTA + Package() {0x0015ffff, 1, 0, 17}, // INTB + Package() {0x0015ffff, 2, 0, 18}, // INTC + Package() {0x0015ffff, 3, 0, 19}, // INTD + + // Bus 0, Device 23 - PCIe port 0 + Package() {0x0017ffff, 0, 0, 20}, // INTA + Package() {0x0017ffff, 1, 0, 21}, // INTB + Package() {0x0017ffff, 2, 0, 22}, // INTC + Package() {0x0017ffff, 3, 0, 23}, // INTD + + // Bus 0, Device 31 + Package() {0x001fffff, 0, 0, 16}, // LPC Bridge + } + ) + } +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciIrq.asi b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciIrq.asi new file mode 100644 index 0000000000..c030047666 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciIrq.asi @@ -0,0 +1,552 @@ +/** @file + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +// Interrupts can be DEB8=all except 13,8,6,2,1,0 + +#ifndef PCIIRQ_ASI +#define PCIIRQ_ASI + +OperationRegion(PRR0, PCI_Config, 0x60, 0x08) +Field(PRR0, ANYACC, NOLOCK, PRESERVE) +{ + PIRA, 8, + PIRB, 8, + PIRC, 8, + PIRD, 8, + PIRE, 8, + PIRF, 8, + PIRG, 8, + PIRH, 8 +} + +Device(LNKA) // PCI IRQ link A +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID, 1) + + Method(_STA,0,NotSerialized) + { + If(And(PIRA, 0x80)) + { + Return(0x9) + } + Else + { + Return(0xB) + } // Don't display + } + + Method(_DIS,0,NotSerialized) + { + Or(PIRA, 0x80, PIRA) + } + + Method(_CRS,0,Serialized) + { + Name(BUF0, + ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + + // Define references to buffer elements + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // Write current settings into IRQ descriptor + If (And(PIRA, 0x80)) + { + Store(Zero, Local0) + } + Else + { + Store(One,Local0) + } + // Shift 1 by value in register 70 + ShiftLeft(Local0,And(PIRA,0x0F),IRQW) // Save in buffer + Return(BUF0) // Return Buf0 + } // End of _CRS method + + Name(_PRS, + ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}}) + + Method(_SRS,1,NotSerialized) + { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual(IRQW,Zero)) + { + And(Local0, 0x7F,Local0) + Decrement(Local0) + } + Else + { + Or(Local0, 0x80,Local0) + } + store(Local0, PIRA) + } // End of _SRS Method +} + +Device(LNKB) // PCI IRQ link B +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID, 2) + + Method(_STA,0,NotSerialized) + { + If(And(PIRB, 0x80)) + { + Return(0x9) + } + Else + { + Return(0xB) + } // Don't display + } + + Method(_DIS,0,NotSerialized) + { + Or(PIRB, 0x80,PIRB) + } + + Method(_CRS,0,Serialized) + { + Name(BUF0, + ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // Define references to buffer elements + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // Write current settings into IRQ descriptor + If (And(PIRB, 0x80)) + { + Store(Zero, Local0) + } + Else + { + Store(One,Local0) + } + // Shift 1 by value in register 70 + ShiftLeft(Local0,And(PIRB,0x0F),IRQW) // Save in buffer + Return(BUF0) // Return Buf0 + } // End of _CRS method + + Name(_PRS, + ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}}) + + Method(_SRS,1,NotSerialized) + { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual(IRQW,Zero)) + { + And(Local0, 0x7F,Local0) + Decrement(Local0) + } + Else + { + Or(Local0, 0x80,Local0) + } + Store(Local0, PIRB) + } // End of _SRS Method +} + +Device(LNKC) // PCI IRQ link C +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID, 3) + + Method(_STA,0,NotSerialized) + { + If(And(PIRC, 0x80)) + { + Return(0x9) + } + Else + { + Return(0xB) + } // Don't display + } + + Method(_DIS,0,NotSerialized) + { + Or(PIRC, 0x80,PIRC) + } + + Method(_CRS,0,Serialized) + { + Name(BUF0, + ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // Define references to buffer elements + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // Write current settings into IRQ descriptor + If (And(PIRC, 0x80)) + { + Store(Zero, Local0) + } + Else + { + Store(One,Local0) + } // Shift 1 by value in register 70 + ShiftLeft(Local0,And(PIRC,0x0F),IRQW) // Save in buffer + Return(BUF0) // Return Buf0 + } // End of _CRS method + + Name(_PRS, + ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}}) + + Method(_SRS,1,NotSerialized) + { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual(IRQW,Zero)) + { + And(Local0, 0x7F,Local0) + Decrement(Local0) + } + Else { + Or(Local0, 0x80,Local0) + } + Store(Local0, PIRC) + } // End of _SRS Method +} + +Device(LNKD) // PCI IRQ link D +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID, 4) + + Method(_STA,0,NotSerialized) + { + If(And(PIRD, 0x80)) + { + Return(0x9) + } + Else + { + Return(0xB) + } // Don't display + } + + Method(_DIS,0,NotSerialized) + { + Or(PIRD, 0x80,PIRD) + } + + Method(_CRS,0,Serialized) + { + Name(BUF0, + ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // Define references to buffer elements + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // Write current settings into IRQ descriptor + If (And(PIRD, 0x80)) + { + Store(Zero, Local0) + } + Else + { + Store(One,Local0) + } // Shift 1 by value in register 70 + ShiftLeft(Local0,And(PIRD,0x0F),IRQW) // Save in buffer + Return(BUF0) // Return Buf0 + } // End of _CRS method + + Name(_PRS, + ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}}) + + Method(_SRS,1,NotSerialized) + { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + + FindSetRightBit(IRQW,Local0)// Set IRQ + If (LNotEqual(IRQW,Zero)) + { + And(Local0, 0x7F,Local0) + Decrement(Local0) + } + Else + { + Or(Local0, 0x80,Local0) + } + Store(Local0, PIRD) + } // End of _SRS Method +} + +Device(LNKE) // PCI IRQ link E +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID, 5) + + Method(_STA,0,NotSerialized) + { + If(And(PIRE, 0x80)) + { + Return(0x9) + } + Else + { + Return(0xB) + } // Don't display + } + + Method(_DIS,0,NotSerialized) + { + Or(PIRE, 0x80, PIRE) + } + + Method(_CRS,0,Serialized) + { + Name(BUF0, + ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + + // Define references to buffer elements + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // Write current settings into IRQ descriptor + If (And(PIRE, 0x80)) + { + Store(Zero, Local0) + } + Else + { + Store(One,Local0) + } + // Shift 1 by value in register 70 + ShiftLeft(Local0,And(PIRE,0x0F),IRQW) // Save in buffer + Return(BUF0) // Return Buf0 + } // End of _CRS method + + Name(_PRS, + ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}}) + + Method(_SRS,1,NotSerialized) + { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual(IRQW,Zero)) + { + And(Local0, 0x7F,Local0) + Decrement(Local0) + } + Else + { + Or(Local0, 0x80,Local0) + } + store(Local0, PIRE) + } // End of _SRS Method +} + +Device(LNKF) // PCI IRQ link F +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID, 6) + + Method(_STA,0,NotSerialized) + { + If(And(PIRF, 0x80)) + { + Return(0x9) + } + Else + { + Return(0xB) + } // Don't display + } + + Method(_DIS,0,NotSerialized) + { + Or(PIRB, 0x80,PIRF) + } + + Method(_CRS,0,Serialized) + { + Name(BUF0, + ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // Define references to buffer elements + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // Write current settings into IRQ descriptor + If (And(PIRF, 0x80)) + { + Store(Zero, Local0) + } + Else + { + Store(One,Local0) + } + // Shift 1 by value in register 70 + ShiftLeft(Local0,And(PIRF,0x0F),IRQW) // Save in buffer + Return(BUF0) // Return Buf0 + } // End of _CRS method + + Name(_PRS, + ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}}) + + Method(_SRS,1,NotSerialized) + { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual(IRQW,Zero)) + { + And(Local0, 0x7F,Local0) + Decrement(Local0) + } + Else + { + Or(Local0, 0x80,Local0) + } + Store(Local0, PIRF) + } // End of _SRS Method +} + +Device(LNKG) // PCI IRQ link G +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID, 7) + + Method(_STA,0,NotSerialized) + { + If(And(PIRG, 0x80)) + { + Return(0x9) + } + Else + { + Return(0xB) + } // Don't display + } + + Method(_DIS,0,NotSerialized) + { + Or(PIRG, 0x80,PIRG) + } + + Method(_CRS,0,Serialized) + { + Name(BUF0, + ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // Define references to buffer elements + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // Write current settings into IRQ descriptor + If (And(PIRG, 0x80)) + { + Store(Zero, Local0) + } + Else + { + Store(One,Local0) + } // Shift 1 by value in register 70 + ShiftLeft(Local0,And(PIRG,0x0F),IRQW) // Save in buffer + Return(BUF0) // Return Buf0 + } // End of _CRS method + + Name(_PRS, + ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}}) + + Method(_SRS,1,NotSerialized) + { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual(IRQW,Zero)) + { + And(Local0, 0x7F,Local0) + Decrement(Local0) + } + Else { + Or(Local0, 0x80,Local0) + } + Store(Local0, PIRG) + } // End of _SRS Method +} + +Device(LNKH) // PCI IRQ link H +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID, 8) + + Method(_STA,0,NotSerialized) + { + If(And(PIRH, 0x80)) + { + Return(0x9) + } + Else + { + Return(0xB) + } // Don't display + } + + Method(_DIS,0,NotSerialized) + { + Or(PIRH, 0x80,PIRH) + } + + Method(_CRS,0,Serialized) + { + Name(BUF0, + ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // Define references to buffer elements + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // Write current settings into IRQ descriptor + If (And(PIRH, 0x80)) + { + Store(Zero, Local0) + } + Else + { + Store(One,Local0) + } // Shift 1 by value in register 70 + ShiftLeft(Local0,And(PIRH,0x0F),IRQW) // Save in buffer + Return(BUF0) // Return Buf0 + } // End of _CRS method + + Name(_PRS, + ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}}) + + Method(_SRS,1,NotSerialized) + { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + + FindSetRightBit(IRQW,Local0)// Set IRQ + If (LNotEqual(IRQW,Zero)) + { + And(Local0, 0x7F,Local0) + Decrement(Local0) + } + Else + { + Or(Local0, 0x80,Local0) + } + Store(Local0, PIRH) + } // End of _SRS Method +} + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PcieExpansionPrt.asi b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PcieExpansionPrt.asi new file mode 100644 index 0000000000..e41230867e --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PcieExpansionPrt.asi @@ -0,0 +1,127 @@ +/** @file +PCI express expansion ports + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PcieExpansionPrt_asi +#define PcieExpansionPrt_asi + +Device (PEX0) // PCI express bus bridged from [Bus 0, Device 23, Function 0] +{ + Name(_ADR,0x00170000) // Device (HI WORD)=23, Func (LO WORD)=0 + Name(_PRW,Package(){0x11,0x03}) // GPE pin 0x11, Wake from S3 -- PCI PME# + + OperationRegion (PES0,PCI_Config,0x40,0xA0) + Field (PES0, AnyAcc, NoLock, Preserve) + { + Offset(0x1A), // SLSTS - Slot Status Register + ABP0, 1, // Bit 0, Attention Button Pressed + , 2, + PDC0, 1, // Bit 3, Presence Detect Changed + , 2, + PDS0, 1, // Bit 6, Presence Detect State + , 1, + LSC0, 1, // Bit 8, Link Active State Changed + offset (0x20), + , 16, + PMS0, 1, // Bit 16, PME Status + offset (0x98), + , 30, + HPE0, 1, // Bit 30, Hot Plug SCI Enable + PCE0, 1, // Bit 31, Power Management SCI Enable. + , 30, + HPS0, 1, // Bit 30, Hot Plug SCI Status + PCS0, 1, // Bit 31, Power Management SCI Status. + } + + Method(_PRT,0,NotSerialized) { + If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing + { + Return ( + Package() + { + // Port 0: INTA->PIRQE,INTB->PIRQF,INTC->PIRQG,INTD->PIRQH + Package() {0x0000ffff, 0, \_SB_.PCI0.LPC.LNKE, 0}, // PCI Slot 1 + Package() {0x0000ffff, 1, \_SB_.PCI0.LPC.LNKF, 0}, + Package() {0x0000ffff, 2, \_SB_.PCI0.LPC.LNKG, 0}, + Package() {0x0000ffff, 3, \_SB_.PCI0.LPC.LNKH, 0}, + } + ) + } + else // IOAPIC Routing + { + Return ( + Package() + { + // Port 0: INTA->PIRQE,INTB->PIRQF,INTC->PIRQG,INTD->PIRQH + Package() {0x0000ffff, 0, 0, 20}, // PCI Slot 1 + Package() {0x0000ffff, 1, 0, 21}, + Package() {0x0000ffff, 2, 0, 22}, + Package() {0x0000ffff, 3, 0, 23}, + } + ) + } + } +} + +Device (PEX1) // PCI express bus bridged from [Bus 0, Device 23, Function 1] +{ + Name(_ADR,0x00170001) // Device (HI WORD)=23, Func (LO WORD)=1 + Name(_PRW,Package(){0x11,0x03}) // GPE pin 0x11, Wake from S3 -- PCI PME# + OperationRegion (PES1,PCI_Config,0x40,0xA0) + Field (PES1, AnyAcc, NoLock, Preserve) + { + Offset(0x1A), // SLSTS - Slot Status Register + ABP1, 1, // Bit 0, Attention Button Pressed + , 2, + PDC1, 1, // Bit 3, Presence Detect Changed + , 2, + PDS1, 1, // Bit 6, Presence Detect State + , 1, + LSC1, 1, // Bit 8, Link Active State Changed + offset (0x20), + , 16, + PMS1, 1, // Bit 16, PME Status + offset (0x98), + , 30, + HPE1, 1, // Bit 30, Hot Plug SCI Enable + PCE1, 1, // Bit 31, Power Management SCI Enable. + , 30, + HPS1, 1, // Bit 30, Hot Plug SCI Status + PCS1, 1, // Bit 31, Power Management SCI Status. + } + Method(_PRT,0,NotSerialized) { + If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing + { + Return ( + Package() + { + // Port 1: INTA->PIRQF,INTB->PIRQG,INTC->PIRQH,INTD->PIRQE + Package() {0x0000ffff, 0, \_SB_.PCI0.LPC.LNKF, 0}, + Package() {0x0000ffff, 1, \_SB_.PCI0.LPC.LNKG, 0}, + Package() {0x0000ffff, 2, \_SB_.PCI0.LPC.LNKH, 0}, + Package() {0x0000ffff, 3, \_SB_.PCI0.LPC.LNKE, 0}, + } + ) + } + else // IOAPIC Routing + { + Return ( + Package() + { + // Port 1: INTA->PIRQF,INTB->PIRQG,INTC->PIRQH,INTD->PIRQE + Package() {0x0000ffff, 0, 0, 21}, + Package() {0x0000ffff, 1, 0, 22}, + Package() {0x0000ffff, 2, 0, 23}, + Package() {0x0000ffff, 3, 0, 20}, + } + ) + } + } +} + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Platform.asl b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Platform.asl new file mode 100644 index 0000000000..35bae8248a --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Platform.asl @@ -0,0 +1,347 @@ +/** @file +Contains root level name space objects for the platform + +Copyright (c) 2013-2019 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// OS TYPE DEFINITION +// +#define WINDOWS_XP 0x01 +#define WINDOWS_XP_SP1 0x02 +#define WINDOWS_XP_SP2 0x04 +#define WINDOWS_2003 0x08 +#define WINDOWS_Vista 0x10 +#define WINDOWS_WIN7 0x11 +#define WINDOWS_WIN8 0x12 +#define WINDOWS_WIN8_1 0x13 +#define LINUX 0xF0 + +// +// GPIO Interrupt Connection Resource Descriptor (GpioInt) usage. +// GpioInt() descriptors maybe used in this file and included .asi files. +// +// The mapping below was provided by the first OS user that requested +// GpioInt() support. +// Other OS users that need GpioInt() support must use the following mapping. +// +#define QUARK_GPIO8_MAPPING 0x00 +#define QUARK_GPIO9_MAPPING 0x01 +#define QUARK_GPIO_SUS0_MAPPING 0x02 +#define QUARK_GPIO_SUS1_MAPPING 0x03 +#define QUARK_GPIO_SUS2_MAPPING 0x04 +#define QUARK_GPIO_SUS3_MAPPING 0x05 +#define QUARK_GPIO_SUS4_MAPPING 0x06 +#define QUARK_GPIO_SUS5_MAPPING 0x07 +#define QUARK_GPIO0_MAPPING 0x08 +#define QUARK_GPIO1_MAPPING 0x09 +#define QUARK_GPIO2_MAPPING 0x0A +#define QUARK_GPIO3_MAPPING 0x0B +#define QUARK_GPIO4_MAPPING 0x0C +#define QUARK_GPIO5_MAPPING 0x0D +#define QUARK_GPIO6_MAPPING 0x0E +#define QUARK_GPIO7_MAPPING 0x0F + +DefinitionBlock ( + "Platform.aml", + "DSDT", + 1, + "INTEL ", + "QuarkNcS", + 3) +{ + // + // Global Variables + // + Name(\GPIC, 0x0) + + // + // Port 80 + // + OperationRegion (DBG0, SystemIO, 0x80, 1) + Field (DBG0, ByteAcc, NoLock, Preserve) + { IO80,8 } + + // + // Access CMOS range + // + OperationRegion (ACMS, SystemIO, 0x72, 2) + Field (ACMS, ByteAcc, NoLock, Preserve) + { INDX, 8, DATA, 8 } + + // + // Global NVS Memory Block + // + OperationRegion (MNVS, SystemMemory, 0xFFFF0000, 512) + Field (MNVS, ByteAcc, NoLock, Preserve) + { + OSTP, 32, + CFGD, 32, + HPEA, 32, // HPET Enabled ? + + P1BB, 32, // Pm1blkIoBaseAddress; + PBAB, 32, // PmbaIoBaseAddress; + GP0B, 32, // Gpe0blkIoBaseAddress; + GPAB, 32, // GbaIoBaseAddress; + + SMBB, 32, // SmbaIoBaseAddress; + NRV1, 32, // GNVS reserved field 1. + WDTB, 32, // WdtbaIoBaseAddress; + + HPTB, 32, // HpetBaseAddress; + HPTS, 32, // HpetSize; + PEXB, 32, // PciExpressBaseAddress; + PEXS, 32, // PciExpressSize; + + RCBB, 32, // RcbaMmioBaseAddress; + RCBS, 32, // RcbaMmioSize; + APCB, 32, // IoApicBaseAddress; + APCS, 32, // IoApicSize; + + TPMP, 32, // TpmPresent ? + DBGP, 32, // DBG2 Present? + PTYP, 32, // Set to one of EFI_PLATFORM_TYPE enums. + ALTS, 32, // Use alternate I2c SLA addresses. + } + + OperationRegion (GPEB, SystemIO, 0x1100, 0x40) //GPE Block + Field (GPEB, AnyAcc, NoLock, Preserve) + { + Offset(0x10), + SMIE, 32, // SMI Enable + SMIS, 32, // SMI Status + } + + // + // Processor Objects + // + Scope(\_PR) { + // + // IO base will be updated at runtime with search key "PRIO" + // + Processor (CPU0, 0x01, 0x4F495250, 0x06) {} + } + + // + // System Sleep States + // + Name (\_S0,Package (){0,0,0,0}) + Name (\_S3,Package (){5,0,0,0}) + Name (\_S4,Package (){6,0,0,0}) + Name (\_S5,Package (){7,0,0,0}) + + // + // General Purpose Event + // + Scope(\_GPE) + { + // + // EGPE generated GPE + // + Method(_L0D, 0x0, NotSerialized) + { + // + // Check EGPE for this wake event + // + Notify (\_SB.SLPB, 0x02) + + } + + // + // GPIO generated GPE + // + Method(_L0E, 0x0, NotSerialized) + { + // + // Check GPIO for this wake event + // + Notify (\_SB.PWRB, 0x02) + + } + + // + // SCLT generated GPE + // + Method(_L0F, 0x0, NotSerialized) + { + // + // Check SCLT for this wake event + // + Notify (\_SB.PCI0.SDIO, 0x02) + Notify (\_SB.PCI0.URT0, 0x02) + Notify (\_SB.PCI0.USBD, 0x02) + Notify (\_SB.PCI0.EHCI, 0x02) + Notify (\_SB.PCI0.OHCI, 0x02) + Notify (\_SB.PCI0.URT1, 0x02) + Notify (\_SB.PCI0.ENT0, 0x02) + Notify (\_SB.PCI0.ENT1, 0x02) + Notify (\_SB.PCI0.SPI0, 0x02) + Notify (\_SB.PCI0.SPI1, 0x02) + Notify (\_SB.PCI0.GIP0, 0x02) + + } + + // + // Remote Management Unit generated GPE + // + Method(_L10, 0x0, NotSerialized) + { + // + // Check Remote Management Unit for this wake event. + // + } + + // + // PCIE generated GPE + // + Method(_L11, 0x0, NotSerialized) + { + // + // Check PCIE for this wake event + // + Notify (\_SB.PCI0.PEX0, 0x02) + Notify (\_SB.PCI0.PEX1, 0x02) + } + } + + // + // define Sleeping button as mentioned in ACPI spec 2.0 + // + Device (\_SB.SLPB) + { + Name (_HID, EISAID ("PNP0C0E")) + Method (_PRW, 0, NotSerialized) + { + Return (Package (0x02) {0x0D,0x04}) + } + } + + // + // define Power Button + // + Device (\_SB.PWRB) + { + Name (_HID, EISAID ("PNP0C0C")) + Method (_PRW, 0, NotSerialized) + { + Return (Package (0x02) {0x0E,0x04}) + } + } + // + // System Wake up + // + Method(_WAK, 1, Serialized) + { + // Do nothing here + Return (0) + } + + // + // System sleep down + // + Method (_PTS, 1, NotSerialized) + { + // Get ready for S3 sleep + if (Lequal(Arg0,3)) + { + Store(0xffffffff,SMIS) // clear SMI status + Store(SMIE, Local0) // SMI Enable + Or(Local0,0x4,SMIE) // Generate SMI on sleep + } + } + + // + // Determing PIC mode + // + Method(\_PIC, 1, NotSerialized) + { + Store(Arg0,\GPIC) + } + + // + // System Bus + // + Scope(\_SB) + { + Device(PCI0) + { + Name(_HID,EISAID ("PNP0A08")) // PCI Express Root Bridge + Name(_CID,EISAID ("PNP0A03")) // Compatible PCI Root Bridge + + Name(_ADR,0x00000000) // Device (HI WORD)=0, Func (LO WORD)=0 + Method (_INI) + { + Store(LINUX, OSTP) // Set the default os is Linux + If (CondRefOf (_OSI)) + { + // + //_OSI is supported, so it is WinXp or Win2003Server + // + If (\_OSI("Windows 2001")) + { + Store (WINDOWS_XP, OSTP) + } + If (\_OSI("Windows 2001 SP1")) + { + Store (WINDOWS_XP_SP1, OSTP) + } + If (\_OSI("Windows 2001 SP2")) + { + Store (WINDOWS_XP_SP2, OSTP) + } + If (\_OSI("Windows 2001.1")) + { + Store (WINDOWS_2003, OSTP) + } + If (\_OSI("Windows 2006")) + { + Store (WINDOWS_Vista, OSTP) + } + If (\_OSI("Windows 2009")) + { + Store (WINDOWS_WIN7, OSTP) + } + If (\_OSI("Windows 2012")) + { + Store (WINDOWS_WIN8, OSTP) + } + If (\_OSI("Windows 2013")) + { + Store (WINDOWS_WIN8_1, OSTP) + } + If (\_OSI("Linux")) + { + Store (LINUX, OSTP) + } + } + } + + Include ("PciHostBridge.asi") // PCI0 Host bridge + Include ("QNC.asi") // QNC miscellaneous + Include ("PcieExpansionPrt.asi") // PCIe expansion bridges/devices + Include ("QuarkSouthCluster.asi") // Quark South Cluster devices + Include ("QNCLpc.asi") // LPC bridge device + Include ("QNCApic.asi") // QNC I/O Apic device + + } + + // + // Include asi files for I2C and SPI onboard devices. + // Devices placed here instead of below relevant controllers. + // Hardware topology information is maintained by the + // ResourceSource arg to the I2CSerialBus/SPISerialBus macros + // within the device asi files. + // + Include ("Tpm.asi") // TPM device. + Include ("CY8C9540A.asi") // CY8C9540A 40Bit I/O Expander & EEPROM + Include ("PCAL9555A.asi") // NXP PCAL9555A I/O expander. + Include ("PCA9685.asi") // NXP PCA9685 PWM/LED controller. + Include ("CAT24C08.asi") // ONSEMI CAT24C08 I2C 8KB EEPROM. + Include ("AD7298.asi") // Analog devices AD7298 ADC. + Include ("ADC108S102.asi") // TI ADC108S102 ADC. + Include ("GpioClient.asi") // Software device to expose GPIO + } +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNC.asi b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNC.asi new file mode 100644 index 0000000000..12ec4fab83 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNC.asi @@ -0,0 +1,49 @@ +/** @file +QNC devices + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef QNC_ASI +#define QNC_ASI + +Device(IOCM) // I/O controller miscellaneous +{ + Name(_HID,EISAID("PNP0C02")) // System board resources device node ID + + Name(CRS, ResourceTemplate() + { + + // PCIEXBAR memory range + Memory32Fixed(ReadOnly, 0, 0, FIX1) + + // RCRB memory range + Memory32Fixed(ReadOnly, 0, 0, FIX2) + + // Option ROM shadow memory range + Memory32Fixed(ReadOnly, 0x000C0000, 0x20000) + + // BIOS ROM shadow memory range + Memory32Fixed(ReadOnly, 0x000E0000, 0x20000) + + // BIOS Firmware just below 4GByte of memory 8MBytes + Memory32Fixed(ReadOnly, 0xFF800000, 0x800000) + } + ) + + Method (_CRS, 0, NotSerialized) { + CreateDWordField (CRS, ^FIX1._BAS, MBR0) + Store(\PEXB, MBR0) + CreateDWordField (CRS, ^FIX1._LEN, MBR1) + Store(\PEXS, MBR1) + CreateDWordField (CRS, ^FIX2._BAS, MBR2) + Store(\RCBB, MBR2) + CreateDWordField (CRS, ^FIX2._LEN, MBR3) + Store(\RCBS, MBR3) + Return (CRS) + } +} +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCApic.asi b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCApic.asi new file mode 100644 index 0000000000..717972a8ac --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCApic.asi @@ -0,0 +1,32 @@ +/** @file +QNC I/O Apic devices + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef QNC_APIC_ASI +#define QNC_APIC_ASI + +Device(APIC) +{ + Name(_HID,EISAID("PNP0003")) // APIC resources + + Name(CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0, 0, FIX1) // IO APIC + } + ) + + Method (_CRS, 0, NotSerialized) { + CreateDWordField (CRS, ^FIX1._BAS, MBR0) + Store(\APCB, MBR0) + CreateDWordField (CRS, ^FIX1._LEN, MBR1) + Store(\APCS, MBR1) + Return (CRS) + } +} + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCLpc.asi b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCLpc.asi new file mode 100644 index 0000000000..7f5fe0a87e --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCLpc.asi @@ -0,0 +1,23 @@ +/** @file +Lpc devices and control methods + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef QNC_LPC_ASI +#define QNC_LPC_ASI + +Device(LPC) +{ + Name(_ADR,0x001f0000) // Device (HI WORD)=31, Func (LO WORD)=0 + + Include ("PciIrq.asi") // PCI routing control methods + Include ("LpcDev.asi") // Static Lpc device resource declaration +} + + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QuarkSouthCluster.asi b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QuarkSouthCluster.asi new file mode 100644 index 0000000000..2c59285eb4 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QuarkSouthCluster.asi @@ -0,0 +1,110 @@ +/** @file +Quark South Cluster Devices. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef QuarkSouthCluster_asi +#define QuarkSouthCluster_asi + +Device (SDIO) // SDIO [Bus 0, Device 20, Function 0] +{ + Name(_ADR,0x00140000) // Device (HI WORD)=20, Func (LO WORD)=0 + Name(_STA,0xF) // Enabled, do Display + Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME# +} + +Device (URT0) // UART0 [Bus 0, Device 20, Function 1] +{ + Name(_ADR,0x00140001) // Device (HI WORD)=20, Func (LO WORD)=1 + Name(_STA,0xF) // Enabled, do Display + Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME# +} + +Device (USBD) // USB Device [Bus 0, Device 20, Function 2] +{ + Name(_ADR,0x00140002) // Device (HI WORD)=20, Func (LO WORD)=2 + Name(_STA,0xF) // Enabled, do Display + Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME# +} + +Device (EHCI) // EHCI [Bus 0, Device 20, Function 3] +{ + Name(_ADR,0x00140003) // Device (HI WORD)=20, Func (LO WORD)=3 + Name(_STA,0xF) // Enabled, do Display + Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME# +} + +Device (OHCI) // OHCI [Bus 0, Device 20, Function 4] +{ + Name(_ADR,0x00140004) // Device (HI WORD)=20, Func (LO WORD)=4 + Name(_STA,0xF) // Enabled, do Display + Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME# +} + +Device (URT1) // UART1 [Bus 0, Device 20, Function 5] +{ + Name(_ADR,0x00140005) // Device (HI WORD)=20, Func (LO WORD)=5 + Name(_STA,0xF) // Enabled, do Display + Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME# +} + +Device (ENT0) // Ethernet0 [Bus 0, Device 20, Function 6] +{ + Name(_ADR,0x00140006) // Device (HI WORD)=20, Func (LO WORD)=6 + Name(_STA,0xF) // Enabled, do Display + Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME# +} + +Device (ENT1) // Ethernet1 [Bus 0, Device 20, Function 7] +{ + Name(_ADR,0x00140007) // Device (HI WORD)=20, Func (LO WORD)=7 + Name(_STA,0xF) // Enabled, do Display + Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME# +} + +Device (SPI0) // SPI0 [Bus 0, Device 21, Function 0] +{ + Name(_ADR,0x00150000) // Device (HI WORD)=21, Func (LO WORD)=0 + Name(_STA,0xF) // Enabled, do Display + Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME# +} + +Device (SPI1) // SPI1 [Bus 0, Device 21, Function 1] +{ + Name(_ADR,0x00150001) // Device (HI WORD)=21, Func (LO WORD)=1 + Name(_STA,0xF) // Enabled, do Display + Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME# +} + +Device (GIP0) // I2C/GPIO [Bus 0, Device 21, Function 2] +{ + Name(_ADR,0x00150002) // Device (HI WORD)=21, Func (LO WORD)=2 + Name(_STA,0xF) // Enabled, do Display + Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME# + + Device(GPO_) // GPIO Virtual Child Device- for BAR0 resources + { + Name(_ADR, 0) + Name(_STA, 0xf) + Name(_PRW, Package(0x2) + { + 0xf, + 0x3 + }) + } + Device(I2C_) // I2C Controller Virtual Child Device- for BAR1 resources + { + Name(_ADR, 1) + Name(_STA, 0xf) + Name(_PRW, Package(0x2) + { + 0xf, + 0x3 + }) + } +} +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Tpm.asi b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Tpm.asi new file mode 100644 index 0000000000..716265596d --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Tpm.asi @@ -0,0 +1,45 @@ +/** @file + +The Infineon SLB9645 TPM ACPI definition block. +Provides TPM device info. and TPM presence check only. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Device (TPM) +{ + // + // Define _HID as Infineon TPM Device, _CID as "PNP0C31" (defined in + // "Secure Startup-FVE and TPM Admin BIOS and Platform Requirements"). + // + Name(_HID ,EISAID("INT3493")) + Name(_CID, EISAID("PNP0C31")) + + // + // Readable name of this device. + // + Name (_STR, Unicode ("Infineon TPM 1.2 Device (SLB9645TT1.2)")) + + // + // Return the resource consumed by TPM device. + // + Name (_CRS, ResourceTemplate () { + I2cSerialBus (0x20, ControllerInitiated, 0x00061A80, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer,,) + }) + + // + // Check if TPM present. + // + Method (_STA, 0) + { + if (LEqual (TPMP, 0)) + { + return (0) + } + Return (0x0f) + } + +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Facs/Facs.aslc b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Facs/Facs.aslc new file mode 100644 index 0000000000..a11fde1d6b --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Facs/Facs.aslc @@ -0,0 +1,74 @@ +/** @file +This file contains the FACS structure definition. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// Statements that include other files +// +#include "Facs.h" + +EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE FACS = { + EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, + sizeof (EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), + + // + // Hardware Signature will be updated at runtime + // + 0x00000000, + EFI_ACPI_FIRMWARE_WAKING_VECTOR, + EFI_ACPI_GLOBAL_LOCK, + EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS, + EFI_ACPI_X_FIRMWARE_WAKING_VECTOR, + EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, + { + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE + } +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) + +{ + // + // Reference the table being generated to prevent the optimizer from removing the + // data structure from the exeutable + // + return (VOID*)&FACS; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Facs/Facs.h b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Facs/Facs.h new file mode 100644 index 0000000000..3110ca0eb9 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Facs/Facs.h @@ -0,0 +1,29 @@ +/** @file +This file describes the contents of the ACPI Firmware ACPI Control Structure (FACS) +. Some additional ACPI values are defined in Acpi10.h, Acpi20.h, and Acpi30.h +All changes to the FACS contents should be done in this file. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FACS_H_ +#define _FACS_H_ + +// +// Statements that include other files +// +#include + +// +// FACS Definitions +// +#define EFI_ACPI_FIRMWARE_WAKING_VECTOR 0x00000000 +#define EFI_ACPI_GLOBAL_LOCK 0x00000000 + +#define EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS 0x00000000 +#define EFI_ACPI_X_FIRMWARE_WAKING_VECTOR 0x0000000000000000 + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.h b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.h new file mode 100644 index 0000000000..0876ea355e --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.h @@ -0,0 +1,102 @@ +/** @file +This file describes the contents of the ACPI Fixed ACPI Description Table (FADT) +. Some additional ACPI values are defined in Acpi10.h, Acpi20.h, and Acpi30.h +All changes to the FADT contents should be done in this file. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FADT_H_ +#define _FADT_H_ + +// +// Statements that include other files +// +#include + +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_OEM_ID 'I','N','T','E','L',' ' // OEMID 6 bytes long +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('T','I','A','N','O',' ',' ',' ') // OEM table id 8 bytes long +#define EFI_ACPI_OEM_REVISION 0x00000004 +#define EFI_ACPI_CREATOR_ID SIGNATURE_32('I','N','T','L') +#define EFI_ACPI_CREATOR_REVISION 0x0100000D + +// +// FADT Definitions +// +#define PM_PROFILE 0x01 +#define INT_MODEL 0x01 +#define SCI_INT_VECTOR 0x0009 +#define ACPI_ENABLE 0x0a0 +#define ACPI_DISABLE 0x0a1 +#define S4BIOS_REQ 0x00 +#define PM1_EVT_LEN 0x04 +#define PM1_CNT_LEN 0x02 +#define PM2_CNT_LEN 0x00 +#define PM_TM_LEN 0x04 +#define GPE0_BLK_LEN 0x08 +#define GPE1_BLK_LEN 0x00 +#define GPE1_BASE 0x00 +#define RESERVED 0x00 +#define P_LVL2_LAT 0x0065 +#define P_LVL3_LAT 0x03e9 +#define FLUSH_SIZE 0x0400 +#define FLUSH_STRIDE 0x0010 +#define DUTY_OFFSET 0x01 +#define DUTY_WIDTH 0x03 +#define DAY_ALRM 0x00 +#define MON_ALRM 0x00 +#define CENTURY 0x00 +#define IAPC_BOOT_ARCH EFI_ACPI_2_0_LEGACY_DEVICES +#define FLAG (EFI_ACPI_1_0_WBINVD | EFI_ACPI_1_0_PROC_C1 | EFI_ACPI_1_0_SLP_BUTTON | EFI_ACPI_1_0_RTC_S4) +#define FLAG2 (EFI_ACPI_2_0_WBINVD | EFI_ACPI_2_0_PROC_C1 | EFI_ACPI_2_0_PWR_BUTTON | EFI_ACPI_2_0_SLP_BUTTON | EFI_ACPI_2_0_RTC_S4 | EFI_ACPI_2_0_RESET_REG_SUP | EFI_ACPI_3_0_USE_PLATFORM_CLOCK) + +#define RESET_REG_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO +#define RESET_REG_BIT_WIDTH 0x08 +#define RESET_REG_BIT_OFFSET 0x00 +#define RESET_REG_ADDRESS 0x0000000000000CF9 +#define RESET_VALUE 0x02 + +#define ACPI_RUNTIME_UPDATE 0x00 + +#define PM1a_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO +#define PM1a_EVT_BLK_BIT_WIDTH 0x20 +#define PM1a_EVT_BLK_BIT_OFFSET 0x00 + +#define PM1b_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO +#define PM1b_EVT_BLK_BIT_WIDTH 0x00 +#define PM1b_EVT_BLK_BIT_OFFSET 0x00 +#define PM1b_EVT_BLK_ADDRESS 0x0000000000000000 + +#define PM1a_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO +#define PM1a_CNT_BLK_BIT_WIDTH 0x10 +#define PM1a_CNT_BLK_BIT_OFFSET 0x00 + +#define PM1b_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO +#define PM1b_CNT_BLK_BIT_WIDTH 0x00 +#define PM1b_CNT_BLK_BIT_OFFSET 0x00 +#define PM1b_CNT_BLK_ADDRESS 0x0000000000000000 + +#define PM2_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO +#define PM2_CNT_BLK_BIT_WIDTH 0x00 +#define PM2_CNT_BLK_BIT_OFFSET 0x00 +#define PM2_CNT_BLK_ADDRESS 0x0000000000000000 + +#define PM_TMR_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO +#define PM_TMR_BLK_BIT_WIDTH 0x20 +#define PM_TMR_BLK_BIT_OFFSET 0x00 + +#define GPE0_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO +#define GPE0_BLK_BIT_WIDTH 0x40 +#define GPE0_BLK_BIT_OFFSET 0x00 + +#define GPE1_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO +#define GPE1_BLK_BIT_WIDTH 0x00 +#define GPE1_BLK_BIT_OFFSET 0x00 +#define GPE1_BLK_ADDRESS 0x0000000000000000 +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt1.0.aslc b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt1.0.aslc new file mode 100644 index 0000000000..75214a25e4 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt1.0.aslc @@ -0,0 +1,76 @@ +/** @file +This file describes the contents of the ACPI Fixed ACPI Description Table +(FADT). Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h. +All changes to the FADT contents should be done in this file. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "Fadt.h" + +EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FADT = { + EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE), + EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION, + 0, // to make sum of entire table == 0 + EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field + EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long) + EFI_ACPI_OEM_REVISION, // OEM revision number + EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID + EFI_ACPI_CREATOR_REVISION, // ASL compiler revision number + 0, // Physical addesss of FACS + 0, // Physical address of DSDT + INT_MODEL, // System Interrupt Model + RESERVED, // reserved + SCI_INT_VECTOR, // System vector of SCI interrupt + SMI_CMD_IO_PORT, // Port address of SMI command port + ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI + ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI + S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state + RESERVED, // reserved - must be zero + PM1a_EVT_BLK_ADDRESS, // Port address of Power Mgt 1a Event Reg Blk + PM1b_EVT_BLK_ADDRESS, // Port address of Power Mgt 1b Event Reg Blk + PM1a_CNT_BLK_ADDRESS, // Port address of Power Mgt 1a Ctrl Reg Blk + PM1b_CNT_BLK_ADDRESS, // Port address of Power Mgt 1b Ctrl Reg Blk + PM2_CNT_BLK_ADDRESS, // Port address of Power Mgt 2 Ctrl Reg Blk + PM_TMR_BLK_ADDRESS, // Port address of Power Mgt Timer Ctrl Reg Blk + GPE0_BLK_ADDRESS, // Port addr of General Purpose Event 0 Reg Blk + GPE1_BLK_ADDRESS, // Port addr of General Purpose Event 1 Reg Blk + PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk + PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk + PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk + PM_TM_LEN, // Byte Length of ports at pm_tm_blk + GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk + GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk + GPE1_BASE, // offset in gpe model where gpe1 events start + RESERVED, // reserved + P_LVL2_LAT, // worst case HW latency to enter/exit C2 state + P_LVL3_LAT, // worst case HW latency to enter/exit C3 state + FLUSH_SIZE, // Size of area read to flush caches + FLUSH_STRIDE, // Stride used in flushing caches + DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg + DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg + DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM + MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM + CENTURY, // index to century in RTC CMOS RAM + RESERVED, // reserved + RESERVED, // reserved + RESERVED, // reserved + FLAG +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) + +{ + // + // Reference the table being generated to prevent the optimizer from removing the + // data structure from the exeutable + // + return (VOID*)&FADT; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt2.0.aslc b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt2.0.aslc new file mode 100644 index 0000000000..fca60af740 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt2.0.aslc @@ -0,0 +1,157 @@ +/** @file +This file describes the contents of the ACPI Fixed ACPI Description Table +(FADT). Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h. +All changes to the FADT contents should be done in this file. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "Fadt.h" + +EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE FADT = { + { + EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE), + EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION, + 0, // to make sum of entire table == 0 + {EFI_ACPI_OEM_ID}, // OEMID is a 6 bytes long field + EFI_ACPI_OEM_TABLE_ID,// OEM table identification(8 bytes long) + EFI_ACPI_OEM_REVISION,// OEM revision number + EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID + EFI_ACPI_CREATOR_REVISION // ASL compiler revision number + }, + 0, // Physical addesss of FACS + 0, // Physical address of DSDT + RESERVED, // reserved + PM_PROFILE, // Preferred powermanagement profile + SCI_INT_VECTOR, // System vector of SCI interrupt + ACPI_RUNTIME_UPDATE, // Port address of SMI command port + ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI + ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI + S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state + RESERVED, // reserved - must be zero + ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 1a Event Reg Blk + PM1b_EVT_BLK_ADDRESS, // Port address of Power Mgt 1b Event Reg Blk + ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 1a Ctrl Reg Blk + PM1b_CNT_BLK_ADDRESS, // Port address of Power Mgt 1b Ctrl Reg Blk + ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 2 Ctrl Reg Blk + ACPI_RUNTIME_UPDATE, // Port address of Power Mgt Timer Ctrl Reg Blk + ACPI_RUNTIME_UPDATE, // Port addr of General Purpose Event 0 Reg Blk + GPE1_BLK_ADDRESS, // Port addr of General Purpose Event 1 Reg Blk + PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk + PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk + PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk + PM_TM_LEN, // Byte Length of ports at pm_tm_blk + GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk + GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk + GPE1_BASE, // offset in gpe model where gpe1 events start + RESERVED, // reserved + P_LVL2_LAT, // worst case HW latency to enter/exit C2 state + P_LVL3_LAT, // worst case HW latency to enter/exit C3 state + FLUSH_SIZE, // Size of area read to flush caches + FLUSH_STRIDE, // Stride used in flushing caches + DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg + DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg + DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM + MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM + CENTURY, // index to century in RTC CMOS RAM + IAPC_BOOT_ARCH, // IA-PC Boot Architecture Flags + RESERVED, // reserved + FLAG2, // Fixed feature flags + + { + RESET_REG_ADDRESS_SPACE_ID, // Address of the reset register + RESET_REG_BIT_WIDTH, + RESET_REG_BIT_OFFSET, + RESERVED, + RESET_REG_ADDRESS + }, + RESET_VALUE, // Value to write to the RESET_REG port + { + RESERVED, + RESERVED, + RESERVED + }, + 0, // 64Bit physical addesss of FACS + 0, // 64Bit physical address of DSDT + + { + PM1a_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Event Reg Blk + PM1a_EVT_BLK_BIT_WIDTH, + PM1a_EVT_BLK_BIT_OFFSET, + RESERVED, + ACPI_RUNTIME_UPDATE + }, + + { + PM1b_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Event Reg Blk + PM1b_EVT_BLK_BIT_WIDTH, + PM1b_EVT_BLK_BIT_OFFSET, + RESERVED, + PM1b_EVT_BLK_ADDRESS + }, + + { + PM1a_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Ctrl Reg Blk + PM1a_CNT_BLK_BIT_WIDTH, + PM1a_CNT_BLK_BIT_OFFSET, + RESERVED, + ACPI_RUNTIME_UPDATE + }, + + { + PM1b_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Ctrl Reg Blk + PM1b_CNT_BLK_BIT_WIDTH, + PM1b_CNT_BLK_BIT_OFFSET, + RESERVED, + PM1b_CNT_BLK_ADDRESS + }, + + { + PM2_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 2 Ctrl Reg Blk + PM2_CNT_BLK_BIT_WIDTH, + PM2_CNT_BLK_BIT_OFFSET, + RESERVED, + ACPI_RUNTIME_UPDATE + }, + + { + PM_TMR_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt Timer Ctrl Reg Blk + PM_TMR_BLK_BIT_WIDTH, + PM_TMR_BLK_BIT_OFFSET, + RESERVED, + ACPI_RUNTIME_UPDATE + }, + + { + GPE0_BLK_ADDRESS_SPACE_ID, // Extended Port address of General Purpose Event 0 Reg Blk + GPE0_BLK_BIT_WIDTH, + GPE0_BLK_BIT_OFFSET, + RESERVED, + ACPI_RUNTIME_UPDATE + }, + + { + GPE1_BLK_ADDRESS_SPACE_ID, // Extended Port address of General Purpose Event 1 Reg Blk + GPE1_BLK_BIT_WIDTH, + GPE1_BLK_BIT_OFFSET, + RESERVED, + GPE1_BLK_ADDRESS + } +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) + +{ + // + // Reference the table being generated to prevent the optimizer from removing the + // data structure from the exeutable + // + return (VOID*)&FADT; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Hpet/Hpet.aslc b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Hpet/Hpet.aslc new file mode 100644 index 0000000000..7834174d28 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Hpet/Hpet.aslc @@ -0,0 +1,68 @@ +/** @file +This file contains a structure definition for the ACPI 1.0 High Precision Event Timer +Description Table (HPET). The contents of this file should only be modified +for bug fixes, no porting is required. The table layout is defined in +HighPrecisionEventTimerTable.h and the table contents are defined in Acpi1.0.h and Hpet.h. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// Statements that include other files +// + +#include "Hpet.h" + +// +// High Precision Event Timer Table +// Please modify all values in Hpet.h only. +// + +EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER Hpet = { + { + EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE, + sizeof (EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER), + EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION, + + // + // Checksum will be updated at runtime + // + 0x00, + + // + // It is expected that these values will be updated at runtime + // + {' ', ' ', ' ', ' ', ' ', ' '}, + + 0, + EFI_ACPI_OEM_HPET_REVISION, + 0, + 0 + }, + EFI_ACPI_EVENT_TIMER_BLOCK_ID, + { + EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS_SPACE_ID, + EFI_ACPI_EVENT_TIMER_BLOCK_BIT_WIDTH, + EFI_ACPI_EVENT_TIMER_BLOCK_BIT_OFFSET, + EFI_ACPI_EVENT_TIMER_ACCESS_SIZE, + ACPI_RUNTIME_UPDATE + }, + EFI_ACPI_HPET_NUMBER, + EFI_ACPI_MIN_CLOCK_TICK, + EFI_ACPI_HPET_ATTRIBUTES +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from removing the + // data structure from the exeutable + // + return (VOID*)&Hpet; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Hpet/Hpet.h b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Hpet/Hpet.h new file mode 100644 index 0000000000..b1695436a3 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Hpet/Hpet.h @@ -0,0 +1,45 @@ +/** @file +This file describes the contents of the ACPI High Precision Event Timer Description Table +(HPET). Some additional ACPI values are defined in Acpi10.h, Acpi20.h, and Acpi30.h +All changes to the HPET contents should be done in this file. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _HPET_H_ +#define _HPET_H_ + +// +// Statements that include other files +// +#include +#include + +// +// HPET Definitions +// + +#define EFI_ACPI_OEM_HPET_REVISION 0x00000001 + +#define EFI_ACPI_EVENT_TIMER_BLOCK_ID 0x8086A201 + +#define ACPI_RUNTIME_UPDATE 0x00 + +// +// Event Timer Block Base Address Information +// +#define EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS_SPACE_ID EFI_ACPI_3_0_SYSTEM_MEMORY +#define EFI_ACPI_EVENT_TIMER_BLOCK_BIT_WIDTH 0x00 +#define EFI_ACPI_EVENT_TIMER_BLOCK_BIT_OFFSET 0x00 +#define EFI_ACPI_EVENT_TIMER_ACCESS_SIZE 0x00 + +#define EFI_ACPI_HPET_NUMBER 0x00 + +#define EFI_ACPI_MIN_CLOCK_TICK 0x0080 + +#define EFI_ACPI_HPET_ATTRIBUTES 0x00 + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Mcfg/Mcfg.aslc b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Mcfg/Mcfg.aslc new file mode 100644 index 0000000000..bef7b12cf9 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Mcfg/Mcfg.aslc @@ -0,0 +1,75 @@ +/** @file +This file contains a structure definition for the ACPI Memory Mapped Configuration +Address Space table (MCFG). Any changes to the number of entries in the table require +updating the structure count in Mcfg.h and then adding the structure to the +MCFG defined in this file. The table layout is defined in Mcfg.h and the +table contents are defined in the MemoryMappedConfigurationSpaceAccessTable.h. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// Statements that include other files +// + +#include "Mcfg.h" + +// +// Multiple APIC Description Table +// + +EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = { + { + EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE), + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION, + + // + // Checksum will be updated at runtime + // + 0x00, + + // + // It is expected that these values will be programmed at runtime + // + {' ', ' ', ' ', ' ', ' ', ' '}, + + 0, + EFI_ACPI_OEM_MCFG_REVISION, + 0, + 0 + }, + // + // Reserved + // + 0x0000000000000000, + + // + // MCFG specific fields + // + + { + { + 0x00000000, // BaseAddress (will be updated at runtime) + 0x0000, // PciSegmentGroupNumber + 0x00, // StartBusNumber + 0x1F, // EndBusNumber + 0x00000000 // Reserved + } + } +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from removing the + // data structure from the exeutable + // + return (VOID*)&Mcfg; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Mcfg/Mcfg.h b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Mcfg/Mcfg.h new file mode 100644 index 0000000000..3703132a9a --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/AcpiTables/Mcfg/Mcfg.h @@ -0,0 +1,56 @@ +/** @file +This file describes the contents of the ACPI Memory Mapped Configuration +Space Access Table (MCFG). Some additional ACPI values are defined in Acpi10.h, +Acpi20.h, and Acpi30.h. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MCFG_H_ +#define _MCFG_H_ + +// +// Statements that include other files +// + +#include +#include + +// +// MCFG Definitions +// + +#define EFI_ACPI_OEM_MCFG_REVISION 0x00000001 + +// +// Define the number of allocation structures so that we can build the table structure. +// + +#define EFI_ACPI_ALLOCATION_STRUCTURE_COUNT 1 + +// +// MCFG structure +// + +// +// Ensure proper structure formats +// +#pragma pack (1) + +// +// MCFG Table structure +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 Reserved; +#if EFI_ACPI_ALLOCATION_STRUCTURE_COUNT > 0 + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE AllocationStructure[EFI_ACPI_ALLOCATION_STRUCTURE_COUNT]; +#endif +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE; + +#pragma pack () + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.c b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.c new file mode 100644 index 0000000000..02738621e5 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.c @@ -0,0 +1,1402 @@ +/** @file +Update the _PRT and _PRW method for pci devices + +Copyright (c) 2013-2016 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ +#include "AcpiPlatform.h" + +PCI_DEVICE_INFO *mQNCPciInfo = NULL; + +/** + Init Pci Device Structure + @param mConfigData - Pointer of Pci Device information Structure + +**/ +VOID +InitPciDeviceInfoStructure ( + PCI_DEVICE_SETTING *mConfigData + ) +{ + // + // Return 0 given that function unsupported. + // Would need to parse ACPI tables and build mQNCPciInfo above + // with found _PRT & _PRW methods for PCI devices. + // + mConfigData->PciDeviceInfoNumber = 0; +} + +/** + return Integer value. + + @param Data - AML data buffer + @param Integer - integer value. + + @return Data size processed. +**/ +UINTN +SdtGetInteger ( + IN UINT8 *Data, + OUT UINT64 *Integer + ) +{ + *Integer = 0; + switch (*Data) { + case AML_ZERO_OP: + return 1; + case AML_ONE_OP: + *Integer = 1; + return 1; + case AML_ONES_OP: + *Integer = (UINTN)-1; + return 1; + case AML_BYTE_PREFIX: + CopyMem (Integer, Data + 1, sizeof(UINT8)); + return 1 + sizeof(UINT8); + case AML_WORD_PREFIX: + CopyMem (Integer, Data + 1, sizeof(UINT16)); + return 1 + sizeof(UINT16); + case AML_DWORD_PREFIX: + CopyMem (Integer, Data + 1, sizeof(UINT32)); + return 1 + sizeof(UINT32); + case AML_QWORD_PREFIX: + CopyMem (Integer, Data + 1, sizeof(UINT64)); + return 1 + sizeof(UINT64); + default: + // Something wrong + ASSERT (FALSE); + return 1; + } +} + + +/** + Check if this handle has expected opcode. + + @param AcpiSdt Pointer to Acpi SDT protocol + @param Handle ACPI handle + @param OpCode Expected OpCode + @param SubOpCode Expected SubOpCode + + @retval TRUE This handle has expected opcode + @retval FALSE This handle does not have expected opcode +**/ +BOOLEAN +SdtIsThisTypeObject ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt, + IN EFI_ACPI_HANDLE Handle, + IN UINT8 OpCode, + IN UINT8 SubOpCode + ) +{ + EFI_STATUS Status; + EFI_ACPI_DATA_TYPE DataType; + UINT8 *Data; + UINTN DataSize; + + Status = AcpiSdt->GetOption (Handle, 0, &DataType, (CONST VOID **)&Data, &DataSize); + ASSERT_EFI_ERROR (Status); + ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE); + + if (OpCode == AML_EXT_OP) { + if (Data[1] == SubOpCode) { + return TRUE; + } + } else { + if (Data[0] == OpCode) { + return TRUE; + } + } + return FALSE; +} + +/** + Check if this handle has expected name and name value. + + @param AcpiSdt Pointer to Acpi SDT protocol + @param Handle ACPI handle + @param Name Expected name + @param Value Expected name value + + @retval TRUE This handle has expected name and name value. + @retval FALSE This handle does not have expected name and name value. +**/ +BOOLEAN +SdtIsNameIntegerValueEqual ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt, + IN EFI_ACPI_HANDLE Handle, + IN CHAR8 *Name, + IN UINT64 Value + ) +{ + EFI_STATUS Status; + EFI_ACPI_DATA_TYPE DataType; + UINT8 *Data; + UINTN DataSize; + UINT64 Integer; + + Status = AcpiSdt->GetOption (Handle, 1, &DataType, (CONST VOID **)&Data, &DataSize); + ASSERT_EFI_ERROR (Status); + ASSERT (DataType == EFI_ACPI_DATA_TYPE_NAME_STRING); + + if (CompareMem (Data, Name, 4) != 0) { + return FALSE; + } + + // + // Name match check object + // + Status = AcpiSdt->GetOption (Handle, 2, &DataType, (CONST VOID **)&Data, &DataSize); + ASSERT_EFI_ERROR (Status); + + Integer = 0; + SdtGetInteger (Data, &Integer); + if (Integer != Value) { + return FALSE; + } + + // All match + return TRUE; +} + +/** + Check if this handle's children has expected name and name value. + + @param AcpiSdt Pointer to Acpi SDT protocol + @param ParentHandle ACPI parent handle + @param Name Expected name + @param Value Expected name value + + @retval TRUE This handle's children has expected name and name value. + @retval FALSE This handle's children does not have expected name and name value. +**/ +BOOLEAN +SdtCheckNameIntegerValue ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt, + IN EFI_ACPI_HANDLE ParentHandle, + IN CHAR8 *Name, + IN UINT64 Value + ) +{ + EFI_ACPI_HANDLE PreviousHandle; + EFI_ACPI_HANDLE Handle; + EFI_STATUS Status; + + Handle = NULL; + while (TRUE) { + PreviousHandle = Handle; + Status = AcpiSdt->GetChild (ParentHandle, &Handle); + ASSERT_EFI_ERROR (Status); + + if (PreviousHandle != NULL) { + Status = AcpiSdt->Close (PreviousHandle); + ASSERT_EFI_ERROR (Status); + } + + // + // Done + // + if (Handle == NULL) { + return FALSE; + } + + // + // Check this name + // + if (SdtIsThisTypeObject (AcpiSdt, Handle, AML_NAME_OP, 0)) { + if (SdtIsNameIntegerValueEqual (AcpiSdt, Handle, Name, Value)) { + return TRUE; + } + } + } + + // + // Should not run here + // +} + +/** + Convert the pci address from VPD (bus,dev,fun) into the address that acpi table + can recognize. + + @param PciAddress Pci address from VPD + + @retval return the address that acpi table can recognize +**/ +UINT32 +SdtConvertToAcpiPciAdress ( + IN UINT32 PciAddress + ) +{ + UINT32 ReturnAddress; + + ReturnAddress = ((PciAddress & 0x0000FF00) << 8) | (PciAddress & 0x000000FF); + + if ((PciAddress & 0x000000FF) == 0x000000FF) + ReturnAddress |= 0x0000FFFF; + + return ReturnAddress; +} + +/** + return AML NameString size. + + @param Buffer - AML name string + + @return AML name string size +**/ +UINTN +SdtGetNameStringSize ( + IN UINT8 *Buffer + ) +{ + UINTN SegCount; + UINTN Length; + + Length = 0; + + // + // Parse root or prefix + // + if (*Buffer == AML_ROOT_CHAR) { + // + // RootChar + // + Buffer ++; + Length ++; + } else if (*Buffer == AML_PARENT_PREFIX_CHAR) { + // + // ParentPrefixChar + // + Buffer ++; + Length ++; + while (*Buffer == AML_PARENT_PREFIX_CHAR) { + Buffer ++; + Length ++; + } + } + + // + // Parse name segment + // + if (*Buffer == AML_DUAL_NAME_PREFIX) { + // + // DualName + // + Buffer ++; + Length ++; + SegCount = 2; + } else if (*Buffer == AML_MULTI_NAME_PREFIX) { + // + // MultiName + // + Buffer ++; + Length ++; + SegCount = *Buffer; + Buffer ++; + Length ++; + } else if (*Buffer == 0) { + // + // NULL Name + // + SegCount = 0; + Length ++; + } else { + // + // NameSeg + // + SegCount = 1; + } + + Buffer += 4 * SegCount; + Length += 4 * SegCount; + + return Length; +} + +/** + The routine to check if this device is PCI root bridge. + + @param AcpiSdt Pointer to Acpi SDT protocol + @param DeviceHandle ACPI device handle + @param Context Context info - not used here + + @retval TRUE This is PCI root bridge + @retval FALSE This is not PCI root bridge +**/ +BOOLEAN +SdtFindRootBridgeHandle ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt, + IN EFI_ACPI_HANDLE CheckHandle, + IN VOID *Context + ) +{ + BOOLEAN Result; + EFI_ACPI_DATA_TYPE DataType; + UINT8 *Data; + UINTN DataSize; + EFI_STATUS Status; + + if (!SdtIsThisTypeObject (AcpiSdt, CheckHandle, AML_EXT_OP, AML_EXT_DEVICE_OP)) + return FALSE; + + Result = SdtCheckNameIntegerValue (AcpiSdt,CheckHandle, "_HID", (UINT64)0x080AD041); // PNP0A08 + if (!Result) { + Result = SdtCheckNameIntegerValue (AcpiSdt, CheckHandle, "_CID", (UINT64)0x030AD041); // PNP0A03 + if (!Result) { + return Result; + } + } + + // + // Found + // + Status = AcpiSdt->GetOption (CheckHandle, 1, &DataType, (CONST VOID **)&Data, &DataSize); + ASSERT_EFI_ERROR (Status); + ASSERT (DataType == EFI_ACPI_DATA_TYPE_NAME_STRING); + + return Result; +} + + +/** + The routine to check if this device is wanted. + + @param AcpiSdt Pointer to Acpi SDT protocol + @param DeviceHandle ACPI device handle + @param Context Context info - not used here + + @retval TRUE This is PCI device wanted + @retval FALSE This is not PCI device wanted +**/ +BOOLEAN +SdtFindPciDeviceHandle ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt, + IN EFI_ACPI_HANDLE CheckHandle, + IN VOID *Context + ) +{ + BOOLEAN Result; + EFI_ACPI_DATA_TYPE DataType; + UINT8 *Data; + UINTN DataSize; + EFI_STATUS Status; + + if (!SdtIsThisTypeObject (AcpiSdt, CheckHandle, AML_EXT_OP, AML_EXT_DEVICE_OP)) + return FALSE; + + Result = SdtCheckNameIntegerValue (AcpiSdt,CheckHandle, "_ADR", (UINT64)*(UINT32 *)Context); + if (!Result) { + return Result; + } + + // + // Found + // + Status = AcpiSdt->GetOption (CheckHandle, 1, &DataType, (CONST VOID **)&Data, &DataSize); + ASSERT_EFI_ERROR (Status); + ASSERT (DataType == EFI_ACPI_DATA_TYPE_NAME_STRING); + + return Result; +} + +/** + Go through the parent handle and find the handle which pass CheckHandleInfo. + + @param AcpiSdt Pointer to Acpi SDT protocol + @param ParentHandle ACPI parent handle + @param CheckHandleInfo The callback routine to check if this handle meet the requirement + @param Context The context of CheckHandleInfo + + @return the handle which is first one can pass CheckHandleInfo. +**/ +EFI_ACPI_HANDLE +SdtGetHandleByScanAllChilds ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt, + IN EFI_ACPI_HANDLE ParentHandle, + IN CHECK_HANDLE_INFO CheckHandleInfo, + IN VOID *Context + ) +{ + EFI_ACPI_HANDLE PreviousHandle; + EFI_ACPI_HANDLE Handle; + EFI_STATUS Status; + EFI_ACPI_HANDLE ReturnHandle; + + // + // Use deep first algo to enumerate all ACPI object + // + Handle = NULL; + while (TRUE) { + PreviousHandle = Handle; + Status = AcpiSdt->GetChild (ParentHandle, &Handle); + ASSERT_EFI_ERROR (Status); + + if (PreviousHandle != NULL) { + Status = AcpiSdt->Close (PreviousHandle); + ASSERT_EFI_ERROR (Status); + } + + // + // Done + // + if (Handle == NULL) { + return NULL; + } + + // + // Check this handle + // + if (CheckHandleInfo (AcpiSdt, Handle, Context)) { + return Handle; + } + + // + // Enumerate + // + ReturnHandle = SdtGetHandleByScanAllChilds (AcpiSdt, Handle, CheckHandleInfo, Context); + if (ReturnHandle != NULL) { + return ReturnHandle; + } + } + + // + // Should not run here + // +} + + +/** + Check whether the INTx package is matched + + @param AcpiSdt Pointer to Acpi SDT protocol + @param INTxPkgHandle ACPI INTx package handle + @param PciAddress Acpi pci address + @param INTx Index of INTx pin + @param IsAPIC Tell whether the returned INTx package is for APIC or not + + @retval TRUE the INTx package is matched + @retval FALSE the INTx package is not matched + +**/ +BOOLEAN +SdtCheckINTxPkgIsMatch ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt, + IN EFI_ACPI_HANDLE INTxPkgHandle, + IN UINT32 PciAddress, + IN UINT8 INTx, + IN BOOLEAN *IsAPIC + ) +{ + EFI_ACPI_HANDLE PreviousHandle; + EFI_STATUS Status; + EFI_ACPI_HANDLE MemberHandle; + EFI_ACPI_DATA_TYPE DataType; + UINT8 *Data; + UINTN DataSize; + UINT64 CurrentPciAddress; + UINT64 CurrentINTx; + UINTN ChildSize; + + + // + // Check the pci address + // + MemberHandle = NULL; + Status = AcpiSdt->GetChild (INTxPkgHandle, &MemberHandle); + ASSERT_EFI_ERROR (Status); + ASSERT (MemberHandle != NULL); + + Status = AcpiSdt->GetOption (MemberHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize); + ASSERT_EFI_ERROR (Status); + ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE); + + CurrentPciAddress = 0; + SdtGetInteger (Data, &CurrentPciAddress); + + if (CurrentPciAddress != PciAddress) { + + Status = AcpiSdt->Close (MemberHandle); + ASSERT_EFI_ERROR (Status); + return FALSE; + } + + // + // Check the pci interrupt pin + // + PreviousHandle = MemberHandle; + Status = AcpiSdt->GetChild (INTxPkgHandle, &MemberHandle); + ASSERT_EFI_ERROR (Status); + ASSERT (MemberHandle != NULL); + + if (PreviousHandle != NULL) { + Status = AcpiSdt->Close (PreviousHandle); + ASSERT_EFI_ERROR (Status); + } + + Status = AcpiSdt->GetOption (MemberHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize); + ASSERT_EFI_ERROR (Status); + ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE); + + CurrentINTx = 0; + ChildSize = SdtGetInteger (Data, &CurrentINTx); + + Status = AcpiSdt->Close (MemberHandle); + ASSERT_EFI_ERROR (Status); + + if (CurrentINTx != INTx) + return FALSE; + + Data += ChildSize; + + if (*Data == AML_BYTE_PREFIX) + Data += 1; + + // + // Check the pci interrupt source + // + if (*Data != 0) + *IsAPIC = FALSE; + else + *IsAPIC = TRUE; + + return TRUE; +} + + + + +/** + Get the wanted INTx package inside the parent package + + @param AcpiSdt Pointer to Acpi SDT protocol + @param ParentPkgHandle ACPI parent package handle + @param PciAddress Acpi pci address + @param INTx Index of INTx pin + @param INTxPkgHandle ACPI INTx package handle + @param IsAPIC Tell whether the returned INTx package is for APIC or not + +**/ +VOID +SdtGetINTxPkgHandle ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt, + IN EFI_ACPI_HANDLE ParentPkgHandle, + IN UINT32 PciAddress, + IN UINT8 INTx, + IN EFI_ACPI_HANDLE *INTxPkgHandle, + IN BOOLEAN *IsAPIC + ) +{ + EFI_ACPI_HANDLE PreviousHandle; + EFI_STATUS Status; + EFI_ACPI_HANDLE ChildPkgHandle; + + ChildPkgHandle = NULL; + while (TRUE) { + PreviousHandle = ChildPkgHandle; + Status = AcpiSdt->GetChild (ParentPkgHandle, &ChildPkgHandle); + ASSERT_EFI_ERROR (Status); + + if (PreviousHandle != NULL) { + Status = AcpiSdt->Close (PreviousHandle); + ASSERT_EFI_ERROR (Status); + } + + if (ChildPkgHandle == NULL) { + break; + } + + if (SdtCheckINTxPkgIsMatch(AcpiSdt, ChildPkgHandle, PciAddress, INTx, IsAPIC)) { + *INTxPkgHandle = ChildPkgHandle; + return; + } + } + + return; +} + +/** + Update the INTx package with the correct pirq value + + @param AcpiSdt Pointer to Acpi SDT protocol + @param INTxPkgHandle ACPI INTx package handle + @param PirqValue Correct pirq value + @param IsAPIC Tell whether the INTx package is for APIC or not + +**/ +VOID +SdtUpdateINTxPkg ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt, + IN EFI_ACPI_HANDLE INTxPkgHandle, + IN UINT8 PirqValue, + IN BOOLEAN IsAPIC + ) +{ + EFI_ACPI_HANDLE PreviousHandle; + EFI_STATUS Status; + EFI_ACPI_HANDLE MemberHandle; + EFI_ACPI_DATA_TYPE DataType; + UINT8 *Data; + UINTN DataSize; + UINT64 TempValue; + UINTN ChildSize; + + + // + // Check the pci address + // + MemberHandle = NULL; + Status = AcpiSdt->GetChild (INTxPkgHandle, &MemberHandle); + ASSERT_EFI_ERROR (Status); + ASSERT (MemberHandle != NULL); + + // + // Check the pci interrupt pin + // + PreviousHandle = MemberHandle; + Status = AcpiSdt->GetChild (INTxPkgHandle, &MemberHandle); + ASSERT_EFI_ERROR (Status); + ASSERT (MemberHandle != NULL); + + if (PreviousHandle != NULL) { + Status = AcpiSdt->Close (PreviousHandle); + ASSERT_EFI_ERROR (Status); + } + + Status = AcpiSdt->GetOption (MemberHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize); + ASSERT_EFI_ERROR (Status); + ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE); + + ChildSize = SdtGetInteger (Data, &TempValue); + + Status = AcpiSdt->Close (MemberHandle); + ASSERT_EFI_ERROR (Status); + + Data += ChildSize; + + // + // update the pci interrupt source or source index + // + if (!IsAPIC) { + ChildSize = SdtGetNameStringSize (Data); + Data += (ChildSize - 1); + + PirqValue += 0x40; // change to ascii char + if (*Data != PirqValue) + *Data = PirqValue; + } else { + + ChildSize = SdtGetInteger (Data, &TempValue); + Data += ChildSize; + + Data += 1; + + if (*Data != PirqValue) + *Data = PirqValue; + } +} + +/** + Check every child package inside this interested parent package for update PRT + + @param AcpiSdt Pointer to Acpi SDT protocol + @param ParentPkgHandle ACPI parent package handle + @param PciDeviceInfo Pointer to PCI_DEVICE_INFO + +**/ +VOID +SdtCheckParentPackage ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt, + IN EFI_ACPI_HANDLE ParentPkgHandle, + IN PCI_DEVICE_INFO *PciDeviceInfo + ) +{ + EFI_ACPI_HANDLE INTAPkgHandle; + EFI_ACPI_HANDLE INTBPkgHandle; + EFI_ACPI_HANDLE INTCPkgHandle; + EFI_ACPI_HANDLE INTDPkgHandle; + UINT32 PciAddress = 0; + BOOLEAN IsAllFunctions = FALSE; + UINT8 IsAPIC = 0; + EFI_STATUS Status; + + INTAPkgHandle = INTBPkgHandle = INTCPkgHandle = INTDPkgHandle = NULL; + + PciAddress = SdtConvertToAcpiPciAdress(PciDeviceInfo->DeviceAddress); + + if ((PciAddress & 0xFFFF) == 0xFFFF) { + IsAllFunctions = TRUE; + } else { + IsAllFunctions = FALSE; + PciAddress = (PciAddress | 0xFFFF); + } + + SdtGetINTxPkgHandle (AcpiSdt, ParentPkgHandle, PciAddress, 0, &INTAPkgHandle, (BOOLEAN *)&IsAPIC); + SdtGetINTxPkgHandle (AcpiSdt, ParentPkgHandle, PciAddress, 1, &INTBPkgHandle, (BOOLEAN *)&IsAPIC); + SdtGetINTxPkgHandle (AcpiSdt, ParentPkgHandle, PciAddress, 2, &INTCPkgHandle, (BOOLEAN *)&IsAPIC); + SdtGetINTxPkgHandle (AcpiSdt, ParentPkgHandle, PciAddress, 3, &INTDPkgHandle, (BOOLEAN *)&IsAPIC); + + // + // Check INTA + // + if ((PciDeviceInfo->INTA[IsAPIC] != 0xFF) && (INTAPkgHandle != NULL)) { + // + // Find INTA package and there is valid INTA update item, update it + // + SdtUpdateINTxPkg (AcpiSdt, INTAPkgHandle, (PciDeviceInfo->INTA[IsAPIC]), IsAPIC); + } else if ((PciDeviceInfo->INTA[IsAPIC] != 0xFF) && (INTAPkgHandle == NULL)) { + // + // There is valid INTA update item, but no INA package exist, should add it + // + DEBUG ((EFI_D_ERROR, "\n\nShould add INTA item for this device(0x%x)\n\n", PciAddress)); + + } else if ((PciDeviceInfo->INTA[IsAPIC] == 0xFF) && (INTAPkgHandle != NULL) && IsAllFunctions) { + // + // For all functions senario, if there is invalid INTA update item, but INTA package does exist, should delete it + // + DEBUG ((EFI_D_ERROR, "\n\nShould remove INTA item for this device(0x%x)\n\n", PciAddress)); + + } + + // + // Check INTB + // + if ((PciDeviceInfo->INTB[IsAPIC] != 0xFF) && (INTBPkgHandle != NULL)) { + // + // Find INTB package and there is valid INTB update item, update it + // + SdtUpdateINTxPkg (AcpiSdt, INTBPkgHandle, (PciDeviceInfo->INTB[IsAPIC]), IsAPIC); + } else if ((PciDeviceInfo->INTB[IsAPIC] != 0xFF) && (INTBPkgHandle == NULL)) { + // + // There is valid INTB update item, but no INTB package exist, should add it + // + DEBUG ((EFI_D_ERROR, "\n\nShould add INTB item for this device(0x%x)\n\n", PciAddress)); + + } else if ((PciDeviceInfo->INTB[IsAPIC] == 0xFF) && (INTBPkgHandle != NULL) && IsAllFunctions) { + // + // For all functions senario, if there is invalid INTB update item, but INTB package does exist, should delete it + // + DEBUG ((EFI_D_ERROR, "\n\nShould remove INTB item for this device(0x%x)\n\n", PciAddress)); + + } + + // + // Check INTC + // + if ((PciDeviceInfo->INTC[IsAPIC] != 0xFF) && (INTCPkgHandle != NULL)) { + // + // Find INTC package and there is valid INTC update item, update it + // + SdtUpdateINTxPkg (AcpiSdt, INTCPkgHandle, (PciDeviceInfo->INTC[IsAPIC]), IsAPIC); + } else if ((PciDeviceInfo->INTC[IsAPIC] != 0xFF) && (INTCPkgHandle == NULL)) { + // + // There is valid INTC update item, but no INTC package exist, should add it + // + DEBUG ((EFI_D_ERROR, "\n\nShould add INTC item for this device(0x%x)\n\n", PciAddress)); + + } else if ((PciDeviceInfo->INTC[IsAPIC] == 0xFF) && (INTCPkgHandle != NULL) && IsAllFunctions) { + // + // For all functions senario, if there is invalid INTC update item, but INTC package does exist, should delete it + // + DEBUG ((EFI_D_ERROR, "\n\nShould remove INTC item for this device(0x%x)\n\n", PciAddress)); + } + + // + // Check INTD + // + if ((PciDeviceInfo->INTD[IsAPIC] != 0xFF) && (INTDPkgHandle != NULL)) { + // + // Find INTD package and there is valid INTD update item, update it + // + SdtUpdateINTxPkg (AcpiSdt, INTDPkgHandle, (PciDeviceInfo->INTD[IsAPIC]), IsAPIC); + } else if ((PciDeviceInfo->INTD[IsAPIC] != 0xFF) && (INTDPkgHandle == NULL)) { + // + // There is valid INTD update item, but no INTD package exist, should add it + // + DEBUG ((EFI_D_ERROR, "\n\nShould add INTD item for this device(0x%x)\n\n", PciAddress)); + + } else if ((PciDeviceInfo->INTD[IsAPIC] == 0xFF) && (INTDPkgHandle != NULL) && IsAllFunctions) { + // + // For all functions senario, if there is invalid INTD update item, but INTD package does exist, should delete it + // + DEBUG ((EFI_D_ERROR, "\n\nShould remove INTD item for this device(0x%x)\n\n", PciAddress)); + } + + + if (INTAPkgHandle != NULL) { + Status = AcpiSdt->Close (INTAPkgHandle); + ASSERT_EFI_ERROR (Status); + } + + if (INTBPkgHandle != NULL) { + Status = AcpiSdt->Close (INTBPkgHandle); + ASSERT_EFI_ERROR (Status); + } + + if (INTCPkgHandle != NULL) { + Status = AcpiSdt->Close (INTCPkgHandle); + ASSERT_EFI_ERROR (Status); + } + + if (INTDPkgHandle != NULL) { + Status = AcpiSdt->Close (INTDPkgHandle); + ASSERT_EFI_ERROR (Status); + } + + return; +} + +/** + Check every return package for update PRT + + @param AcpiSdt Pointer to Acpi SDT protocol + @param ParentHandle ACPI pci device handle + @param PciDeviceInfo Pointer to PCI_DEVICE_INFO + +**/ +VOID +SdtCheckReturnPackage ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt, + IN EFI_ACPI_HANDLE MethodHandle, + IN PCI_DEVICE_INFO *PciDeviceInfo + ) +{ + EFI_ACPI_HANDLE PreviousHandle; + EFI_ACPI_HANDLE ReturnHandle; + EFI_ACPI_HANDLE PackageHandle; + EFI_ACPI_HANDLE NamePkgHandle; + EFI_STATUS Status; + EFI_ACPI_DATA_TYPE DataType; + UINT8 *Data; + UINTN DataSize; + CHAR8 NameStr[128]; + + ReturnHandle = NULL; + while (TRUE) { + PreviousHandle = ReturnHandle; + Status = AcpiSdt->GetChild (MethodHandle, &ReturnHandle); + ASSERT_EFI_ERROR (Status); + + if (PreviousHandle != NULL) { + Status = AcpiSdt->Close (PreviousHandle); + ASSERT_EFI_ERROR (Status); + } + + if (ReturnHandle == NULL) { + break; + } + + Status = AcpiSdt->GetOption (ReturnHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize); + ASSERT_EFI_ERROR (Status); + ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE); + + if (*Data == AML_RETURN_OP) { + // + // Find the return method handle, then look for the returned package data + // + Status = AcpiSdt->GetOption (ReturnHandle, 1, &DataType, (CONST VOID **)&Data, &DataSize); + ASSERT_EFI_ERROR (Status); + + + if (DataType == EFI_ACPI_DATA_TYPE_NAME_STRING) { + ZeroMem (NameStr, 128); + AsciiStrCpy (NameStr, "\\_SB."); + DataSize = SdtGetNameStringSize (Data); + AsciiStrnCat (NameStr, (CHAR8 *)Data, DataSize); + + NamePkgHandle = NULL; + Status = AcpiSdt->FindPath (mDsdtHandle, NameStr, &NamePkgHandle); + ASSERT_EFI_ERROR (Status); + ASSERT (NamePkgHandle != NULL); + + Status = AcpiSdt->GetOption (NamePkgHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize); + ASSERT_EFI_ERROR (Status); + ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE); + ASSERT (*Data == AML_NAME_OP); + + Status = AcpiSdt->GetOption (NamePkgHandle, 2, &DataType, (CONST VOID **)&Data, &DataSize); + ASSERT_EFI_ERROR (Status); + ASSERT (DataType == EFI_ACPI_DATA_TYPE_CHILD); + } + + ASSERT (DataType == EFI_ACPI_DATA_TYPE_CHILD); + + // + // Get the parent package handle + // + PackageHandle = NULL; + Status = AcpiSdt->Open (Data, &PackageHandle); + ASSERT_EFI_ERROR (Status); + + // + // Check the parent package for update pci routing + // + SdtCheckParentPackage (AcpiSdt, PackageHandle, PciDeviceInfo); + + Status = AcpiSdt->Close (PackageHandle); + ASSERT_EFI_ERROR (Status); + + Status = AcpiSdt->Close (ReturnHandle); + ASSERT_EFI_ERROR (Status); + + break; + } + + // + // Not ReturnOp, search it as parent + // + SdtCheckReturnPackage (AcpiSdt, ReturnHandle, PciDeviceInfo); + } + + // + // Done + // + return; + +} + +/** + update interrupt info inside the PRT method for the given pci device handle + + @param AcpiSdt Pointer to Acpi SDT protocol + @param PciHandle ACPI pci device handle + @param PciDeviceInfo Pointer to PCI_DEVICE_INFO + +**/ +EFI_STATUS +SdtUpdatePrtMethod ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt, + IN EFI_ACPI_HANDLE PciHandle, + IN PCI_DEVICE_INFO *PciDeviceInfo + ) +{ + EFI_STATUS Status; + EFI_ACPI_HANDLE PrtMethodHandle; + + // + // Find the PRT method under this pci device + // + PrtMethodHandle = NULL; + Status = AcpiSdt->FindPath (PciHandle, "_PRT", &PrtMethodHandle); + + if (EFI_ERROR (Status)) { + return EFI_INVALID_PARAMETER; + } + + if (PrtMethodHandle == NULL) { + return EFI_INVALID_PARAMETER; + } + + SdtCheckReturnPackage(AcpiSdt, PrtMethodHandle, PciDeviceInfo); + + Status = AcpiSdt->Close (PrtMethodHandle); + ASSERT_EFI_ERROR (Status); + + return Status; +} + + +/** + Update the package inside name op with correct wakeup resources + + @param AcpiSdt Pointer to Acpi SDT protocol + @param InPkgHandle ACPI inside package handle + @param GPEPin Correct gpe pin + @param SxNum Correct system state the device can wake up from + +**/ +VOID +SdtUpdatePackageInName ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt, + IN EFI_ACPI_HANDLE INTxPkgHandle, + IN UINT8 GPEPin, + IN UINT8 SxNum + ) +{ + EFI_ACPI_HANDLE PreviousHandle; + EFI_STATUS Status; + EFI_ACPI_HANDLE MemberHandle; + EFI_ACPI_DATA_TYPE DataType; + UINT8 *Data; + UINTN DataSize; + + // + // Check the gpe pin + // + MemberHandle = NULL; + Status = AcpiSdt->GetChild (INTxPkgHandle, &MemberHandle); + ASSERT_EFI_ERROR (Status); + ASSERT (MemberHandle != NULL); + + Status = AcpiSdt->GetOption (MemberHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize); + ASSERT_EFI_ERROR (Status); + ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE); + + // + // Skip byte prefix + // + Data += 1; + + if (*Data != GPEPin) { + + *Data = GPEPin; + } + + // + // Check the sx number + // + PreviousHandle = MemberHandle; + Status = AcpiSdt->GetChild (INTxPkgHandle, &MemberHandle); + ASSERT_EFI_ERROR (Status); + ASSERT (MemberHandle != NULL); + + if (PreviousHandle != NULL) { + Status = AcpiSdt->Close (PreviousHandle); + ASSERT_EFI_ERROR (Status); + } + + Status = AcpiSdt->GetOption (MemberHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize); + ASSERT_EFI_ERROR (Status); + ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE); + + // + // Skip byte prefix + // + Data += 1; + + if (*Data != SxNum) { + + *Data = SxNum; + } + + Status = AcpiSdt->Close (MemberHandle); + ASSERT_EFI_ERROR (Status); + +} + +/** + Check the name package belonged to PRW + + @param AcpiSdt Pointer to Acpi SDT protocol + @param PrwPkgHandle ACPI PRW package handle + @param PciDeviceInfo Pointer to PCI_DEVICE_INFO + +**/ +VOID +SdtCheckNamePackage ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt, + IN EFI_ACPI_HANDLE PrwPkgHandle, + IN PCI_DEVICE_INFO *PciDeviceInfo + ) +{ + EFI_ACPI_HANDLE InPkgHandle; + EFI_STATUS Status; + EFI_ACPI_DATA_TYPE DataType; + UINT8 *Data; + UINTN DataSize; + + Status = AcpiSdt->GetOption (PrwPkgHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize); + ASSERT_EFI_ERROR (Status); + ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE); + ASSERT (*Data == AML_NAME_OP); + + Status = AcpiSdt->GetOption (PrwPkgHandle, 2, &DataType, (CONST VOID **)&Data, &DataSize); + ASSERT_EFI_ERROR (Status); + ASSERT (DataType == EFI_ACPI_DATA_TYPE_CHILD); + + // + // Get the inside package handle + // + InPkgHandle = NULL; + Status = AcpiSdt->Open (Data, &InPkgHandle); + ASSERT_EFI_ERROR (Status); + + // + // update the package in name op for wakeup info + // + if ((PciDeviceInfo->GPEPin != 0xFF) && (PciDeviceInfo->SxNum != 0xFF)) + SdtUpdatePackageInName (AcpiSdt, InPkgHandle, PciDeviceInfo->GPEPin, PciDeviceInfo->SxNum); + + Status = AcpiSdt->Close (InPkgHandle); + ASSERT_EFI_ERROR (Status); + + return; + +} + +/** + update wakeup info inside the PRW method for the given pci device handle + + @param AcpiSdt Pointer to Acpi SDT protocol + @param PciHandle ACPI pci device handle + @param PciDeviceInfo Pointer to PCI_DEVICE_INFO + +**/ +EFI_STATUS +SdtUpdatePrwPackage ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt, + IN EFI_ACPI_HANDLE PciHandle, + IN PCI_DEVICE_INFO *PciDeviceInfo + ) +{ + EFI_STATUS Status; + EFI_ACPI_HANDLE PrwPkgHandle; + + // + // Find the PRT method under this pci device + // + PrwPkgHandle = NULL; + Status = AcpiSdt->FindPath (PciHandle, "_PRW", &PrwPkgHandle); + + if (EFI_ERROR (Status)) { + return EFI_INVALID_PARAMETER; + } + + if (PrwPkgHandle == NULL) { + return EFI_INVALID_PARAMETER; + } + + SdtCheckNamePackage(AcpiSdt, PrwPkgHandle, PciDeviceInfo); + + Status = AcpiSdt->Close (PrwPkgHandle); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + update pci routing information in acpi table based on pcd settings + + @param AcpiSdt Pointer to Acpi SDT protocol + @param PciRootHandle ACPI root bridge handle + @param PciDeviceInfo Pointer to PCI_DEVICE_INFO + +**/ +EFI_STATUS +SdtUpdatePciRouting ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt, + IN EFI_ACPI_HANDLE PciRootHandle, + IN PCI_DEVICE_INFO *PciDeviceInfo + ) +{ + EFI_STATUS Status; + EFI_ACPI_HANDLE PciBridgeHandle; + UINT32 PciAddress; + + + PciBridgeHandle = NULL; + if (PciDeviceInfo->BridgeAddress == 0x00000000) { + // + // Its bridge is the host root bridge + // + PciBridgeHandle = PciRootHandle; + + } else { + + // + // Its bridge is just a pci device under the host bridge + // + + // + // Conver the bridge address into one that acpi table can recognize + // + PciAddress = SdtConvertToAcpiPciAdress (PciDeviceInfo->BridgeAddress); + + // + // Scan the whole table to find the pci device + // + PciBridgeHandle = SdtGetHandleByScanAllChilds(AcpiSdt, PciRootHandle, SdtFindPciDeviceHandle, &PciAddress); + if (PciBridgeHandle == NULL) { + + return EFI_INVALID_PARAMETER; + } + } + + Status = SdtUpdatePrtMethod(AcpiSdt, PciBridgeHandle, PciDeviceInfo); + + if (PciDeviceInfo->BridgeAddress != 0x00000000) { + Status = AcpiSdt->Close (PciBridgeHandle); + ASSERT_EFI_ERROR (Status); + } + + return Status; +} + + +/** + update power resource wake up information in acpi table based on pcd settings + + @param AcpiSdt Pointer to Acpi SDT protocol + @param PciRootHandle ACPI root bridge handle + @param PciDeviceInfo Pointer to PCI_DEVICE_INFO + +**/ +EFI_STATUS +SdtUpdatePowerWake ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt, + IN EFI_ACPI_HANDLE PciRootHandle, + IN PCI_DEVICE_INFO *PciDeviceInfo + ) +{ + EFI_STATUS Status; + EFI_ACPI_HANDLE PciBridgeHandle; + EFI_ACPI_HANDLE PciDeviceHandle; + UINT32 PciAddress; + + PciBridgeHandle = NULL; + if (PciDeviceInfo->BridgeAddress == 0x00000000) { + // + // Its bridge is the host root bridge + // + PciBridgeHandle = PciRootHandle; + + } else { + + // + // Its bridge is just a pci device under the host bridge + // + + // + // Conver the bridge address into one that acpi table can recognize + // + PciAddress = SdtConvertToAcpiPciAdress (PciDeviceInfo->BridgeAddress); + + // + // Scan the whole table to find the pci device + // + PciBridgeHandle = SdtGetHandleByScanAllChilds(AcpiSdt, PciRootHandle, SdtFindPciDeviceHandle, &PciAddress); + + if (PciBridgeHandle == NULL) { + + Status = AcpiSdt->Close (PciRootHandle); + ASSERT_EFI_ERROR (Status); + + return EFI_INVALID_PARAMETER; + } + } + + PciDeviceHandle = NULL; + + // + // Conver the device address into one that acpi table can recognize + // + PciAddress = SdtConvertToAcpiPciAdress (PciDeviceInfo->DeviceAddress); + + // + // Scan the whole table to find the pci device + // + PciDeviceHandle = SdtGetHandleByScanAllChilds(AcpiSdt, PciBridgeHandle, SdtFindPciDeviceHandle, &PciAddress); + + if (PciDeviceHandle == NULL) { + if (PciDeviceInfo->BridgeAddress != 0x00000000) { + Status = AcpiSdt->Close (PciBridgeHandle); + ASSERT_EFI_ERROR (Status); + } + + return EFI_INVALID_PARAMETER; + } + + Status = SdtUpdatePrwPackage(AcpiSdt, PciDeviceHandle, PciDeviceInfo); + + Status = AcpiSdt->Close (PciDeviceHandle); + ASSERT_EFI_ERROR (Status); + + if (PciDeviceInfo->BridgeAddress != 0x00000000) { + Status = AcpiSdt->Close (PciBridgeHandle); + ASSERT_EFI_ERROR (Status); + } + + return Status; +} + + +/** + Get the root bridge handle by scanning the acpi table + + @param AcpiSdt Pointer to Acpi SDT protocol + @param DsdtHandle ACPI root handle + + @retval EFI_ACPI_HANDLE the handle of the root bridge +**/ +EFI_ACPI_HANDLE +SdtGetRootBridgeHandle ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt, + IN EFI_ACPI_HANDLE DsdtHandle + ) +{ + EFI_ACPI_HANDLE PciRootHandle; + + // + // Scan the whole table to find the root bridge + // + PciRootHandle = NULL; + PciRootHandle = SdtGetHandleByScanAllChilds(AcpiSdt, DsdtHandle, SdtFindRootBridgeHandle, NULL); + ASSERT (PciRootHandle != NULL); + + return PciRootHandle; +} + + +/** + Check input Pci device info is changed from the default values + @param PciDeviceInfo Pointer to PCI_DEVICE_INFO + @param UpdatePRT Pointer to BOOLEAN + @param UpdatePRW Pointer to BOOLEAN + +**/ +VOID +SdtCheckPciDeviceInfoChanged ( + IN PCI_DEVICE_INFO *PciDeviceInfo, + IN BOOLEAN *UpdatePRT, + IN BOOLEAN *UpdatePRW + ) +{ + UINTN Index = 0; + + if (mQNCPciInfo == NULL) { + *UpdatePRT = FALSE; + *UpdatePRW = FALSE; + return; + } + + *UpdatePRT = TRUE; + *UpdatePRW = TRUE; + + for (Index = 0;Index < CURRENT_PCI_DEVICE_NUM; Index++) { + if ((mQNCPciInfo[Index].BridgeAddress == PciDeviceInfo->BridgeAddress) + && (mQNCPciInfo[Index].DeviceAddress == PciDeviceInfo->DeviceAddress)) { + // + // Find one matched entry + // + if (CompareMem (&(mQNCPciInfo[Index].INTA[0]), &PciDeviceInfo->INTA[0], 10) == 0) { + *UpdatePRT = FALSE; + *UpdatePRW = FALSE; + //DEBUG ((EFI_D_ERROR, "Find one matched entry[%d] and no change\n", Index)); + } else { + if (CompareMem (&(mQNCPciInfo[Index].INTA[0]), &PciDeviceInfo->INTA[0], 8) == 0) + *UpdatePRT = FALSE; + + if (CompareMem (&(mQNCPciInfo[Index].GPEPin), &PciDeviceInfo->GPEPin, 2) == 0) + *UpdatePRW = FALSE; + + if (*(UINT64 *)(&PciDeviceInfo->INTA[0]) == 0xFFFFFFFFFFFFFFFFULL) + *UpdatePRT = FALSE; + + if (*(UINT16 *)(&PciDeviceInfo->GPEPin) == 0xFFFF) + *UpdatePRW = FALSE; + + //DEBUG ((EFI_D_ERROR, "Find one matched entry[%d] and but need update PRT:0x%x PRW:0x%x\n", Index, *UpdatePRT, *UpdatePRW)); + } + break; + } + } + + //if (Index == 42) { + // DEBUG ((EFI_D_ERROR, "Find No matched entry\n")); + //} + + return; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.h b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.h new file mode 100644 index 0000000000..7d16dc47b9 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.h @@ -0,0 +1,316 @@ +/** @file +Update the _PRT and _PRW method for pci devices + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ +#ifndef _ACPI_PCI_UPDATE_H_ +#define _ACPI_PCI_UPDATE_H_ + + +// +// Primary OpCode +// +#define AML_ZERO_OP 0x00 +#define AML_ONE_OP 0x01 +#define AML_ALIAS_OP 0x06 +#define AML_NAME_OP 0x08 +#define AML_BYTE_PREFIX 0x0a +#define AML_WORD_PREFIX 0x0b +#define AML_DWORD_PREFIX 0x0c +#define AML_STRING_PREFIX 0x0d +#define AML_QWORD_PREFIX 0x0e +#define AML_SCOPE_OP 0x10 +#define AML_BUFFER_OP 0x11 +#define AML_PACKAGE_OP 0x12 +#define AML_VAR_PACKAGE_OP 0x13 +#define AML_METHOD_OP 0x14 +#define AML_DUAL_NAME_PREFIX 0x2e +#define AML_MULTI_NAME_PREFIX 0x2f +#define AML_NAME_CHAR_A 0x41 +#define AML_NAME_CHAR_B 0x42 +#define AML_NAME_CHAR_C 0x43 +#define AML_NAME_CHAR_D 0x44 +#define AML_NAME_CHAR_E 0x45 +#define AML_NAME_CHAR_F 0x46 +#define AML_NAME_CHAR_G 0x47 +#define AML_NAME_CHAR_H 0x48 +#define AML_NAME_CHAR_I 0x49 +#define AML_NAME_CHAR_J 0x4a +#define AML_NAME_CHAR_K 0x4b +#define AML_NAME_CHAR_L 0x4c +#define AML_NAME_CHAR_M 0x4d +#define AML_NAME_CHAR_N 0x4e +#define AML_NAME_CHAR_O 0x4f +#define AML_NAME_CHAR_P 0x50 +#define AML_NAME_CHAR_Q 0x51 +#define AML_NAME_CHAR_R 0x52 +#define AML_NAME_CHAR_S 0x53 +#define AML_NAME_CHAR_T 0x54 +#define AML_NAME_CHAR_U 0x55 +#define AML_NAME_CHAR_V 0x56 +#define AML_NAME_CHAR_W 0x57 +#define AML_NAME_CHAR_X 0x58 +#define AML_NAME_CHAR_Y 0x59 +#define AML_NAME_CHAR_Z 0x5a +#define AML_ROOT_CHAR 0x5c +#define AML_PARENT_PREFIX_CHAR 0x5e +#define AML_NAME_CHAR__ 0x5f +#define AML_LOCAL0 0x60 +#define AML_LOCAL1 0x61 +#define AML_LOCAL2 0x62 +#define AML_LOCAL3 0x63 +#define AML_LOCAL4 0x64 +#define AML_LOCAL5 0x65 +#define AML_LOCAL6 0x66 +#define AML_LOCAL7 0x67 +#define AML_ARG0 0x68 +#define AML_ARG1 0x69 +#define AML_ARG2 0x6a +#define AML_ARG3 0x6b +#define AML_ARG4 0x6c +#define AML_ARG5 0x6d +#define AML_ARG6 0x6e +#define AML_STORE_OP 0x70 +#define AML_REF_OF_OP 0x71 +#define AML_ADD_OP 0x72 +#define AML_CONCAT_OP 0x73 +#define AML_SUBTRACT_OP 0x74 +#define AML_INCREMENT_OP 0x75 +#define AML_DECREMENT_OP 0x76 +#define AML_MULTIPLY_OP 0x77 +#define AML_DIVIDE_OP 0x78 +#define AML_SHIFT_LEFT_OP 0x79 +#define AML_SHIFT_RIGHT_OP 0x7a +#define AML_AND_OP 0x7b +#define AML_NAND_OP 0x7c +#define AML_OR_OP 0x7d +#define AML_NOR_OP 0x7e +#define AML_XOR_OP 0x7f +#define AML_NOT_OP 0x80 +#define AML_FIND_SET_LEFT_BIT_OP 0x81 +#define AML_FIND_SET_RIGHT_BIT_OP 0x82 +#define AML_DEREF_OF_OP 0x83 +#define AML_CONCAT_RES_OP 0x84 +#define AML_MOD_OP 0x85 +#define AML_NOTIFY_OP 0x86 +#define AML_SIZE_OF_OP 0x87 +#define AML_INDEX_OP 0x88 +#define AML_MATCH_OP 0x89 +#define AML_CREATE_DWORD_FIELD_OP 0x8a +#define AML_CREATE_WORD_FIELD_OP 0x8b +#define AML_CREATE_BYTE_FIELD_OP 0x8c +#define AML_CREATE_BIT_FIELD_OP 0x8d +#define AML_OBJECT_TYPE_OP 0x8e +#define AML_CREATE_QWORD_FIELD_OP 0x8f +#define AML_LAND_OP 0x90 +#define AML_LOR_OP 0x91 +#define AML_LNOT_OP 0x92 +#define AML_LEQUAL_OP 0x93 +#define AML_LGREATER_OP 0x94 +#define AML_LLESS_OP 0x95 +#define AML_TO_BUFFER_OP 0x96 +#define AML_TO_DEC_STRING_OP 0x97 +#define AML_TO_HEX_STRING_OP 0x98 +#define AML_TO_INTEGER_OP 0x99 +#define AML_TO_STRING_OP 0x9c +#define AML_COPY_OBJECT_OP 0x9d +#define AML_MID_OP 0x9e +#define AML_CONTINUE_OP 0x9f +#define AML_IF_OP 0xa0 +#define AML_ELSE_OP 0xa1 +#define AML_WHILE_OP 0xa2 +#define AML_NOOP_OP 0xa3 +#define AML_RETURN_OP 0xa4 +#define AML_BREAK_OP 0xa5 +#define AML_BREAK_POINT_OP 0xcc +#define AML_ONES_OP 0xff + +// +// Extended OpCode +// +#define AML_EXT_OP 0x5b + +#define AML_EXT_MUTEX_OP 0x01 +#define AML_EXT_EVENT_OP 0x02 +#define AML_EXT_COND_REF_OF_OP 0x12 +#define AML_EXT_CREATE_FIELD_OP 0x13 +#define AML_EXT_LOAD_TABLE_OP 0x1f +#define AML_EXT_LOAD_OP 0x20 +#define AML_EXT_STALL_OP 0x21 +#define AML_EXT_SLEEP_OP 0x22 +#define AML_EXT_ACQUIRE_OP 0x23 +#define AML_EXT_SIGNAL_OP 0x24 +#define AML_EXT_WAIT_OP 0x25 +#define AML_EXT_RESET_OP 0x26 +#define AML_EXT_RELEASE_OP 0x27 +#define AML_EXT_FROM_BCD_OP 0x28 +#define AML_EXT_TO_BCD_OP 0x29 +#define AML_EXT_UNLOAD_OP 0x2a +#define AML_EXT_REVISION_OP 0x30 +#define AML_EXT_DEBUG_OP 0x31 +#define AML_EXT_FATAL_OP 0x32 +#define AML_EXT_TIMER_OP 0x33 +#define AML_EXT_REGION_OP 0x80 +#define AML_EXT_FIELD_OP 0x81 +#define AML_EXT_DEVICE_OP 0x82 +#define AML_EXT_PROCESSOR_OP 0x83 +#define AML_EXT_POWER_RES_OP 0x84 +#define AML_EXT_THERMAL_ZONE_OP 0x85 +#define AML_EXT_INDEX_FIELD_OP 0x86 +#define AML_EXT_BANK_FIELD_OP 0x87 +#define AML_EXT_DATA_REGION_OP 0x88 + +#pragma pack(1) + +typedef struct { + UINT32 BridgeAddress; + UINT32 DeviceAddress; + UINT8 INTA[2]; // the first member record the 8259 link, the second member record the io apic irq number + UINT8 INTB[2]; + UINT8 INTC[2]; + UINT8 INTD[2]; + + UINT8 GPEPin; + UINT8 SxNum; +} PCI_DEVICE_INFO; + +#pragma pack() + +#define PCI_DEVICE_INFO_MAX_NUM 50 +#define CURRENT_PCI_DEVICE_NUM 13 + +#define PIRQ_LINKA 1 +#define PIRQ_LINKB 2 +#define PIRQ_LINKC 3 +#define PIRQ_LINKD 4 +#define PIRQ_LINKE 5 +#define PIRQ_LINKF 6 +#define PIRQ_LINKG 7 +#define PIRQ_LINKH 8 +#define PIRQ_INVALID 0xFF + +typedef struct _PCI_DEVICE_SETTING{ + UINT8 PciDeviceInfoNumber; + PCI_DEVICE_INFO PciDeviceInfo[PCI_DEVICE_INFO_MAX_NUM]; +}PCI_DEVICE_SETTING; + +typedef struct _AML_BYTE_ENCODING AML_BYTE_ENCODING; + +// +// AML Handle Entry definition. +// +// Signature must be set to EFI_AML_HANDLE_SIGNATURE or EFI_AML_ROOT_HANDLE_SIGNATURE +// Buffer is the ACPI node buffer pointer, the first/second bytes are opcode. +// This buffer should not be freed. +// Size is the total size of this ACPI node buffer. +// +typedef struct { + UINT32 Signature; + UINT8 *Buffer; + UINTN Size; + AML_BYTE_ENCODING *AmlByteEncoding; + BOOLEAN Modified; +} EFI_AML_HANDLE; + +typedef UINT32 AML_OP_PARSE_INDEX; + +typedef UINT32 AML_OP_PARSE_FORMAT; + +typedef UINT32 AML_OP_ATTRIBUTE; + +struct _AML_BYTE_ENCODING { + UINT8 OpCode; + UINT8 SubOpCode; + AML_OP_PARSE_INDEX MaxIndex; + AML_OP_PARSE_FORMAT Format[6]; + AML_OP_ATTRIBUTE Attribute; +}; + + +// +// Check device info fucntion prototype +// +typedef +BOOLEAN +(* CHECK_HANDLE_INFO) ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt, + IN EFI_ACPI_HANDLE CheckHandle, + IN VOID *Context + ); + +extern EFI_ACPI_HANDLE mDsdtHandle; +extern EFI_ACPI_SDT_PROTOCOL *mAcpiSdt; + +/** + Init Pci Device Structure + + @param mConfigData - Pointer of Pci Device information Structure + +**/ +VOID +InitPciDeviceInfoStructure ( + PCI_DEVICE_SETTING *mConfigData + ); +/** + update pci routing information in acpi table based on pcd settings + + @param AcpiSdt Pointer to Acpi SDT protocol + @param DsdtHandle ACPI root handle + @param PciDeviceInfo Pointer to PCI_DEVICE_INFO + +**/ +EFI_STATUS +SdtUpdatePciRouting ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt, + IN EFI_ACPI_HANDLE DsdtHandle, + IN PCI_DEVICE_INFO *PciDeviceInfo + ); + + +/** + update power resource wake up information in acpi table based on pcd settings + + @param AcpiSdt Pointer to Acpi SDT protocol + @param DsdtHandle ACPI root handle + @param PciDeviceInfo Pointer to PCI_DEVICE_INFO + +**/ +EFI_STATUS +SdtUpdatePowerWake ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt, + IN EFI_ACPI_HANDLE DsdtHandle, + IN PCI_DEVICE_INFO *PciDeviceInfo + ); + +/** + Get the root bridge handle by scanning the acpi table + + @param AcpiSdt Pointer to Acpi SDT protocol + @param DsdtHandle ACPI root handle + + @retval EFI_ACPI_HANDLE the handle of the root bridge +**/ +EFI_ACPI_HANDLE +SdtGetRootBridgeHandle ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt, + IN EFI_ACPI_HANDLE DsdtHandle + ); + +/** + Check input Pci device info is changed from the default values + @param PciDeviceInfo Pointer to PCI_DEVICE_INFO + @param UpdatePRT Pointer to BOOLEAN + @param UpdatePRW Pointer to BOOLEAN + +**/ +VOID +SdtCheckPciDeviceInfoChanged ( + IN PCI_DEVICE_INFO *PciDeviceInfo, + IN BOOLEAN *UpdatePRT, + IN BOOLEAN *UpdatePRW + ); +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.c b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.c new file mode 100644 index 0000000000..bb7cc92212 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.c @@ -0,0 +1,805 @@ +/** @file +ACPI Platform Driver + +Copyright (c) 2013-2016 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include "AcpiPlatform.h" + +// +// Global Variable +// +EFI_GLOBAL_NVS_AREA_PROTOCOL mGlobalNvsArea; +EFI_ACPI_SDT_PROTOCOL *mAcpiSdt; + +EFI_ACPI_HANDLE mDsdtHandle = NULL; + + +EFI_STATUS +LocateSupportProtocol ( + IN EFI_GUID *Protocol, + OUT VOID **Instance, + IN UINT32 Type + ) +/*++ + +Routine Description: + + Locate the first instance of a protocol. If the protocol requested is an + FV protocol, then it will return the first FV that contains the ACPI table + storage file. + +Arguments: + + Protocol The protocol to find. + Instance Return pointer to the first instance of the protocol + +Returns: + + EFI_SUCCESS The function completed successfully. + EFI_NOT_FOUND The protocol could not be located. + EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol. + +--*/ +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + EFI_FV_FILETYPE FileType; + UINT32 FvStatus; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINTN Size; + UINTN i; + + FvStatus = 0; + + // + // Locate protocol. + // + Status = gBS->LocateHandleBuffer ( + ByProtocol, + Protocol, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + + // + // Defined errors at this time are not found and out of resources. + // + return Status; + } + + + + // + // Looking for FV with ACPI storage file + // + + for (i = 0; i < NumberOfHandles; i++) { + // + // Get the protocol on this handle + // This should not fail because of LocateHandleBuffer + // + Status = gBS->HandleProtocol ( + HandleBuffer[i], + Protocol, + Instance + ); + ASSERT_EFI_ERROR (Status); + + if (!Type) { + // + // Not looking for the FV protocol, so find the first instance of the + // protocol. There should not be any errors because our handle buffer + // should always contain at least one or LocateHandleBuffer would have + // returned not found. + // + break; + } + + // + // See if it has the ACPI storage file + // + + Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL*) (*Instance))->ReadFile (*Instance, + (EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile), + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + + // + // If we found it, then we are done + // + if (Status == EFI_SUCCESS) { + break; + } + } + + // + // Our exit status is determined by the success of the previous operations + // If the protocol was found, Instance already points to it. + // + + // + // Free any allocated buffers + // + gBS->FreePool (HandleBuffer); + + return Status; +} + + +VOID +DsdtTableUpdate ( + IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ) +/*++ + + Routine Description: + + Update the DSDT table + + Arguments: + + Table - The table to be set + Version - Version to publish + + Returns: + + None + +--*/ +{ + + UINT8 *CurrPtr; + UINT8 *DsdtPointer; + UINT32 *Signature; + UINT8 *Operation; + UINT32 *Address; + UINT16 *Size; + // + // Loop through the ASL looking for values that we must fix up. + // + CurrPtr = (UINT8 *) TableHeader; + for (DsdtPointer = CurrPtr; + DsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length); + DsdtPointer++ + ) + { + Signature = (UINT32 *) DsdtPointer; + switch (*Signature) { + // + // MNVS operation region + // + case (SIGNATURE_32 ('M', 'N', 'V', 'S')): + // + // Conditional match. For Region Objects, the Operator will always be the + // byte immediately before the specific name. Therefore, subtract 1 to check + // the Operator. + // + Operation = DsdtPointer - 1; + if (*Operation == AML_OPREGION_OP) { + Address = (UINT32 *) (DsdtPointer + 6); + *Address = (UINT32) (UINTN) mGlobalNvsArea.Area; + Size = (UINT16 *) (DsdtPointer + 11); + *Size = sizeof (EFI_GLOBAL_NVS_AREA); + } + break; + + // + // Update processor PBLK register I/O base address + // + case (SIGNATURE_32 ('P', 'R', 'I', 'O')): + // + // Conditional match. Update the following ASL code: + // Processor (CPU0, 0x01, 0x4F495250, 0x06) {} + // The 3rd parameter will be updated to the actual PBLK I/O base address. + // the Operator. + // + Operation = DsdtPointer - 8; + if ((*Operation == AML_EXT_OP) && (*(Operation + 1) == AML_EXT_PROCESSOR_OP)) { + *(UINT32 *)DsdtPointer = PcdGet16(PcdPmbaIoBaseAddress); + } + break; + default: + break; + } + } +} + + +VOID +ApicTableUpdate ( + IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ) +/*++ + + Routine Description: + + Update the processors information in the APIC table + + Arguments: + + Table - The table to be set + Version - Version to publish + + Returns: + + None + +--*/ +{ + EFI_STATUS Status; + EFI_MP_SERVICES_PROTOCOL *MpService; + UINT8 *CurrPtr; + UINT8 *EndPtr; + UINT8 CurrIoApic; + UINT8 CurrProcessor; + UINTN NumberOfCPUs; + UINTN NumberOfEnabledCPUs; + EFI_PROCESSOR_INFORMATION MpContext; + ACPI_APIC_STRUCTURE_PTR *ApicPtr; + + CurrIoApic = 0; + CurrProcessor = 0; + // + // Find the MP Protocol. This is an MP platform, so MP protocol must be + // there. + // + Status = gBS->LocateProtocol ( + &gEfiMpServiceProtocolGuid, + NULL, + (VOID**)&MpService + ); + if (EFI_ERROR (Status)) { + // + // Failed to get MP information, doesn't publish the invalid table + // + *Version = EFI_ACPI_TABLE_VERSION_NONE; + return; + } + + // + // Determine the number of processors + // + MpService->GetNumberOfProcessors ( + MpService, + &NumberOfCPUs, + &NumberOfEnabledCPUs + ); + + CurrPtr = (UINT8*) &(TableHeader[1]); + CurrPtr = CurrPtr + 8; // Size of Local APIC Address & Flag + EndPtr = (UINT8*) TableHeader; + EndPtr = EndPtr + TableHeader->Length; + + while (CurrPtr < EndPtr) { + + ApicPtr = (ACPI_APIC_STRUCTURE_PTR*) CurrPtr; + switch (ApicPtr->AcpiApicCommon.Type) { + + case EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC: + ApicPtr->AcpiLocalApic.Flags = 0; + ApicPtr->AcpiLocalApic.ApicId = 0; + Status = MpService->GetProcessorInfo ( + MpService, + CurrProcessor, + &MpContext + ); + + if (!EFI_ERROR (Status)) { + if (MpContext.StatusFlag & PROCESSOR_ENABLED_BIT) { + ApicPtr->AcpiLocalApic.Flags = EFI_ACPI_3_0_LOCAL_APIC_ENABLED; + } + ApicPtr->AcpiLocalApic.ApicId = (UINT8)MpContext.ProcessorId; + } + CurrProcessor++; + break; + + case EFI_ACPI_1_0_IO_APIC: + // + // IO APIC entries can be patched here + // + if (CurrIoApic == 0) { + // + // Update SOC internel IOAPIC base + // + ApicPtr->AcpiIoApic.IoApicId = PcdGet8 (PcdIoApicSettingIoApicId); + ApicPtr->AcpiIoApic.IoApicAddress = (UINT32)PcdGet64(PcdIoApicBaseAddress); + ApicPtr->AcpiIoApic.GlobalSystemInterruptBase = 0; + } else { + // + // Porting is required to update other IOAPIC entries if available + // + ASSERT (0); + } + CurrIoApic++; + break; + + default: + break; + }; + CurrPtr = CurrPtr + ApicPtr->AcpiApicCommon.Length; + } +} + +VOID +AcpiUpdateTable ( + IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ) +/*++ + + Routine Description: + + Set the correct table revision upon the setup value + + Arguments: + + Table - The table to be set + Version - Version to publish + + Returns: + + None + +--*/ + +{ + EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE *FadtHeader1; + EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *FadtHeader2; + EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *FadtHeader3; + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE *AllocationStructurePtr; + + if (TableHeader != NULL && Version != NULL) { + + *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0; + // + // Here we use all 3.0 signature because all version use same signature if they supported + // + switch (TableHeader->Signature) { + // + // "APIC" Multiple APIC Description Table + // + case EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE: + ApicTableUpdate (TableHeader, Version); + break; + // + // "DSDT" Differentiated System Description Table + // + case EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE: + DsdtTableUpdate (TableHeader, Version); + break; + + // + // "FACP" Fixed ACPI Description Table (FADT) + // + case EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE: + *Version = EFI_ACPI_TABLE_VERSION_NONE; + if (TableHeader->Revision == EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) { + *Version = EFI_ACPI_TABLE_VERSION_1_0B; + FadtHeader1 = (EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE *) TableHeader; + FadtHeader1->SmiCmd = PcdGet16(PcdSmmActivationPort); + FadtHeader1->Pm1aEvtBlk = PcdGet16(PcdPm1blkIoBaseAddress); + FadtHeader1->Pm1aCntBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C; + FadtHeader1->PmTmrBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1T; + FadtHeader1->Gpe0Blk = PcdGet16(PcdGpe0blkIoBaseAddress); + } else if (TableHeader->Revision == EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) { + *Version = EFI_ACPI_TABLE_VERSION_2_0; + FadtHeader2 = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *) TableHeader; + FadtHeader2->SmiCmd = PcdGet16(PcdSmmActivationPort); + FadtHeader2->Pm1aEvtBlk = PcdGet16(PcdPm1blkIoBaseAddress); + FadtHeader2->Pm1aCntBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C; + FadtHeader2->PmTmrBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1T; + FadtHeader2->Gpe0Blk = PcdGet16(PcdGpe0blkIoBaseAddress); + FadtHeader2->XPm1aEvtBlk.Address = FadtHeader2->Pm1aEvtBlk; + FadtHeader2->XPm1aCntBlk.Address = FadtHeader2->Pm1aCntBlk; + FadtHeader2->XPmTmrBlk.Address = FadtHeader2->PmTmrBlk; + FadtHeader2->XGpe0Blk.Address = FadtHeader2->Gpe0Blk; + } else if (TableHeader->Revision == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) { + *Version = EFI_ACPI_TABLE_VERSION_3_0; + FadtHeader3 = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *) TableHeader; + FadtHeader3->SmiCmd = PcdGet16(PcdSmmActivationPort); + FadtHeader3->Pm1aEvtBlk = PcdGet16(PcdPm1blkIoBaseAddress); + FadtHeader3->Pm1aCntBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C; + FadtHeader3->PmTmrBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1T; + FadtHeader3->Gpe0Blk = PcdGet16(PcdGpe0blkIoBaseAddress); + FadtHeader3->XPm1aEvtBlk.Address = FadtHeader3->Pm1aEvtBlk; + FadtHeader3->XPm1aCntBlk.Address = FadtHeader3->Pm1aCntBlk; + FadtHeader3->XPmTmrBlk.Address = FadtHeader3->PmTmrBlk; + FadtHeader3->XGpe0Blk.Address = FadtHeader3->Gpe0Blk; + } + break; + // + // "FACS" Firmware ACPI Control Structure + // + case EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE: + break; + // + // "SSDT" Secondary System Description Table + // + case EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE: + break; + // + // "HPET" IA-PC High Precision Event Timer Table + // + case EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE: + // + // If HPET is disabled in setup, don't publish the table. + // + if (mGlobalNvsArea.Area->HpetEnable == 0) { + *Version = EFI_ACPI_TABLE_VERSION_NONE; + } + ((EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER *) TableHeader)->BaseAddressLower32Bit.Address + = PcdGet64 (PcdHpetBaseAddress); + break; + // + // "SPCR" Serial Port Concole Redirection Table + // + case EFI_ACPI_3_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE: + break; + // + // "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table + // + case EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE: + AllocationStructurePtr = (EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE *) + ((UINT8 *)TableHeader + sizeof(EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER)); + AllocationStructurePtr->BaseAddress = PcdGet64(PcdPciExpressBaseAddress); + break; + // Lakeport platform doesn't support the following table + /* + // + // "ECDT" Embedded Controller Boot Resources Table + // + case EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE: + break; + // + // "PSDT" Persistent System Description Table + // + case EFI_ACPI_3_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE: + break; + // + // "SBST" Smart Battery Specification Table + // + case EFI_ACPI_3_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE: + break; + // + // "SLIT" System Locality Information Table + // + case EFI_ACPI_3_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE: + break; + // + // "SRAT" Static Resource Affinity Table + // + case EFI_ACPI_3_0_STATIC_RESOURCE_AFFINITY_TABLE_SIGNATURE: + break; + // + // "XSDT" Extended System Description Table + // + case EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE: + break; + // + // "BOOT" MS Simple Boot Spec + // + case EFI_ACPI_3_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE: + break; + // + // "CPEP" Corrected Platform Error Polling Table + // + case EFI_ACPI_3_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE: + break; + // + // "DBGP" MS Debug Port Spec + // + case EFI_ACPI_3_0_DEBUG_PORT_TABLE_SIGNATURE: + break; + // + // "ETDT" Event Timer Description Table + // + case EFI_ACPI_3_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE: + break; + // + // "SPMI" Server Platform Management Interface Table + // + case EFI_ACPI_3_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE: + break; + // + // "TCPA" Trusted Computing Platform Alliance Capabilities Table + // + case EFI_ACPI_3_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE: + break; + */ + default: + break; + } + } +} + +// +// Description: +// Entrypoint of Acpi Platform driver +// In: +// ImageHandle +// SystemTable +// Out: +// EFI_SUCCESS +// EFI_LOAD_ERROR +// EFI_OUT_OF_RESOURCES +// + +EFI_STATUS +AcpiPlatformEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol; + INTN Instance; + EFI_ACPI_COMMON_HEADER *CurrentTable; + UINTN TableHandle; + UINT32 FvStatus; + UINTN Size; + EFI_ACPI_TABLE_VERSION Version; + EFI_HANDLE Handle; + UINTN Index; + PCI_DEVICE_INFO *PciDeviceInfo; + EFI_ACPI_HANDLE PciRootHandle; + BOOLEAN UpdatePRT; + BOOLEAN UpdatePRW; + PCI_DEVICE_SETTING *mConfigData; + + DEBUG((DEBUG_INFO, "ACPI Platform start...\n")); + + Instance = 0; + TableHandle = 0; + CurrentTable = NULL; + mConfigData = NULL; + + // + // Initialize the EFI Driver Library + // + + ASSERT (sizeof (EFI_GLOBAL_NVS_AREA) == 512); + + Status = gBS->AllocatePool ( + EfiACPIMemoryNVS, + sizeof (EFI_GLOBAL_NVS_AREA), + (VOID**)&mGlobalNvsArea.Area + ); + + Handle = NULL; + Status = gBS->InstallProtocolInterface ( + &Handle, + &gEfiGlobalNvsAreaProtocolGuid, + EFI_NATIVE_INTERFACE, + &mGlobalNvsArea + ); + + ASSERT_EFI_ERROR (Status); + if (!EFI_ERROR (Status)) { + SetMem ( + mGlobalNvsArea.Area, + sizeof (EFI_GLOBAL_NVS_AREA), + 0 + ); + } + + // + // Initialize the data. Eventually, this will be controlled by setup options. + // + mGlobalNvsArea.Area->HpetEnable = PcdGetBool (PcdHpetEnable); + mGlobalNvsArea.Area->Pm1blkIoBaseAddress = PcdGet16(PcdPm1blkIoBaseAddress); + mGlobalNvsArea.Area->PmbaIoBaseAddress = PcdGet16(PcdPmbaIoBaseAddress); + mGlobalNvsArea.Area->Gpe0blkIoBaseAddress = PcdGet16(PcdGpe0blkIoBaseAddress); + mGlobalNvsArea.Area->GbaIoBaseAddress = PcdGet16(PcdGbaIoBaseAddress); + mGlobalNvsArea.Area->SmbaIoBaseAddress = PcdGet16(PcdSmbaIoBaseAddress); + mGlobalNvsArea.Area->WdtbaIoBaseAddress = PcdGet16(PcdWdtbaIoBaseAddress); + mGlobalNvsArea.Area->HpetBaseAddress = (UINT32)PcdGet64(PcdHpetBaseAddress); + mGlobalNvsArea.Area->HpetSize = (UINT32)PcdGet64(PcdHpetSize); + mGlobalNvsArea.Area->PciExpressBaseAddress= (UINT32)PcdGet64(PcdPciExpressBaseAddress); + mGlobalNvsArea.Area->PciExpressSize = (UINT32)PcdGet64(PcdPciExpressSize); + mGlobalNvsArea.Area->RcbaMmioBaseAddress = (UINT32)PcdGet64(PcdRcbaMmioBaseAddress); + mGlobalNvsArea.Area->RcbaMmioSize = (UINT32)PcdGet64(PcdRcbaMmioSize); + mGlobalNvsArea.Area->IoApicBaseAddress = (UINT32)PcdGet64(PcdIoApicBaseAddress); + mGlobalNvsArea.Area->IoApicSize = (UINT32)PcdGet64(PcdIoApicSize); + mGlobalNvsArea.Area->TpmPresent = (UINT32)(FALSE); + mGlobalNvsArea.Area->DBG2Present = (UINT32)(FALSE); + mGlobalNvsArea.Area->PlatformType = (UINT32)PcdGet16 (PcdPlatformType); + + // + // Configure platform IO expander I2C Slave Address. + // + if (mGlobalNvsArea.Area->PlatformType == Galileo) { + if (PlatformLegacyGpioGetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)) { + mGlobalNvsArea.Area->AlternateSla = FALSE; + } else { + mGlobalNvsArea.Area->AlternateSla = TRUE; + } + } + + // + // Find the AcpiTable protocol + // + Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID**)&AcpiTable); + if (EFI_ERROR (Status)) { + return EFI_ABORTED; + } + + // + // Initialize MADT table + // + Status = MadtTableInitialize (&CurrentTable, &Size); + ASSERT_EFI_ERROR (Status); + // + // Perform any table specific updates. + // + AcpiUpdateTable ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable, &Version); + + // + // Update the check sum + // It needs to be zeroed before the checksum calculation + // + ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum = 0; + ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum = + CalculateCheckSum8 ((VOID *)CurrentTable, CurrentTable->Length); + + // + // Add the table + // + TableHandle = 0; + Status = AcpiTable->InstallAcpiTable ( + AcpiTable, + CurrentTable, + CurrentTable->Length, + &TableHandle + ); + ASSERT_EFI_ERROR (Status); + CurrentTable = NULL; + + // + // Init Pci Device PRT PRW information structure from PCD + // + mConfigData = (PCI_DEVICE_SETTING *)AllocateZeroPool (sizeof (PCI_DEVICE_SETTING)); + ASSERT (mConfigData != NULL); + InitPciDeviceInfoStructure (mConfigData); + // + // Get the Acpi SDT protocol for manipulation on acpi table + // + Status = gBS->LocateProtocol (&gEfiAcpiSdtProtocolGuid, NULL, (VOID **)&mAcpiSdt); + ASSERT_EFI_ERROR (Status); + // + // Locate the firmware volume protocol + // + Status = LocateSupportProtocol (&gEfiFirmwareVolume2ProtocolGuid, (VOID**)&FwVol, 1); + if (EFI_ERROR (Status)) { + return EFI_ABORTED; + } + // + // Read tables from the storage file. + // + + while (Status == EFI_SUCCESS) { + + Status = FwVol->ReadSection ( + FwVol, + (EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile), + EFI_SECTION_RAW, + Instance, + (VOID**)&CurrentTable, + &Size, + &FvStatus + ); + + if (!EFI_ERROR(Status)) { + // + // Perform any table specific updates. + // + AcpiUpdateTable ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable, &Version); + + // + // Update the check sum + // It needs to be zeroed before the checksum calculation + // + ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum = 0; + ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum = + CalculateCheckSum8 ((VOID *)CurrentTable, CurrentTable->Length); + + // + // Add the table + // + TableHandle = 0; + Status = AcpiTable->InstallAcpiTable ( + AcpiTable, + CurrentTable, + ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length, + &TableHandle + ); + if (EFI_ERROR(Status)) { + return EFI_ABORTED; + } + // + // If this table is the DSDT table, then update the _PRT and _PRW based on + // the settings from pcds + // + if (CurrentTable->Signature == EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) { + // + // Create the root handle for DSDT table + // + Status = mAcpiSdt->OpenSdt (TableHandle, &mDsdtHandle); + ASSERT_EFI_ERROR (Status); + + PciRootHandle = NULL; + PciRootHandle = SdtGetRootBridgeHandle (mAcpiSdt, mDsdtHandle); + ASSERT (PciRootHandle != NULL); + + PciDeviceInfo = NULL; + for (Index = 0; Index < mConfigData->PciDeviceInfoNumber; Index++) { + PciDeviceInfo = &(mConfigData->PciDeviceInfo[Index]); + + // + // Check whether this is a valid item + // + if ((PciDeviceInfo->BridgeAddress != 0xFFFFFFFF) && (PciDeviceInfo->DeviceAddress != 0xFFFFFFFF)) { + + //DEBUG ((EFI_D_ERROR, "Valid pci info structure: bridge address:0x%x, device address:0x%x\n", PciDeviceInfo->BridgeAddress, PciDeviceInfo->DeviceAddress)); + + UpdatePRT = FALSE; + UpdatePRW = FALSE; + + SdtCheckPciDeviceInfoChanged (PciDeviceInfo, &UpdatePRT, &UpdatePRW); + // + // Check whether there is any valid pci routing item + // + if (UpdatePRT) { + // + // Update the pci routing information + // + //DEBUG ((EFI_D_ERROR, "Update _PRT\n")); + SdtUpdatePciRouting (mAcpiSdt, PciRootHandle, PciDeviceInfo); + } + // + // Check whether there is any valid pci routing item + // + if (UpdatePRW) { + // + // Update the pci wakeup information + // + //DEBUG ((EFI_D_ERROR, "Update _PRW\n")); + SdtUpdatePowerWake (mAcpiSdt, PciRootHandle, PciDeviceInfo); + } + } + } + Status = mAcpiSdt->Close (PciRootHandle); + ASSERT_EFI_ERROR (Status); + // + // Mark the root handle as modified , let SDT protocol recaculate the checksum + // + ((EFI_AML_HANDLE *)mDsdtHandle)->Modified = TRUE; + Status = mAcpiSdt->Close (mDsdtHandle); + ASSERT_EFI_ERROR (Status); + } + // + // Increment the instance + // + Instance++; + CurrentTable = NULL; + } + } + + gBS->FreePool (mConfigData); + return EFI_SUCCESS; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.h b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.h new file mode 100644 index 0000000000..920c7ef3a9 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.h @@ -0,0 +1,120 @@ +/** @file +This is an implementation of the ACPI platform driver. Requirements for +this driver are defined in the Tiano ACPI External Product Specification, +revision 0.3.6. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#ifndef _ACPI_PLATFORM_H_ +#define _ACPI_PLATFORM_H_ + +// +// Statements that include other header files +// + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "Madt.h" +#include "AcpiPciUpdate.h" + +#pragma pack(1) +typedef struct { + UINT8 StartByte; + UINT32 NameStr; + UINT8 OpCode; + UINT16 Size; // Hardcode to 16bit width because the table we use is fixed size + UINT8 NumEntries; +} EFI_ACPI_NAME_COMMAND; + +typedef struct { + UINT8 PackageOp; + UINT8 PkgLeadByte; + UINT8 NumEntries; + UINT8 DwordPrefix0; + UINT32 CoreFreq; + UINT8 DwordPrefix1; + UINT32 Power; + UINT8 DwordPrefix2; + UINT32 TransLatency; + UINT8 DwordPrefix3; + UINT32 BMLatency; + UINT8 DwordPrefix4; + UINT32 Control; + UINT8 DwordPrefix5; + UINT32 Status; +} EFI_PSS_PACKAGE; +#pragma pack() + + +#define AML_NAME_OP 0x08 +#define AML_METHOD_OP 0x14 +#define AML_OPREGION_OP 0x80 +#define AML_PACKAGE_OP 0x12 // Package operator. + +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_OEM_ID "INTEL " +#define EFI_ACPI_OEM_TABLE_ID 0x2020204F4E414954ULL // "TIANO " +#define EFI_ACPI_OEM_REVISION 0x00000002 +#define EFI_ACPI_CREATOR_ID 0x5446534D // "MSFT" +#define EFI_ACPI_CREATOR_REVISION 0x01000013 + +#define ACPI_COMPATIBLE_1_0 0 +#define ACPI_COMPATIBLE_2_0 1 +#define ACPI_COMPATIBLE_3_0 2 + + + + +// +// Private Driver Data +// + +// +// Define Union of IO APIC & Local APIC structure; +// + +typedef union { + EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE AcpiLocalApic; + EFI_ACPI_2_0_IO_APIC_STRUCTURE AcpiIoApic; + struct { + UINT8 Type; + UINT8 Length; + } AcpiApicCommon; +} ACPI_APIC_STRUCTURE_PTR; + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.inf b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.inf new file mode 100644 index 0000000000..5cbfd14ae6 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.inf @@ -0,0 +1,196 @@ +## @file +# Component description file for AcpiPlatform module. +# +# This is an implementation of the ACPI platform driver, +# whose requirements are from ACPI External Product Specification. +# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = AcpiPlatform + FILE_GUID = 368B3649-F204-4cd0-89A8-091077C070FA + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = AcpiPlatformEntryPoint + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 EBC +# + +[Sources] + AcpiPlatform.c + AcpiPlatform.h + MadtPlatform.c + Madt.h + AcpiPciUpdate.c + AcpiPciUpdate.h + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + QuarkSocPkg/QuarkSocPkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + +[LibraryClasses] + UefiLib + DxeServicesLib + PcdLib + IoLib + BaseMemoryLib + DebugLib + UefiRuntimeServicesTableLib + UefiBootServicesTableLib + UefiDriverEntryPoint + DevicePathLib + PlatformHelperLib + +[Protocols] + gEfiGlobalNvsAreaProtocolGuid # PROTOCOL ALWAYS_CONSUMED + gEfiMpServiceProtocolGuid # PROTOCOL SOMETIMES_CONSUMED + gEfiAcpiSdtProtocolGuid # PROTOCOL ALWAYS_CONSUMED + gEfiAcpiTableProtocolGuid # PROTOCOL ALWAYS_CONSUMED + +[Pcd] + gQuarkPlatformTokenSpaceGuid.PcdPlatformType + + gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress + + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0Enable + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0SourceIrq + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0Polarity + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0TrigerMode + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0GlobalIrq + + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1Enable + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1SourceIrq + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1Polarity + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1TrigerMode + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1GlobalIrq + + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2Enable + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2SourceIrq + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2Polarity + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2TrigerMode + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2GlobalIrq + + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3Enable + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3SourceIrq + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3Polarity + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3TrigerMode + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3GlobalIrq + + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4Enable + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4SourceIrq + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4Polarity + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4TrigerMode + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4GlobalIrq + + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5Enable + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5SourceIrq + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5Polarity + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5TrigerMode + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5GlobalIrq + + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6Enable + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6SourceIrq + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6Polarity + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6TrigerMode + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6GlobalIrq + + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7Enable + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7SourceIrq + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7Polarity + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7TrigerMode + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7GlobalIrq + + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8Enable + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8SourceIrq + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8Polarity + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8TrigerMode + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8GlobalIrq + + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9Enable + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9SourceIrq + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9Polarity + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9TrigerMode + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9GlobalIrq + + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10Enable + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10SourceIrq + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10Polarity + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10TrigerMode + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10GlobalIrq + + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11Enable + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11SourceIrq + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11Polarity + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11TrigerMode + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11GlobalIrq + + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12Enable + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12SourceIrq + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12Polarity + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12TrigerMode + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12GlobalIrq + + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13Enable + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13SourceIrq + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13Polarity + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13TrigerMode + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13GlobalIrq + + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14Enable + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14SourceIrq + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14Polarity + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14TrigerMode + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14GlobalIrq + + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15Enable + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15SourceIrq + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15Polarity + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15TrigerMode + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15GlobalIrq + + gEfiQuarkNcSocIdTokenSpaceGuid.PcdIoApicBaseAddress + gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingIoApicAddress + gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingGlobalInterruptBase + gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingIoApicId + gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingNmiEnable + gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingNmiSource + gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingPolarity + gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingTrigerMode + gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingNmiEnabelApicIdMask + gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingAddressOverrideEnable + gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingPolarity + gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingTrigerMode + gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingLocalApicLint + gQuarkPlatformTokenSpaceGuid.PcdLocalApicAddressOverride + + gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmmActivationPort + gEfiQuarkNcSocIdTokenSpaceGuid.PcdPm1blkIoBaseAddress + gEfiQuarkNcSocIdTokenSpaceGuid.PcdGpe0blkIoBaseAddress + gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoBaseAddress + gEfiQuarkNcSocIdTokenSpaceGuid.PcdGbaIoBaseAddress + gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmbaIoBaseAddress + gEfiQuarkNcSocIdTokenSpaceGuid.PcdHpetBaseAddress + gEfiQuarkNcSocIdTokenSpaceGuid.PcdHpetSize + gEfiQuarkNcSocIdTokenSpaceGuid.PcdIoApicBaseAddress + gEfiQuarkNcSocIdTokenSpaceGuid.PcdIoApicSize + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciExpressSize + gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioBaseAddress + gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioSize + gEfiQuarkNcSocIdTokenSpaceGuid.PcdWdtbaIoBaseAddress + gQuarkPlatformTokenSpaceGuid.PcdHpetEnable + gEfiQuarkNcSocIdTokenSpaceGuid.PcdDeviceEnables + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile + +[Depex] + gEfiMpServiceProtocolGuid AND gEfiAcpiTableProtocolGuid diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/Madt.h b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/Madt.h new file mode 100644 index 0000000000..7c67056944 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/Madt.h @@ -0,0 +1,207 @@ +/** @file +This file describes the contents of the ACPI Multiple APIC Description +Table (MADT). Some additional ACPI values are defined in Acpi10.h and +Acpi20.h. +To make changes to the MADT, it is necessary to update the count for the +APIC structure being updated, and to modify table found in Madt.c. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#ifndef _MADT_H +#define _MADT_H + + +// +// Statements that include other files +// + +#include +#include + +// +// MADT Definitions +// + +#define EFI_ACPI_OEM_MADT_REVISION 0x00000001 + +// +// Local APIC address +// + +#define EFI_ACPI_LOCAL_APIC_ADDRESS 0xFEE00000 + +// +// Multiple APIC Flags are defined in AcpiX.0.h +// +#define EFI_ACPI_1_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_1_0_PCAT_COMPAT) +#define EFI_ACPI_2_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_2_0_PCAT_COMPAT) + +// +// Define the number of each table type. +// This is where the table layout is modified. +// + +#define EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT 2 +#define EFI_ACPI_IO_APIC_COUNT 1 +#define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT 2 +#define EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT 0 +#define EFI_ACPI_LOCAL_APIC_NMI_COUNT 2 +#define EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT 0 +#define EFI_ACPI_IO_SAPIC_COUNT 0 +#define EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT 0 +#define EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT 0 + +#define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT_MAX 16 + +// +// MADT structure +// + +// +// Ensure proper structure formats +// +#pragma pack (1) + +// +// ACPI 1.0 Table structure +// +typedef struct { + EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + +#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0 + EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT]; +#endif + +#if EFI_ACPI_IO_APIC_COUNT > 0 + EFI_ACPI_1_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT]; +#endif + +#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 + EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0 + EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0 + EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0 + EFI_ACPI_1_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_OVERRIDE_COUNT]; +#endif + +} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + +// +// ACPI 2.0 Table structure +// +typedef struct { + EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + +#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0 + EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT]; +#endif + +#if EFI_ACPI_IO_APIC_COUNT > 0 + EFI_ACPI_2_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT]; +#endif + +#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 + EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0 + EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0 + EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0 + EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_IO_SAPIC_COUNT > 0 + EFI_ACPI_2_0_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT]; +#endif + +#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0 + EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT]; +#endif + +#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0 + EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT]; +#endif + +} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#define _PcdIntSettingTblEnable(x) PcdGet8 (PcdInterruptOverrideSettingTable##x##Enable) +#define PcdIntSettingTblEnable(x) _PcdIntSettingTblEnable(x) + +#define _PcdIntSettingTblSourceIrq(x) PcdGet8 (PcdInterruptOverrideSettingTable##x##Enable) +#define PcdIntSettingTblSourceIrq(x) _PcdIntSettingTblSourceIrq(x) + +#define _PcdIntSettingTblPolarity(x) PcdGet8 (PcdInterruptOverrideSettingTable##x##Polarity) +#define PcdIntSettingTblPolarity(x) _PcdIntSettingTblPolarity(x) + +#define _PcdIntSettingTableTrigerMode(x) PcdGet8 (PcdInterruptOverrideSettingTable##x##TrigerMode) +#define PcdIntSettingTableTrigerMode(x) _PcdIntSettingTableTrigerMode(x) + +#define _PcdIntSettingTableGlobalIrq(x) PcdGet32 (PcdInterruptOverrideSettingTable##x##GlobalIrq) +#define PcdIntSettingTableGlobalIrq(x) _PcdIntSettingTableGlobalIrq(x) + +typedef struct { + UINT8 Enable; + UINT8 SourceIrq; + UINT8 Polarity; + UINT8 TrigerMode; + UINT32 GlobalIrq; +} INTERRUPT_OVERRIDE_SETTING; + + +typedef struct { + UINT32 IoApicAddress; + UINT32 GlobalInterruptBase; + UINT8 IoApicId; + UINT8 NmiEnable; + UINT8 NmiSource; + UINT8 Polarity; + UINT8 TrigerMode; +} IO_APIC_SETTING; + +typedef struct { + UINT8 NmiEnabelApicIdMask; + UINT8 AddressOverrideEnable; + UINT8 Polarity; + UINT8 TrigerMode; + UINT8 LocalApicLint; + UINT8 Reserve[3]; + UINT32 LocalApicAddress; + UINT64 LocalApicAddressOverride; +} LOCAL_APIC_SETTING; + +typedef struct _MADT_CONFIG_DATA { + INTERRUPT_OVERRIDE_SETTING MadtInterruptSetting[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT_MAX]; + IO_APIC_SETTING MadtIoApicSetting; + LOCAL_APIC_SETTING MadtLocalApicSetting; +}MADT_CONFIG_DATA; + +#pragma pack () + +EFI_STATUS +EFIAPI +MadtTableInitialize ( + OUT EFI_ACPI_COMMON_HEADER **MadtTable, + OUT UINTN *Size + ); + + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/MadtPlatform.c b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/MadtPlatform.c new file mode 100644 index 0000000000..a7d24b013b --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/MadtPlatform.c @@ -0,0 +1,300 @@ +/** @file +This file contains Madt Talbe initialized work. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +// +// Statements that include other files +// + +#include "AcpiPlatform.h" + +VOID +InitMadtConfigData (MADT_CONFIG_DATA *mConfigData) +{ + mConfigData->MadtInterruptSetting[0].Enable = PcdGet8 (PcdInterruptOverrideSettingTable0Enable); + mConfigData->MadtInterruptSetting[0].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable0SourceIrq); + mConfigData->MadtInterruptSetting[0].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable0Polarity); + mConfigData->MadtInterruptSetting[0].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable0TrigerMode); + mConfigData->MadtInterruptSetting[0].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable0GlobalIrq); + + mConfigData->MadtInterruptSetting[1].Enable = PcdGet8 (PcdInterruptOverrideSettingTable1Enable); + mConfigData->MadtInterruptSetting[1].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable1SourceIrq); + mConfigData->MadtInterruptSetting[1].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable1Polarity); + mConfigData->MadtInterruptSetting[1].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable1TrigerMode); + mConfigData->MadtInterruptSetting[1].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable1GlobalIrq); + + mConfigData->MadtInterruptSetting[2].Enable = PcdGet8 (PcdInterruptOverrideSettingTable2Enable); + mConfigData->MadtInterruptSetting[2].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable2SourceIrq); + mConfigData->MadtInterruptSetting[2].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable2Polarity); + mConfigData->MadtInterruptSetting[2].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable2TrigerMode); + mConfigData->MadtInterruptSetting[2].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable2GlobalIrq); + + mConfigData->MadtInterruptSetting[3].Enable = PcdGet8 (PcdInterruptOverrideSettingTable3Enable); + mConfigData->MadtInterruptSetting[3].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable3SourceIrq); + mConfigData->MadtInterruptSetting[3].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable3Polarity); + mConfigData->MadtInterruptSetting[3].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable3TrigerMode); + mConfigData->MadtInterruptSetting[3].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable3GlobalIrq); + + mConfigData->MadtInterruptSetting[4].Enable = PcdGet8 (PcdInterruptOverrideSettingTable4Enable); + mConfigData->MadtInterruptSetting[4].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable4SourceIrq); + mConfigData->MadtInterruptSetting[4].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable4Polarity); + mConfigData->MadtInterruptSetting[4].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable4TrigerMode); + mConfigData->MadtInterruptSetting[4].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable4GlobalIrq); + + mConfigData->MadtInterruptSetting[5].Enable = PcdGet8 (PcdInterruptOverrideSettingTable5Enable); + mConfigData->MadtInterruptSetting[5].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable5SourceIrq); + mConfigData->MadtInterruptSetting[5].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable5Polarity); + mConfigData->MadtInterruptSetting[5].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable5TrigerMode); + mConfigData->MadtInterruptSetting[5].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable5GlobalIrq); + + mConfigData->MadtInterruptSetting[6].Enable = PcdGet8 (PcdInterruptOverrideSettingTable6Enable); + mConfigData->MadtInterruptSetting[6].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable6SourceIrq); + mConfigData->MadtInterruptSetting[6].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable6Polarity); + mConfigData->MadtInterruptSetting[6].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable6TrigerMode); + mConfigData->MadtInterruptSetting[6].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable6GlobalIrq); + + mConfigData->MadtInterruptSetting[7].Enable = PcdGet8 (PcdInterruptOverrideSettingTable7Enable); + mConfigData->MadtInterruptSetting[7].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable7SourceIrq); + mConfigData->MadtInterruptSetting[7].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable7Polarity); + mConfigData->MadtInterruptSetting[7].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable7TrigerMode); + mConfigData->MadtInterruptSetting[7].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable7GlobalIrq); + + mConfigData->MadtInterruptSetting[8].Enable = PcdGet8 (PcdInterruptOverrideSettingTable8Enable); + mConfigData->MadtInterruptSetting[8].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable8SourceIrq); + mConfigData->MadtInterruptSetting[8].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable8Polarity); + mConfigData->MadtInterruptSetting[8].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable8TrigerMode); + mConfigData->MadtInterruptSetting[8].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable8GlobalIrq); + + mConfigData->MadtInterruptSetting[9].Enable = PcdGet8 (PcdInterruptOverrideSettingTable9Enable); + mConfigData->MadtInterruptSetting[9].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable9SourceIrq); + mConfigData->MadtInterruptSetting[9].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable9Polarity); + mConfigData->MadtInterruptSetting[9].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable9TrigerMode); + mConfigData->MadtInterruptSetting[9].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable9GlobalIrq); + + mConfigData->MadtInterruptSetting[10].Enable = PcdGet8 (PcdInterruptOverrideSettingTable10Enable); + mConfigData->MadtInterruptSetting[10].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable10SourceIrq); + mConfigData->MadtInterruptSetting[10].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable10Polarity); + mConfigData->MadtInterruptSetting[10].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable10TrigerMode); + mConfigData->MadtInterruptSetting[10].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable10GlobalIrq); + + mConfigData->MadtInterruptSetting[11].Enable = PcdGet8 (PcdInterruptOverrideSettingTable11Enable); + mConfigData->MadtInterruptSetting[11].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable11SourceIrq); + mConfigData->MadtInterruptSetting[11].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable11Polarity); + mConfigData->MadtInterruptSetting[11].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable11TrigerMode); + mConfigData->MadtInterruptSetting[11].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable11GlobalIrq); + + mConfigData->MadtInterruptSetting[12].Enable = PcdGet8 (PcdInterruptOverrideSettingTable12Enable); + mConfigData->MadtInterruptSetting[12].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable12SourceIrq); + mConfigData->MadtInterruptSetting[12].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable12Polarity); + mConfigData->MadtInterruptSetting[12].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable12TrigerMode); + mConfigData->MadtInterruptSetting[12].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable12GlobalIrq); + + mConfigData->MadtInterruptSetting[13].Enable = PcdGet8 (PcdInterruptOverrideSettingTable13Enable); + mConfigData->MadtInterruptSetting[13].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable13SourceIrq); + mConfigData->MadtInterruptSetting[13].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable13Polarity); + mConfigData->MadtInterruptSetting[13].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable13TrigerMode); + mConfigData->MadtInterruptSetting[13].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable13GlobalIrq); + + mConfigData->MadtInterruptSetting[14].Enable = PcdGet8 (PcdInterruptOverrideSettingTable14Enable); + mConfigData->MadtInterruptSetting[14].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable14SourceIrq); + mConfigData->MadtInterruptSetting[14].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable14Polarity); + mConfigData->MadtInterruptSetting[14].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable14TrigerMode); + mConfigData->MadtInterruptSetting[14].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable14GlobalIrq); + + mConfigData->MadtInterruptSetting[15].Enable = PcdGet8 (PcdInterruptOverrideSettingTable15Enable); + mConfigData->MadtInterruptSetting[15].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable15SourceIrq); + mConfigData->MadtInterruptSetting[15].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable15Polarity); + mConfigData->MadtInterruptSetting[15].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable15TrigerMode); + mConfigData->MadtInterruptSetting[15].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable15GlobalIrq); + + mConfigData->MadtIoApicSetting.IoApicAddress = (UINT32)PcdGet64(PcdIoApicBaseAddress); + mConfigData->MadtIoApicSetting.GlobalInterruptBase = PcdGet32 (PcdIoApicSettingGlobalInterruptBase); + mConfigData->MadtIoApicSetting.IoApicId = PcdGet8 (PcdIoApicSettingIoApicId); + mConfigData->MadtIoApicSetting.NmiEnable = PcdGet8 (PcdIoApicSettingNmiEnable); + mConfigData->MadtIoApicSetting.NmiSource = PcdGet8 (PcdIoApicSettingNmiSource); + mConfigData->MadtIoApicSetting.Polarity = PcdGet8 (PcdIoApicSettingPolarity); + mConfigData->MadtIoApicSetting.TrigerMode = PcdGet8 (PcdIoApicSettingTrigerMode); + + mConfigData->MadtLocalApicSetting.NmiEnabelApicIdMask = PcdGet8 (PcdLocalApicSettingNmiEnabelApicIdMask); + mConfigData->MadtLocalApicSetting.AddressOverrideEnable = PcdGet8 (PcdLocalApicSettingAddressOverrideEnable); + mConfigData->MadtLocalApicSetting.Polarity = PcdGet8 (PcdLocalApicSettingPolarity); + mConfigData->MadtLocalApicSetting.TrigerMode = PcdGet8 (PcdLocalApicSettingTrigerMode); + mConfigData->MadtLocalApicSetting.LocalApicLint = PcdGet8 (PcdLocalApicSettingLocalApicLint); + mConfigData->MadtLocalApicSetting.LocalApicAddressOverride = PcdGet64 (PcdLocalApicAddressOverride); + mConfigData->MadtLocalApicSetting.LocalApicAddress = PcdGet32 (PcdCpuLocalApicBaseAddress); +} +UINT32 +GetAcutalMadtTableSize ( + IN MADT_CONFIG_DATA * MadtConfigData, + IN INTN NumberOfCPUs + ) +{ + UINT32 MadtSize; + UINT8 Index; + MadtSize = (UINT32)(sizeof (EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER) + + sizeof (EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE) * NumberOfCPUs + + sizeof (EFI_ACPI_2_0_IO_APIC_STRUCTURE) + + sizeof (EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE) * (MadtConfigData->MadtLocalApicSetting.AddressOverrideEnable != 0?1:0) + ); + for (Index = 0; Index < EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT_MAX; Index ++ ) { + if (MadtConfigData->MadtInterruptSetting[Index].Enable != 0) { + MadtSize += sizeof (EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE); + } + } + for (Index = 0; Index < NumberOfCPUs; Index ++ ) { + if (0 != (MadtConfigData->MadtLocalApicSetting.NmiEnabelApicIdMask & (1 << Index))) { + MadtSize += sizeof (EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE); + } + } + if (0 != MadtConfigData->MadtIoApicSetting.NmiEnable) { + MadtSize += sizeof (EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE); + } + return MadtSize; +} + +// +// Init Multiple APIC Description Table +// +EFI_STATUS +MadtTableInitialize ( + OUT EFI_ACPI_COMMON_HEADER **MadtTable, + OUT UINTN *Size + ) +{ + EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *Madt; + EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE *ProcLocalApic; + EFI_ACPI_2_0_IO_APIC_STRUCTURE *IoApic; + EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE *InterruptSourceOverride; + EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE *IoApicNmiSource; + EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE *LocalApicNmiSource; + EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE *LocalApicAddressOverride; + + EFI_MP_SERVICES_PROTOCOL *MpService; + UINTN NumberOfCPUs; + UINTN NumberOfEnabledCPUs; + MADT_CONFIG_DATA MadtConfigData; + + UINT32 MadtSize; + UINTN Index; + EFI_STATUS Status; + + + ASSERT (NULL != MadtTable); + ASSERT (NULL != Size); + // + // Init Madt table data + // + InitMadtConfigData (&MadtConfigData); + // + // Find the MP Protocol. This is an MP platform, so MP protocol must be + // there. + // + Status = gBS->LocateProtocol ( + &gEfiMpServiceProtocolGuid, + NULL, + (VOID **)&MpService + ); + ASSERT_EFI_ERROR (Status); + // + // Determine the number of processors + // + MpService->GetNumberOfProcessors ( + MpService, + &NumberOfCPUs, + &NumberOfEnabledCPUs + ); + //ASSERT (NumberOfCPUs <= 2 && NumberOfCPUs > 0); + MadtSize = GetAcutalMadtTableSize (&MadtConfigData, NumberOfCPUs); + Madt = (EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *)AllocateZeroPool (MadtSize); + ASSERT (Madt != NULL); + // + // Initialize MADT Header information + // + Madt->Header.Signature = EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE; + Madt->Header.Length = MadtSize; + Madt->Header.Revision = EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION; + Madt->Header.OemTableId = EFI_ACPI_OEM_TABLE_ID; + Madt->Header.OemRevision = EFI_ACPI_OEM_MADT_REVISION; + Madt->Header.CreatorId = EFI_ACPI_CREATOR_ID; + Madt->LocalApicAddress = MadtConfigData.MadtLocalApicSetting.LocalApicAddress; + Madt->Flags = EFI_ACPI_2_0_MULTIPLE_APIC_FLAGS; + CopyMem (Madt->Header.OemId, EFI_ACPI_OEM_ID, 6); + + ProcLocalApic = (EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE *) (Madt + 1); + // + // Initialization of Processor's local APICs + // + for (Index = 0;Index < NumberOfCPUs; Index++) { + ProcLocalApic[Index].Type = EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC; + ProcLocalApic[Index].Length = sizeof (EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE); + ProcLocalApic[Index].AcpiProcessorId = (UINT8)(Index + 1); + ProcLocalApic[Index].ApicId = 0xff; + ProcLocalApic[Index].Flags = 0; + } + // + // Initialization of IO APIC. + // Note: Here assumes that there must be one and only one IO APIC in platform. + // + IoApic = (EFI_ACPI_2_0_IO_APIC_STRUCTURE *) (&ProcLocalApic[Index]); + IoApic->Type = EFI_ACPI_2_0_IO_APIC; + IoApic->Length = sizeof (EFI_ACPI_2_0_IO_APIC_STRUCTURE); + IoApic->IoApicId = MadtConfigData.MadtIoApicSetting.IoApicId; + IoApic->IoApicAddress = MadtConfigData.MadtIoApicSetting.IoApicAddress; + IoApic->GlobalSystemInterruptBase = MadtConfigData.MadtIoApicSetting.GlobalInterruptBase; + + InterruptSourceOverride = (EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE *) (IoApic + 1); + for (Index = 0;Index < EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT_MAX; Index++ ){ + if (MadtConfigData.MadtInterruptSetting[Index].Enable) { + InterruptSourceOverride->Type = EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE; + InterruptSourceOverride->Length = sizeof (EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE); + InterruptSourceOverride->Bus = 0; + InterruptSourceOverride->Source = MadtConfigData.MadtInterruptSetting[Index].SourceIrq; + InterruptSourceOverride->Flags = ((MadtConfigData.MadtInterruptSetting[Index].TrigerMode & 0x03) << 2) | (MadtConfigData.MadtInterruptSetting[Index].Polarity & 0x03); + InterruptSourceOverride->GlobalSystemInterrupt = MadtConfigData.MadtInterruptSetting[Index].GlobalIrq; + InterruptSourceOverride++; + } + } + // + // support NMI source configuration. + // + IoApicNmiSource = (EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE *) InterruptSourceOverride; + if ((BOOLEAN) MadtConfigData.MadtIoApicSetting.NmiEnable) { + IoApicNmiSource->Type = EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE; + IoApicNmiSource->Length = sizeof (EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE); + IoApicNmiSource->Flags = ((MadtConfigData.MadtIoApicSetting.TrigerMode & 0x03) << 2) | (MadtConfigData.MadtIoApicSetting.Polarity & 0x03); + IoApicNmiSource->GlobalSystemInterrupt = MadtConfigData.MadtIoApicSetting.NmiSource; + IoApicNmiSource ++; + } + // + // Assume each processor has same NMI interrupt source. + // + LocalApicNmiSource = (EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE *) IoApicNmiSource; + for (Index = 0;Index < NumberOfCPUs; Index++) { + if (0 != (MadtConfigData.MadtLocalApicSetting.NmiEnabelApicIdMask & (1 << Index))){ + LocalApicNmiSource->Type = EFI_ACPI_2_0_LOCAL_APIC_NMI; + LocalApicNmiSource->Length = sizeof (EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE); + LocalApicNmiSource->LocalApicLint = MadtConfigData.MadtLocalApicSetting.LocalApicLint; + LocalApicNmiSource->Flags = ((MadtConfigData.MadtLocalApicSetting.TrigerMode & 0x03) << 2) | (MadtConfigData.MadtLocalApicSetting.Polarity & 0x03); + LocalApicNmiSource->AcpiProcessorId = (UINT8)(Index + 1); + LocalApicNmiSource++; + } + } + + LocalApicAddressOverride = (EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE *) LocalApicNmiSource; + if ((BOOLEAN) MadtConfigData.MadtLocalApicSetting.AddressOverrideEnable) { + LocalApicAddressOverride->Type = EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE; + LocalApicAddressOverride->Length = sizeof (EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE); + LocalApicAddressOverride->LocalApicAddress = MadtConfigData.MadtLocalApicSetting.LocalApicAddressOverride; + LocalApicAddressOverride++; + } + *Size = MadtSize; + *MadtTable = (EFI_ACPI_COMMON_HEADER *) Madt; + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/BootScriptExecutorDxe.inf b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/BootScriptExecutorDxe.inf new file mode 100644 index 0000000000..a89cba774a --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/BootScriptExecutorDxe.inf @@ -0,0 +1,77 @@ +## @file +# Boot Script Executor Module +# +# This is a standalone Boot Script Executor. Standalone means it does not +# depends on any PEI or DXE service. +# +# Copyright (c) 2013-2015 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = BootScriptExecutorDxe + FILE_GUID = FA20568B-548B-4b2b-81EF-1BA08D4A3CEC + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = BootScriptExecutorEntryPoint + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 +# + +[Sources] + ScriptExecute.h + ScriptExecute.c + +[Sources.Ia32] + IA32/SetIdtEntry.c + IA32/S3Asm.asm + IA32/S3Asm.S + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + QuarkSocPkg/QuarkSocPkg.dec + +[LibraryClasses] + TimerLib + PcdLib + BaseMemoryLib + SmbusLib + UefiDriverEntryPoint + BaseLib + PciLib + IoLib + S3BootScriptLib + PeCoffLib + DxeServicesLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + CacheMaintenanceLib + UefiLib + DebugAgentLib + LockBoxLib + IntelQNCLib + QNCAccessLib + +[Guids] + gEfiBootScriptExecutorVariableGuid + gEfiBootScriptExecutorContextGuid + gPerformanceProtocolGuid + gEfiEventExitBootServicesGuid + +[FeaturePcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable + +[Depex] + gEfiLockBoxProtocolGuid diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/S3Asm.S b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/S3Asm.S new file mode 100644 index 0000000000..1cb7b86fc3 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/S3Asm.S @@ -0,0 +1,44 @@ +## @file +# +# Copyright (c) 2013-2015 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent + +#----------------------------------------- +#VOID +#AsmTransferControl ( +# IN UINT32 S3WakingVector, +# IN UINT32 AcpiLowMemoryBase +# ); +#----------------------------------------- + +ASM_GLOBAL ASM_PFX(AsmTransferControl) +ASM_PFX(AsmTransferControl): + # S3WakingVector :DWORD + # AcpiLowMemoryBase :DWORD + pushl %ebp + movl %esp,%ebp + leal LABLE, %eax + pushl $0x28 # CS + pushl %eax + movl 8(%ebp),%ecx + shrdl $20,%ecx,%ebx + andl $0xf,%ecx + movw %cx,%bx + movl %ebx, jmp_addr + lret +LABLE: + .byte 0xb8,0x30,0 # mov ax, 30h as selector + movw %ax,%ds + movw %ax,%es + movw %ax,%fs + movw %ax,%gs + movw %ax,%ss + movl %cr0, %eax # Get control register 0 + .byte 0x66 + .byte 0x83,0xe0,0xfe # and eax, 0fffffffeh ; Clear PE bit (bit #0) + .byte 0xf,0x22,0xc0 # mov cr0, eax ; Activate real mode + .byte 0xea # jmp far @jmp_addr +jmp_addr: + .long 0 + diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/S3Asm.asm b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/S3Asm.asm new file mode 100644 index 0000000000..e932200c89 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/S3Asm.asm @@ -0,0 +1,51 @@ +;; @file +; This is the assembly code for transferring to control to OS S3 waking vector +; for IA32 platform +; +; Copyright (c) 2013-2015 Intel Corporation. +; +; SPDX-License-Identifier: BSD-2-Clause-Patent + + .586P + .model flat,C + .code + +;----------------------------------------- +;VOID +;AsmTransferControl ( +; IN UINT32 S3WakingVector, +; IN UINT32 AcpiLowMemoryBase +; ); +;----------------------------------------- + +AsmTransferControl PROC + ; S3WakingVector :DWORD + ; AcpiLowMemoryBase :DWORD + push ebp + mov ebp, esp + lea eax, @F + push 28h ; CS + push eax + mov ecx, [ebp + 8] + shrd ebx, ecx, 20 + and ecx, 0fh + mov bx, cx + mov @jmp_addr, ebx + retf +@@: + DB 0b8h, 30h, 0 ; mov ax, 30h as selector + mov ds, ax + mov es, ax + mov fs, ax + mov gs, ax + mov ss, ax + mov eax, cr0 ; Get control register 0 + DB 66h + DB 83h, 0e0h, 0feh ; and eax, 0fffffffeh ; Clear PE bit (bit #0) + DB 0fh, 22h, 0c0h ; mov cr0, eax ; Activate real mode + DB 0eah ; jmp far @jmp_addr +@jmp_addr DD ? + +AsmTransferControl ENDP + + END diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/SetIdtEntry.c b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/SetIdtEntry.c new file mode 100644 index 0000000000..e234c16f01 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/SetIdtEntry.c @@ -0,0 +1,57 @@ +/** @file +Set a IDT entry for debug purpose + +Set a IDT entry for interrupt vector 3 for debug purpose for IA32 platform + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include "ScriptExecute.h" +// +// INTERRUPT_GATE_DESCRIPTOR and SetIdtEntry () are used to setup IDT to do debug +// + +#pragma pack(1) + +typedef struct { + UINT16 OffsetLow; + UINT16 SegmentSelector; + UINT16 Attributes; + UINT16 OffsetHigh; +} INTERRUPT_GATE_DESCRIPTOR; + +#define INTERRUPT_GATE_ATTRIBUTE 0x8e00 + +#pragma pack() +/** + Set a IDT entry for interrupt vector 3 for debug purpose. + + @param AcpiS3Context a pointer to a structure of ACPI_S3_CONTEXT + +**/ +VOID +SetIdtEntry ( + IN ACPI_S3_CONTEXT *AcpiS3Context + ) +{ + INTERRUPT_GATE_DESCRIPTOR *IdtEntry; + IA32_DESCRIPTOR *IdtDescriptor; + UINTN S3DebugBuffer; + + // + // Restore IDT for debug + // + IdtDescriptor = (IA32_DESCRIPTOR *) (UINTN) (AcpiS3Context->IdtrProfile); + IdtEntry = (INTERRUPT_GATE_DESCRIPTOR *)(IdtDescriptor->Base + (3 * sizeof (INTERRUPT_GATE_DESCRIPTOR))); + S3DebugBuffer = (UINTN) (AcpiS3Context->S3DebugBufferAddress); + + IdtEntry->OffsetLow = (UINT16)S3DebugBuffer; + IdtEntry->SegmentSelector = (UINT16)AsmReadCs (); + IdtEntry->Attributes = (UINT16)INTERRUPT_GATE_ATTRIBUTE; + IdtEntry->OffsetHigh = (UINT16)(S3DebugBuffer >> 16); + + AsmWriteIdtr (IdtDescriptor); +} + diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/ScriptExecute.c b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/ScriptExecute.c new file mode 100644 index 0000000000..bfd273f142 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/ScriptExecute.c @@ -0,0 +1,379 @@ +/** @file +This is the code for Boot Script Executer module. + +This driver is dispatched by Dxe core and the driver will reload itself to ACPI NVS memory +in the entry point. The functionality is to interpret and restore the S3 boot script + +Copyright (c) 2013-2016 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "ScriptExecute.h" + +#pragma pack(1) +typedef union { + struct { + UINT32 LimitLow : 16; + UINT32 BaseLow : 16; + UINT32 BaseMid : 8; + UINT32 Type : 4; + UINT32 System : 1; + UINT32 Dpl : 2; + UINT32 Present : 1; + UINT32 LimitHigh : 4; + UINT32 Software : 1; + UINT32 Reserved : 1; + UINT32 DefaultSize : 1; + UINT32 Granularity : 1; + UINT32 BaseHigh : 8; + } Bits; + UINT64 Uint64; +} IA32_GDT; + +#pragma pack() + +EFI_GUID mBootScriptExecutorImageGuid = { + 0x9a8d3433, 0x9fe8, 0x42b6, {0x87, 0xb, 0x1e, 0x31, 0xc8, 0x4e, 0xbe, 0x3b} +}; + +// +// Global Descriptor Table (GDT) +// +GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT mGdtEntries[] = { +/* selector { Global Segment Descriptor } */ +/* 0x00 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, +/* 0x08 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, +/* 0x10 */ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 1, 1, 0}}, +/* 0x18 */ {{0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 1, 1, 0}}, +/* 0x20 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, +/* 0x28 */ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 0, 1, 0}}, +/* 0x30 */ {{0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 0, 1, 0}}, +/* 0x38 */ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 1, 0, 1, 0}}, +/* 0x40 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, +}; + +// +// IA32 Gdt register +// +GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR mGdt = { + sizeof (mGdtEntries) - 1, + (UINTN) mGdtEntries + }; + +/** + Entry function of Boot script exector. This function will be executed in + S3 boot path. + This function should not return, because it is invoked by switch stack. + + @param AcpiS3Context a pointer to a structure of ACPI_S3_CONTEXT + @param PeiS3ResumeState a pointer to a structure of PEI_S3_RESUME_STATE + + @retval EFI_INVALID_PARAMETER - OS waking vector not found + @retval EFI_UNSUPPORTED - something wrong when we resume to OS +**/ +EFI_STATUS +EFIAPI +S3BootScriptExecutorEntryFunction ( + IN ACPI_S3_CONTEXT *AcpiS3Context, + IN PEI_S3_RESUME_STATE *PeiS3ResumeState + ) +{ + EFI_STATUS Status; + + // + // Disable interrupt of Debug timer, since new IDT table cannot handle it. + // + SaveAndSetDebugTimerInterrupt (FALSE); + + // + // Restore IDT for debug + // + SetIdtEntry (AcpiS3Context); + + // + // Initialize Debug Agent to support source level debug in S3 path. + // + InitializeDebugAgent (DEBUG_AGENT_INIT_S3, NULL, NULL); + + // + // Because not install BootScriptExecute PPI(used just in this module), So just pass NULL + // for that parameter. + // + Status = S3BootScriptExecute (); + + AsmWbinvd (); + + // + // We need turn back to S3Resume - install boot script done ppi and report status code on S3resume. + // + if (PeiS3ResumeState != 0) { + // + // Need report status back to S3ResumePeim. + // If boot script execution is failed, S3ResumePeim wil report the error status code. + // + PeiS3ResumeState->ReturnStatus = (UINT64)(UINTN)Status; + // + // IA32 S3 Resume + // + DEBUG ((EFI_D_INFO, "Call SwitchStack() to return to S3 Resume in PEI Phase\n")); + PeiS3ResumeState->AsmTransferControl = (EFI_PHYSICAL_ADDRESS)(UINTN)PlatformTransferControl16; + + SwitchStack ( + (SWITCH_STACK_ENTRY_POINT)(UINTN)PeiS3ResumeState->ReturnEntryPoint, + (VOID *)(UINTN)AcpiS3Context, + (VOID *)(UINTN)PeiS3ResumeState, + (VOID *)(UINTN)PeiS3ResumeState->ReturnStackPointer + ); + + // + // Never run to here + // + CpuDeadLoop(); + return EFI_UNSUPPORTED; + } + + // + // Never run to here + // + CpuDeadLoop(); + return EFI_UNSUPPORTED; +} +/** + Entrypoint of Boot script exector driver, this function will be executed in + normal boot phase and invoked by DXE dispatch. + + @param[in] ImageHandle The firmware allocated handle for the EFI image. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + @retval other Some error occurs when executing this entry point. +**/ +EFI_STATUS +EFIAPI +BootScriptExecutorEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINT8 *Buffer; + UINTN BufferSize; + UINTN Pages; + EFI_PHYSICAL_ADDRESS FfsBuffer; + PE_COFF_LOADER_IMAGE_CONTEXT ImageContext; + BOOT_SCRIPT_EXECUTOR_VARIABLE *EfiBootScriptExecutorVariable; + EFI_PHYSICAL_ADDRESS BootScriptExecutorBuffer; + EFI_STATUS Status; + VOID *DevicePath; + EFI_HANDLE NewImageHandle; + + // + // Test if the gEfiCallerIdGuid of this image is already installed. if not, the entry + // point is loaded by DXE code which is the first time loaded. or else, it is already + // be reloaded be itself.This is a work-around + // + Status = gBS->LocateProtocol (&gEfiCallerIdGuid, NULL, &DevicePath); + if (EFI_ERROR (Status)) { + + // + // This is the first-time loaded by DXE core. reload itself to NVS mem + // + // + // A workarouond: Here we install a dummy handle + // + NewImageHandle = NULL; + Status = gBS->InstallProtocolInterface ( + &NewImageHandle, + &gEfiCallerIdGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + + Status = GetSectionFromAnyFv ( + &gEfiCallerIdGuid, + EFI_SECTION_PE32, + 0, + (VOID **) &Buffer, + &BufferSize + ); + ImageContext.Handle = Buffer; + ImageContext.ImageRead = PeCoffLoaderImageReadFromMemory; + // + // Get information about the image being loaded + // + Status = PeCoffLoaderGetImageInfo (&ImageContext); + if (EFI_ERROR (Status)) { + return Status; + } + Pages = EFI_SIZE_TO_PAGES(BufferSize + ImageContext.SectionAlignment); + FfsBuffer = 0xFFFFFFFF; + Status = gBS->AllocatePages ( + AllocateMaxAddress, + EfiACPIMemoryNVS, + Pages, + &FfsBuffer + ); + if (EFI_ERROR (Status)) { + return EFI_OUT_OF_RESOURCES; + } + ImageContext.ImageAddress = (PHYSICAL_ADDRESS)(UINTN)FfsBuffer; + // + // Align buffer on section boundary + // + ImageContext.ImageAddress += ImageContext.SectionAlignment - 1; + ImageContext.ImageAddress &= ~(ImageContext.SectionAlignment - 1); + // + // Load the image to our new buffer + // + Status = PeCoffLoaderLoadImage (&ImageContext); + if (EFI_ERROR (Status)) { + gBS->FreePages (FfsBuffer, Pages); + return Status; + } + + // + // Relocate the image in our new buffer + // + Status = PeCoffLoaderRelocateImage (&ImageContext); + + if (EFI_ERROR (Status)) { + PeCoffLoaderUnloadImage (&ImageContext); + gBS->FreePages (FfsBuffer, Pages); + return Status; + } + // + // Flush the instruction cache so the image data is written before we execute it + // + InvalidateInstructionCacheRange ((VOID *)(UINTN)ImageContext.ImageAddress, (UINTN)ImageContext.ImageSize); + Status = ((EFI_IMAGE_ENTRY_POINT)(UINTN)(ImageContext.EntryPoint)) (NewImageHandle, SystemTable); + if (EFI_ERROR (Status)) { + gBS->FreePages (FfsBuffer, Pages); + return Status; + } + // + // Additional step for BootScript integrity + // Save BootScriptExecutor image + // + Status = SaveLockBox ( + &mBootScriptExecutorImageGuid, + (VOID *)(UINTN)ImageContext.ImageAddress, + (UINTN)ImageContext.ImageSize + ); + ASSERT_EFI_ERROR (Status); + + Status = SetLockBoxAttributes (&mBootScriptExecutorImageGuid, LOCK_BOX_ATTRIBUTE_RESTORE_IN_PLACE); + ASSERT_EFI_ERROR (Status); + + } else { + // + // the entry point is invoked after reloading. following code only run in ACPI NVS + // + BufferSize = sizeof (BOOT_SCRIPT_EXECUTOR_VARIABLE); + + BootScriptExecutorBuffer = 0xFFFFFFFF; + Pages = EFI_SIZE_TO_PAGES(BufferSize); + Status = gBS->AllocatePages ( + AllocateMaxAddress, + EfiACPIMemoryNVS, + Pages, + &BootScriptExecutorBuffer + ); + if (EFI_ERROR (Status)) { + return EFI_OUT_OF_RESOURCES; + } + + EfiBootScriptExecutorVariable = (BOOT_SCRIPT_EXECUTOR_VARIABLE *)(UINTN)BootScriptExecutorBuffer; + EfiBootScriptExecutorVariable->BootScriptExecutorEntrypoint = (UINTN) S3BootScriptExecutorEntryFunction ; + + Status = SaveLockBox ( + &gEfiBootScriptExecutorVariableGuid, + &BootScriptExecutorBuffer, + sizeof(BootScriptExecutorBuffer) + ); + ASSERT_EFI_ERROR (Status); + + // + // Additional step for BootScript integrity + // Save BootScriptExecutor context + // + Status = SaveLockBox ( + &gEfiBootScriptExecutorContextGuid, + EfiBootScriptExecutorVariable, + sizeof(*EfiBootScriptExecutorVariable) + ); + ASSERT_EFI_ERROR (Status); + + Status = SetLockBoxAttributes (&gEfiBootScriptExecutorContextGuid, LOCK_BOX_ATTRIBUTE_RESTORE_IN_PLACE); + ASSERT_EFI_ERROR (Status); + + } + + return EFI_SUCCESS; +} + +/** + Platform specific mechanism to transfer control to 16bit OS waking vector + + @param[in] AcpiWakingVector The 16bit OS waking vector + @param[in] AcpiLowMemoryBase A buffer under 1M which could be used during the transfer + +**/ +VOID +PlatformTransferControl16 ( + IN UINT32 AcpiWakingVector, + IN UINT32 AcpiLowMemoryBase + ) +{ + UINT32 NewValue; + UINT64 BaseAddress; + UINT64 SmramLength; + UINTN Index; + + DEBUG (( EFI_D_INFO, "PlatformTransferControl - Entry\r\n")); + + // + // Need to make sure the GDT is loaded with values that support long mode and real mode. + // + AsmWriteGdtr (&mGdt); + + // + // Disable eSram block (this will also clear/zero eSRAM) + // We only use eSRAM in the PEI phase. Disable now that we are resuming the OS + // + NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK); + NewValue |= BLOCK_DISABLE_PG; + QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK, NewValue); + + // + // Update HMBOUND to top of DDR3 memory and LOCK + // We disabled eSRAM so now we move HMBOUND down to top of DDR3 + // + QNCGetTSEGMemoryRange (&BaseAddress, &SmramLength); + NewValue = (UINT32)(BaseAddress + SmramLength); + DEBUG ((EFI_D_INFO,"Locking HMBOUND at: = 0x%8x\n",NewValue)); + QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_HMBOUND_REG, (NewValue | HMBOUND_LOCK)); + + // + // Lock all IMR regions now that HMBOUND is locked + // + for (Index = (QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXL); Index <= (QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXL); Index += 4) { + NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, Index); + NewValue |= IMR_LOCK; + QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, Index, NewValue); + } + + // + // Call ASM routine to switch to real mode and jump to 16bit OS waking vector + // + AsmTransferControl(AcpiWakingVector, 0); + + // + // Never run to here + // + CpuDeadLoop(); +} + + + + diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/ScriptExecute.h b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/ScriptExecute.h new file mode 100644 index 0000000000..f2d83b2687 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/ScriptExecute.h @@ -0,0 +1,70 @@ +/** @file +The header file for Boot Script Executer module. + +This driver is dispatched by Dxe core and the driver will reload itself to ACPI NVS memory +in the entry point. The functionality is to interpret and restore the S3 boot script + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _SCRIPT_EXECUTE_H_ +#define _SCRIPT_EXECUTE_H_ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/** + a ASM function to transfer control to OS. + + @param S3WakingVector The S3 waking up vector saved in ACPI Facs table + @param AcpiLowMemoryBase a buffer under 1M which could be used during the transfer +**/ +VOID +AsmTransferControl ( + IN UINT32 S3WakingVector, + IN UINT32 AcpiLowMemoryBase + ); + +VOID +SetIdtEntry ( + IN ACPI_S3_CONTEXT *AcpiS3Context + ); + +/** + Platform specific mechanism to transfer control to 16bit OS waking vector + + @param[in] AcpiWakingVector The 16bit OS waking vector + @param[in] AcpiLowMemoryBase A buffer under 1M which could be used during the transfer + +**/ +VOID +PlatformTransferControl16 ( + IN UINT32 AcpiWakingVector, + IN UINT32 AcpiLowMemoryBase + ); + +#endif //_SCRIPT_EXECUTE_H_ diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.c b/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.c new file mode 100644 index 0000000000..f7f7ca3196 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.c @@ -0,0 +1,1011 @@ +/** @file +ACPISMM Driver implementation file. + +This is QNC Smm platform driver + +Copyright (c) 2013-2016 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#include + +#define PCILIB_TO_COMMON_ADDRESS(Address) \ + ((UINT64) ((((UINTN) ((Address>>20) & 0xff)) << 24) + (((UINTN) ((Address>>15) & 0x1f)) << 16) + (((UINTN) ((Address>>12) & 0x07)) << 8) + ((UINTN) (Address & 0xfff )))) + +// +// Modular variables needed by this driver +// +EFI_ACPI_SMM_DEV mAcpiSmm; + +UINT8 mPciCfgRegTable[] = { + // + // Logic to decode the table masks to arrive at the registers saved + // Dword Registers are saved. For a given mask, the Base+offset register + // will be saved as in the table below. + // (example) To save register 0x24, 0x28 the mask at the Base 0x20 will be 0x06 + // Base 0x00 0x20 0x40 0x60 0x80 0xA0 0xC0 0xE0 + // Mask offset + // 0x01 0x00 + // 0x02 0x04 + // 0x04 0x08 + // 0x08 0x0C + // 0x10 0x10 + // 0x20 0x14 + // 0x40 0x18 + // 0x80 0x1C + // + + // + // Bus, Dev, Func, + // 00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF + // Only Bus 0 device is supported now + // + + // + // Quark South Cluster devices + // + PCI_DEVICE (0, 20, 0), + PCI_REG_MASK (0x18, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + + PCI_DEVICE (0, 20, 1), + PCI_REG_MASK (0x38, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + + PCI_DEVICE (0, 20, 2), + PCI_REG_MASK (0x18, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + + PCI_DEVICE (0, 20, 3), + PCI_REG_MASK (0x18, 0x98, 0x00, 0x01, 0x00, 0x00, 0x03, 0x00), + + PCI_DEVICE (0, 20, 4), + PCI_REG_MASK (0x18, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + + PCI_DEVICE (0, 20, 5), + PCI_REG_MASK (0x38, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + + PCI_DEVICE (0, 20, 6), + PCI_REG_MASK (0x18, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + + PCI_DEVICE (0, 20, 7), + PCI_REG_MASK (0x18, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + + PCI_DEVICE (0, 21, 0), + PCI_REG_MASK (0x18, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + + PCI_DEVICE (0, 21, 1), + PCI_REG_MASK (0x18, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + + PCI_DEVICE (0, 21, 2), + PCI_REG_MASK (0x38, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + + // + // Quark North Cluster devices + // + PCI_DEVICE (0, 0, 0), + PCI_REG_MASK (0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + + PCI_DEVICE (0, 23, 0), + PCI_REG_MASK (0xC0, 0x8F, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00), + + PCI_DEVICE (0, 23, 1), + PCI_REG_MASK (0xC0, 0x8F, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00), + + PCI_DEVICE (0, 31, 0), + PCI_REG_MASK (0x00, 0x08, 0x4E, 0x03, 0x02, 0x00, 0x60, 0x10), + + PCI_DEVICE_END +}; + +EFI_PLATFORM_TYPE mPlatformType; + + // These registers have to set in byte order +const UINT8 QNCS3SaveExtReg[] = { + QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HSMMC, // SMRAM settings + + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXL, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXH, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXRM, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXWM, + + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR1+QUARK_NC_MEMORY_MANAGER_IMRXL, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR1+QUARK_NC_MEMORY_MANAGER_IMRXH, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR1+QUARK_NC_MEMORY_MANAGER_IMRXRM, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR1+QUARK_NC_MEMORY_MANAGER_IMRXWM, + + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR2+QUARK_NC_MEMORY_MANAGER_IMRXL, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR2+QUARK_NC_MEMORY_MANAGER_IMRXH, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR2+QUARK_NC_MEMORY_MANAGER_IMRXRM, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR2+QUARK_NC_MEMORY_MANAGER_IMRXWM, + + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR3+QUARK_NC_MEMORY_MANAGER_IMRXL, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR3+QUARK_NC_MEMORY_MANAGER_IMRXH, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR3+QUARK_NC_MEMORY_MANAGER_IMRXRM, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR3+QUARK_NC_MEMORY_MANAGER_IMRXWM, + + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR4+QUARK_NC_MEMORY_MANAGER_IMRXL, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR4+QUARK_NC_MEMORY_MANAGER_IMRXH, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR4+QUARK_NC_MEMORY_MANAGER_IMRXRM, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR4+QUARK_NC_MEMORY_MANAGER_IMRXWM, + + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR5+QUARK_NC_MEMORY_MANAGER_IMRXL, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR5+QUARK_NC_MEMORY_MANAGER_IMRXH, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR5+QUARK_NC_MEMORY_MANAGER_IMRXRM, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR5+QUARK_NC_MEMORY_MANAGER_IMRXWM, + + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR6+QUARK_NC_MEMORY_MANAGER_IMRXL, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR6+QUARK_NC_MEMORY_MANAGER_IMRXH, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR6+QUARK_NC_MEMORY_MANAGER_IMRXRM, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR6+QUARK_NC_MEMORY_MANAGER_IMRXWM, + + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXL, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXH, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXRM, + QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXWM, + + QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_END_MEM_REG, // ECC Scrub settings + QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_START_MEM_REG, + QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_NEXT_READ_REG, + QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_CONFIG_REG, + + 0xFF + }; + +/** + Allocate EfiACPIMemoryNVS below 4G memory address. + + This function allocates EfiACPIMemoryNVS below 4G memory address. + + @param Size Size of memory to allocate. + + @return Allocated address for output. + +**/ +VOID* +AllocateAcpiNvsMemoryBelow4G ( + IN UINTN Size + ) +{ + UINTN Pages; + EFI_PHYSICAL_ADDRESS Address; + EFI_STATUS Status; + VOID* Buffer; + + Pages = EFI_SIZE_TO_PAGES (Size); + Address = 0xffffffff; + + Status = gBS->AllocatePages ( + AllocateMaxAddress, + EfiACPIMemoryNVS, + Pages, + &Address + ); + if (EFI_ERROR (Status)) { + return NULL; + } + + Buffer = (VOID *) (UINTN) Address; + ZeroMem (Buffer, Size); + + return Buffer; +} + +EFI_STATUS +EFIAPI +ReservedS3Memory ( + UINTN SystemMemoryLength + + ) +/*++ + +Routine Description: + + Reserved S3 memory for InstallS3Memory + +Arguments: + + +Returns: + + EFI_OUT_OF_RESOURCES - Insufficient resources to complete function. + EFI_SUCCESS - Function has completed successfully. + +--*/ +{ + + VOID *GuidHob; + EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *DescriptorBlock; + VOID *AcpiReservedBase; + + UINTN TsegIndex; + UINTN TsegSize; + UINTN TsegBase; + RESERVED_ACPI_S3_RANGE *AcpiS3Range; + // + // Get Hob list for SMRAM desc + // + GuidHob = GetFirstGuidHob (&gEfiSmmPeiSmramMemoryReserveGuid); + ASSERT (GuidHob); + DescriptorBlock = GET_GUID_HOB_DATA (GuidHob); + ASSERT (DescriptorBlock); + + // + // Use the hob to get SMRAM capabilities + // + TsegIndex = DescriptorBlock->NumberOfSmmReservedRegions - 1; + ASSERT (TsegIndex <= (MAX_SMRAM_RANGES - 1)); + TsegBase = (UINTN)DescriptorBlock->Descriptor[TsegIndex].PhysicalStart; + TsegSize = (UINTN)DescriptorBlock->Descriptor[TsegIndex].PhysicalSize; + + DEBUG ((EFI_D_INFO, "SMM Base: %08X\n", TsegBase)); + DEBUG ((EFI_D_INFO, "SMM Size: %08X\n", TsegSize)); + + // + // Now find the location of the data structure that is used to store the address + // of the S3 reserved memory. + // + AcpiS3Range = (RESERVED_ACPI_S3_RANGE*) (UINTN) (TsegBase + RESERVED_ACPI_S3_RANGE_OFFSET); + + // + // Allocate reserved ACPI memory for S3 resume. Pointer to this region is + // stored in SMRAM in the first page of TSEG. + // + AcpiReservedBase = AllocateAcpiNvsMemoryBelow4G (PcdGet32 (PcdS3AcpiReservedMemorySize)); + if (AcpiReservedBase != NULL) { + AcpiS3Range->AcpiReservedMemoryBase = (UINT32)(UINTN) AcpiReservedBase; + AcpiS3Range->AcpiReservedMemorySize = PcdGet32 (PcdS3AcpiReservedMemorySize); + } + AcpiS3Range->SystemMemoryLength = (UINT32)SystemMemoryLength; + + DEBUG ((EFI_D_INFO, "S3 Memory Base: %08X\n", AcpiS3Range->AcpiReservedMemoryBase)); + DEBUG ((EFI_D_INFO, "S3 Memory Size: %08X\n", AcpiS3Range->AcpiReservedMemorySize)); + DEBUG ((EFI_D_INFO, "S3 SysMemoryLength: %08X\n", AcpiS3Range->SystemMemoryLength)); + + return EFI_SUCCESS; +} + + +EFI_STATUS +EFIAPI +InitAcpiSmmPlatform ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +/*++ + +Routine Description: + + Initializes the SMM S3 Handler Driver. + +Arguments: + + ImageHandle - The image handle of Sleep State Wake driver. + SystemTable - The starndard EFI system table. + +Returns: + + EFI_OUT_OF_RESOURCES - Insufficient resources to complete function. + EFI_SUCCESS - Function has completed successfully. + Other - Error occured during execution. + +--*/ +{ + EFI_STATUS Status; + EFI_GLOBAL_NVS_AREA_PROTOCOL *AcpiNvsProtocol = NULL; + UINTN MemoryLength; + EFI_PEI_HOB_POINTERS Hob; + + Status = gBS->LocateProtocol ( + &gEfiGlobalNvsAreaProtocolGuid, + NULL, + (VOID **) &AcpiNvsProtocol + ); + ASSERT_EFI_ERROR (Status); + + mAcpiSmm.BootScriptSaved = 0; + + mPlatformType = (EFI_PLATFORM_TYPE)PcdGet16 (PcdPlatformType); + + // + // Calculate the system memory length by memory hobs + // + MemoryLength = 0x100000; + Hob.Raw = GetFirstHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR); + ASSERT (Hob.Raw != NULL); + while ((Hob.Raw != NULL) && (!END_OF_HOB_LIST (Hob))) { + if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) { + // + // Skip the memory region below 1MB + // + if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) { + MemoryLength += (UINTN)Hob.ResourceDescriptor->ResourceLength; + } + } + Hob.Raw = GET_NEXT_HOB (Hob); + Hob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, Hob.Raw); + } + + ReservedS3Memory(MemoryLength); + + // + // Locate and Register to Parent driver + // + Status = RegisterToDispatchDriver (); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +EFI_STATUS +RegisterToDispatchDriver ( + VOID + ) +/*++ + +Routine Description: + + Register to dispatch driver. + +Arguments: + + None. + +Returns: + + EFI_SUCCESS - Successfully init the device. + Other - Error occured whening calling Dxe lib functions. + +--*/ +{ + UINTN Length; + EFI_STATUS Status; + EFI_SMM_SX_DISPATCH2_PROTOCOL *SxDispatch; + EFI_SMM_SW_DISPATCH2_PROTOCOL *SwDispatch; + EFI_SMM_SX_REGISTER_CONTEXT *EntryDispatchContext; + EFI_SMM_SX_REGISTER_CONTEXT *EntryS1DispatchContext; + EFI_SMM_SX_REGISTER_CONTEXT *EntryS3DispatchContext; + EFI_SMM_SX_REGISTER_CONTEXT *EntryS4DispatchContext; + EFI_SMM_SX_REGISTER_CONTEXT *EntryS5DispatchContext; + EFI_SMM_SW_REGISTER_CONTEXT *SwContext; + EFI_SMM_SW_REGISTER_CONTEXT *AcpiDisableSwContext; + EFI_SMM_SW_REGISTER_CONTEXT *AcpiEnableSwContext; + + Status = gSmst->SmmLocateProtocol ( + &gEfiSmmSxDispatch2ProtocolGuid, + NULL, + (VOID **) &SxDispatch + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = gSmst->SmmLocateProtocol ( + &gEfiSmmSwDispatch2ProtocolGuid, + NULL, + (VOID **) &SwDispatch + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Length = sizeof (EFI_SMM_SX_REGISTER_CONTEXT) * 4 + sizeof (EFI_SMM_SW_REGISTER_CONTEXT) * 2; + Status = gSmst->SmmAllocatePool ( + EfiRuntimeServicesData, + Length, + (VOID **) &EntryDispatchContext + ); + if (EFI_ERROR (Status)) { + return Status; + } + + SetMem (EntryDispatchContext, Length, 0); + + EntryS1DispatchContext = EntryDispatchContext++; + EntryS3DispatchContext = EntryDispatchContext++; + EntryS4DispatchContext = EntryDispatchContext++; + EntryS5DispatchContext = EntryDispatchContext++; + + SwContext = (EFI_SMM_SW_REGISTER_CONTEXT *)EntryDispatchContext; + AcpiDisableSwContext = SwContext++; + AcpiEnableSwContext = SwContext++; + + // + // Register the enable handler + // + AcpiEnableSwContext->SwSmiInputValue = EFI_ACPI_ACPI_ENABLE; + Status = SwDispatch->Register ( + SwDispatch, + EnableAcpiCallback, + AcpiEnableSwContext, + &(mAcpiSmm.DisableAcpiHandle) + ); + + // + // Register the disable handler + // + AcpiDisableSwContext->SwSmiInputValue = EFI_ACPI_ACPI_DISABLE; + Status = SwDispatch->Register ( + SwDispatch, + DisableAcpiCallback, + AcpiDisableSwContext, + &(mAcpiSmm.EnableAcpiHandle) + ); + + + // + // Register entry phase call back function for S1 + // + EntryS1DispatchContext->Type = SxS1; + EntryS1DispatchContext->Phase = SxEntry; + Status = SxDispatch->Register ( + SxDispatch, + SxSleepEntryCallBack, + EntryS1DispatchContext, + &(mAcpiSmm.S1SleepEntryHandle) + ); + + // + // Register entry phase call back function + // + EntryS3DispatchContext->Type = SxS3; + EntryS3DispatchContext->Phase = SxEntry; + Status = SxDispatch->Register ( + SxDispatch, + SxSleepEntryCallBack, + EntryS3DispatchContext, + &(mAcpiSmm.S3SleepEntryHandle) + ); + + // + // Register entry phase call back function for S4 + // + EntryS4DispatchContext->Type = SxS4; + EntryS4DispatchContext->Phase = SxEntry; + Status = SxDispatch->Register ( + SxDispatch, + SxSleepEntryCallBack, + EntryS4DispatchContext, + &(mAcpiSmm.S4SleepEntryHandle) + ); + + // + // Register callback for S5 in order to workaround the LAN shutdown issue + // + EntryS5DispatchContext->Type = SxS5; + EntryS5DispatchContext->Phase = SxEntry; + Status = SxDispatch->Register ( + SxDispatch, + SxSleepEntryCallBack, + EntryS5DispatchContext, + &(mAcpiSmm.S5SoftOffEntryHandle) + ); + + return Status; +} + + +EFI_STATUS +RestoreQncS3SwCallback ( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *DispatchContext, + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommBufferSize + ) +/*++ + +Routine Description: + SMI handler to restore QncS3 code & context for S3 path + This will be only triggered when BootScript got executed during resume + +Arguments: + DispatchHandle - EFI Handle + DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT + +Returns: + Nothing + +--*/ +{ + // + // Restore to original address by default + // + RestoreLockBox(&gQncS3CodeInLockBoxGuid, NULL, NULL); + RestoreLockBox(&gQncS3ContextInLockBoxGuid, NULL, NULL); + return EFI_SUCCESS; +} + +EFI_STATUS +DisableAcpiCallback ( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *DispatchContext, + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommBufferSize + ) +/*++ + +Routine Description: + SMI handler to disable ACPI mode + + Dispatched on reads from APM port with value 0xA1 + + ACPI events are disabled and ACPI event status is cleared. + SCI mode is then disabled. + Clear all ACPI event status and disable all ACPI events + Disable PM sources except power button + Clear status bits + Disable GPE0 sources + Clear status bits + Disable GPE1 sources + Clear status bits + Disable SCI + +Arguments: + DispatchHandle - EFI Handle + DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT + +Returns: + Nothing + +--*/ +{ + EFI_STATUS Status; + UINT16 Pm1Cnt; + + Status = GetAllQncPmBase (gSmst); + ASSERT_EFI_ERROR (Status); + Pm1Cnt = IoRead16 (mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1C); + + // + // Disable SCI + // + Pm1Cnt &= ~B_QNC_PM1BLK_PM1C_SCIEN; + + IoWrite16 (mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1C, Pm1Cnt); + + return EFI_SUCCESS; +} + +EFI_STATUS +EnableAcpiCallback ( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *DispatchContext, + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommBufferSize + ) +/*++ + +Routine Description: + SMI handler to enable ACPI mode + + Dispatched on reads from APM port with value 0xA0 + + Disables the SW SMI Timer. + ACPI events are disabled and ACPI event status is cleared. + SCI mode is then enabled. + + Disable SW SMI Timer + + Clear all ACPI event status and disable all ACPI events + Disable PM sources except power button + Clear status bits + + Disable GPE0 sources + Clear status bits + + Disable GPE1 sources + Clear status bits + + Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) + + Enable SCI + +Arguments: + DispatchHandle - EFI Handle + DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT + +Returns: + Nothing + +--*/ +{ + EFI_STATUS Status; + UINT32 SmiEn; + UINT16 Pm1Cnt; + UINT8 Data8; + + Status = GetAllQncPmBase (gSmst); + ASSERT_EFI_ERROR (Status); + + SmiEn = IoRead32 (mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_SMIE); + + // + // Disable SW SMI Timer + // + SmiEn &= ~(B_QNC_GPE0BLK_SMIE_SWT); + IoWrite32 (mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_SMIE, SmiEn); + + // + // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) + // + Data8 = RTC_ADDRESS_REGISTER_D; + IoWrite8 (R_IOPORT_CMOS_STANDARD_INDEX, Data8); + Data8 = 0x0; + IoWrite8 (R_IOPORT_CMOS_STANDARD_DATA, Data8); + + // + // Enable SCI + // + Pm1Cnt = IoRead16 (mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1C); + Pm1Cnt |= B_QNC_PM1BLK_PM1C_SCIEN; + IoWrite16 (mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1C, Pm1Cnt); + + // + // Do platform specific stuff for ACPI enable SMI + // + + + return EFI_SUCCESS; +} + +EFI_STATUS +SxSleepEntryCallBack ( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *DispatchContext, + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommBufferSize + ) +/*++ + +Routine Description: + + Callback function entry for Sx sleep state. + +Arguments: + + DispatchHandle - The handle of this callback, obtained when registering. + DispatchContext - The predefined context which contained sleep type and phase. + +Returns: + + EFI_SUCCESS - Operation successfully performed. + EFI_INVALID_PARAMETER - Invalid parameter passed in. + +--*/ +{ + EFI_STATUS Status; + UINT8 Data8; + UINT16 Data16; + UINT32 Data32; + + REPORT_STATUS_CODE (EFI_PROGRESS_CODE, PcdGet32 (PcdProgressCodeS3SuspendStart)); + + // + // Reget QNC power mgmr regs base in case of OS changing it at runtime + // + Status = GetAllQncPmBase (gSmst); + + // + // Clear RTC Alarm (if set) + // + Data8 = RTC_ADDRESS_REGISTER_C; + IoWrite8 (R_IOPORT_CMOS_STANDARD_INDEX, Data8); + Data8 = IoRead8 (R_IOPORT_CMOS_STANDARD_DATA); + + // + // Clear all ACPI status bits + // + Data32 = B_QNC_GPE0BLK_GPE0S_ALL; + Status = gSmst->SmmIo.Io.Write( &gSmst->SmmIo, SMM_IO_UINT32, mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_GPE0S, 1, &Data32 ); + Data16 = B_QNC_PM1BLK_PM1S_ALL; + Status = gSmst->SmmIo.Io.Write( &gSmst->SmmIo, SMM_IO_UINT16, mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1S, 1, &Data16 ); + + // + // Handling S1 - setting appropriate wake bits in GPE0_EN + // + if ((DispatchHandle == mAcpiSmm.S1SleepEntryHandle) && (((EFI_SMM_SX_REGISTER_CONTEXT *)DispatchContext)->Type == SxS1)) { + // + // Enable bit13 (EGPE), 14 (GPIO) ,17 (PCIE) in GPE0_EN + // + Status = gSmst->SmmIo.Io.Read( &gSmst->SmmIo, SMM_IO_UINT32, mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_GPE0E, 1, &Data32 ); + Data32 |= (B_QNC_GPE0BLK_GPE0E_EGPE | B_QNC_GPE0BLK_GPE0E_GPIO | B_QNC_GPE0BLK_GPE0E_PCIE); + Status = gSmst->SmmIo.Io.Write( &gSmst->SmmIo, SMM_IO_UINT32, mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_GPE0E, 1, &Data32 ); + + // + // Enable bit10 (RTC) in PM1E + // + Status = gSmst->SmmIo.Io.Read( &gSmst->SmmIo, SMM_IO_UINT16, mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1E, 1, &Data16 ); + Data16 |= B_QNC_PM1BLK_PM1E_RTC; + Status = gSmst->SmmIo.Io.Write( &gSmst->SmmIo, SMM_IO_UINT16, mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1E, 1, &Data16 ); + + return EFI_SUCCESS; + } + + // + // Handling S4, S5 and WOL - setting appropriate wake bits in GPE0_EN + // + if (((DispatchHandle == mAcpiSmm.S4SleepEntryHandle) && (((EFI_SMM_SX_REGISTER_CONTEXT *)DispatchContext)->Type == SxS4)) || + ((DispatchHandle == mAcpiSmm.S5SoftOffEntryHandle) && (((EFI_SMM_SX_REGISTER_CONTEXT *)DispatchContext)->Type == SxS5)) + ) { + // + // Enable bit13 (EGPE), 14 (GPIO) ,17 (PCIE) in GPE0_EN + // Enable the WOL bits in GPE0_EN reg here for PME + // + Status = gSmst->SmmIo.Io.Read( &gSmst->SmmIo, SMM_IO_UINT32, mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_GPE0E, 1, &Data32 ); + Data32 |= (B_QNC_GPE0BLK_GPE0E_EGPE | B_QNC_GPE0BLK_GPE0E_GPIO | B_QNC_GPE0BLK_GPE0E_PCIE); + Status = gSmst->SmmIo.Io.Write( &gSmst->SmmIo, SMM_IO_UINT32, mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_GPE0E, 1, &Data32 ); + + // + // Enable bit10 (RTC) in PM1E + // + Status = gSmst->SmmIo.Io.Read( &gSmst->SmmIo, SMM_IO_UINT16, mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1E, 1, &Data16 ); + Data16 |= B_QNC_PM1BLK_PM1E_RTC; + Status = gSmst->SmmIo.Io.Write( &gSmst->SmmIo, SMM_IO_UINT16, mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1E, 1, &Data16 ); + + } else { + + if ((DispatchHandle != mAcpiSmm.S3SleepEntryHandle) || (((EFI_SMM_SX_REGISTER_CONTEXT *)DispatchContext)->Type != SxS3)) { + return EFI_INVALID_PARAMETER; + } + + Status = SaveRuntimeScriptTable (gSmst); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Enable bit13 (EGPE), 14 (GPIO), 17 (PCIE) in GPE0_EN + // Enable the WOL bits in GPE0_EN reg here for PME + // + Status = gSmst->SmmIo.Io.Read( &gSmst->SmmIo, SMM_IO_UINT32, mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_GPE0E, 1, &Data32 ); + Data32 |= (B_QNC_GPE0BLK_GPE0E_EGPE | B_QNC_GPE0BLK_GPE0E_GPIO | B_QNC_GPE0BLK_GPE0E_PCIE); + Status = gSmst->SmmIo.Io.Write( &gSmst->SmmIo, SMM_IO_UINT32, mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_GPE0E, 1, &Data32 ); + + // + // Enable bit10 (RTC) in PM1E + // + Status = gSmst->SmmIo.Io.Read( &gSmst->SmmIo, SMM_IO_UINT16, mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1E, 1, &Data16 ); + Data16 |= B_QNC_PM1BLK_PM1E_RTC; + Status = gSmst->SmmIo.Io.Write( &gSmst->SmmIo, SMM_IO_UINT16, mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1E, 1, &Data16 ); + } + + // + // When entering a power-managed state like S3, + // PERST# must be asserted in advance of power-off. + // + PlatformPERSTAssert (mPlatformType); + + return EFI_SUCCESS; +} + +EFI_STATUS +GetAllQncPmBase ( + IN EFI_SMM_SYSTEM_TABLE2 *Smst + ) +/*++ + +Routine Description: + + Get QNC chipset LPC Power Management I/O Base at runtime. + +Arguments: + + Smst - The standard SMM system table. + +Returns: + + EFI_SUCCESS - Successfully init the device. + Other - Error occured whening calling Dxe lib functions. + +--*/ +{ + mAcpiSmm.QncPmBase = PciRead16 (PCI_LIB_ADDRESS(PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, R_QNC_LPC_PM1BLK)) & B_QNC_LPC_PM1BLK_MASK; + mAcpiSmm.QncGpe0Base = PciRead16 (PCI_LIB_ADDRESS(PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, R_QNC_LPC_GPE0BLK)) & B_QNC_LPC_GPE0BLK_MASK; + + // + // Quark does not support Changing Primary SoC IOBARs from what was + // setup in SEC/PEI UEFI stages. + // + ASSERT (mAcpiSmm.QncPmBase == (UINT32) PcdGet16 (PcdPm1blkIoBaseAddress)); + ASSERT (mAcpiSmm.QncGpe0Base == (UINT32) PcdGet16 (PcdGpe0blkIoBaseAddress)); + return EFI_SUCCESS; +} + +EFI_STATUS +SaveRuntimeScriptTable ( + IN EFI_SMM_SYSTEM_TABLE2 *Smst + ) +{ + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress; + UINT32 Data32; + UINT16 Data16; + UINT8 Mask; + UINTN Index; + UINTN Offset; + UINT16 DeviceId; + + // + // Check what Soc we are running on (read Host bridge DeviceId) + // + DeviceId = QncGetSocDeviceId(); + + // + // Save PCI-Host bridge settings (0, 0, 0). 0x90, 94 and 9c are changed by CSM + // and vital to S3 resume. That's why we put save code here + // + Index = 0; + while (mPciCfgRegTable[Index] != PCI_DEVICE_END) { + + PciAddress.Bus = mPciCfgRegTable[Index++]; + PciAddress.Device = mPciCfgRegTable[Index++]; + PciAddress.Function = mPciCfgRegTable[Index++]; + PciAddress.Register = 0; + PciAddress.ExtendedRegister = 0; + + Data16 = PciRead16 (PCI_LIB_ADDRESS(PciAddress.Bus, PciAddress.Device, PciAddress.Function, PciAddress.Register)); + if (Data16 == 0xFFFF) { + Index += 8; + continue; + } + + for (Offset = 0, Mask = 0x01; Offset < 256; Offset += 4, Mask <<= 1) { + + if (Mask == 0x00) { + Mask = 0x01; + } + + if (mPciCfgRegTable[Index + Offset / 32] & Mask) { + + PciAddress.Register = (UINT8) Offset; + Data32 = PciRead32 (PCI_LIB_ADDRESS(PciAddress.Bus, PciAddress.Device, PciAddress.Function, PciAddress.Register)); + + + // + // Save latest settings to runtime script table + // + S3BootScriptSavePciCfgWrite ( + S3BootScriptWidthUint32, + PCILIB_TO_COMMON_ADDRESS (PCI_LIB_ADDRESS(PciAddress.Bus, PciAddress.Device, PciAddress.Function, PciAddress.Register)), + 1, + &Data32 + ); + } + } + + Index += 8; + + } + + // + // Save message bus registers + // + Index = 0; + while (QNCS3SaveExtReg[Index] != 0xFF) { + Data32 = QNCPortRead (QNCS3SaveExtReg[Index], QNCS3SaveExtReg[Index + 1]); + + // + // Save IMR settings with IMR protection disabled initially + // HMBOUND and IMRs will be locked just before jumping to the OS waking vector + // + if (QNCS3SaveExtReg[Index] == QUARK_NC_MEMORY_MANAGER_SB_PORT_ID) { + if ((QNCS3SaveExtReg[Index + 1] >= (QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXL)) && (QNCS3SaveExtReg[Index + 1] <= (QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXWM)) && ((QNCS3SaveExtReg[Index + 1] & 0x03) == QUARK_NC_MEMORY_MANAGER_IMRXL)) { + Data32 &= ~IMR_LOCK; + if (DeviceId == QUARK2_MC_DEVICE_ID) { + Data32 &= ~IMR_EN; + } + } + if ((QNCS3SaveExtReg[Index + 1] >= (QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXRM)) && (QNCS3SaveExtReg[Index + 1] <= (QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXWM)) && ((QNCS3SaveExtReg[Index + 1] & 0x03) >= QUARK_NC_MEMORY_MANAGER_IMRXRM)) { + Data32 = (UINT32)IMRX_ALL_ACCESS; + } + } + + // + // Save latest settings to runtime script table + // + S3BootScriptSavePciCfgWrite ( + S3BootScriptWidthUint32, + PCILIB_TO_COMMON_ADDRESS (PCI_LIB_ADDRESS(0, 0, 0, QNC_ACCESS_PORT_MDR)), + 1, + &Data32 + ); + + Data32 = MESSAGE_WRITE_DW (QNCS3SaveExtReg[Index], QNCS3SaveExtReg[Index + 1]); + + S3BootScriptSavePciCfgWrite ( + S3BootScriptWidthUint32, + PCILIB_TO_COMMON_ADDRESS (PCI_LIB_ADDRESS(0, 0, 0, QNC_ACCESS_PORT_MCR)), + 1, + &Data32 + ); + Index += 2; + } + + Index = 0; + while (QNCS3SaveExtReg[Index] != 0xFF) { + // + // Save IMR settings with IMR protection enabled (above script was to handle restoring all settings first - now we want to enable) + // + if (QNCS3SaveExtReg[Index] == QUARK_NC_MEMORY_MANAGER_SB_PORT_ID) { + if (DeviceId == QUARK2_MC_DEVICE_ID) { + if ((QNCS3SaveExtReg[Index + 1] >= (QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXL)) && (QNCS3SaveExtReg[Index + 1] <= (QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXWM)) && ((QNCS3SaveExtReg[Index + 1] & 0x03) == QUARK_NC_MEMORY_MANAGER_IMRXL)) { + Data32 = QNCPortRead (QNCS3SaveExtReg[Index], QNCS3SaveExtReg[Index + 1]); + Data32 &= ~IMR_LOCK; + + // + // Save latest settings to runtime script table + // + S3BootScriptSavePciCfgWrite ( + S3BootScriptWidthUint32, + PCILIB_TO_COMMON_ADDRESS (PCI_LIB_ADDRESS(0, 0, 0, QNC_ACCESS_PORT_MDR)), + 1, + &Data32 + ); + + Data32 = MESSAGE_WRITE_DW (QNCS3SaveExtReg[Index], QNCS3SaveExtReg[Index + 1]); + + S3BootScriptSavePciCfgWrite ( + S3BootScriptWidthUint32, + PCILIB_TO_COMMON_ADDRESS (PCI_LIB_ADDRESS(0, 0, 0, QNC_ACCESS_PORT_MCR)), + 1, + &Data32 + ); + } + } else { + if ((QNCS3SaveExtReg[Index + 1] >= (QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXRM)) && (QNCS3SaveExtReg[Index + 1] <= (QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXWM)) && ((QNCS3SaveExtReg[Index + 1] & 0x03) >= QUARK_NC_MEMORY_MANAGER_IMRXRM)) { + Data32 = QNCPortRead (QNCS3SaveExtReg[Index], QNCS3SaveExtReg[Index + 1]); + + // + // Save latest settings to runtime script table + // + S3BootScriptSavePciCfgWrite ( + S3BootScriptWidthUint32, + PCILIB_TO_COMMON_ADDRESS (PCI_LIB_ADDRESS(0, 0, 0, QNC_ACCESS_PORT_MDR)), + 1, + &Data32 + ); + + Data32 = MESSAGE_WRITE_DW (QNCS3SaveExtReg[Index], QNCS3SaveExtReg[Index + 1]); + + S3BootScriptSavePciCfgWrite ( + S3BootScriptWidthUint32, + PCILIB_TO_COMMON_ADDRESS (PCI_LIB_ADDRESS(0, 0, 0, QNC_ACCESS_PORT_MCR)), + 1, + &Data32 + ); + } + } + } + Index += 2; + } + + // Check if ECC scrub enabled and need re-enabling on resume + // All scrub related configuration registers are saved on suspend + // as part of QNCS3SaveExtReg configuration table script. + // The code below extends the S3 resume script with scrub reactivation + // message (if needed only) + Data32 = QNCPortRead (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_CONFIG_REG); + if( 0 != (Data32 & SCRUB_CFG_ACTIVE)) { + + Data32 = SCRUB_RESUME_MSG(); + + S3BootScriptSavePciCfgWrite ( + S3BootScriptWidthUint32, + PCILIB_TO_COMMON_ADDRESS (PCI_LIB_ADDRESS(0, 0, 0, QNC_ACCESS_PORT_MCR)), + 1, + &Data32 + ); + } + + // + // Save I/O ports to S3 script table + // + + // + // Important to trap Sx for SMM + // + Data32 = IoRead32 (mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_SMIE); + S3BootScriptSaveIoWrite(S3BootScriptWidthUint32, (mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_SMIE), 1, &Data32); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.h b/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.h new file mode 100644 index 0000000000..1a218cd143 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.h @@ -0,0 +1,167 @@ +/** @file +Header file for SMM S3 Handler Driver. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#ifndef _ACPI_SMM_DRIVER_H +#define _ACPI_SMM_DRIVER_H +// +// Include files +// +// +// Driver Consumed Protocol Prototypes +// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "Platform.h" +#include + +#define EFI_ACPI_ACPI_ENABLE 0xA0 +#define EFI_ACPI_ACPI_DISABLE 0xA1 + +#define R_IOPORT_CMOS_STANDARD_INDEX 0x70 +#define R_IOPORT_CMOS_STANDARD_DATA 0x71 +#define RTC_ADDRESS_REGISTER_C 12 +#define RTC_ADDRESS_REGISTER_D 13 + +#define PCI_DEVICE(Bus, Dev, Func) \ + Bus, Dev, Func + +#define PCI_REG_MASK(Byte0, Byte1, Byte2, Byte3, Byte4, Byte5, Byte6, Byte7) \ + Byte0, Byte1, Byte2, Byte3, Byte4, Byte5, Byte6, Byte7 + +#define PCI_DEVICE_END 0xFF + +// +// Related data structures definition +// +typedef struct _EFI_ACPI_SMM_DEV { + + // + // Parent dispatch driver returned sleep handle + // + EFI_HANDLE S3SleepEntryHandle; + + EFI_HANDLE S4SleepEntryHandle; + + EFI_HANDLE S1SleepEntryHandle; + + EFI_HANDLE S5SoftOffEntryHandle; + + EFI_HANDLE EnableAcpiHandle; + + EFI_HANDLE DisableAcpiHandle; + + EFI_HANDLE PpCallbackHandle; + + EFI_HANDLE MorCallbackHandle; + + // + // QNC Power Management I/O register base + // + UINT32 QncPmBase; + + // + // QNC General Purpose Event0 register base + // + UINT32 QncGpe0Base; + + UINT32 BootScriptSaved; + +} EFI_ACPI_SMM_DEV; + +// +// Prototypes +// +EFI_STATUS +InitPlatformAcpiSmm ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable, + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommBufferSize + ); + +EFI_STATUS +SxSleepEntryCallBack ( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *DispatchContext, + + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommBufferSize + ); + +EFI_STATUS +DisableAcpiCallback ( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *DispatchContext, + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommBufferSize + ); + +EFI_STATUS +EnableAcpiCallback ( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *DispatchContext, + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommBufferSize + ); + +EFI_STATUS +RegisterToDispatchDriver ( + VOID + ); + +EFI_STATUS +GetAllQncPmBase ( + IN EFI_SMM_SYSTEM_TABLE2 *Smst + ); + +EFI_STATUS +SaveRuntimeScriptTable ( + IN EFI_SMM_SYSTEM_TABLE2 *Smst + ); + +EFI_STATUS +RestoreQncS3SwCallback ( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *DispatchContext, + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommBufferSize + ); + +extern EFI_GUID gQncS3CodeInLockBoxGuid; +extern EFI_GUID gQncS3ContextInLockBoxGuid; + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.inf b/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.inf new file mode 100644 index 0000000000..0a83bd14bb --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.inf @@ -0,0 +1,78 @@ +## @file +# Component description file for ACPI SMM Platform handler module +# +# This is QNC Smm platform driver . +# Copyright (c) 2013-2015 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = AcpiSmmPlatform + FILE_GUID = F5AC7057-5650-466e-B692-76A47223EFB0 + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = InitAcpiSmmPlatform + +[Sources] + AcpiSmmPlatform.c + AcpiSmmPlatform.h + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFrameworkPkg/IntelFrameworkPkg.dec + IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec + QuarkSocPkg/QuarkSocPkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + ReportStatusCodeLib + UefiDriverEntryPoint + DebugLib + IoLib + PciLib + BaseMemoryLib + BaseLib + SmmServicesTableLib + PcdLib + HobLib + S3BootScriptLib + LockBoxLib + PlatformHelperLib + IntelQNCLib + PlatformPcieHelperLib + +[Protocols] + gEfiSmmSxDispatch2ProtocolGuid + gEfiPciRootBridgeIoProtocolGuid + gEfiVariableArchProtocolGuid + gEfiVariableWriteArchProtocolGuid + gEfiGlobalNvsAreaProtocolGuid + gEfiSmmSwDispatch2ProtocolGuid + +[Guids] + gEfiSmmPeiSmramMemoryReserveGuid + gQncS3CodeInLockBoxGuid + gQncS3ContextInLockBoxGuid + +[Pcd] + gQuarkPlatformTokenSpaceGuid.PcdPlatformType + gEfiMdeModulePkgTokenSpaceGuid.PcdProgressCodeS3SuspendStart + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize + gEfiQuarkNcSocIdTokenSpaceGuid.PcdGpe0blkIoBaseAddress + gEfiQuarkNcSocIdTokenSpaceGuid.PcdPm1blkIoBaseAddress + +[Depex] + gEfiSmmSxDispatch2ProtocolGuid AND + gEfiPciRootBridgeIoProtocolGuid AND + gEfiVariableArchProtocolGuid AND + gEfiVariableWriteArchProtocolGuid AND + gEfiGlobalNvsAreaProtocolGuid AND + gEfiQncS3SupportProtocolGuid diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/Ppm.c b/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/Ppm.c new file mode 100644 index 0000000000..708ff74cb9 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/Ppm.c @@ -0,0 +1,372 @@ +/** @file + +Processor power management initialization code. + +Copyright (c) 2013-2016 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#include "SmmPowerManagement.h" + +// +// Global variables +// +extern EFI_ACPI_SDT_PROTOCOL *mAcpiSdt; +extern EFI_ACPI_TABLE_PROTOCOL *mAcpiTable; + +extern EFI_GUID gPowerManagementAcpiTableStorageGuid; + +/** + This function is the entry of processor power management initialization code. + It initializes the processor's power management features based on the user + configurations and hardware capabilities. +**/ +VOID +PpmInit ( + VOID + ) +{ + // + // Processor Power Management Flags + // + mGlobalNvsAreaPtr->Cfgd = PcdGet32(PcdPpmFlags); + + // + // Patch and publish power management related acpi tables + // + PpmPatchAndPublishAcpiTables(); +} + +/** + This function is to patch and publish power management related acpi tables. +**/ +VOID +PpmPatchAndPublishAcpiTables ( + VOID + ) +{ + // + // Patch FADT table to enable C2,C3 + // + PpmPatchFadtTable(); + + // + // Load all the power management acpi tables and patch IST table + // + PpmLoadAndPatchPMTables(); +} + +/** + This function is to patch PLvl2Lat and PLvl3Lat to enable C2, C3 support in OS. +**/ +VOID +PpmPatchFadtTable ( + VOID + ) +{ + EFI_STATUS Status; + EFI_ACPI_DESCRIPTION_HEADER *Table; + EFI_ACPI_SDT_HEADER *CurrentTable; + EFI_ACPI_TABLE_VERSION Version; + UINTN Index; + UINTN Handle; + + // + // Scan all the acpi tables to find FADT 2.0 + // + Index = 0; + do { + Status = mAcpiSdt->GetAcpiTable ( + Index, + &CurrentTable, + &Version, + &Handle + ); + if (Status == EFI_NOT_FOUND) { + break; + } + ASSERT_EFI_ERROR (Status); + Index++; + } while (CurrentTable->Signature != EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE || CurrentTable->Revision != 0x03); + + ASSERT (CurrentTable->Signature == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE); + + Table = NULL; + Status = gBS->AllocatePool (EfiBootServicesData, CurrentTable->Length, (VOID **) &Table); + ASSERT (Table != NULL); + CopyMem (Table, CurrentTable, CurrentTable->Length); + + // + // Update the ACPI table and recalculate checksum + // + Status = mAcpiTable->UninstallAcpiTable (mAcpiTable, Handle); + if (EFI_ERROR (Status)) { + // + // Should not get an error here ever, but abort if we do. + // + return ; + } + + // + // Update the check sum + // It needs to be zeroed before the checksum calculation + // + ((EFI_ACPI_SDT_HEADER *)Table)->Checksum = 0; + ((EFI_ACPI_SDT_HEADER *)Table)->Checksum = + CalculateCheckSum8 ((VOID *)Table, Table->Length); + + // + // Add the table + // + Status = mAcpiTable->InstallAcpiTable ( + mAcpiTable, + Table, + Table->Length, + &Handle + ); + ASSERT_EFI_ERROR (Status); + gBS->FreePool (Table); +} + +VOID +SsdtTableUpdate ( + IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader + ) +/*++ + + Routine Description: + + Update the SSDT table + + Arguments: + + Table - The SSDT table to be patched + + Returns: + + None + +--*/ +{ + UINT8 *CurrPtr; + UINT8 *SsdtPointer; + UINT32 *Signature; + + // + // Loop through the ASL looking for values that we must fix up. + // + CurrPtr = (UINT8 *) TableHeader; + for (SsdtPointer = CurrPtr; + SsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length); + SsdtPointer++ + ) + { + Signature = (UINT32 *) SsdtPointer; + if ((*Signature) == SIGNATURE_32 ('P', 'M', 'B', 'A')) { + switch (*(Signature+1)) { + case (SIGNATURE_32 ('L', 'V', 'L', '0')): + Signature[0] = PcdGet16(PcdPmbaIoBaseAddress); + Signature[1] = 0; + break; + case (SIGNATURE_32 ('L', 'V', 'L', '2')): + Signature[0] = PcdGet16(PcdPmbaIoLVL2); + Signature[1] = 0; + break; + } + } + } +} + +EFI_STATUS +LocateSupportProtocol ( + IN EFI_GUID *Protocol, + OUT VOID **Instance, + IN UINT32 Type + ) +/*++ + +Routine Description: + + Locate the first instance of a protocol. If the protocol requested is an + FV protocol, then it will return the first FV that contains the ACPI table + storage file. + +Arguments: + + Protocol The protocol to find. + Instance Return pointer to the first instance of the protocol + +Returns: + + EFI_SUCCESS The function completed successfully. + EFI_NOT_FOUND The protocol could not be located. + EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol. + +--*/ +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + EFI_FV_FILETYPE FileType; + UINT32 FvStatus; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINTN Size; + UINTN i; + + FvStatus = 0; + + // + // Locate protocol. + // + Status = gBS->LocateHandleBuffer ( + ByProtocol, + Protocol, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + + // + // Defined errors at this time are not found and out of resources. + // + return Status; + } + + + + // + // Looking for FV with ACPI storage file + // + + for (i = 0; i < NumberOfHandles; i++) { + // + // Get the protocol on this handle + // This should not fail because of LocateHandleBuffer + // + Status = gBS->HandleProtocol ( + HandleBuffer[i], + Protocol, + Instance + ); + ASSERT_EFI_ERROR (Status); + + if (!Type) { + // + // Not looking for the FV protocol, so find the first instance of the + // protocol. There should not be any errors because our handle buffer + // should always contain at least one or LocateHandleBuffer would have + // returned not found. + // + break; + } + + // + // See if it has the ACPI storage file + // + + Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL*) (*Instance))->ReadFile (*Instance, + &gPowerManagementAcpiTableStorageGuid, + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + + // + // If we found it, then we are done + // + if (Status == EFI_SUCCESS) { + break; + } + } + + // + // Our exit status is determined by the success of the previous operations + // If the protocol was found, Instance already points to it. + // + + // + // Free any allocated buffers + // + gBS->FreePool (HandleBuffer); + + return Status; +} + +/** + This function is to load all the power management acpi tables and patch IST table. +**/ +VOID +PpmLoadAndPatchPMTables ( + VOID + ) +{ + EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol; + EFI_STATUS Status; + INTN Instance; + EFI_ACPI_COMMON_HEADER *CurrentTable; + UINTN TableHandle; + UINT32 FvStatus; + UINTN Size; + + Status = LocateSupportProtocol (&gEfiFirmwareVolume2ProtocolGuid, (VOID**)&FwVol, 1); + if (EFI_ERROR (Status)) { + return; + } + + // + // Read tables from the storage file. + // + Instance = 0; + CurrentTable = NULL; + + while (Status == EFI_SUCCESS) { + + Status = FwVol->ReadSection ( + FwVol, + &gPowerManagementAcpiTableStorageGuid, + EFI_SECTION_RAW, + Instance, + (VOID**)&CurrentTable, + &Size, + &FvStatus + ); + + if (!EFI_ERROR(Status)) { + SsdtTableUpdate ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable); + + // + // Update the check sum + // It needs to be zeroed before the checksum calculation + // + ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum = 0; + ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum = (UINT8) + CalculateCheckSum8 ((VOID *)CurrentTable, CurrentTable->Length); + + // + // Add the table + // + TableHandle = 0; + Status = mAcpiTable->InstallAcpiTable ( + mAcpiTable, + CurrentTable, + CurrentTable->Length, + &TableHandle + ); + + ASSERT_EFI_ERROR (Status); + + // + // Increment the instance + // + Instance++; + CurrentTable = NULL; + } + } + +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/Ppm.h b/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/Ppm.h new file mode 100644 index 0000000000..cc7bb3c382 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/Ppm.h @@ -0,0 +1,150 @@ +/** @file + +Processor power management initialization code. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#ifndef _PPM_H +#define _PPM_H + +// +// Bit definitions of PPMFlags +// +#define PPM_GV3 (1 << 0) // Geyserville 3 +#define PPM_TURBO (1 << 1) // Turbo Mode +#define PPM_SUPER_LFM (1 << 2) // N/2 Ratio +#define PPM_C1 (1 << 4) // C1 Capable, Enabled +#define PPM_C2 (1 << 5) // C2 Capable, Enabled +#define PPM_C3 (1 << 6) // C3 Capable, Enabled +#define PPM_C4 (1 << 7) // C4 Capable, Enabled +#define PPM_C5 (1 << 8) // C5/Deep C4 Capable, Enabled +#define PPM_C6 (1 << 9) // C6 Capable, Enabled +#define PPM_C1E (1 << 10) // C1E Enabled +#define PPM_C2E (1 << 11) // C2E Enabled +#define PPM_C3E (1 << 12) // C3E Enabled +#define PPM_C4E (1 << 13) // C4E Enabled +#define PPM_HARD_C4E (1 << 14) // Hard C4E Capable, Enabled +#define PPM_TM1 (1 << 16) // Thermal Monitor 1 +#define PPM_TM2 (1 << 17) // Thermal Monitor 2 +#define PPM_PHOT (1 << 19) // Bi-directional ProcHot +#define PPM_MWAIT_EXT (1 << 21) // MWAIT extensions supported +#define PPM_CMP (1 << 24) // CMP supported, Enabled +#define PPM_TSTATE (1 << 28) // CPU T states supported + +#define PPM_C_STATES (PPM_C1 + PPM_C2 + PPM_C3 + PPM_C4 + PPM_C5 + PPM_C6) +#define PPM_CE_STATES (PPM_C1E + PPM_C2E + PPM_C3E + PPM_C4E + PPM_HARD_C4E) + + +#define MAX_P_STATES_NUM 12 + +#define AML_NAME_OP 0x08 +#define AML_SCOPE_OP 0x10 +#define AML_PACKAGE_OP 0x12 +#define AML_METHOD_OP 0x14 + +#define S3_CPU_REGISTER_TABLE_GUID \ + { \ + 0xc4ef988d, 0xe5e, 0x4403, { 0xbe, 0xeb, 0xf1, 0xbb, 0x6, 0x79, 0x6e, 0xdf } \ + } + +#pragma pack(1) +typedef struct { + UINT8 StartByte; + UINT32 NameStr; + UINT8 OpCode; + UINT16 Size; // Hardcode to 16bit width because the table we use is fixed size + UINT8 NumEntries; +} EFI_ACPI_NAME_COMMAND; + +typedef struct { + UINT8 PackageOp; + UINT8 PkgLeadByte; + UINT8 NumEntries; + UINT8 DwordPrefix0; + UINT32 CoreFreq; + UINT8 DwordPrefix1; + UINT32 Power; + UINT8 DwordPrefix2; + UINT32 TransLatency; + UINT8 DwordPrefix3; + UINT32 BMLatency; + UINT8 DwordPrefix4; + UINT32 Control; + UINT8 DwordPrefix5; + UINT32 Status; +} EFI_PSS_PACKAGE; +#pragma pack() + +typedef struct { + UINT32 Index; + UINT64 Value; +} S3_CPU_REGISTER; + +// +// Function prototypes +// + +/** + This function is the entry of processor power management initialization code. + It initializes the processor's power management features based on the user + configurations and hardware capablities. +**/ +VOID +PpmInit ( + VOID + ); + +/** + This function is to determine the Processor Power Management Flags + based on the hardware capability. +**/ +VOID +PpmDetectCapability ( + VOID + ); + +/** + This function is to determine the user configuration mask +**/ +VOID +PpmGetUserConfigurationMask ( + VOID + ); + +/** + This function is to patch and publish power management related acpi tables. +**/ +VOID +PpmPatchAndPublishAcpiTables ( + VOID + ); + +/** + This function is to patch PLvl2Lat and PLvl3Lat to enable C2, C3 support in OS. +**/ +VOID +PpmPatchFadtTable ( + VOID + ); + +/** + This function is to load all the power management acpi tables and patch IST table. +**/ +VOID +PpmLoadAndPatchPMTables ( + VOID + ); + +/** + This function is to save cpu registers for s3 resume. +**/ +VOID +PpmS3SaveRegisters ( + VOID + ); +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.c b/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.c new file mode 100644 index 0000000000..3a63223c14 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.c @@ -0,0 +1,113 @@ +/** @file + +This is QNC Smm Power Management driver + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#include "SmmPowerManagement.h" + +// +// Global variables +// +EFI_SMM_CPU_PROTOCOL *mSmmCpu = NULL; +EFI_GLOBAL_NVS_AREA *mGlobalNvsAreaPtr = NULL; +EFI_MP_SERVICES_PROTOCOL *mMpService = NULL; +EFI_ACPI_SDT_PROTOCOL *mAcpiSdt = NULL; +EFI_ACPI_TABLE_PROTOCOL *mAcpiTable = NULL; + +EFI_GUID mS3CpuRegisterTableGuid = S3_CPU_REGISTER_TABLE_GUID; + +EFI_STATUS +EFIAPI +InitializePowerManagement ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +/*++ + +Routine Description: + + Initializes the SMM Handler Driver + +Arguments: + + ImageHandle - + + SystemTable - + +Returns: + + None + +--*/ +{ + EFI_STATUS Status; + EFI_SMM_SW_DISPATCH2_PROTOCOL *SwDispatch; + EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsAreaProtocol; + + // + // Get SMM CPU protocol + // + Status = gSmst->SmmLocateProtocol ( + &gEfiSmmCpuProtocolGuid, + NULL, + (VOID **)&mSmmCpu + ); + ASSERT_EFI_ERROR (Status); + + // + // Get the Sw dispatch protocol + // + Status = gSmst->SmmLocateProtocol ( + &gEfiSmmSwDispatch2ProtocolGuid, + NULL, + (VOID**)&SwDispatch + ); + ASSERT_EFI_ERROR (Status); + + // + // Get Global NVS Area Protocol + // + Status = gBS->LocateProtocol (&gEfiGlobalNvsAreaProtocolGuid, NULL, (VOID **)&GlobalNvsAreaProtocol); + ASSERT_EFI_ERROR (Status); + mGlobalNvsAreaPtr = GlobalNvsAreaProtocol->Area; + + // + // Locate and cache PI AcpiSdt Protocol. + // + Status = gBS->LocateProtocol ( + &gEfiAcpiSdtProtocolGuid, + NULL, + (VOID **) &mAcpiSdt + ); + ASSERT_EFI_ERROR (Status); + + + // + // Locate and cache PI AcpiSdt Protocol. + // + Status = gBS->LocateProtocol ( + &gEfiAcpiTableProtocolGuid, + NULL, + (VOID **) &mAcpiTable + ); + ASSERT_EFI_ERROR (Status); + + + // + // Get MpService protocol + // + Status = gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&mMpService); + ASSERT_EFI_ERROR (Status); + // + // Initialize power management features on processors + // + PpmInit(); + + return Status; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.h b/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.h new file mode 100644 index 0000000000..30d30d9cda --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.h @@ -0,0 +1,52 @@ +/** @file +Header file for QNC Smm Power Management driver + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SMM_POWER_MANAGEMENT_H_ +#define _SMM_POWER_MANAGEMENT_H_ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include "Ppm.h" + +// +// Module global variable +// +extern EFI_SMM_CPU_PROTOCOL *mSmmCpu; +extern EFI_GLOBAL_NVS_AREA *mGlobalNvsAreaPtr; +extern EFI_MP_SERVICES_PROTOCOL *mMpService; + +// +// Function prototypes +// + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.inf b/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.inf new file mode 100644 index 0000000000..a9ba170ca7 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.inf @@ -0,0 +1,74 @@ +## @file +# Component description file for SMM Power Management module +# +# This is QNC Smm Power Management driver . +# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SmmPowerManagement + FILE_GUID = 271F1343-20D6-4e14-9B62-3C0297F56F07 + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = InitializePowerManagement + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 EBC +# + +[Sources] + SmmPowerManagement.c + SmmPowerManagement.h + Ppm.c + Ppm.h + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + QuarkSocPkg/QuarkSocPkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + DebugLib + PcdLib + IoLib + PciLib + BaseLib + BaseMemoryLib + SmmServicesTableLib + UefiBootServicesTableLib + S3BootScriptLib + MemoryAllocationLib + +[Protocols] + gEfiSmmCpuProtocolGuid # PROTOCOL ALWAYS_CONSUMED + gEfiSmmSwDispatch2ProtocolGuid # PROTOCOL ALWAYS_CONSUMED + gEfiGlobalNvsAreaProtocolGuid # PROTOCOL ALWAYS_CONSUMED + gEfiFirmwareVolume2ProtocolGuid # PROTOCOL ALWAYS_CONSUMED + gEfiMpServiceProtocolGuid # PROTOCOL ALWAYS_CONSUMED + gEfiAcpiSdtProtocolGuid # PROTOCOL ALWAYS_CONSUMED + gEfiAcpiTableProtocolGuid # PROTOCOL ALWAYS_CONSUMED + +[Guids] + gPowerManagementAcpiTableStorageGuid + +[Pcd] + gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoBaseAddress + gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoLVL2 + gQuarkPlatformTokenSpaceGuid.PcdPpmFlags + +[Depex] + gEfiSmmCpuProtocolGuid AND + gEfiSmmSwDispatch2ProtocolGuid AND + gEfiGlobalNvsAreaProtocolGuid AND + gEfiAcpiTableProtocolGuid AND + gEfiMpServiceProtocolGuid diff --git a/Platform/Intel/QuarkPlatformPkg/Application/ForceRecovery/ForceRecovery.c b/Platform/Intel/QuarkPlatformPkg/Application/ForceRecovery/ForceRecovery.c new file mode 100644 index 0000000000..7132ec9dbf --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Application/ForceRecovery/ForceRecovery.c @@ -0,0 +1,47 @@ +/** @file + Application that sets a sticky bit to force recovery on next reset. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include + +/** + The user Entry Point for Application. The user code starts with this function + as the real entry point for the application. + + @param[in] ImageHandle The firmware allocated handle for the EFI image. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + @retval other Some error occurs when executing this entry point. + +**/ +EFI_STATUS +EFIAPI +UefiMain ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + // + // Set 'B_CFG_STICKY_RW_FORCE_RECOVERY' sticky bit so we know we need to do a recovery following warm reset + // + QNCAltPortWrite ( + QUARK_SCSS_SOC_UNIT_SB_PORT_ID, + QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW, + QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW) | B_CFG_STICKY_RW_FORCE_RECOVERY + ); + + // + // Do a warm reset + // + gRT->ResetSystem (EfiResetWarm, EFI_SUCCESS, 0, NULL); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Application/ForceRecovery/ForceRecovery.inf b/Platform/Intel/QuarkPlatformPkg/Application/ForceRecovery/ForceRecovery.inf new file mode 100644 index 0000000000..f5401e9d8a --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Application/ForceRecovery/ForceRecovery.inf @@ -0,0 +1,34 @@ +## @file +# Application that sets a sticky bit to force recovery on next reset. +# +# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = ForceRecovery + FILE_GUID = 3A61FD45-69A0-42AD-B261-24DA451BF442 + MODULE_TYPE = UEFI_APPLICATION + VERSION_STRING = 1.0 + ENTRY_POINT = UefiMain + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 +# + +[Sources] + ForceRecovery.c + +[Packages] + MdePkg/MdePkg.dec + QuarkSocPkg/QuarkSocPkg.dec + +[LibraryClasses] + UefiApplicationEntryPoint + UefiRuntimeServicesTableLib + QNCAccessLib diff --git a/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c b/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c new file mode 100644 index 0000000000..0a6f5405c1 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c @@ -0,0 +1,262 @@ +/** @file + Platform Flash Access library. + + Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +// +// SPI default opcode slots +// +#define SPI_OPCODE_JEDEC_ID_INDEX 0 +#define SPI_OPCODE_READ_ID_INDEX 1 +#define SPI_OPCODE_WRITE_S_INDEX 2 +#define SPI_OPCODE_WRITE_INDEX 3 +#define SPI_OPCODE_READ_INDEX 4 +#define SPI_OPCODE_ERASE_INDEX 5 +#define SPI_OPCODE_READ_S_INDEX 6 +#define SPI_OPCODE_CHIP_ERASE_INDEX 7 + +#define SPI_ERASE_SECTOR_SIZE SIZE_4KB //This is the chipset requirement + +STATIC EFI_PHYSICAL_ADDRESS mInternalFdAddress; +EFI_SPI_PROTOCOL *mSpiProtocol; + +/** + Writes specified number of bytes from the input buffer to the address + + @param[in] WriteAddress The flash address to be written. + @param[in, out] NumBytes The number of bytes. + @param[in] Buffer The data buffer to be written. + + @return The status of flash write. +**/ +EFI_STATUS +FlashFdWrite ( + IN UINTN WriteAddress, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + + Status = EFI_SUCCESS; + + Status = mSpiProtocol->Execute ( + mSpiProtocol, + SPI_OPCODE_WRITE_INDEX, // OpcodeIndex + 0, // PrefixOpcodeIndex + TRUE, // DataCycle + TRUE, // Atomic + TRUE, // ShiftOut + WriteAddress, // Address + (UINT32) (*NumBytes), // Data Number + Buffer, + EnumSpiRegionBios + ); + DEBUG((DEBUG_INFO, "FlashFdWrite - 0x%x - %r\n", (UINTN)WriteAddress, Status)); + + AsmWbinvd (); + + return Status; +} + +/** + Erase a certain block from address LbaWriteAddress + + @param[in] WriteAddress The flash address to be erased. + + @return The status of flash erase. +**/ +EFI_STATUS +FlashFdErase ( + IN UINTN WriteAddress + ) +{ + EFI_STATUS Status; + + Status = mSpiProtocol->Execute ( + mSpiProtocol, + SPI_OPCODE_ERASE_INDEX, // OpcodeIndex + 0, // PrefixOpcodeIndex + FALSE, // DataCycle + TRUE, // Atomic + FALSE, // ShiftOut + WriteAddress, // Address + 0, // Data Number + NULL, + EnumSpiRegionBios // SPI_REGION_TYPE + ); + DEBUG((DEBUG_INFO, "FlashFdErase - 0x%x - %r\n", (UINTN)WriteAddress, Status)); + + AsmWbinvd (); + + return Status; +} + +/** + Perform flash write operation with progress indicator. The start and end + completion percentage values are passed into this function. If the requested + flash write operation is broken up, then completion percentage between the + start and end values may be passed to the provided Progress function. The + caller of this function is required to call the Progress function for the + start and end completion percentage values. This allows the Progress, + StartPercentage, and EndPercentage parameters to be ignored if the requested + flash write operation can not be broken up + + @param[in] FirmwareType The type of firmware. + @param[in] FlashAddress The address of flash device to be accessed. + @param[in] FlashAddressType The type of flash device address. + @param[in] Buffer The pointer to the data buffer. + @param[in] Length The length of data buffer in bytes. + @param[in] Progress A function used report the progress of the + firmware update. This is an optional parameter + that may be NULL. + @param[in] StartPercentage The start completion percentage value that may + be used to report progress during the flash + write operation. + @param[in] EndPercentage The end completion percentage value that may + be used to report progress during the flash + write operation. + + @retval EFI_SUCCESS The operation returns successfully. + @retval EFI_WRITE_PROTECTED The flash device is read only. + @retval EFI_UNSUPPORTED The flash device access is unsupported. + @retval EFI_INVALID_PARAMETER The input parameter is not valid. +**/ +EFI_STATUS +EFIAPI +PerformFlashWriteWithProgress ( + IN PLATFORM_FIRMWARE_TYPE FirmwareType, + IN EFI_PHYSICAL_ADDRESS FlashAddress, + IN FLASH_ADDRESS_TYPE FlashAddressType, + IN VOID *Buffer, + IN UINTN Length, + IN EFI_FIRMWARE_MANAGEMENT_UPDATE_IMAGE_PROGRESS Progress, OPTIONAL + IN UINTN StartPercentage, + IN UINTN EndPercentage + ) +{ + EFI_STATUS Status; + UINTN SectorNum; + UINTN Index; + UINTN NumBytes; + + DEBUG((DEBUG_INFO, "PerformFlashWrite - 0x%x(%x) - 0x%x\n", (UINTN)FlashAddress, (UINTN)FlashAddressType, Length)); + if (FlashAddressType == FlashAddressTypeAbsoluteAddress) { + FlashAddress = FlashAddress - mInternalFdAddress; + } + + // + // Erase & Write + // + SectorNum = Length / SPI_ERASE_SECTOR_SIZE; + for (Index = 0; Index < SectorNum; Index++){ + if (Progress != NULL) { + Progress (StartPercentage + ((Index * (EndPercentage - StartPercentage)) / SectorNum)); + } + + if (CompareMem( + (UINT8 *)(UINTN)(FlashAddress + mInternalFdAddress) + Index * SPI_ERASE_SECTOR_SIZE, + (UINT8 *)Buffer + Index * SPI_ERASE_SECTOR_SIZE, + SPI_ERASE_SECTOR_SIZE) == 0) { + DEBUG((DEBUG_INFO, "Sector - 0x%x - skip\n", Index)); + continue; + } + DEBUG((DEBUG_INFO, "Sector - 0x%x - update...\n", Index)); + + Status = FlashFdErase ( + (UINTN)FlashAddress + Index * SPI_ERASE_SECTOR_SIZE + ); + if (Status != EFI_SUCCESS){ + break; + } + NumBytes = SPI_ERASE_SECTOR_SIZE; + Status = FlashFdWrite ( + (UINTN)FlashAddress + Index * SPI_ERASE_SECTOR_SIZE, + &NumBytes, + (UINT8 *)Buffer + Index * SPI_ERASE_SECTOR_SIZE + ); + if (Status != EFI_SUCCESS){ + break; + } + } + if (Progress != NULL) { + Progress (EndPercentage); + } + + return EFI_SUCCESS; +} + +/** + Perform flash write operation. + + @param[in] FirmwareType The type of firmware. + @param[in] FlashAddress The address of flash device to be accessed. + @param[in] FlashAddressType The type of flash device address. + @param[in] Buffer The pointer to the data buffer. + @param[in] Length The length of data buffer in bytes. + + @retval EFI_SUCCESS The operation returns successfully. + @retval EFI_WRITE_PROTECTED The flash device is read only. + @retval EFI_UNSUPPORTED The flash device access is unsupported. + @retval EFI_INVALID_PARAMETER The input parameter is not valid. +**/ +EFI_STATUS +EFIAPI +PerformFlashWrite ( + IN PLATFORM_FIRMWARE_TYPE FirmwareType, + IN EFI_PHYSICAL_ADDRESS FlashAddress, + IN FLASH_ADDRESS_TYPE FlashAddressType, + IN VOID *Buffer, + IN UINTN Length + ) +{ + return PerformFlashWriteWithProgress ( + FirmwareType, + FlashAddress, + FlashAddressType, + Buffer, + Length, + NULL, + 0, + 0 + ); +} + +/** + Platform Flash Access Lib Constructor. + + @param[in] ImageHandle The firmware allocated handle for the EFI image. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS Constructor returns successfully. +**/ +EFI_STATUS +EFIAPI +PerformFlashAccessLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + mInternalFdAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32(PcdFlashAreaBaseAddress); + DEBUG((DEBUG_INFO, "PcdFlashAreaBaseAddress - 0x%x\n", mInternalFdAddress)); + + Status = gBS->LocateProtocol(&gEfiSpiProtocolGuid, NULL, (VOID **)&mSpiProtocol); + ASSERT_EFI_ERROR(Status); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf b/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf new file mode 100644 index 0000000000..3d0e6c6b35 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf @@ -0,0 +1,47 @@ +## @file +# Platform Flash Access library. +# +# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformFlashAccessLibDxe + FILE_GUID = 9168384A-5F66-4CF7-AEB6-845BDEBD3012 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformFlashAccessLib|DXE_DRIVER DXE_RUNTIME_DRIVER + CONSTRUCTOR = PerformFlashAccessLibConstructor + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 EBC +# + +[Sources] + PlatformFlashAccessLibDxe.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + SignedCapsulePkg/SignedCapsulePkg.dec + QuarkSocPkg/QuarkSocPkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + +[LibraryClasses] + BaseMemoryLib + PcdLib + DebugLib + UefiBootServicesTableLib + +[Protocols] + gEfiSpiProtocolGuid + +[Pcd] + gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress + +[Depex] + gEfiSpiProtocolGuid diff --git a/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.c b/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.c new file mode 100644 index 0000000000..70cb3467f9 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.c @@ -0,0 +1,330 @@ +/** @file + SPI flash device description. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#include "SpiFlashDevice.h" + +#define FLASH_SIZE (FixedPcdGet32 (PcdFlashAreaSize)) + +SPI_INIT_TABLE mSpiInitTable[] = { + // + // Macronix 32Mbit part + // + { + SPI_MX25L3205_ID1, + SPI_MX25L3205_ID2, + SPI_MX25L3205_ID3, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase} + }, + (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // Winbond 32Mbit part + // + { + SPI_W25X32_ID1, + SF_DEVICE_ID0_W25QXX, + SF_DEVICE_ID1_W25Q32, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // Winbond 32Mbit part + // + { + SPI_W25X32_ID1, + SPI_W25X32_ID2, + SPI_W25X32_ID3, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase} + }, + (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // Atmel 32Mbit part + // + { + SPI_AT26DF321_ID1, + SPI_AT26DF321_ID2, // issue: byte 2 identifies family/density for Atmel + SPI_AT26DF321_ID3, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase} + }, + (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + + // + // Intel 32Mbit part bottom boot + // + { + SPI_QH25F320_ID1, + SPI_QH25F320_ID2, + SPI_QH25F320_ID3, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_ENABLE + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase} + }, + 0, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // SST 64Mbit part + // + { + SPI_SST25VF080B_ID1, // VendorId + SF_DEVICE_ID0_25VF064C, // DeviceId 0 + SF_DEVICE_ID1_25VF064C, // DeviceId 1 + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // NUMONYX 64Mbit part + // + { + SF_VENDOR_ID_NUMONYX, // VendorId + SF_DEVICE_ID0_M25PX64, // DeviceId 0 + SF_DEVICE_ID1_M25PX64, // DeviceId 1 + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // Atmel 64Mbit part + // + { + SF_VENDOR_ID_ATMEL, // VendorId + SF_DEVICE_ID0_AT25DF641, // DeviceId 0 + SF_DEVICE_ID1_AT25DF641, // DeviceId 1 + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + + // + // Spansion 64Mbit part + // + { + SF_VENDOR_ID_SPANSION, // VendorId + SF_DEVICE_ID0_S25FL064K, // DeviceId 0 + SF_DEVICE_ID1_S25FL064K, // DeviceId 1 + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + + // + // Macronix 64Mbit part bottom boot + // + { + SF_VENDOR_ID_MX, // VendorId + SF_DEVICE_ID0_25L6405D, // DeviceId 0 + SF_DEVICE_ID1_25L6405D, // DeviceId 1 + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // Winbond 64Mbit part bottom boot + // + { + SPI_W25X64_ID1, + SF_DEVICE_ID0_W25QXX, + SF_DEVICE_ID1_W25Q64, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // Winbond 64Mbit part bottom boot + // + { + SPI_W25X64_ID1, + SPI_W25X64_ID2, + SPI_W25X64_ID3, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // Intel 64Mbit part bottom boot + // + { + SPI_QH25F640_ID1, + SPI_QH25F640_ID2, + SPI_QH25F640_ID3, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + } +}; diff --git a/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.h b/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.h new file mode 100644 index 0000000000..fdf305d727 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.h @@ -0,0 +1,180 @@ +/** @file + SPI flash device header file. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SPI_FLASH_DEVICE_H_ +#define _SPI_FLASH_DEVICE_H_ + +#include +#include +#include + +// +// Supported SPI Flash Devices +// +typedef enum { + EnumSpiFlash25L3205D, // Macronix 32Mbit part + EnumSpiFlashW25Q32, // Winbond 32Mbit part + EnumSpiFlashW25X32, // Winbond 32Mbit part + EnumSpiFlashAT25DF321, // Atmel 32Mbit part + EnumSpiFlashQH25F320, // Intel 32Mbit part + EnumSpiFlash25VF064C, // SST 64Mbit part + EnumSpiFlashM25PX64, // NUMONYX 64Mbit part + EnumSpiFlashAT25DF641, // Atmel 64Mbit part + EnumSpiFlashS25FL064K, // Spansion 64Mbit part + EnumSpiFlash25L6405D, // Macronix 64Mbit part + EnumSpiFlashW25Q64, // Winbond 64Mbit part + EnumSpiFlashW25X64, // Winbond 64Mbit part + EnumSpiFlashQH25F640, // Intel 64Mbit part + EnumSpiFlashMax +} SPI_FLASH_TYPES_SUPPORTED; + +// +// Flash Device commands +// +// If a supported device uses a command different from the list below, a device specific command +// will be defined just below it's JEDEC id section. +// +#define SPI_COMMAND_WRITE 0x02 +#define SPI_COMMAND_WRITE_AAI 0xAD +#define SPI_COMMAND_READ 0x03 +#define SPI_COMMAND_ERASE 0x20 +#define SPI_COMMAND_WRITE_DISABLE 0x04 +#define SPI_COMMAND_READ_S 0x05 +#define SPI_COMMAND_WRITE_ENABLE 0x06 +#define SPI_COMMAND_READ_ID 0xAB +#define SPI_COMMAND_JEDEC_ID 0x9F +#define SPI_COMMAND_WRITE_S_EN 0x50 +#define SPI_COMMAND_WRITE_S 0x01 +#define SPI_COMMAND_CHIP_ERASE 0xC7 +#define SPI_COMMAND_BLOCK_ERASE 0xD8 + +// +// Flash JEDEC device ids +// +// SST 8Mbit part +// +#define SPI_SST25VF080B_ID1 0xBF +#define SPI_SST25VF080B_ID2 0x25 +#define SPI_SST25VF080B_ID3 0x8E +// +// SST 16Mbit part +// +#define SPI_SST25VF016B_ID1 0xBF +#define SPI_SST25VF016B_ID2 0x25 +#define SPI_SST25V016BF_ID3 0x41 +// +// Macronix 32Mbit part +// +// MX25 part does not support WRITE_AAI comand (0xAD) +// +#define SPI_MX25L3205_ID1 0xC2 +#define SPI_MX25L3205_ID2 0x20 +#define SPI_MX25L3205_ID3 0x16 +// +// Intel 32Mbit part bottom boot +// +#define SPI_QH25F320_ID1 0x89 +#define SPI_QH25F320_ID2 0x89 +#define SPI_QH25F320_ID3 0x12 // 32Mbit bottom boot +// +// Intel 64Mbit part bottom boot +// +#define SPI_QH25F640_ID1 0x89 +#define SPI_QH25F640_ID2 0x89 +#define SPI_QH25F640_ID3 0x13 // 64Mbit bottom boot +// +// QH part does not support command 0x20 for erase; only 0xD8 (sector erase) +// QH part has 0x40 command for erase of parameter block (8 x 8K blocks at bottom of part) +// 0x40 command ignored if address outside of parameter block range +// +#define SPI_QH25F320_COMMAND_PBLOCK_ERASE 0x40 +// +// Winbond 32Mbit part +// +#define SPI_W25X32_ID1 0xEF +#define SPI_W25X32_ID2 0x30 // Memory Type +#define SPI_W25X32_ID3 0x16 // Capacity +#define SF_DEVICE_ID1_W25Q32 0x16 + +// +// Winbond 64Mbit part +// +#define SPI_W25X64_ID1 0xEF +#define SPI_W25X64_ID2 0x30 // Memory Type +#define SPI_W25X64_ID3 0x17 // Capacity +#define SF_DEVICE_ID0_W25QXX 0x40 +#define SF_DEVICE_ID1_W25Q64 0x17 +// +// Winbond 128Mbit part +// +#define SF_DEVICE_ID0_W25Q128 0x40 +#define SF_DEVICE_ID1_W25Q128 0x18 + +// +// Atmel 32Mbit part +// +#define SPI_AT26DF321_ID1 0x1F +#define SPI_AT26DF321_ID2 0x47 // [7:5]=Family, [4:0]=Density +#define SPI_AT26DF321_ID3 0x00 + +#define SF_VENDOR_ID_ATMEL 0x1F +#define SF_DEVICE_ID0_AT25DF641 0x48 +#define SF_DEVICE_ID1_AT25DF641 0x00 + +// +// SST 8Mbit part +// +#define SPI_SST25VF080B_ID1 0xBF +#define SPI_SST25VF080B_ID2 0x25 +#define SPI_SST25VF080B_ID3 0x8E +#define SF_DEVICE_ID0_25VF064C 0x25 +#define SF_DEVICE_ID1_25VF064C 0x4B + +// +// SST 16Mbit part +// +#define SPI_SST25VF016B_ID1 0xBF +#define SPI_SST25VF016B_ID2 0x25 +#define SPI_SST25V016BF_ID3 0x41 + +// +// Winbond 32Mbit part +// +#define SPI_W25X32_ID1 0xEF +#define SPI_W25X32_ID2 0x30 // Memory Type +#define SPI_W25X32_ID3 0x16 // Capacity + +#define SF_VENDOR_ID_MX 0xC2 +#define SF_DEVICE_ID0_25L6405D 0x20 +#define SF_DEVICE_ID1_25L6405D 0x17 + +#define SF_VENDOR_ID_NUMONYX 0x20 +#define SF_DEVICE_ID0_M25PX64 0x71 +#define SF_DEVICE_ID1_M25PX64 0x17 + +// +// Spansion 64Mbit part +// +#define SF_VENDOR_ID_SPANSION 0xEF +#define SF_DEVICE_ID0_S25FL064K 0x40 +#define SF_DEVICE_ID1_S25FL064K 0x00 + +// +// index for prefix opcodes +// +#define SPI_WREN_INDEX 0 // Prefix Opcode 0: SPI_COMMAND_WRITE_ENABLE +#define SPI_EWSR_INDEX 1 // Prefix Opcode 1: SPI_COMMAND_WRITE_S_EN +#define BIOS_CTRL 0xDC + +#define PFAB_CARD_DEVICE_ID 0x5150 +#define PFAB_CARD_VENDOR_ID 0x8086 +#define PFAB_CARD_SETUP_REGISTER 0x40 +#define PFAB_CARD_SETUP_BYTE 0x0d + + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc b/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc new file mode 100644 index 0000000000..ae2c24510e --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc @@ -0,0 +1,83 @@ +/** @file + System Firmware descriptor. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +#define PACKAGE_VERSION 0xFFFFFFFF +#define PACKAGE_VERSION_STRING L"Unknown" + +#define CURRENT_FIRMWARE_VERSION 0x00000002 +#define CURRENT_FIRMWARE_VERSION_STRING L"0x00000002" +#define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000001 + +#define IMAGE_ID SIGNATURE_64('Q', 'U', 'A', 'R', 'K', '_', 'F', 'd') +#define IMAGE_ID_STRING L"QuarkPlatformFd" + +// PcdSystemFmpCapsuleImageTypeIdGuid +#define IMAGE_TYPE_ID_GUID { 0x62af20c0, 0x7016, 0x424a, { 0x9b, 0xf8, 0x9c, 0xcc, 0x86, 0x58, 0x40, 0x90 } } + +typedef struct { + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR Descriptor; + // real string data + CHAR16 ImageIdNameStr[sizeof(IMAGE_ID_STRING)/sizeof(CHAR16)]; + CHAR16 VersionNameStr[sizeof(CURRENT_FIRMWARE_VERSION_STRING)/sizeof(CHAR16)]; + CHAR16 PackageVersionNameStr[sizeof(PACKAGE_VERSION_STRING)/sizeof(CHAR16)]; +} IMAGE_DESCRIPTOR; + +IMAGE_DESCRIPTOR mImageDescriptor = +{ + { + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE, + sizeof(EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR), + sizeof(IMAGE_DESCRIPTOR), + PACKAGE_VERSION, // PackageVersion + OFFSET_OF (IMAGE_DESCRIPTOR, PackageVersionNameStr), // PackageVersionName + 1, // ImageIndex; + {0x0}, // Reserved + IMAGE_TYPE_ID_GUID, // ImageTypeId; + IMAGE_ID, // ImageId; + OFFSET_OF (IMAGE_DESCRIPTOR, ImageIdNameStr), // ImageIdName; + CURRENT_FIRMWARE_VERSION, // Version; + OFFSET_OF (IMAGE_DESCRIPTOR, VersionNameStr), // VersionName; + {0x0}, // Reserved2 + FixedPcdGet32(PcdFlashAreaSize), // Size; + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | + IMAGE_ATTRIBUTE_RESET_REQUIRED | + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED | + IMAGE_ATTRIBUTE_IN_USE, // AttributesSupported; + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | + IMAGE_ATTRIBUTE_RESET_REQUIRED | + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED | + IMAGE_ATTRIBUTE_IN_USE, // AttributesSetting; + 0x0, // Compatibilities; + LOWEST_SUPPORTED_FIRMWARE_VERSION, // LowestSupportedImageVersion; + 0x00000000, // LastAttemptVersion; + 0, // LastAttemptStatus; + {0x0}, // Reserved3 + 0, // HardwareInstance; + }, + // real string data + {IMAGE_ID_STRING}, + {CURRENT_FIRMWARE_VERSION_STRING}, + {PACKAGE_VERSION_STRING}, +}; + + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&mImageDescriptor; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf b/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf new file mode 100644 index 0000000000..5d243e5008 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf @@ -0,0 +1,40 @@ +## @file +# System Firmware descriptor. +# +# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SystemFirmwareDescriptor + FILE_GUID = 90B2B846-CA6D-4D6E-A8D3-C140A8E110AC + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = SystemFirmwareDescriptorPeimEntry + +[Sources] + SystemFirmwareDescriptorPei.c + SystemFirmwareDescriptor.aslc + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + SignedCapsulePkg/SignedCapsulePkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + +[LibraryClasses] + PcdLib + PeiServicesLib + DebugLib + PeimEntryPoint + +[FixedPcd] + gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize + +[Pcd] + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor + +[Depex] + TRUE diff --git a/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c b/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c new file mode 100644 index 0000000000..d21ee52184 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c @@ -0,0 +1,60 @@ +/** @file + System Firmware descriptor producer. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +/** + Entrypoint for SystemFirmwareDescriptor PEIM. + + @param[in] FileHandle Handle of the file being invoked. + @param[in] PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS PPI successfully installed. +**/ +EFI_STATUS +EFIAPI +SystemFirmwareDescriptorPeimEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR *Descriptor; + UINTN Size; + UINTN Index; + UINT32 AuthenticationStatus; + + // + // Search RAW section. + // + Index = 0; + while (TRUE) { + Status = PeiServicesFfsFindSectionData3(EFI_SECTION_RAW, Index, FileHandle, (VOID **)&Descriptor, &AuthenticationStatus); + if (EFI_ERROR(Status)) { + // Should not happen, must something wrong in FDF. + ASSERT(FALSE); + return EFI_NOT_FOUND; + } + if (Descriptor->Signature == EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE) { + break; + } + Index++; + } + + DEBUG((DEBUG_INFO, "EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR size - 0x%x\n", Descriptor->Length)); + + Size = Descriptor->Length; + PcdSetPtrS (PcdEdkiiSystemFirmwareImageDescriptor, &Size, Descriptor); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini b/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini new file mode 100644 index 0000000000..ab46869873 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Feature/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini @@ -0,0 +1,57 @@ +## @file +# +# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Head] +NumOfUpdate = 4 +NumOfRecovery = 2 +Update0 = QuarkFvMain +Update1 = QuarkFvBinary +Update2 = QuarkFvRecovery +Update3 = QuarkFvNvRam +Recovery0 = QuarkFvMain +Recovery1 = QuarkFvPayload + +[QuarkFvPayload] +FirmwareType = 0 # SystemFirmware +AddressType = 0 # 0 - relative address, 1 - absolute address. +BaseAddress = 0x00400000 # Base address offset on flash +Length = 0x00100000 # Length +ImageOffset = 0x00400000 # Image offset of this SystemFirmware image +FileGuid = 14D83A59-A810-4556-8192-1C0A593C065C # PcdEdkiiSystemFirmwareFileGuid + +[QuarkFvMain] +FirmwareType = 0 # SystemFirmware +AddressType = 0 # 0 - relative address, 1 - absolute address. +BaseAddress = 0x00500000 # Base address offset on flash +Length = 0x001E0000 # Length +ImageOffset = 0x00500000 # Image offset of this SystemFirmware image +FileGuid = 14D83A59-A810-4556-8192-1C0A593C065C # PcdEdkiiSystemFirmwareFileGuid + +[QuarkFvNvRam] +FirmwareType = 1 # NvRam +AddressType = 0 # 0 - relative address, 1 - absolute address. +BaseAddress = 0x006E0000 # Base address offset on flash +Length = 0x00020000 # Length +ImageOffset = 0x006E0000 # Image offset of this SystemFirmware image +FileGuid = 14D83A59-A810-4556-8192-1C0A593C065C # PcdEdkiiSystemFirmwareFileGuid + +[QuarkFvBinary] +FirmwareType = 0 # SystemFirmware +AddressType = 0 # 0 - relative address, 1 - absolute address. +BaseAddress = 0x00700000 # Base address offset on flash +Length = 0x00010000 # Length +ImageOffset = 0x00700000 # Image offset of this SystemFirmware image +FileGuid = 14D83A59-A810-4556-8192-1C0A593C065C # PcdEdkiiSystemFirmwareFileGuid + +[QuarkFvRecovery] +FirmwareType = 0 # SystemFirmware +AddressType = 0 # 0 - relative address, 1 - absolute address. +BaseAddress = 0x00710000 # Base address offset on flash +Length = 0x000F0000 # Length +ImageOffset = 0x00710000 # Image offset of this SystemFirmware image +FileGuid = 14D83A59-A810-4556-8192-1C0A593C065C # PcdEdkiiSystemFirmwareFileGuid + diff --git a/Platform/Intel/QuarkPlatformPkg/Include/Guid/CapsuleOnDataCD.h b/Platform/Intel/QuarkPlatformPkg/Include/Guid/CapsuleOnDataCD.h new file mode 100644 index 0000000000..d97caced1e --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Include/Guid/CapsuleOnDataCD.h @@ -0,0 +1,23 @@ +/** @file +Capsule on Data CD GUID. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +This is the contract between the recovery module and device recovery module +in order to convey the name of a given recovery module type + +**/ + +#ifndef _CAPSULE_ON_DATA_CD_H +#define _CAPSULE_ON_DATA_CD_H + +#define PEI_CAPSULE_ON_DATA_CD_GUID \ + { \ + 0x5cac0099, 0x0dc9, 0x48e5, {0x80, 0x68, 0xbb, 0x95, 0xf5, 0x40, 0x0a, 0x9f } \ + }; + +extern EFI_GUID gPeiCapsuleOnDataCDGuid; + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Include/Guid/CapsuleOnFatFloppyDisk.h b/Platform/Intel/QuarkPlatformPkg/Include/Guid/CapsuleOnFatFloppyDisk.h new file mode 100644 index 0000000000..a6a92e0f69 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Include/Guid/CapsuleOnFatFloppyDisk.h @@ -0,0 +1,23 @@ +/** @file +Capsule on Fat Floppy Disk GUID. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +This is the contract between the recovery module and device recovery module +in order to convey the name of a given recovery module type + +**/ + +#ifndef _CAPSULE_ON_FAT_FLOPPY_DISK_H +#define _CAPSULE_ON_FAT_FLOPPY_DISK_H + +#define PEI_CAPSULE_ON_FAT_FLOPPY_DISK_GUID \ + { \ + 0x2e3d2e75, 0x9b2e, 0x412d, {0xb4, 0xb1, 0x70, 0x41, 0x6b, 0x87, 0x0, 0xff }\ + }; + +extern EFI_GUID gPeiCapsuleOnFatFloppyDiskGuid; + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Include/Guid/CapsuleOnFatIdeDisk.h b/Platform/Intel/QuarkPlatformPkg/Include/Guid/CapsuleOnFatIdeDisk.h new file mode 100644 index 0000000000..34c633048c --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Include/Guid/CapsuleOnFatIdeDisk.h @@ -0,0 +1,24 @@ +/** @file +Capsule on Fat Ide Disk GUID. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +This is the contract between the recovery module and device recovery module +in order to convey the name of a given recovery module type + +**/ + +#ifndef _CAPSULE_ON_FAT_IDE_DISK_H +#define _CAPSULE_ON_FAT_IDE_DISK_H + +#define PEI_CAPSULE_ON_FAT_IDE_DISK_GUID \ + { \ + 0xb38573b6, 0x6200, 0x4ac5, {0xb5, 0x1d, 0x82, 0xe6, 0x59, 0x38, 0xd7, 0x83 }\ + }; + +extern EFI_GUID gPeiCapsuleOnFatIdeDiskGuid; + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Include/Guid/CapsuleOnFatUsbDisk.h b/Platform/Intel/QuarkPlatformPkg/Include/Guid/CapsuleOnFatUsbDisk.h new file mode 100644 index 0000000000..61ffc5b65e --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Include/Guid/CapsuleOnFatUsbDisk.h @@ -0,0 +1,24 @@ +/** @file +Capsule on Fat Usb Disk GUID. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +This is the contract between the recovery module and device recovery module +in order to convey the name of a given recovery module type + +**/ + +#ifndef _PEI_CAPSULE_ON_FAT_USB_DISK_H +#define _PEI_CAPSULE_ON_FAT_USB_DISK_H + +#define PEI_CAPSULE_ON_FAT_USB_DISK_GUID \ + { \ + 0x0ffbce19, 0x324c, 0x4690, {0xa0, 0x09, 0x98, 0xc6, 0xae, 0x2e, 0xb1, 0x86 } \ + }; + +extern EFI_GUID gPeiCapsuleOnFatUsbDiskGuid; + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Include/Guid/MemoryConfigData.h b/Platform/Intel/QuarkPlatformPkg/Include/Guid/MemoryConfigData.h new file mode 100644 index 0000000000..885a4beb28 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Include/Guid/MemoryConfigData.h @@ -0,0 +1,23 @@ +/** @file +Define a GUID name for GUID HOB which is used to pass Memory +Configuration Data information to different modules. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MEMORY_CONFIG_DATA_H_ +#define _MEMORY_CONFIG_DATA_H_ + +#define EFI_MEMORY_CONFIG_DATA_GUID \ + { \ + 0x80dbd530, 0xb74c, 0x4f11, {0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 } \ + } + +#define EFI_MEMORY_CONFIG_DATA_NAME L"MemoryConfig" + +extern EFI_GUID gEfiMemoryConfigDataGuid; + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Include/Guid/QuarkCapsuleGuid.h b/Platform/Intel/QuarkPlatformPkg/Include/Guid/QuarkCapsuleGuid.h new file mode 100644 index 0000000000..22d455f851 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Include/Guid/QuarkCapsuleGuid.h @@ -0,0 +1,46 @@ +/** @file + +Capsule format guid for Quark capsule image. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _QUARK_CAPSULE_GUID_H_ +#define _QUARK_CAPSULE_GUID_H_ + +#define QUARK_CAPSULE_GUID \ + { 0xd400d1e4, 0xa314, 0x442b, { 0x89, 0xed, 0xa9, 0x2e, 0x4c, 0x81, 0x97, 0xcb } } + +#define SMI_INPUT_UPDATE_CAP 0x27 +#define SMI_INPUT_GET_CAP 0x28 + +#define SMI_CAP_FUNCTION 0xEF + +#pragma pack(1) +typedef struct { + UINT64 Address; + UINT32 BufferOffset; + UINT32 Size; + UINT32 Flags; + UINT32 Reserved; +} CAPSULE_FRAGMENT; + +typedef struct { + UINTN CapsuleLocation; // Top of the capsule that point to structure CAPSULE_FRAGMENT + UINTN CapsuleSize; // Size of the capsule + EFI_STATUS Status; // Returned status +} CAPSULE_INFO_PACKET; + +typedef struct { + UINTN BlocksCompleted; // # of blocks processed + UINTN TotalBlocks; // Total # of blocks to be processed + EFI_STATUS Status; // returned status +} UPDATE_STATUS_PACKET; +#pragma pack() + +extern EFI_GUID gEfiQuarkCapsuleGuid; + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Include/Guid/QuarkVariableLock.h b/Platform/Intel/QuarkPlatformPkg/Include/Guid/QuarkVariableLock.h new file mode 100644 index 0000000000..5f346d3bd6 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Include/Guid/QuarkVariableLock.h @@ -0,0 +1,23 @@ +/** @file + +Guid and variable name used to trigger quark lock of specific UEFI variables. + +Copyright (c) 2013 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _QUARK_VARIABLE_LOCK_GUID_H_ +#define _QUARK_VARIABLE_LOCK_GUID_H_ + +#define QUARK_VARIABLE_LOCK_GUID \ + { \ + 0xeef749c2, 0xc047, 0x4d6e, { 0xb1, 0xbc, 0xd3, 0x6e, 0xb3, 0xa5, 0x55, 0x9c } \ + } + +#define QUARK_VARIABLE_LOCK_NAME L"QuarkVariableLock" + +extern EFI_GUID gQuarkVariableLockGuid; + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Include/Guid/SystemNvDataHobGuid.h b/Platform/Intel/QuarkPlatformPkg/Include/Guid/SystemNvDataHobGuid.h new file mode 100644 index 0000000000..b26da9a108 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Include/Guid/SystemNvDataHobGuid.h @@ -0,0 +1,29 @@ +/** @file +GUIDs used for System Non Volatile HOB entries in the in the HOB list and FV Guids carrying +the System specific information. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SYSTEM_NV_DATA_HOB_GUID_H_ +#define _SYSTEM_NV_DATA_HOB_GUID_H_ + +#define EFI_SYSTEM_NV_DATA_HOB_GUID \ + {0xd6e5092d, 0xc7b2, 0x4872, {0xaf, 0x66, 0xfd, 0xc0, 0xe6, 0xf9, 0x5e, 0x78}} + +typedef struct { + EFI_GUID SystemNvDataHobGuid; + EFI_GUID SystemNvDataFvGuid; + EFI_LBA StartLba; + UINTN StartLbaOffset; + EFI_LBA EndLba; + UINTN EndLbaOffset; + UINT32 DataTypeSignature; +} NV_SYSTEM_DATA_GUID_TYPE; + +extern EFI_GUID gEfiSystemNvDataHobGuid; + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Include/Library/PlatformHelperLib.h b/Platform/Intel/QuarkPlatformPkg/Include/Library/PlatformHelperLib.h new file mode 100644 index 0000000000..65429626c8 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Include/Library/PlatformHelperLib.h @@ -0,0 +1,266 @@ +/** @file +PlatformHelperLib function prototype definitions. + +Copyright (c) 2013 - 2016 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PLATFORM_HELPER_LIB_H__ +#define __PLATFORM_HELPER_LIB_H__ + +#include "Platform.h" + +// +// Function prototypes for routines exported by this library. +// + +/** + Find pointer to RAW data in Firmware volume file. + + @param FvNameGuid Firmware volume to search. If == NULL search all. + @param FileNameGuid Firmware volume file to search for. + @param SectionData Pointer to RAW data section of found file. + @param SectionDataSize Pointer to UNITN to get size of RAW data. + + @retval EFI_SUCCESS Raw Data found. + @retval EFI_INVALID_PARAMETER FileNameGuid == NULL. + @retval EFI_NOT_FOUND Firmware volume file not found. + @retval EFI_UNSUPPORTED Unsupported in current enviroment (PEI or DXE). + +**/ +EFI_STATUS +EFIAPI +PlatformFindFvFileRawDataSection ( + IN CONST EFI_GUID *FvNameGuid OPTIONAL, + IN CONST EFI_GUID *FileNameGuid, + OUT VOID **SectionData, + OUT UINTN *SectionDataSize + ); + +/** + Find free spi protect register and write to it to protect a flash region. + + @param DirectValue Value to directly write to register. + if DirectValue == 0 the use Base & Length below. + @param BaseAddress Base address of region in Flash Memory Map. + @param Length Length of region to protect. + + @retval EFI_SUCCESS Free spi protect register found & written. + @retval EFI_NOT_FOUND Free Spi protect register not found. + @retval EFI_DEVICE_ERROR Unable to write to spi protect register. + +**/ +EFI_STATUS +EFIAPI +PlatformWriteFirstFreeSpiProtect ( + IN CONST UINT32 DirectValue, + IN CONST UINT32 BaseAddress, + IN CONST UINT32 Length + ); + +/** + Lock legacy SPI static configuration information. + + Function will assert if unable to lock config. + +**/ +VOID +EFIAPI +PlatformFlashLockConfig ( + VOID + ); + +/** + Lock regions and config of SPI flash given the policy for this platform. + + Function will assert if unable to lock regions or config. + + @param PreBootPolicy If TRUE do Pre Boot Flash Lock Policy. + +**/ +VOID +EFIAPI +PlatformFlashLockPolicy ( + IN CONST BOOLEAN PreBootPolicy + ); + +/** Check if System booted with recovery Boot Stage1 image. + + @retval TRUE If system booted with recovery Boot Stage1 image. + @retval FALSE If system booted with normal stage1 image. + +**/ +BOOLEAN +EFIAPI +PlatformIsBootWithRecoveryStage1 ( + VOID + ); + +/** + Clear SPI Protect registers. + + @retval EFI_SUCESS SPI protect registers cleared. + @retval EFI_ACCESS_DENIED Unable to clear SPI protect registers. +**/ + +EFI_STATUS +EFIAPI +PlatformClearSpiProtect ( + VOID + ); + +/** + Determine if an SPI address range is protected. + + @param SpiBaseAddress Base of SPI range. + @param Length Length of SPI range. + + @retval TRUE Range is protected. + @retval FALSE Range is not protected. +**/ +BOOLEAN +EFIAPI +PlatformIsSpiRangeProtected ( + IN CONST UINT32 SpiBaseAddress, + IN CONST UINT32 Length + ); + +/** + Set Legacy GPIO Level + + @param LevelRegOffset GPIO level register Offset from GPIO Base Address. + @param GpioNum GPIO bit to change. + @param HighLevel If TRUE set GPIO High else Set GPIO low. + +**/ +VOID +EFIAPI +PlatformLegacyGpioSetLevel ( + IN CONST UINT32 LevelRegOffset, + IN CONST UINT32 GpioNum, + IN CONST BOOLEAN HighLevel + ); + +/** + Get Legacy GPIO Level + + @param LevelRegOffset GPIO level register Offset from GPIO Base Address. + @param GpioNum GPIO bit to check. + + @retval TRUE If bit is SET. + @retval FALSE If bit is CLEAR. + +**/ +BOOLEAN +EFIAPI +PlatformLegacyGpioGetLevel ( + IN CONST UINT32 LevelRegOffset, + IN CONST UINT32 GpioNum + ); + +/** + Set the direction of Pcal9555 IO Expander GPIO pin. + + @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander. + @param GpioNum Gpio direction to configure - values 0-7 for Port0 + and 8-15 for Port1. + @param CfgAsInput If TRUE set pin direction as input else set as output. + +**/ +VOID +EFIAPI +PlatformPcal9555GpioSetDir ( + IN CONST UINT32 Pcal9555SlaveAddr, + IN CONST UINT32 GpioNum, + IN CONST BOOLEAN CfgAsInput + ); + +/** + Set the level of Pcal9555 IO Expander GPIO high or low. + + @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander. + @param GpioNum Gpio to change values 0-7 for Port0 and 8-15 + for Port1. + @param HighLevel If TRUE set pin high else set pin low. + +**/ +VOID +EFIAPI +PlatformPcal9555GpioSetLevel ( + IN CONST UINT32 Pcal9555SlaveAddr, + IN CONST UINT32 GpioNum, + IN CONST BOOLEAN HighLevel + ); + +/** + + Enable pull-up/pull-down resistors of Pcal9555 GPIOs. + + @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander. + @param GpioNum Gpio to change values 0-7 for Port0 and 8-15 + for Port1. + +**/ +VOID +EFIAPI +PlatformPcal9555GpioEnablePull ( + IN CONST UINT32 Pcal9555SlaveAddr, + IN CONST UINT32 GpioNum + ); + +/** + + Disable pull-up/pull-down resistors of Pcal9555 GPIOs. + + @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander. + @param GpioNum Gpio to change values 0-7 for Port0 and 8-15 + for Port1. + +**/ +VOID +EFIAPI +PlatformPcal9555GpioDisablePull ( + IN CONST UINT32 Pcal9555SlaveAddr, + IN CONST UINT32 GpioNum + ); + +BOOLEAN +EFIAPI +PlatformPcal9555GpioGetState ( + IN CONST UINT32 Pcal9555SlaveAddr, + IN CONST UINT32 GpioNum + ); + +/** + Init platform LEDs into known state. + + @param PlatformType Executing platform type. + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +PlatformLedInit ( + IN CONST EFI_PLATFORM_TYPE Type + ); + +/** + Turn on or off platform flash update LED. + + @param PlatformType Executing platform type. + @param TurnOn If TRUE turn on else turn off. + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +PlatformFlashUpdateLed ( + IN CONST EFI_PLATFORM_TYPE Type, + IN CONST BOOLEAN TurnOn + ); + +#endif // #ifndef __PLATFORM_HELPER_LIB_H__ diff --git a/Platform/Intel/QuarkPlatformPkg/Include/Library/PlatformPcieHelperLib.h b/Platform/Intel/QuarkPlatformPkg/Include/Library/PlatformPcieHelperLib.h new file mode 100644 index 0000000000..2f848537a0 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Include/Library/PlatformPcieHelperLib.h @@ -0,0 +1,56 @@ +/** @file +PlatformPcieHelperLib function prototype definitions. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PLATFORM_PCIE_HELPER_LIB_H__ +#define __PLATFORM_PCIE_HELPER_LIB_H__ + +#include "Platform.h" + +// +// Function prototypes for routines exported by this library. +// + +/** + Platform assert PCI express PERST# signal. + + @param PlatformType See EFI_PLATFORM_TYPE enum definitions. + +**/ +VOID +EFIAPI +PlatformPERSTAssert ( + IN CONST EFI_PLATFORM_TYPE PlatformType + ); + +/** + Platform de assert PCI express PERST# signal. + + @param PlatformType See EFI_PLATFORM_TYPE enum definitions. + +**/ +VOID +EFIAPI +PlatformPERSTDeAssert ( + IN CONST EFI_PLATFORM_TYPE PlatformType + ); + +/** Early initialisation of the PCIe controller. + + @param PlatformType See EFI_PLATFORM_TYPE enum definitions. + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +PlatformPciExpressEarlyInit ( + IN CONST EFI_PLATFORM_TYPE PlatformType + ); + +#endif // #ifndef __PLATFORM_PCIE_HELPER_LIB_H__ diff --git a/Platform/Intel/QuarkPlatformPkg/Include/Pcal9555.h b/Platform/Intel/QuarkPlatformPkg/Include/Pcal9555.h new file mode 100644 index 0000000000..a9aded7b31 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Include/Pcal9555.h @@ -0,0 +1,24 @@ +/** @file +Definition for Pcal9555 I2c IO Expander. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#ifndef __PCAL9555_H__ +#define __PCAL9555_H__ + +#define PCAL9555_REG_IN_PORT0 0x00 +#define PCAL9555_REG_IN_PORT1 0x01 +#define PCAL9555_REG_OUT_PORT0 0x02 +#define PCAL9555_REG_OUT_PORT1 0x03 +#define PCAL9555_REG_CFG_PORT0 0x06 +#define PCAL9555_REG_CFG_PORT1 0x07 + +#define PCAL9555_REG_PULL_EN_PORT0 0x46 +#define PCAL9555_REG_PULL_EN_PORT1 0x47 + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Include/Platform.h b/Platform/Intel/QuarkPlatformPkg/Include/Platform.h new file mode 100644 index 0000000000..1ffb7f7e4a --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Include/Platform.h @@ -0,0 +1,119 @@ +/** @file +Quark platform specific information. + +Copyright (c) 2013 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ +#include "Uefi.h" + +#ifndef __PLATFORM_H__ +#define __PLATFORM_H__ + +// +// Constant definition +// +#define MAX_SMRAM_RANGES 4 +#define MAX_NODE 1 + +#define QUARK_STAGE1_IMAGE_TYPE_MASK 0xF0 +#define QUARK_STAGE1_BOOT_IMAGE_TYPE 0x00 // Stage1 Boot images 0x00 -> 0x0F. +#define QUARK_STAGE1_RECOVERY_IMAGE_TYPE 0x10 // Stage1 Recovery images 0x10 -> 0x1F. + +#define QUARK_BOOTROM_BASE_ADDRESS 0xFFFE0000 // Base address of Quark ROM in memory map. +#define QUARK_BOOTROM_SIZE_BYTES 0x20000 // Quark ROM is 128KB. +#define SMM_DEFAULT_SMBASE 0x30000 // Default SMBASE address. +#define SMM_DEFAULT_SMBASE_SIZE_BYTES 0x10000 // Size in bytes of default SMRAM. + +// +// Gpio to be used to assert / deassert PCI express PERST# signal. +// +#define PCIEXP_PERST_RESUMEWELL_GPIO 3 + +// +// Minimum time in microseconds for assertion of PERST# signal. +// +#define PCIEXP_PERST_MIN_ASSERT_US 100 + +// +// Microsecond delay post issueing common lane reset. +// +#define PCIEXP_DELAY_US_POST_CMNRESET_RESET 1 + +// +// Microsecond delay to wait for PLL to lock. +// +#define PCIEXP_DELAY_US_WAIT_PLL_LOCK 80 + +// +// Microsecond delay post issueing sideband interface reset. +// +#define PCIEXP_DELAY_US_POST_SBI_RESET 20 + +// +// Microsecond delay post deasserting PERST#. +// +#define PCIEXP_DELAY_US_POST_PERST_DEASSERT 10 + +// +// Catastrophic Trip point in degrees Celsius for this platform. +// +#define PLATFORM_CATASTROPHIC_TRIP_CELSIUS 105 + +// +// Platform flash update LED common definitions. +// +#define PLATFORM_FLASH_UPDATE_LED_TOGGLE_COUNT 7 +#define PLATFORM_FLASH_UPDATE_LED_TOGGLE_DELTA (1000 * 1000) // In Microseconds for EFI_STALL. + +// +// This structure stores the base and size of the ACPI reserved memory used when +// resuming from S3. This region must be allocated by the platform code. +// +typedef struct { + UINT32 AcpiReservedMemoryBase; + UINT32 AcpiReservedMemorySize; + UINT32 SystemMemoryLength; +} RESERVED_ACPI_S3_RANGE; + +#define RESERVED_ACPI_S3_RANGE_OFFSET (EFI_PAGE_SIZE - sizeof (RESERVED_ACPI_S3_RANGE)) + +// +// Define valid platform types. +// First add value before TypePlatformMax in EFI_PLATFORM_TYPE definition +// and then add string description to end of EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION. +// Value shown for supported platforms to help sanity checking with build tools +// and ACPI method usage. +// +typedef enum { + TypeUnknown = 0, // !!! SHOULD BE THE FIRST ENTRY !!! + QuarkEmulation = 1, + ClantonPeakSVP = 2, + KipsBay = 3, + CrossHill = 4, + ClantonHill = 5, + Galileo = 6, + TypePlatformRsv7 = 7, + GalileoGen2 = 8, + TypePlatformMax // !!! SHOULD BE THE LAST ENTRY !!! +} EFI_PLATFORM_TYPE; + +#define EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION \ + L"TypeUnknown",\ + L"QuarkEmulation",\ + L"ClantonPeakSVP",\ + L"KipsBay",\ + L"CrossHill",\ + L"ClantonHill",\ + L"Galileo",\ + L"TypePlatformRsv7",\ + L"GalileoGen2",\ + +typedef struct { + UINT32 EntryOffset; + UINT8 ImageIndex; +} QUARK_EDKII_STAGE1_HEADER; + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Include/PlatformBoards.h b/Platform/Intel/QuarkPlatformPkg/Include/PlatformBoards.h new file mode 100644 index 0000000000..9b0ef88804 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Include/PlatformBoards.h @@ -0,0 +1,166 @@ +/** @file +Board config definitions for each of the boards supported by this platform +package. + +Copyright (c) 2013 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ +#include "Platform.h" + +#ifndef __PLATFORM_BOARDS_H__ +#define __PLATFORM_BOARDS_H__ + +// +// Constant definition +// + +// +// Default resume well TPM reset. +// +#define PLATFORM_RESUMEWELL_TPM_RST_GPIO 5 + +// +// Basic Configs for GPIO table definitions. +// +#define NULL_LEGACY_GPIO_INITIALIZER {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} +#define ALL_INPUT_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x3f,0x00,0x00,0x00,0x00,0x00,0x3f,0x00} +#define QUARK_EMULATION_LEGACY_GPIO_INITIALIZER ALL_INPUT_LEGACY_GPIO_INITIALIZER +#define CLANTON_PEAK_SVP_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x3f,0x00,0x00,0x3f,0x3f,0x00,0x3f,0x00} +#define KIPS_BAY_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x25,0x10,0x00,0x00,0x00,0x00,0x3f,0x00} +#define CROSS_HILL_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x03,0x10,0x00,0x03,0x03,0x00,0x3f,0x00} +#define CLANTON_HILL_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x06,0x10,0x00,0x04,0x04,0x00,0x3f,0x00} +#define GALILEO_LEGACY_GPIO_INITIALIZER {0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x21,0x14,0x00,0x00,0x00,0x00,0x3f,0x00} +#define GALILEO_GEN2_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x1c,0x02,0x00,0x00,0x00,0x00,0x3f,0x00} + +#define NULL_GPIO_CONTROLLER_INITIALIZER {0,0,0,0,0,0,0,0} +#define ALL_INPUT_GPIO_CONTROLLER_INITIALIZER NULL_GPIO_CONTROLLER_INITIALIZER +#define QUARK_EMULATION_GPIO_CONTROLLER_INITIALIZER NULL_GPIO_CONTROLLER_INITIALIZER +#define CLANTON_PEAK_SVP_GPIO_CONTROLLER_INITIALIZER NULL_GPIO_CONTROLLER_INITIALIZER +#define KIPS_BAY_GPIO_CONTROLLER_INITIALIZER {0x05,0x05,0,0,0,0,0,0} +#define CROSS_HILL_GPIO_CONTROLLER_INITIALIZER {0x0D,0x2D,0,0,0,0,0,0} +#define CLANTON_HILL_GPIO_CONTROLLER_INITIALIZER {0x01,0x39,0,0,0,0,0,0} +#define GALILEO_GPIO_CONTROLLER_INITIALIZER {0x05,0x15,0,0,0,0,0,0} +#define GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER {0x05,0x05,0,0,0,0,0,0} + +// +// Legacy Gpio to be used to assert / deassert PCI express PERST# signal +// on Galileo Gen 2 platform. +// +#define GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO 0 + +// +// Io expander slave address. +// + +// +// On Galileo value of Jumper J2 determines slave address of io expander. +// +#define GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO 5 +#define GALILEO_IOEXP_J2HI_7BIT_SLAVE_ADDR 0x20 +#define GALILEO_IOEXP_J2LO_7BIT_SLAVE_ADDR 0x21 + +// +// Three IO Expmanders at fixed addresses on Galileo Gen2. +// +#define GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR 0x25 +#define GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR 0x26 +#define GALILEO_GEN2_IOEXP2_7BIT_SLAVE_ADDR 0x27 + +// +// Led GPIOs for flash update / recovery. +// +#define GALILEO_FLASH_UPDATE_LED_RESUMEWELL_GPIO 1 +#define GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO 5 + +// +// Legacy GPIO config struct for each element in PLATFORM_LEGACY_GPIO_TABLE_DEFINITION. +// +typedef struct { + UINT32 CoreWellEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGEN_CORE_WELL. + UINT32 CoreWellIoSelect; ///< Value for QNC NC Reg R_QNC_GPIO_CGIO_CORE_WELL. + UINT32 CoreWellLvlForInputOrOutput; ///< Value for QNC NC Reg R_QNC_GPIO_CGLVL_CORE_WELL. + UINT32 CoreWellTriggerPositiveEdge; ///< Value for QNC NC Reg R_QNC_GPIO_CGTPE_CORE_WELL. + UINT32 CoreWellTriggerNegativeEdge; ///< Value for QNC NC Reg R_QNC_GPIO_CGTNE_CORE_WELL. + UINT32 CoreWellGPEEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGGPE_CORE_WELL. + UINT32 CoreWellSMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGSMI_CORE_WELL. + UINT32 CoreWellTriggerStatus; ///< Value for QNC NC Reg R_QNC_GPIO_CGTS_CORE_WELL. + UINT32 CoreWellNMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGNMIEN_CORE_WELL. + UINT32 ResumeWellEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGEN_RESUME_WELL. + UINT32 ResumeWellIoSelect; ///< Value for QNC NC Reg R_QNC_GPIO_RGIO_RESUME_WELL. + UINT32 ResumeWellLvlForInputOrOutput;///< Value for QNC NC Reg R_QNC_GPIO_RGLVL_RESUME_WELL. + UINT32 ResumeWellTriggerPositiveEdge;///< Value for QNC NC Reg R_QNC_GPIO_RGTPE_RESUME_WELL. + UINT32 ResumeWellTriggerNegativeEdge;///< Value for QNC NC Reg R_QNC_GPIO_RGTNE_RESUME_WELL. + UINT32 ResumeWellGPEEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGGPE_RESUME_WELL. + UINT32 ResumeWellSMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGSMI_RESUME_WELL. + UINT32 ResumeWellTriggerStatus; ///< Value for QNC NC Reg R_QNC_GPIO_RGTS_RESUME_WELL. + UINT32 ResumeWellNMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGNMIEN_RESUME_WELL. +} BOARD_LEGACY_GPIO_CONFIG; + +// +// GPIO controller config struct for each element in PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION. +// +typedef struct { + UINT32 PortADR; ///< Value for IOH REG GPIO_SWPORTA_DR. + UINT32 PortADir; ///< Value for IOH REG GPIO_SWPORTA_DDR. + UINT32 IntEn; ///< Value for IOH REG GPIO_INTEN. + UINT32 IntMask; ///< Value for IOH REG GPIO_INTMASK. + UINT32 IntType; ///< Value for IOH REG GPIO_INTTYPE_LEVEL. + UINT32 IntPolarity; ///< Value for IOH REG GPIO_INT_POLARITY. + UINT32 Debounce; ///< Value for IOH REG GPIO_DEBOUNCE. + UINT32 LsSync; ///< Value for IOH REG GPIO_LS_SYNC. +} BOARD_GPIO_CONTROLLER_CONFIG; + +/// +/// Table of BOARD_LEGACY_GPIO_CONFIG structures for each board supported +/// by this platform package. +/// Table indexed with EFI_PLATFORM_TYPE enum value. +/// +#define PLATFORM_LEGACY_GPIO_TABLE_DEFINITION \ + /* EFI_PLATFORM_TYPE - TypeUnknown*/\ + NULL_LEGACY_GPIO_INITIALIZER,\ + /* EFI_PLATFORM_TYPE - QuarkEmulation*/\ + QUARK_EMULATION_LEGACY_GPIO_INITIALIZER,\ + /* EFI_PLATFORM_TYPE - ClantonPeakSVP*/\ + CLANTON_PEAK_SVP_LEGACY_GPIO_INITIALIZER,\ + /* EFI_PLATFORM_TYPE - KipsBay*/\ + KIPS_BAY_LEGACY_GPIO_INITIALIZER,\ + /* EFI_PLATFORM_TYPE - CrossHill*/\ + CROSS_HILL_LEGACY_GPIO_INITIALIZER,\ + /* EFI_PLATFORM_TYPE - ClantonHill*/\ + CLANTON_HILL_LEGACY_GPIO_INITIALIZER,\ + /* EFI_PLATFORM_TYPE - Galileo*/\ + GALILEO_LEGACY_GPIO_INITIALIZER,\ + /* EFI_PLATFORM_TYPE - TypePlatformRsv7*/\ + NULL_LEGACY_GPIO_INITIALIZER,\ + /* EFI_PLATFORM_TYPE - GalileoGen2*/\ + GALILEO_GEN2_LEGACY_GPIO_INITIALIZER,\ + +/// +/// Table of BOARD_GPIO_CONTROLLER_CONFIG structures for each board +/// supported by this platform package. +/// Table indexed with EFI_PLATFORM_TYPE enum value. +/// +#define PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION \ + /* EFI_PLATFORM_TYPE - TypeUnknown*/\ + NULL_GPIO_CONTROLLER_INITIALIZER,\ + /* EFI_PLATFORM_TYPE - QuarkEmulation*/\ + QUARK_EMULATION_GPIO_CONTROLLER_INITIALIZER,\ + /* EFI_PLATFORM_TYPE - ClantonPeakSVP*/\ + CLANTON_PEAK_SVP_GPIO_CONTROLLER_INITIALIZER,\ + /* EFI_PLATFORM_TYPE - KipsBay*/\ + KIPS_BAY_GPIO_CONTROLLER_INITIALIZER,\ + /* EFI_PLATFORM_TYPE - CrossHill*/\ + CROSS_HILL_GPIO_CONTROLLER_INITIALIZER,\ + /* EFI_PLATFORM_TYPE - ClantonHill*/\ + CLANTON_HILL_GPIO_CONTROLLER_INITIALIZER,\ + /* EFI_PLATFORM_TYPE - Galileo*/\ + GALILEO_GPIO_CONTROLLER_INITIALIZER,\ + /* EFI_PLATFORM_TYPE - TypePlatformRsv7 */\ + NULL_GPIO_CONTROLLER_INITIALIZER,\ + /* EFI_PLATFORM_TYPE - GalileoGen2*/\ + GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER,\ + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Include/Protocol/GlobalNvsArea.h b/Platform/Intel/QuarkPlatformPkg/Include/Protocol/GlobalNvsArea.h new file mode 100644 index 0000000000..fca6ad7067 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Include/Protocol/GlobalNvsArea.h @@ -0,0 +1,82 @@ +/** @file +Definition of the global NVS area protocol. This protocol +publishes the address and format of a global ACPI NVS buffer +used as a communications buffer between SMM code and ASL code. +The format is derived from the ACPI reference code, version 0.95. +Note: Data structures defined in this protocol are not naturally aligned. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _GLOBAL_NVS_AREA_H_ +#define _GLOBAL_NVS_AREA_H_ + +// +// Forward reference for pure ANSI compatability +// + +typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL EFI_GLOBAL_NVS_AREA_PROTOCOL; + +// +// Global NVS Area Protocol GUID +// +#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \ +{ 0x74e1e48, 0x8132, 0x47a1, {0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc} } + + +// +// Global NVS Area definition +// +#pragma pack (1) +typedef struct { + // + // Miscellaneous Dynamic Values + // + UINT32 OperatingSystemType; // Os type indicator + UINT32 Cfgd; // System configuration description + UINT32 HpetEnable; + + UINT32 Pm1blkIoBaseAddress; + UINT32 PmbaIoBaseAddress; + UINT32 Gpe0blkIoBaseAddress; + UINT32 GbaIoBaseAddress; + + UINT32 SmbaIoBaseAddress; + UINT32 Reserved1; + UINT32 WdtbaIoBaseAddress; + + UINT32 HpetBaseAddress; + UINT32 HpetSize; + UINT32 PciExpressBaseAddress; + UINT32 PciExpressSize; + + UINT32 RcbaMmioBaseAddress; + UINT32 RcbaMmioSize; + UINT32 IoApicBaseAddress; + UINT32 IoApicSize; + + UINT32 TpmPresent; + UINT32 DBG2Present; + UINT32 PlatformType; // Set to one of EFI_PLATFORM_TYPE enums. + UINT32 AlternateSla; // If TRUE use alternate I2C Slave addresses. + + UINT8 Reserved[512 - 4 * 22]; // Total 512 Bytes +} EFI_GLOBAL_NVS_AREA; +#pragma pack () + +// +// Global NVS Area Protocol +// +struct _EFI_GLOBAL_NVS_AREA_PROTOCOL { + EFI_GLOBAL_NVS_AREA *Area; +}; + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid; + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Include/Protocol/PlatformSmmSpiReady.h b/Platform/Intel/QuarkPlatformPkg/Include/Protocol/PlatformSmmSpiReady.h new file mode 100644 index 0000000000..5913e4467b --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Include/Protocol/PlatformSmmSpiReady.h @@ -0,0 +1,23 @@ +/** @file +This protocol indicates that the platform SPI interface is ready for use. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#ifndef _PLATFORM_SPI_READY_H_ +#define _PLATFORM_SPI_READY_H_ + +// {7A5DBC75-5B2B-4e67-BDE1-D48EEE761562} +#define EFI_SMM_SPI_READY_PROTOCOL_GUID \ + { 0x7a5dbc75, 0x5b2b, 0x4e67, 0xbd, 0xe1, 0xd4, 0x8e, 0xee, 0x76, 0x15, 0x62 } + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiSmmSpiReadyProtocolGuid; + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c b/Platform/Intel/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c new file mode 100644 index 0000000000..c00284c262 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c @@ -0,0 +1,472 @@ +/** @file +This file include all platform action which can be customized +by IBV/OEM. + +Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PlatformBootManager.h" + +/** + Return the index of the load option in the load option array. + + The function consider two load options are equal when the + OptionType, Attributes, Description, FilePath and OptionalData are equal. + + @param Key Pointer to the load option to be found. + @param Array Pointer to the array of load options to be found. + @param Count Number of entries in the Array. + + @retval -1 Key wasn't found in the Array. + @retval 0 ~ Count-1 The index of the Key in the Array. +**/ +INTN +PlatformFindLoadOption ( + IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Key, + IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Array, + IN UINTN Count + ) +{ + UINTN Index; + + for (Index = 0; Index < Count; Index++) { + if ((Key->OptionType == Array[Index].OptionType) && + (Key->Attributes == Array[Index].Attributes) && + (StrCmp (Key->Description, Array[Index].Description) == 0) && + (CompareMem (Key->FilePath, Array[Index].FilePath, GetDevicePathSize (Key->FilePath)) == 0) && + (Key->OptionalDataSize == Array[Index].OptionalDataSize) && + (CompareMem (Key->OptionalData, Array[Index].OptionalData, Key->OptionalDataSize) == 0)) { + return (INTN) Index; + } + } + + return -1; +} + +VOID +PlatformRegisterFvBootOption ( + EFI_GUID *FileGuid, + CHAR16 *Description, + UINT32 Attributes + ) +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN HandleCount; + UINTN IndexFv; + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv; + CHAR16 *UiSection; + UINTN UiSectionLength; + UINT32 AuthenticationStatus; + EFI_HANDLE FvHandle; + MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions; + UINTN BootOptionCount; + UINTN OptionIndex; + EFI_BOOT_MANAGER_LOAD_OPTION NewOption; + + // + // Locate all available FVs. + // + HandleBuffer = NULL; + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiFirmwareVolume2ProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + return; + } + + // + // Go through FVs one by one to find the required FFS file + // + for (IndexFv = 0, FvHandle = NULL; IndexFv < HandleCount && FvHandle == NULL; IndexFv++) { + Status = gBS->HandleProtocol ( + HandleBuffer[IndexFv], + &gEfiFirmwareVolume2ProtocolGuid, + (VOID **)&Fv + ); + if (EFI_ERROR (Status)) { + continue; + } + + // + // Attempt to read a EFI_SECTION_USER_INTERFACE section from the required FFS file + // + UiSection = NULL; + Status = Fv->ReadSection ( + Fv, + FileGuid, + EFI_SECTION_USER_INTERFACE, + 0, + (VOID **) &UiSection, + &UiSectionLength, + &AuthenticationStatus + ); + if (EFI_ERROR (Status)) { + continue; + } + FreePool (UiSection); + + // + // Save the handle of the FV where the FFS file was found + // + FvHandle = HandleBuffer[IndexFv]; + } + + // + // Free the buffer of FV handles + // + FreePool (HandleBuffer); + + // + // If the FFS file was not found, then return + // + if (FvHandle == NULL) { + return; + } + + // + // Create a device path for the FFS file that was found + // + EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid); + DevicePath = AppendDevicePathNode ( + DevicePathFromHandle (FvHandle), + (EFI_DEVICE_PATH_PROTOCOL *) &FileNode + ); + + // + // Create and add a new load option for the FFS file that was found + // + Status = EfiBootManagerInitializeLoadOption ( + &NewOption, + LoadOptionNumberUnassigned, + LoadOptionTypeBoot, + Attributes, + Description, + DevicePath, + NULL, + 0 + ); + if (!EFI_ERROR (Status)) { + BootOptions = EfiBootManagerGetLoadOptions (&BootOptionCount, LoadOptionTypeBoot); + + OptionIndex = PlatformFindLoadOption (&NewOption, BootOptions, BootOptionCount); + + if (OptionIndex == -1) { + Status = EfiBootManagerAddLoadOptionVariable (&NewOption, (UINTN) -1); + ASSERT_EFI_ERROR (Status); + } + EfiBootManagerFreeLoadOption (&NewOption); + EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount); + } +} + +VOID +EFIAPI +InternalBdsEmptyCallbackFuntion ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + return; +} + +/** + Do the platform specific action before the console is connected. + + Such as: + Update console variable; + Register new Driver#### or Boot####; + Signal ReadyToLock event. +**/ +VOID +EFIAPI +PlatformBootManagerBeforeConsole ( + VOID + ) +{ + EFI_STATUS Status; + UINTN Index; + EFI_INPUT_KEY Enter; + EFI_INPUT_KEY F2; + EFI_BOOT_MANAGER_LOAD_OPTION BootOption; + ESRT_MANAGEMENT_PROTOCOL *EsrtManagement; + EFI_BOOT_MODE BootMode; + EFI_ACPI_S3_SAVE_PROTOCOL *AcpiS3Save; + EFI_HANDLE Handle; + EFI_EVENT EndOfDxeEvent; + + // + // Update the console variables. + // + for (Index = 0; gPlatformConsole[Index].DevicePath != NULL; Index++) { + if ((gPlatformConsole[Index].ConnectType & CONSOLE_IN) == CONSOLE_IN) { + EfiBootManagerUpdateConsoleVariable (ConIn, gPlatformConsole[Index].DevicePath, NULL); + } + + if ((gPlatformConsole[Index].ConnectType & CONSOLE_OUT) == CONSOLE_OUT) { + EfiBootManagerUpdateConsoleVariable (ConOut, gPlatformConsole[Index].DevicePath, NULL); + } + + if ((gPlatformConsole[Index].ConnectType & STD_ERROR) == STD_ERROR) { + EfiBootManagerUpdateConsoleVariable (ErrOut, gPlatformConsole[Index].DevicePath, NULL); + } + } + + // + // Register ENTER as CONTINUE key + // + Enter.ScanCode = SCAN_NULL; + Enter.UnicodeChar = CHAR_CARRIAGE_RETURN; + EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL); + + // + // Map F2 to Boot Manager Menu + // + F2.ScanCode = SCAN_F2; + F2.UnicodeChar = CHAR_NULL; + EfiBootManagerGetBootManagerMenu (&BootOption); + EfiBootManagerAddKeyOptionVariable (NULL, (UINT16) BootOption.OptionNumber, 0, &F2, NULL); + + // + // Register UEFI Shell + // + PlatformRegisterFvBootOption (&gUefiShellFileGuid, L"UEFI Shell", LOAD_OPTION_ACTIVE); + + Status = gBS->LocateProtocol(&gEsrtManagementProtocolGuid, NULL, (VOID **)&EsrtManagement); + if (EFI_ERROR(Status)) { + EsrtManagement = NULL; + } + + BootMode = GetBootModeHob(); + switch (BootMode) { + case BOOT_ON_FLASH_UPDATE: + DEBUG((DEBUG_INFO, "ProcessCapsules Before EndOfDxe ......\n")); + Status = ProcessCapsules (); + DEBUG((DEBUG_INFO, "ProcessCapsules %r\n", Status)); + break; + case BOOT_IN_RECOVERY_MODE: + break; + case BOOT_ASSUMING_NO_CONFIGURATION_CHANGES: + case BOOT_WITH_MINIMAL_CONFIGURATION: + case BOOT_ON_S4_RESUME: + if (EsrtManagement != NULL) { + // + // Lock ESRT cache repository before EndofDxe if ESRT sync is not needed + // + EsrtManagement->LockEsrtRepository(); + } + break; + default: + // + // Require to sync ESRT from FMP in a new boot + // + if (EsrtManagement != NULL) { + EsrtManagement->SyncEsrtFmp(); + } + break; + } + + // + // Prepare for S3 + // + Status = gBS->LocateProtocol (&gEfiAcpiS3SaveProtocolGuid, NULL, (VOID **)&AcpiS3Save); + if (!EFI_ERROR (Status)) { + AcpiS3Save->S3Save (AcpiS3Save, NULL); + } + + // + // Inform PI SMM drivers that BDS may run 3rd party code + // Create and signal End of DXE event group + // + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + InternalBdsEmptyCallbackFuntion, + NULL, + &gEfiEndOfDxeEventGroupGuid, + &EndOfDxeEvent + ); + ASSERT_EFI_ERROR (Status); + gBS->SignalEvent (EndOfDxeEvent); + gBS->CloseEvent (EndOfDxeEvent); + + DEBUG((EFI_D_INFO,"All EndOfDxe callbacks have returned successfully\n")); + + // + // Install SMM Ready To Lock protocol so all resources can be locked down + // before BDS runs 3rd party code. This action must be done last so all + // other SMM driver signals are processed before this final lock down action. + // + Handle = NULL; + Status = gBS->InstallProtocolInterface ( + &Handle, + &gEfiDxeSmmReadyToLockProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + ASSERT_EFI_ERROR (Status); + + // + // Dispatch deferred images after EndOfDxe event and ReadyToLock installation. + // + EfiBootManagerDispatchDeferredImages (); +} + +/** + Do the platform specific action after the console is connected. + + Such as: + Dynamically switch output mode; + Signal console ready platform customized event; + Run diagnostics like memory testing; + Connect certain devices; + Dispatch additional option ROMs +**/ +VOID +EFIAPI +PlatformBootManagerAfterConsole ( + VOID + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + ESRT_MANAGEMENT_PROTOCOL *EsrtManagement; + VOID *Buffer; + UINTN Size; + + Status = gBS->LocateProtocol(&gEsrtManagementProtocolGuid, NULL, (VOID **)&EsrtManagement); + if (EFI_ERROR(Status)) { + EsrtManagement = NULL; + } + + BootMode = GetBootModeHob(); + + DEBUG((DEBUG_INFO, "PlatformBootManagerAfterConsole(): BootMode = %02x\n", BootMode)); + + switch (BootMode) { + case BOOT_ASSUMING_NO_CONFIGURATION_CHANGES: + case BOOT_WITH_MINIMAL_CONFIGURATION: + case BOOT_ON_S4_RESUME: + EfiBootManagerRefreshAllBootOption (); + break; + + case BOOT_ON_FLASH_UPDATE: + if (FeaturePcdGet(PcdSupportUpdateCapsuleReset)) { + EfiBootManagerConnectAll (); + EfiBootManagerRefreshAllBootOption (); + + // + // Always sync ESRT Cache from FMP Instances after connect all and before capsule process + // + if (EsrtManagement != NULL) { + EsrtManagement->SyncEsrtFmp(); + } + + DEBUG((DEBUG_INFO, "ProcessCapsules After ConnectAll ......\n")); + Status = ProcessCapsules(); + DEBUG((DEBUG_INFO, "ProcessCapsules %r\n", Status)); + } + break; + + default: + EfiBootManagerConnectAll (); + EfiBootManagerRefreshAllBootOption (); + + // + // Sync ESRT Cache from FMP Instance on demand after Connect All + // + if (EsrtManagement != NULL) { + EsrtManagement->SyncEsrtFmp(); + } + break; + } + + Print ( + L"\n" + L"F2 to enter Boot Manager Menu.\n" + L"ENTER to boot directly.\n" + L"\n" + ); + + // + // Check if the platform is using test key. + // + Status = GetSectionFromAnyFv( + PcdGetPtr(PcdEdkiiRsa2048Sha256TestPublicKeyFileGuid), + EFI_SECTION_RAW, + 0, + &Buffer, + &Size + ); + if (!EFI_ERROR(Status)) { + if ((Size == PcdGetSize(PcdRsa2048Sha256PublicKeyBuffer)) && + (CompareMem(Buffer, PcdGetPtr(PcdRsa2048Sha256PublicKeyBuffer), Size) == 0)) { + Print(L"WARNING: Recovery Test Key is used.\n"); + PcdSetBoolS(PcdTestKeyUsed, TRUE); + } + FreePool(Buffer); + } + Status = GetSectionFromAnyFv( + PcdGetPtr(PcdEdkiiPkcs7TestPublicKeyFileGuid), + EFI_SECTION_RAW, + 0, + &Buffer, + &Size + ); + if (!EFI_ERROR(Status)) { + if ((Size == PcdGetSize(PcdPkcs7CertBuffer)) && + (CompareMem(Buffer, PcdGetPtr(PcdPkcs7CertBuffer), Size) == 0)) { + Print(L"WARNING: Capsule Test Key is used.\n"); + PcdSetBoolS(PcdTestKeyUsed, TRUE); + } + FreePool(Buffer); + } + + // + // Use a DynamicHii type pcd to save the boot status, which is used to + // control configuration mode, such as FULL/MINIMAL/NO_CHANGES configuration. + // + if (PcdGetBool(PcdBootState)) { + Status = PcdSetBoolS (PcdBootState, FALSE); + ASSERT_EFI_ERROR (Status); + } +} + +/** + This function is called each second during the boot manager waits the timeout. + + @param TimeoutRemain The remaining timeout. +**/ +VOID +EFIAPI +PlatformBootManagerWaitCallback ( + UINT16 TimeoutRemain + ) +{ + Print (L"\r%-2d seconds remained...", TimeoutRemain); +} + +/** + The function is called when no boot option could be launched, + including platform recovery options and options pointing to applications + built into firmware volumes. + + If this function returns, BDS attempts to enter an infinite loop. +**/ +VOID +EFIAPI +PlatformBootManagerUnableToBoot ( + VOID + ) +{ + return; +} + diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h b/Platform/Intel/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h new file mode 100644 index 0000000000..bd4f224783 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h @@ -0,0 +1,49 @@ +/** @file +Head file for BDS Platform specific code + +Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_BOOT_MANAGER_H +#define _PLATFORM_BOOT_MANAGER_H + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + UINTN ConnectType; +} PLATFORM_CONSOLE_CONNECT_ENTRY; + +extern PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[]; + +#define CONSOLE_OUT BIT0 +#define CONSOLE_IN BIT1 +#define STD_ERROR BIT2 + +#endif // _PLATFORM_BOOT_MANAGER_H diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/Platform/Intel/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf new file mode 100644 index 0000000000..d58c243357 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf @@ -0,0 +1,83 @@ +## @file +# Include all platform action which can be customized by IBV/OEM. +# +# Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformBootManagerLib + FILE_GUID = EC67889B-9E62-4c81-8CA0-86E6A6EEE61A + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformBootManagerLib|DXE_DRIVER + CONSTRUCTOR = InitializePlatformBootManagerLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 EBC +# + +[Sources] + PlatformData.c + PlatformBootManager.c + PlatformBootManager.h + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFrameworkPkg/IntelFrameworkPkg.dec + IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec + SourceLevelDebugPkg/SourceLevelDebugPkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + SecurityPkg/SecurityPkg.dec + ShellPkg/ShellPkg.dec + SignedCapsulePkg/SignedCapsulePkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + PcdLib + DebugLib + DevicePathLib + MemoryAllocationLib + UefiBootServicesTableLib + UefiLib + UefiBootManagerLib + PrintLib + HobLib + CapsuleLib + DxeServicesLib + +[Protocols] + gEfiFirmwareVolume2ProtocolGuid + gEfiAcpiS3SaveProtocolGuid + gEfiDxeSmmReadyToLockProtocolGuid + gEsrtManagementProtocolGuid + +[Guids] + gEfiPcAnsiGuid + gEfiVT100Guid + gEfiVT100PlusGuid + gEfiVTUTF8Guid + gEfiTtyTermGuid + gEfiEndOfDxeEventGroupGuid + gUefiShellFileGuid + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState + gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiRsa2048Sha256TestPublicKeyFileGuid + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiPkcs7TestPublicKeyFileGuid + gEfiSecurityPkgTokenSpaceGuid.PcdRsa2048Sha256PublicKeyBuffer + gEfiSecurityPkgTokenSpaceGuid.PcdPkcs7CertBuffer + gEfiMdeModulePkgTokenSpaceGuid.PcdTestKeyUsed + diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformData.c b/Platform/Intel/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformData.c new file mode 100644 index 0000000000..a62fc34ead --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformData.c @@ -0,0 +1,275 @@ +/** @file +Defined the platform specific device path which will be filled to +ConIn/ConOut variables. + +Copyright (c) 2015, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PlatformBootManager.h" + +/// +/// the short form device path for Usb keyboard +/// +#define CLASS_HID 3 +#define SUBCLASS_BOOT 1 +#define PROTOCOL_KEYBOARD 1 + +/// +/// PcdDefaultTerminalType values +/// +#define PCANSITYPE 0 +#define VT100TYPE 1 +#define VT100PLUSTYPE 2 +#define VTUTF8TYPE 3 +#define TTYTERMTYPE 4 + +// +// Below is the platform console device path +// +typedef struct { + ACPI_HID_DEVICE_PATH PciRootBridge; + PCI_DEVICE_PATH PciUart; + UART_DEVICE_PATH Uart; + VENDOR_DEVICE_PATH TerminalType; + EFI_DEVICE_PATH_PROTOCOL End; +} PCI_UART_DEVICE_PATH; + +typedef struct { + VENDOR_DEVICE_PATH VendorHardware; + UART_DEVICE_PATH Uart; + VENDOR_DEVICE_PATH TerminalType; + EFI_DEVICE_PATH_PROTOCOL End; +} VENDOR_UART_DEVICE_PATH; + +typedef struct { + USB_CLASS_DEVICE_PATH UsbClass; + EFI_DEVICE_PATH_PROTOCOL End; +} USB_CLASS_FORMAT_DEVICE_PATH; + +#define PNPID_DEVICE_PATH_NODE(PnpId) \ + { \ + { \ + ACPI_DEVICE_PATH, \ + ACPI_DP, \ + { \ + (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \ + (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \ + } \ + }, \ + EISA_PNP_ID((PnpId)), \ + 0 \ + } + +#define PCI_DEVICE_PATH_NODE(Func, Dev) \ + { \ + { \ + HARDWARE_DEVICE_PATH, \ + HW_PCI_DP, \ + { \ + (UINT8) (sizeof (PCI_DEVICE_PATH)), \ + (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \ + }, \ + }, \ + (Func), \ + (Dev) \ + } + +#define gEndEntire \ + { \ + END_DEVICE_PATH_TYPE, \ + END_ENTIRE_DEVICE_PATH_SUBTYPE, \ + { \ + END_DEVICE_PATH_LENGTH, \ + 0 \ + } \ + } + +// +// Platform specific serial device path +// +PCI_UART_DEVICE_PATH gPciUartDevicePath0 = { + PNPID_DEVICE_PATH_NODE(0x0A03), + PCI_DEVICE_PATH_NODE(1, 20), + { + { + MESSAGING_DEVICE_PATH, + MSG_UART_DP, + { + (UINT8)(sizeof (UART_DEVICE_PATH)), + (UINT8)((sizeof (UART_DEVICE_PATH)) >> 8) + } + }, + 0, // Reserved + 921600, // BaudRate + 8, // DataBits + 1, // Parity + 1 // StopBits + }, + { + { + MESSAGING_DEVICE_PATH, + MSG_VENDOR_DP, + { + (UINT8)(sizeof (VENDOR_DEVICE_PATH)), + (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8) + }, + }, + DEVICE_PATH_MESSAGING_PC_ANSI + }, + gEndEntire +}; + +PCI_UART_DEVICE_PATH gPciUartDevicePath1 = { + PNPID_DEVICE_PATH_NODE(0x0A03), + PCI_DEVICE_PATH_NODE(5, 20), + { + { + MESSAGING_DEVICE_PATH, + MSG_UART_DP, + { + (UINT8)(sizeof (UART_DEVICE_PATH)), + (UINT8)((sizeof (UART_DEVICE_PATH)) >> 8) + } + }, + 0, // Reserved + 921600, // BaudRate + 8, // DataBits + 1, // Parity + 1 // StopBits + }, + { + { + MESSAGING_DEVICE_PATH, + MSG_VENDOR_DP, + { + (UINT8)(sizeof (VENDOR_DEVICE_PATH)), + (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8) + } + }, + DEVICE_PATH_MESSAGING_PC_ANSI + }, + gEndEntire +}; + +VENDOR_UART_DEVICE_PATH gDebugAgentUartDevicePath = { + { + { + HARDWARE_DEVICE_PATH, + HW_VENDOR_DP, + { + (UINT8) (sizeof (VENDOR_DEVICE_PATH)), + (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) + } + }, + EFI_DEBUG_AGENT_GUID, + }, + { + { + MESSAGING_DEVICE_PATH, + MSG_UART_DP, + { + (UINT8) (sizeof (UART_DEVICE_PATH)), + (UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8) + } + }, + 0, // Reserved + 0, // BaudRate - Default + 0, // DataBits - Default + 0, // Parity - Default + 0, // StopBits - Default + }, + { + { + MESSAGING_DEVICE_PATH, + MSG_VENDOR_DP, + { + (UINT8)(sizeof (VENDOR_DEVICE_PATH)), + (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8) + } + }, + DEVICE_PATH_MESSAGING_PC_ANSI + }, + gEndEntire +}; + +USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath = { + { + { + MESSAGING_DEVICE_PATH, + MSG_USB_CLASS_DP, + { + (UINT8)(sizeof (USB_CLASS_DEVICE_PATH)), + (UINT8)((sizeof (USB_CLASS_DEVICE_PATH)) >> 8) + } + }, + 0xffff, // VendorId - Match any vendor + 0xffff, // ProductId - Match any product + CLASS_HID, // DeviceClass + SUBCLASS_BOOT, // DeviceSubClass + PROTOCOL_KEYBOARD // DeviceProtocol + }, + gEndEntire +}; + +// +// Predefined platform default console device path +// +PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[] = { + { (EFI_DEVICE_PATH_PROTOCOL *) &gPciUartDevicePath0, (CONSOLE_OUT | CONSOLE_IN) }, + { (EFI_DEVICE_PATH_PROTOCOL *) &gPciUartDevicePath1, (CONSOLE_OUT | CONSOLE_IN) }, + { (EFI_DEVICE_PATH_PROTOCOL *) &gDebugAgentUartDevicePath, (CONSOLE_OUT | CONSOLE_IN) }, + { (EFI_DEVICE_PATH_PROTOCOL *) &gUsbClassKeyboardDevicePath, (CONSOLE_IN) }, + { NULL, 0 } +}; + +EFI_STATUS +EFIAPI +InitializePlatformBootManagerLib ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_GUID *TerminalTypeGuid; + + // + // Update UART device path nodes based on UART PCD settings + // + gPciUartDevicePath0.Uart.BaudRate = PcdGet64 (PcdUartDefaultBaudRate); + gPciUartDevicePath0.Uart.DataBits = PcdGet8 (PcdUartDefaultDataBits); + gPciUartDevicePath0.Uart.Parity = PcdGet8 (PcdUartDefaultParity); + gPciUartDevicePath0.Uart.StopBits = PcdGet8 (PcdUartDefaultStopBits); + gPciUartDevicePath1.Uart.BaudRate = PcdGet64 (PcdUartDefaultBaudRate); + gPciUartDevicePath1.Uart.DataBits = PcdGet8 (PcdUartDefaultDataBits); + gPciUartDevicePath1.Uart.Parity = PcdGet8 (PcdUartDefaultParity); + gPciUartDevicePath1.Uart.StopBits = PcdGet8 (PcdUartDefaultStopBits); + + // + // Update Vendor device path nodes based on terminal type PCD settings + // + switch (PcdGet8 (PcdDefaultTerminalType)) { + case PCANSITYPE: + TerminalTypeGuid = &gEfiPcAnsiGuid; + break; + case VT100TYPE: + TerminalTypeGuid = &gEfiVT100Guid; + break; + case VT100PLUSTYPE: + TerminalTypeGuid = &gEfiVT100PlusGuid; + break; + case VTUTF8TYPE: + TerminalTypeGuid = &gEfiVTUTF8Guid; + break; + case TTYTERMTYPE: + TerminalTypeGuid = &gEfiTtyTermGuid; + break; + default: + TerminalTypeGuid = &gEfiPcAnsiGuid; + break; + } + CopyGuid (&gPciUartDevicePath0.TerminalType.Guid, TerminalTypeGuid); + CopyGuid (&gPciUartDevicePath1.TerminalType.Guid, TerminalTypeGuid); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/CommonHeader.h b/Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/CommonHeader.h new file mode 100644 index 0000000000..8016309f57 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/CommonHeader.h @@ -0,0 +1,51 @@ +/** @file +Common header file shared by all source files in this component. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __COMMON_HEADER_H_ +#define __COMMON_HEADER_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +// +// Routines shared between souce modules in this component. +// + +EFI_STATUS +WriteFirstFreeSpiProtect ( + IN CONST UINT32 PchRootComplexBar, + IN CONST UINT32 DirectValue, + IN CONST UINT32 BaseAddress, + IN CONST UINT32 Length, + OUT UINT32 *OffsetPtr + ); + +VOID +Pcal9555SetPortRegBit ( + IN CONST UINT32 Pcal9555SlaveAddr, + IN CONST UINT32 GpioNum, + IN CONST UINT8 RegBase, + IN CONST BOOLEAN LogicOne + ); + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/DxePlatformHelperLib.inf b/Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/DxePlatformHelperLib.inf new file mode 100644 index 0000000000..6272b33cfd --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/DxePlatformHelperLib.inf @@ -0,0 +1,70 @@ +## @file +# Library producing helper routines for this platform. +# +# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = DxePlatformHelperLib + FILE_GUID = 02805010-2591-4ed3-827B-A218F34AE0D7 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformHelperLib|DXE_DRIVER DXE_RUNTIME_DRIVER SMM_CORE DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 +# + +[Sources] + PlatformHelperLib.c + PlatformHelperDxe.c + PlatformLeds.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + QuarkSocPkg/QuarkSocPkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + +[LibraryClasses] + BaseLib + PcdLib + BaseMemoryLib + SerialPortLib + S3BootScriptLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + DxeServicesLib + HobLib + IntelQNCLib + I2cLib + +[Protocols] + gEfiSpiProtocolGuid + gEfiSmmSpiProtocolGuid + gEfiSmmBase2ProtocolGuid + gEdkiiVariableLockProtocolGuid ## CONSUMES + +[Guids] + gEfiGlobalVariableGuid + gEfiImageSecurityDatabaseGuid + gEfiQuarkCapsuleGuid + gQuarkVariableLockGuid ## CONSUMES + gEfiMemoryConfigDataGuid ## CONSUMES + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress + gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoveryBase + gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoverySize + gQuarkPlatformTokenSpaceGuid.PcdPkX509File + gQuarkPlatformTokenSpaceGuid.PcdKekX509File + gQuarkPlatformTokenSpaceGuid.PcdKekRsa2048File + gQuarkPlatformTokenSpaceGuid.PcdSpiFlashDeviceSize diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/PeiPlatformHelperLib.inf b/Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/PeiPlatformHelperLib.inf new file mode 100644 index 0000000000..0c78f9b3d2 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/PeiPlatformHelperLib.inf @@ -0,0 +1,45 @@ +## @file +# Library producing helper routines for this platform. +# +# Copyright (c) 2013-2015 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiPlatformHelperLib + FILE_GUID = 024D3127-7B60-48f4-A6FE-726E19CD4CEB + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformHelperLib|PEIM PEI_CORE SEC + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 +# + +[Sources] + PlatformHelperLib.c + PlatformHelperPei.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + QuarkSocPkg/QuarkSocPkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + +[LibraryClasses] + BaseLib + PcdLib + BaseMemoryLib + PeiServicesTablePointerLib + PeiServicesLib + SerialPortLib + QNCAccessLib + I2cLib + +[Pcd] + gQuarkPlatformTokenSpaceGuid.PcdEsramStage1Base diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperDxe.c b/Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperDxe.c new file mode 100644 index 0000000000..a0acf88c2b --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperDxe.c @@ -0,0 +1,337 @@ +/** @file +Implementation of helper routines for DXE environment. + +Copyright (c) 2013 - 2016 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "CommonHeader.h" + +#define FLASH_BLOCK_SIZE SIZE_4KB + +// +// Global variables. +// +EFI_SPI_PROTOCOL *mPlatHelpSpiProtocolRef = NULL; + +// +// Routines defined in other source modules of this component. +// + +// +// Routines local to this component. +// + +// +// Routines shared with other souce modules in this component. +// + +EFI_SPI_PROTOCOL * +LocateSpiProtocol ( + IN EFI_SMM_SYSTEM_TABLE2 *Smst + ) +{ + if (mPlatHelpSpiProtocolRef == NULL) { + if (Smst != NULL) { + Smst->SmmLocateProtocol ( + &gEfiSmmSpiProtocolGuid, + NULL, + (VOID **) &mPlatHelpSpiProtocolRef + ); + } else { + gBS->LocateProtocol ( + &gEfiSpiProtocolGuid, + NULL, + (VOID **) &mPlatHelpSpiProtocolRef + ); + } + ASSERT (mPlatHelpSpiProtocolRef != NULL); + } + return mPlatHelpSpiProtocolRef; +} + +// +// Routines exported by this source module. +// + +/** + Find pointer to RAW data in Firmware volume file. + + @param FvNameGuid Firmware volume to search. If == NULL search all. + @param FileNameGuid Firmware volume file to search for. + @param SectionData Pointer to RAW data section of found file. + @param SectionDataSize Pointer to UNITN to get size of RAW data. + + @retval EFI_SUCCESS Raw Data found. + @retval EFI_INVALID_PARAMETER FileNameGuid == NULL. + @retval EFI_NOT_FOUND Firmware volume file not found. + @retval EFI_UNSUPPORTED Unsupported in current enviroment (PEI or DXE). + +**/ +EFI_STATUS +EFIAPI +PlatformFindFvFileRawDataSection ( + IN CONST EFI_GUID *FvNameGuid OPTIONAL, + IN CONST EFI_GUID *FileNameGuid, + OUT VOID **SectionData, + OUT UINTN *SectionDataSize + ) +{ + if (FileNameGuid == NULL || SectionData == NULL || SectionDataSize == NULL) { + return EFI_INVALID_PARAMETER; + } + if (FvNameGuid != NULL) { + return EFI_UNSUPPORTED; // Searching in specific FV unsupported in DXE. + } + + return GetSectionFromAnyFv (FileNameGuid, EFI_SECTION_RAW, 0, SectionData, SectionDataSize); +} + +/** + Find free spi protect register and write to it to protect a flash region. + + @param DirectValue Value to directly write to register. + if DirectValue == 0 the use Base & Length below. + @param BaseAddress Base address of region in Flash Memory Map. + @param Length Length of region to protect. + + @retval EFI_SUCCESS Free spi protect register found & written. + @retval EFI_NOT_FOUND Free Spi protect register not found. + @retval EFI_DEVICE_ERROR Unable to write to spi protect register. +**/ +EFI_STATUS +EFIAPI +PlatformWriteFirstFreeSpiProtect ( + IN CONST UINT32 DirectValue, + IN CONST UINT32 BaseAddress, + IN CONST UINT32 Length + ) +{ + UINT32 FreeOffset; + UINT32 PchRootComplexBar; + EFI_STATUS Status; + + PchRootComplexBar = QNC_RCRB_BASE; + + Status = WriteFirstFreeSpiProtect ( + PchRootComplexBar, + DirectValue, + BaseAddress, + Length, + &FreeOffset + ); + + if (!EFI_ERROR (Status)) { + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint32, + (UINTN) (PchRootComplexBar + FreeOffset), + 1, + (VOID *) (UINTN) (PchRootComplexBar + FreeOffset) + ); + } + + return Status; +} + +/** + Lock legacy SPI static configuration information. + + Function will assert if unable to lock config. + +**/ +VOID +EFIAPI +PlatformFlashLockConfig ( + VOID + ) +{ + EFI_STATUS Status; + EFI_SPI_PROTOCOL *SpiProtocol; + + // + // Enable lock of legacy SPI static configuration information. + // + + SpiProtocol = LocateSpiProtocol (NULL); // This routine will not be called in SMM. + ASSERT (SpiProtocol != NULL); + if (SpiProtocol != NULL) { + Status = SpiProtocol->Lock (SpiProtocol); + + if (!EFI_ERROR (Status)) { + DEBUG ((EFI_D_INFO, "Platform: Spi Config Locked Down\n")); + } else if (Status == EFI_ACCESS_DENIED) { + DEBUG ((EFI_D_INFO, "Platform: Spi Config already locked down\n")); + } else { + ASSERT_EFI_ERROR (Status); + } + } +} + +/** + Platform Variable Lock. + + @retval EFI_SUCCESS Platform Variable Lock successful. + @retval EFI_NOT_FOUND No protocol instances were found that match Protocol and + Registration. + +**/ +VOID +EFIAPI +PlatformVariableLock ( + ) +{ + EFI_STATUS Status; + EDKII_VARIABLE_LOCK_PROTOCOL *VariableLockProtocol; + + Status = gBS->LocateProtocol (&gEdkiiVariableLockProtocolGuid, NULL, (VOID **)&VariableLockProtocol); + ASSERT_EFI_ERROR (Status); + + Status = VariableLockProtocol->RequestToLock ( + VariableLockProtocol, + QUARK_VARIABLE_LOCK_NAME, + &gQuarkVariableLockGuid + ); + ASSERT_EFI_ERROR (Status); + + // Memory Config Data shouldn't be writable when Quark Variable Lock is enabled. + Status = VariableLockProtocol->RequestToLock ( + VariableLockProtocol, + EFI_MEMORY_CONFIG_DATA_NAME, + &gEfiMemoryConfigDataGuid + ); + ASSERT_EFI_ERROR (Status); +} + +/** + Lock regions and config of SPI flash given the policy for this platform. + + Function will assert if unable to lock regions or config. + + @param PreBootPolicy If TRUE do Pre Boot Flash Lock Policy. + +**/ +VOID +EFIAPI +PlatformFlashLockPolicy ( + IN CONST BOOLEAN PreBootPolicy + ) +{ + EFI_STATUS Status; + UINT64 CpuAddressNvStorage; + UINT64 CpuAddressFlashDevice; + UINT64 SpiAddress; + EFI_BOOT_MODE BootMode; + UINTN SpiFlashDeviceSize; + + BootMode = GetBootModeHob (); + + SpiFlashDeviceSize = (UINTN) PcdGet32 (PcdSpiFlashDeviceSize); + CpuAddressFlashDevice = SIZE_4GB - SpiFlashDeviceSize; + DEBUG ( + (EFI_D_INFO, + "Platform:FlashDeviceSize = 0x%08x Bytes\n", + SpiFlashDeviceSize) + ); + + // + // If not in update or recovery mode, lock stuff down + // + if ((BootMode != BOOT_IN_RECOVERY_MODE) && (BootMode != BOOT_ON_FLASH_UPDATE)) { + + // + // Lock regions + // + CpuAddressNvStorage = (UINT64) PcdGet32 (PcdFlashNvStorageVariableBase); + + // + // Lock from start of flash device up to Smi writable flash storage areas. + // + SpiAddress = 0; + if (!PlatformIsSpiRangeProtected ((UINT32) SpiAddress, (UINT32) (CpuAddressNvStorage - CpuAddressFlashDevice))) { + DEBUG ( + (EFI_D_INFO, + "Platform: Protect Region Base:Len 0x%08x:0x%08x\n", + (UINTN) SpiAddress, (UINTN)(CpuAddressNvStorage - CpuAddressFlashDevice)) + ); + Status = PlatformWriteFirstFreeSpiProtect ( + 0, + (UINT32) SpiAddress, + (UINT32) (CpuAddressNvStorage - CpuAddressFlashDevice) + ); + + ASSERT_EFI_ERROR (Status); + } + // + // Move Spi Address to after Smi writable flash storage areas. + // + SpiAddress = CpuAddressNvStorage - CpuAddressFlashDevice; + SpiAddress += ((UINT64) PcdGet32 (PcdFlashNvStorageVariableSize)); + + // + // Lock from end of OEM area to end of flash part. + // + if (!PlatformIsSpiRangeProtected ((UINT32) SpiAddress, SpiFlashDeviceSize - ((UINT32) SpiAddress))) { + DEBUG ( + (EFI_D_INFO, + "Platform: Protect Region Base:Len 0x%08x:0x%08x\n", + (UINTN) SpiAddress, + (UINTN) (SpiFlashDeviceSize - ((UINT32) SpiAddress))) + ); + ASSERT (SpiAddress < ((UINT64) SpiFlashDeviceSize)); + Status = PlatformWriteFirstFreeSpiProtect ( + 0, + (UINT32) SpiAddress, + SpiFlashDeviceSize - ((UINT32) SpiAddress) + ); + + ASSERT_EFI_ERROR (Status); + } + } + + // + // Always Lock flash config registers if about to boot a boot option + // else lock depending on boot mode. + // + if (PreBootPolicy || (BootMode != BOOT_ON_FLASH_UPDATE)) { + PlatformFlashLockConfig (); + } + + // + // Enable Quark Variable lock if PreBootPolicy. + // + if (PreBootPolicy) { + PlatformVariableLock (); + } +} + +/** Check if System booted with recovery Boot Stage1 image. + + @retval TRUE If system booted with recovery Boot Stage1 image. + @retval FALSE If system booted with normal stage1 image. + +**/ +BOOLEAN +EFIAPI +PlatformIsBootWithRecoveryStage1 ( + VOID + ) +{ + ASSERT_EFI_ERROR (EFI_UNSUPPORTED); + return FALSE; +} + diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperLib.c b/Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperLib.c new file mode 100644 index 0000000000..c7f707c8df --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperLib.c @@ -0,0 +1,481 @@ +/** @file +Helper routines with common PEI / DXE implementation. + +Copyright (c) 2013-2016 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "CommonHeader.h" +#include + +CHAR16 *mPlatTypeNameTable[] = { EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION }; +UINTN mPlatTypeNameTableLen = ((sizeof(mPlatTypeNameTable)) / sizeof (CHAR16 *)); + +// +// Routines defined in other source modules of this component. +// + +// +// Routines local to this source module. +// + +// +// Routines shared with other souce modules in this component. +// + +EFI_STATUS +WriteFirstFreeSpiProtect ( + IN CONST UINT32 PchRootComplexBar, + IN CONST UINT32 DirectValue, + IN CONST UINT32 BaseAddress, + IN CONST UINT32 Length, + OUT UINT32 *OffsetPtr + ) +{ + UINT32 RegVal; + UINT32 Offset; + UINT32 StepLen; + + ASSERT (PchRootComplexBar > 0); + + Offset = 0; + if (OffsetPtr != NULL) { + *OffsetPtr = Offset; + } + if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) == 0) { + Offset = R_QNC_RCRB_SPIPBR0; + } else { + if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR1) == 0) { + Offset = R_QNC_RCRB_SPIPBR1; + } else { + if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR2) == 0) { + Offset = R_QNC_RCRB_SPIPBR2; + } + } + } + if (Offset != 0) { + if (DirectValue == 0) { + StepLen = ALIGN_VALUE (Length,SIZE_4KB); // Bring up to 4K boundary. + RegVal = BaseAddress + StepLen - 1; + RegVal &= 0x00FFF000; // Set EDS Protected Range Limit (PRL). + RegVal |= ((BaseAddress >> 12) & 0xfff); // or in EDS Protected Range Base (PRB). + } else { + RegVal = DirectValue; + } + // + // Enable protection. + // + RegVal |= B_QNC_RCRB_SPIPBRn_WPE; + MmioWrite32 (PchRootComplexBar + Offset, RegVal); + if (RegVal == MmioRead32 (PchRootComplexBar + Offset)) { + if (OffsetPtr != NULL) { + *OffsetPtr = Offset; + } + return EFI_SUCCESS; + } + return EFI_DEVICE_ERROR; + } + return EFI_NOT_FOUND; +} + +// +// Routines exported by this component. +// + +/** + Clear SPI Protect registers. + + @retval EFI_SUCCESS SPI protect registers cleared. + @retval EFI_ACCESS_DENIED Unable to clear SPI protect registers. +**/ + +EFI_STATUS +EFIAPI +PlatformClearSpiProtect ( + VOID + ) +{ + UINT32 PchRootComplexBar; + + PchRootComplexBar = QNC_RCRB_BASE; + // + // Check if the SPI interface has been locked-down. + // + if ((MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIS) & B_QNC_RCRB_SPIS_SCL) != 0) { + return EFI_ACCESS_DENIED; + } + MmioWrite32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0, 0); + if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) != 0) { + return EFI_ACCESS_DENIED; + } + MmioWrite32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR1, 0); + if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) != 0) { + return EFI_ACCESS_DENIED; + } + MmioWrite32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR2, 0); + if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) != 0) { + return EFI_ACCESS_DENIED; + } + return EFI_SUCCESS; +} + +/** + Determine if an SPI address range is protected. + + @param SpiBaseAddress Base of SPI range. + @param Length Length of SPI range. + + @retval TRUE Range is protected. + @retval FALSE Range is not protected. +**/ +BOOLEAN +EFIAPI +PlatformIsSpiRangeProtected ( + IN CONST UINT32 SpiBaseAddress, + IN CONST UINT32 Length + ) +{ + UINT32 RegVal; + UINT32 Offset; + UINT32 Limit; + UINT32 ProtectedBase; + UINT32 ProtectedLimit; + UINT32 PchRootComplexBar; + + PchRootComplexBar = QNC_RCRB_BASE; + + if (Length > 0) { + Offset = R_QNC_RCRB_SPIPBR0; + Limit = SpiBaseAddress + (Length - 1); + do { + RegVal = MmioRead32 (PchRootComplexBar + Offset); + if ((RegVal & B_QNC_RCRB_SPIPBRn_WPE) != 0) { + ProtectedBase = (RegVal & 0xfff) << 12; + ProtectedLimit = (RegVal & 0x00fff000) + 0xfff; + if (SpiBaseAddress >= ProtectedBase && Limit <= ProtectedLimit) { + return TRUE; + } + } + if (Offset == R_QNC_RCRB_SPIPBR0) { + Offset = R_QNC_RCRB_SPIPBR1; + } else if (Offset == R_QNC_RCRB_SPIPBR1) { + Offset = R_QNC_RCRB_SPIPBR2; + } else { + break; + } + } while (TRUE); + } + return FALSE; +} + +/** + Set Legacy GPIO Level + + @param LevelRegOffset GPIO level register Offset from GPIO Base Address. + @param GpioNum GPIO bit to change. + @param HighLevel If TRUE set GPIO High else Set GPIO low. + +**/ +VOID +EFIAPI +PlatformLegacyGpioSetLevel ( + IN CONST UINT32 LevelRegOffset, + IN CONST UINT32 GpioNum, + IN CONST BOOLEAN HighLevel + ) +{ + UINT32 RegValue; + UINT32 GpioBaseAddress; + UINT32 GpioNumMask; + + GpioBaseAddress = LpcPciCfg32 (R_QNC_LPC_GBA_BASE) & B_QNC_LPC_GPA_BASE_MASK; + ASSERT (GpioBaseAddress > 0); + + RegValue = IoRead32 (GpioBaseAddress + LevelRegOffset); + GpioNumMask = (1 << GpioNum); + if (HighLevel) { + RegValue |= (GpioNumMask); + } else { + RegValue &= ~(GpioNumMask); + } + IoWrite32 (GpioBaseAddress + LevelRegOffset, RegValue); +} + +/** + Get Legacy GPIO Level + + @param LevelRegOffset GPIO level register Offset from GPIO Base Address. + @param GpioNum GPIO bit to check. + + @retval TRUE If bit is SET. + @retval FALSE If bit is CLEAR. + +**/ +BOOLEAN +EFIAPI +PlatformLegacyGpioGetLevel ( + IN CONST UINT32 LevelRegOffset, + IN CONST UINT32 GpioNum + ) +{ + UINT32 RegValue; + UINT32 GpioBaseAddress; + UINT32 GpioNumMask; + + GpioBaseAddress = LpcPciCfg32 (R_QNC_LPC_GBA_BASE) & B_QNC_LPC_GPA_BASE_MASK; + RegValue = IoRead32 (GpioBaseAddress + LevelRegOffset); + GpioNumMask = (1 << GpioNum); + return ((RegValue & GpioNumMask) != 0); +} + + +BOOLEAN +Pcal9555GetPortRegBit ( + IN CONST UINT32 Pcal9555SlaveAddr, + IN CONST UINT32 GpioNum, + IN CONST UINT8 RegBase + ) +{ + EFI_STATUS Status; + UINTN ReadLength; + UINTN WriteLength; + UINT8 Data[2]; + EFI_I2C_DEVICE_ADDRESS I2cDeviceAddr; + EFI_I2C_ADDR_MODE I2cAddrMode; + UINT8 *RegValuePtr; + UINT8 GpioNumMask; + UINT8 SubAddr; + + I2cDeviceAddr.I2CDeviceAddress = (UINTN)Pcal9555SlaveAddr; + I2cAddrMode = EfiI2CSevenBitAddrMode; + + if (GpioNum < 8) { + SubAddr = RegBase; + GpioNumMask = (UINT8)(1 << GpioNum); + } else { + SubAddr = RegBase + 1; + GpioNumMask = (UINT8)(1 << (GpioNum - 8)); + } + + // + // Output port value always at 2nd byte in Data variable. + // + RegValuePtr = &Data[1]; + + // + // On read entry sub address at 2nd byte, on read exit output + // port value in 2nd byte. + // + Data[1] = SubAddr; + WriteLength = 1; + ReadLength = 1; + Status = I2cReadMultipleByte ( + I2cDeviceAddr, + I2cAddrMode, + &WriteLength, + &ReadLength, + &Data[1] + ); + ASSERT_EFI_ERROR (Status); + + // + // Adjust output port bit given callers request. + // + return ((*RegValuePtr & GpioNumMask) != 0); +} + +VOID +Pcal9555SetPortRegBit ( + IN CONST UINT32 Pcal9555SlaveAddr, + IN CONST UINT32 GpioNum, + IN CONST UINT8 RegBase, + IN CONST BOOLEAN LogicOne + ) +{ + EFI_STATUS Status; + UINTN ReadLength; + UINTN WriteLength; + UINT8 Data[2]; + EFI_I2C_DEVICE_ADDRESS I2cDeviceAddr; + EFI_I2C_ADDR_MODE I2cAddrMode; + UINT8 *RegValuePtr; + UINT8 GpioNumMask; + UINT8 SubAddr; + + I2cDeviceAddr.I2CDeviceAddress = (UINTN)Pcal9555SlaveAddr; + I2cAddrMode = EfiI2CSevenBitAddrMode; + + if (GpioNum < 8) { + SubAddr = RegBase; + GpioNumMask = (UINT8)(1 << GpioNum); + } else { + SubAddr = RegBase + 1; + GpioNumMask = (UINT8)(1 << (GpioNum - 8)); + } + + // + // Output port value always at 2nd byte in Data variable. + // + RegValuePtr = &Data[1]; + + // + // On read entry sub address at 2nd byte, on read exit output + // port value in 2nd byte. + // + Data[1] = SubAddr; + WriteLength = 1; + ReadLength = 1; + Status = I2cReadMultipleByte ( + I2cDeviceAddr, + I2cAddrMode, + &WriteLength, + &ReadLength, + &Data[1] + ); + ASSERT_EFI_ERROR (Status); + + // + // Adjust output port bit given callers request. + // + if (LogicOne) { + *RegValuePtr = *RegValuePtr | GpioNumMask; + } else { + *RegValuePtr = *RegValuePtr & ~(GpioNumMask); + } + + // + // Update register. Sub address at 1st byte, value at 2nd byte. + // + WriteLength = 2; + Data[0] = SubAddr; + Status = I2cWriteMultipleByte ( + I2cDeviceAddr, + I2cAddrMode, + &WriteLength, + Data + ); + ASSERT_EFI_ERROR (Status); +} + +/** +Set the direction of Pcal9555 IO Expander GPIO pin. + +@param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander. +@param GpioNum Gpio direction to configure - values 0-7 for Port0 +and 8-15 for Port1. +@param CfgAsInput If TRUE set pin direction as input else set as output. + +**/ +VOID +EFIAPI +PlatformPcal9555GpioSetDir ( + IN CONST UINT32 Pcal9555SlaveAddr, + IN CONST UINT32 GpioNum, + IN CONST BOOLEAN CfgAsInput + ) +{ + Pcal9555SetPortRegBit ( + Pcal9555SlaveAddr, + GpioNum, + PCAL9555_REG_CFG_PORT0, + CfgAsInput + ); +} + +/** +Set the level of Pcal9555 IO Expander GPIO high or low. + +@param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander. +@param GpioNum Gpio to change values 0-7 for Port0 and 8-15 +for Port1. +@param HighLevel If TRUE set pin high else set pin low. + +**/ +VOID +EFIAPI +PlatformPcal9555GpioSetLevel ( + IN CONST UINT32 Pcal9555SlaveAddr, + IN CONST UINT32 GpioNum, + IN CONST BOOLEAN HighLevel + ) +{ + Pcal9555SetPortRegBit ( + Pcal9555SlaveAddr, + GpioNum, + PCAL9555_REG_OUT_PORT0, + HighLevel + ); +} + +/** + +Enable pull-up/pull-down resistors of Pcal9555 GPIOs. + +@param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander. +@param GpioNum Gpio to change values 0-7 for Port0 and 8-15 +for Port1. + +**/ +VOID +EFIAPI +PlatformPcal9555GpioEnablePull ( + IN CONST UINT32 Pcal9555SlaveAddr, + IN CONST UINT32 GpioNum + ) +{ + Pcal9555SetPortRegBit ( + Pcal9555SlaveAddr, + GpioNum, + PCAL9555_REG_PULL_EN_PORT0, + TRUE + ); +} + +/** + +Disable pull-up/pull-down resistors of Pcal9555 GPIOs. + +@param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander. +@param GpioNum Gpio to change values 0-7 for Port0 and 8-15 +for Port1. + +**/ +VOID +EFIAPI +PlatformPcal9555GpioDisablePull ( + IN CONST UINT32 Pcal9555SlaveAddr, + IN CONST UINT32 GpioNum + ) +{ + Pcal9555SetPortRegBit ( + Pcal9555SlaveAddr, + GpioNum, + PCAL9555_REG_PULL_EN_PORT0, + FALSE + ); +} + +/** + +Get state of Pcal9555 GPIOs. + +@param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander. +@param GpioNum Gpio to change values 0-7 for Port0 and 8-15 +for Port1. + +@retval TRUE GPIO pin is high +@retval FALSE GPIO pin is low +**/ +BOOLEAN +EFIAPI +PlatformPcal9555GpioGetState ( + IN CONST UINT32 Pcal9555SlaveAddr, + IN CONST UINT32 GpioNum + ) +{ + return Pcal9555GetPortRegBit (Pcal9555SlaveAddr, GpioNum, PCAL9555_REG_IN_PORT0); +} + + diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperPei.c b/Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperPei.c new file mode 100644 index 0000000000..9de3f613e0 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperPei.c @@ -0,0 +1,159 @@ +/** @file +Implementation of Helper routines for PEI enviroment. + +Copyright (c) 2013-2016 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include + +#include "CommonHeader.h" + +// +// Routines defined in other source modules of this component. +// + +// +// Routines local to this source module. +// + +// +// Routines exported by this source module. +// + +/** + Find pointer to RAW data in Firmware volume file. + + @param FvNameGuid Firmware volume to search. If == NULL search all. + @param FileNameGuid Firmware volume file to search for. + @param SectionData Pointer to RAW data section of found file. + @param SectionDataSize Pointer to UNITN to get size of RAW data. + + @retval EFI_SUCCESS Raw Data found. + @retval EFI_INVALID_PARAMETER FileNameGuid == NULL. + @retval EFI_NOT_FOUND Firmware volume file not found. + @retval EFI_UNSUPPORTED Unsupported in current enviroment (PEI or DXE). + +**/ +EFI_STATUS +EFIAPI +PlatformFindFvFileRawDataSection ( + IN CONST EFI_GUID *FvNameGuid OPTIONAL, + IN CONST EFI_GUID *FileNameGuid, + OUT VOID **SectionData, + OUT UINTN *SectionDataSize + ) +{ + EFI_STATUS Status; + UINTN Instance; + EFI_PEI_FV_HANDLE VolumeHandle; + EFI_PEI_FILE_HANDLE FileHandle; + EFI_SECTION_TYPE SearchType; + EFI_FV_INFO VolumeInfo; + EFI_FV_FILE_INFO FileInfo; + + if (FileNameGuid == NULL || SectionData == NULL || SectionDataSize == NULL) { + return EFI_INVALID_PARAMETER; + } + *SectionData = NULL; + *SectionDataSize = 0; + + SearchType = EFI_SECTION_RAW; + for (Instance = 0; !EFI_ERROR((PeiServicesFfsFindNextVolume (Instance, &VolumeHandle))); Instance++) { + if (FvNameGuid != NULL) { + Status = PeiServicesFfsGetVolumeInfo (VolumeHandle, &VolumeInfo); + if (EFI_ERROR (Status)) { + continue; + } + if (!CompareGuid (FvNameGuid, &VolumeInfo.FvName)) { + continue; + } + } + Status = PeiServicesFfsFindFileByName (FileNameGuid, VolumeHandle, &FileHandle); + if (!EFI_ERROR (Status)) { + Status = PeiServicesFfsGetFileInfo (FileHandle, &FileInfo); + if (EFI_ERROR (Status)) { + continue; + } + if (IS_SECTION2(FileInfo.Buffer)) { + *SectionDataSize = SECTION2_SIZE(FileInfo.Buffer) - sizeof(EFI_COMMON_SECTION_HEADER2); + } else { + *SectionDataSize = SECTION_SIZE(FileInfo.Buffer) - sizeof(EFI_COMMON_SECTION_HEADER); + } + Status = PeiServicesFfsFindSectionData (SearchType, FileHandle, SectionData); + if (!EFI_ERROR (Status)) { + return Status; + } + } + } + return EFI_NOT_FOUND; +} + +/** + Find free spi protect register and write to it to protect a flash region. + + @param DirectValue Value to directly write to register. + if DirectValue == 0 the use Base & Length below. + @param BaseAddress Base address of region in Flash Memory Map. + @param Length Length of region to protect. + + @retval EFI_SUCCESS Free spi protect register found & written. + @retval EFI_NOT_FOUND Free Spi protect register not found. + @retval EFI_DEVICE_ERROR Unable to write to spi protect register. +**/ +EFI_STATUS +EFIAPI +PlatformWriteFirstFreeSpiProtect ( + IN CONST UINT32 DirectValue, + IN CONST UINT32 BaseAddress, + IN CONST UINT32 Length + ) +{ + return WriteFirstFreeSpiProtect ( + QNC_RCRB_BASE, + DirectValue, + BaseAddress, + Length, + NULL + ); +} + +/** Check if System booted with recovery Boot Stage1 image. + + @retval TRUE If system booted with recovery Boot Stage1 image. + @retval FALSE If system booted with normal stage1 image. + +**/ +BOOLEAN +EFIAPI +PlatformIsBootWithRecoveryStage1 ( + VOID + ) +{ + BOOLEAN IsRecoveryBoot; + QUARK_EDKII_STAGE1_HEADER *Edk2ImageHeader; + + Edk2ImageHeader = (QUARK_EDKII_STAGE1_HEADER *) PcdGet32 (PcdEsramStage1Base); + switch ((UINT8)Edk2ImageHeader->ImageIndex & QUARK_STAGE1_IMAGE_TYPE_MASK) { + case QUARK_STAGE1_RECOVERY_IMAGE_TYPE: + // + // Recovery Boot + // + IsRecoveryBoot = TRUE; + break; + default: + // + // Normal Boot + // + IsRecoveryBoot = FALSE; + break; + } + + return IsRecoveryBoot; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformLeds.c b/Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformLeds.c new file mode 100644 index 0000000000..8846f3cd02 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformLeds.c @@ -0,0 +1,146 @@ +/** @file +Platform helper LED routines. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include "CommonHeader.h" + +// +// Routines defined in other source modules of this component. +// + +// +// Routines local to this source module. +// + +VOID +GalileoGen2RouteOutFlashUpdateLed ( + VOID + ) +{ + // + // For GpioNums below values 0 to 7 are for Port0 ie P0-0 - P0-7 and + // values 8 to 15 are for Port1 ie P1-0 - P1-7. + // + + // + // Disable Pull-ups / pull downs on EXP0 pin for LVL_B_PU7 signal. + // + PlatformPcal9555GpioDisablePull ( + GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0. + 15 // P1-7. + ); + + // + // Make LVL_B_OE7_N an output pin. + // + PlatformPcal9555GpioSetDir ( + GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0. + 14, // P1-6. + FALSE + ); + + // + // Set level of LVL_B_OE7_N to low. + // + PlatformPcal9555GpioSetLevel ( + GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, + 14, + FALSE + ); + + // + // Make MUX8_SEL an output pin. + // + PlatformPcal9555GpioSetDir ( + GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1. + 14, // P1-6. + FALSE + ); + + // + // Set level of MUX8_SEL to low to route GPIO_SUS<5> to LED. + // + PlatformPcal9555GpioSetLevel ( + GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1. + 14, // P1-6. + FALSE + ); +} + +// +// Routines exported by this source module. +// + +/** + Init platform LEDs into known state. + + @param PlatformType Executing platform type. + @param I2cBus Pointer to I2c Host controller protocol. + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +PlatformLedInit ( + IN CONST EFI_PLATFORM_TYPE Type + ) +{ + EFI_BOOT_MODE BootMode; + + BootMode = GetBootModeHob (); + + // + // Init Flash update / recovery LED in OFF state. + // + if (BootMode == BOOT_ON_FLASH_UPDATE || BootMode == BOOT_IN_RECOVERY_MODE) { + if (Type == GalileoGen2) { + PlatformLegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO, FALSE); + GalileoGen2RouteOutFlashUpdateLed (); + } else if (Type == Galileo) { + PlatformLegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_FLASH_UPDATE_LED_RESUMEWELL_GPIO, FALSE); + } else { + // + // These platforms have no flash update LED. + // + } + } + + return EFI_SUCCESS; +} + +/** + Turn on or off platform flash update LED. + + @param PlatformType Executing platform type. + @param TurnOn If TRUE turn on else turn off. + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +PlatformFlashUpdateLed ( + IN CONST EFI_PLATFORM_TYPE Type, + IN CONST BOOLEAN TurnOn + ) +{ + if (Type == GalileoGen2) { + PlatformLegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO, TurnOn); + } else if (Type == Galileo) { + PlatformLegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_FLASH_UPDATE_LED_RESUMEWELL_GPIO, TurnOn); + } else { + // + // These platforms have no flash update LED. + // + } + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformPcieHelperLib/CommonHeader.h b/Platform/Intel/QuarkPlatformPkg/Library/PlatformPcieHelperLib/CommonHeader.h new file mode 100644 index 0000000000..339baac186 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformPcieHelperLib/CommonHeader.h @@ -0,0 +1,55 @@ +/** @file +Common header file shared by all source files in this component. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __COMMON_HEADER_H_ +#define __COMMON_HEADER_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +// +// Routines shared between souce modules in this component. +// + +VOID +EFIAPI +PlatformPcieErratas ( + VOID + ); + +EFI_STATUS +EFIAPI +SocUnitEarlyInitialisation ( + VOID + ); + +EFI_STATUS +EFIAPI +SocUnitReleasePcieControllerPreWaitPllLock ( + IN CONST EFI_PLATFORM_TYPE PlatformType + ); + +EFI_STATUS +EFIAPI +SocUnitReleasePcieControllerPostPllLock ( + IN CONST EFI_PLATFORM_TYPE PlatformType + ); + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.c b/Platform/Intel/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.c new file mode 100644 index 0000000000..8aaeb73342 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.c @@ -0,0 +1,114 @@ +/** @file +Platform Pcie Helper Lib. + +Copyright (c) 2013 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "CommonHeader.h" + +// +// Routines local to this source module. +// +VOID +LegacyGpioSetLevel ( + IN CONST UINT32 LevelRegOffset, + IN CONST UINT32 GpioNum, + IN CONST BOOLEAN HighLevel + ) +{ + UINT32 RegValue; + UINT32 GpioBaseAddress; + UINT32 GpioNumMask; + + GpioBaseAddress = LpcPciCfg32 (R_QNC_LPC_GBA_BASE) & B_QNC_LPC_GPA_BASE_MASK; + ASSERT (GpioBaseAddress > 0); + + RegValue = IoRead32 (GpioBaseAddress + LevelRegOffset); + GpioNumMask = (1 << GpioNum); + if (HighLevel) { + RegValue |= (GpioNumMask); + } else { + RegValue &= ~(GpioNumMask); + } + IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGLVL_RESUME_WELL, RegValue); +} + +// +// Routines exported by this component. +// + +/** + Platform assert PCI express PERST# signal. + + @param PlatformType See EFI_PLATFORM_TYPE enum definitions. + +**/ +VOID +EFIAPI +PlatformPERSTAssert ( + IN CONST EFI_PLATFORM_TYPE PlatformType + ) +{ + if (PlatformType == GalileoGen2) { + LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO, FALSE); + } else { + LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, PCIEXP_PERST_RESUMEWELL_GPIO, FALSE); + } +} + +/** + Platform de assert PCI express PERST# signal. + + @param PlatformType See EFI_PLATFORM_TYPE enum definitions. + +**/ +VOID +EFIAPI +PlatformPERSTDeAssert ( + IN CONST EFI_PLATFORM_TYPE PlatformType + ) +{ + if (PlatformType == GalileoGen2) { + LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO, TRUE); + } else { + LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, PCIEXP_PERST_RESUMEWELL_GPIO, TRUE); + } +} + +/** Early initialisation of the PCIe controller. + + @param PlatformType See EFI_PLATFORM_TYPE enum definitions. + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +PlatformPciExpressEarlyInit ( + IN CONST EFI_PLATFORM_TYPE PlatformType + ) +{ + + // + // Release and wait for PCI controller to come out of reset. + // + SocUnitReleasePcieControllerPreWaitPllLock (PlatformType); + MicroSecondDelay (PCIEXP_DELAY_US_WAIT_PLL_LOCK); + SocUnitReleasePcieControllerPostPllLock (PlatformType); + + // + // Early PCIe initialisation + // + SocUnitEarlyInitialisation (); + + // + // Do North cluster early PCIe init. + // + PciExpressEarlyInit (); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.inf b/Platform/Intel/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.inf new file mode 100644 index 0000000000..0fdaf22494 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.inf @@ -0,0 +1,41 @@ +## @file +# Library producing Pci Express Helper routines. +# +# Copyright (c) 2013 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformPcieHelperLib + FILE_GUID = C153F460-5D8A-4d44-83BB-A8AF5CEF132C + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformPcieHelperLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 +# + +[Sources] + PlatformPcieHelperLib.c + SocUnit.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + QuarkSocPkg/QuarkSocPkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + +[LibraryClasses] + BaseLib + PcdLib + IoLib + DebugLib + TimerLib + QNCAccessLib + IntelQNCLib diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformPcieHelperLib/SocUnit.c b/Platform/Intel/QuarkPlatformPkg/Library/PlatformPcieHelperLib/SocUnit.c new file mode 100644 index 0000000000..8babbe869a --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformPcieHelperLib/SocUnit.c @@ -0,0 +1,125 @@ +/** @file +System On Chip Unit (SOCUnit) routines. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "CommonHeader.h" + +/** Early initialisation of the SOC Unit + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +SocUnitEarlyInitialisation ( + VOID + ) +{ + UINT32 NewValue; + + // + // Set the mixer load resistance + // + NewValue = QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0); + NewValue &= OCFGPIMIXLOAD_1_0_MASK; + QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0, NewValue); + + NewValue = QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1); + NewValue &= OCFGPIMIXLOAD_1_0_MASK; + QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1, NewValue); + + return EFI_SUCCESS; +} + +/** Tasks to release PCI controller from reset pre wait for PLL Lock. + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +SocUnitReleasePcieControllerPreWaitPllLock ( + IN CONST EFI_PLATFORM_TYPE PlatformType + ) +{ + UINT32 NewValue; + + // + // Assert PERST# and validate time assertion time. + // + PlatformPERSTAssert (PlatformType); + ASSERT (PCIEXP_PERST_MIN_ASSERT_US <= (PCIEXP_DELAY_US_POST_CMNRESET_RESET + PCIEXP_DELAY_US_WAIT_PLL_LOCK + PCIEXP_DELAY_US_POST_SBI_RESET)); + + // + // PHY Common lane reset. + // + NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG); + NewValue |= SOCCLKEN_CONFIG_PHY_I_CMNRESET_L; + QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue); + + // + // Wait post common lane reset. + // + MicroSecondDelay (PCIEXP_DELAY_US_POST_CMNRESET_RESET); + + // + // PHY Sideband interface reset. + // Controller main reset + // + NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG); + NewValue |= (SOCCLKEN_CONFIG_SBI_RST_100_CORE_B | SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L); + QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue); + + return EFI_SUCCESS; +} + +/** Tasks to release PCI controller from reset after PLL has locked + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +SocUnitReleasePcieControllerPostPllLock ( + IN CONST EFI_PLATFORM_TYPE PlatformType + ) +{ + UINT32 NewValue; + + // + // Controller sideband interface reset. + // + NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG); + NewValue |= SOCCLKEN_CONFIG_SBI_BB_RST_B; + QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue); + + // + // Wait post sideband interface reset. + // + MicroSecondDelay (PCIEXP_DELAY_US_POST_SBI_RESET); + + // + // Deassert PERST#. + // + PlatformPERSTDeAssert (PlatformType); + + // + // Wait post de assert PERST#. + // + MicroSecondDelay (PCIEXP_DELAY_US_POST_PERST_DEASSERT); + + // + // Controller primary interface reset. + // + NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG); + NewValue |= SOCCLKEN_CONFIG_BB_RST_B; + QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/Ia32/Flat32.S b/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/Ia32/Flat32.S new file mode 100644 index 0000000000..1ba63abd7b --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/Ia32/Flat32.S @@ -0,0 +1,796 @@ +#------------------------------------------------------------------------------ +# +# Copyright (c) 2013 - 2016 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# Module Name: +# +# Flat32.S +# +# Abstract: +# +# This is the code that goes from real-mode to protected mode. +# It consumes the reset vector, configures the stack. +# +# +#------------------------------------------------------------------------------ + +.macro RET32 + jmp *%esp +.endm + +# +# ROM/SPI/MEMORY Definitions +# +.equ QUARK_DDR3_MEM_BASE_ADDRESS, (0x000000000) # Memory Base Address = 0 +.equ QUARK_MAX_DDR3_MEM_SIZE_BYTES, (0x80000000) # DDR3 Memory Size = 2GB +.equ QUARK_ESRAM_MEM_SIZE_BYTES, (0x00080000) # eSRAM Memory Size = 512K +.equ QUARK_STACK_SIZE_BYTES, (0x008000) # Quark stack size = 32K + +# +# RTC/CMOS definitions +# +.equ RTC_INDEX, (0x70) +.equ NMI_DISABLE, (0x80) # Bit7=1 disables NMI +.equ NMI_ENABLE, (0x00) # Bit7=0 disables NMI +.equ RTC_DATA, (0x71) + +# +# PCI Configuration definitions +# +.equ PCI_CFG, (0x80000000) # PCI configuration access mechanism +.equ PCI_ADDRESS_PORT, (0xCF8) +.equ PCI_DATA_PORT, (0xCFC) + +# +# Quark PCI devices +# +.equ HOST_BRIDGE_PFA, (0x0000) # B0:D0:F0 (Host Bridge) +.equ ILB_PFA, (0x00F8) # B0:D31:F0 (Legacy Block) + +# +# ILB PCI Config Registers +# +.equ BDE, (0x0D4) # BIOS Decode Enable register +.equ DECODE_ALL_REGIONS_ENABLE, (0xFF000000) # Decode all BIOS decode ranges + +# +# iLB Reset Register +# +.equ ILB_RESET_REG, (0x0CF9) +.equ CF9_WARM_RESET, (0x02) +.equ CF9_COLD_RESET, (0x08) + +# +# Host Bridge PCI Config Registers +# +.equ MESSAGE_BUS_CONTROL_REG, (0xD0) # Message Bus Control Register +.equ SB_OPCODE_FIELD, (0x18) # Bit location of Opcode field +.equ OPCODE_SIDEBAND_REG_READ, (0x10) # Read opcode +.equ OPCODE_SIDEBAND_REG_WRITE, (0x11) # Write opcode +.equ OPCODE_SIDEBAND_ALT_REG_READ, (0x06) # Alternate Read opcode +.equ OPCODE_SIDEBAND_ALT_REG_WRITE, (0x07) # Alternate Write opcode +.equ OPCODE_WARM_RESET_REQUEST, (0xF4) # Reset Warm +.equ OPCODE_COLD_RESET_REQUEST, (0xF5) # Reset Cold +.equ SB_PORT_FIELD, (0x10) # Bit location of Port ID field +.equ MEMORY_ARBITER_PORT_ID, (0x00) +.equ HOST_BRIDGE_PORT_ID, (0x03) +.equ RMU_PORT_ID, (0x04) +.equ MEMORY_MANAGER_PORT_ID, (0x05) +.equ SOC_UNIT_PORT_ID, (0x31) +.equ SB_ADDR_FIELD, (0x08) # Bit location of Register field +.equ SB_BE_FIELD, (0x04) # Bit location of Byte Enables field +.equ ALL_BYTE_EN, (0x0F) # All Byte Enables +.equ MESSAGE_DATA_REG, (0xD4) # Message Data Register + +# +# Memory Arbiter Config Registers +# +.equ AEC_CTRL_OFFSET, (0x00) + +# +# Host Bridge Config Registers +# +.equ HMISC2_OFFSET, (0x03) # PCI configuration access mechanism +.equ OR_PM_FIELD, (0x10) +.equ SMI_EN, (0x00080000) + +.equ HMBOUND_OFFSET, (0x08) +.equ HMBOUND_ADDRESS, (QUARK_DDR3_MEM_BASE_ADDRESS + QUARK_MAX_DDR3_MEM_SIZE_BYTES + QUARK_ESRAM_MEM_SIZE_BYTES) +.equ HMBOUND_LOCK, (0x01) +.equ HECREG_OFFSET, (0x09) +.equ EC_BASE, (0xE0000000) +.equ EC_ENABLE, (0x01) +.equ HLEGACY_OFFSET, (0x0A) +.equ NMI, (0x00004000) +.equ SMI, (0x00001000) +.equ INTR, (0x00000400) + +# +# Memory Manager Config Registers +# +.equ ESRAMPGCTRL_BLOCK_OFFSET, (0x82) +.equ BLOCK_ENABLE_PG, (0x10000000) +.equ BIMRVCTL_OFFSET, (0x19) +.equ ENABLE_IMR_INTERRUPT, (0x80000000) + +# +# SOC UNIT Debug Registers +# +.equ CFGSTICKY_W1_OFFSET, (0x50) +.equ FORCE_COLD_RESET, (0x00000001) +.equ CFGSTICKY_RW_OFFSET, (0x51) +.equ RESET_FOR_ESRAM_LOCK, (0x00000020) +.equ RESET_FOR_HMBOUND_LOCK, (0x00000040) +.equ CFGNONSTICKY_W1_OFFSET, (0x52) +.equ FORCE_WARM_RESET, (0x00000001) + +# +# CR0 cache control bit definition +# +.equ CR0_CACHE_DISABLE, 0x040000000 +.equ CR0_NO_WRITE, 0x020000000 + +ASM_GLOBAL ASM_PFX(PcdGet32(PcdEsramStage1Base)) + + +# +# Contrary to the name, this file contains 16 bit code as well. +# +.text +#---------------------------------------------------------------------------- +# +# Procedure: _ModuleEntryPoint +# +# Input: None +# +# Output: None +# +# Destroys: Assume all registers +# +# Description: +# +# Transition to non-paged flat-model protected mode from a +# hard-coded GDT that provides exactly two descriptors. +# This is a bare bones transition to protected mode only +# used for a while in PEI and possibly DXE. +# +# After enabling protected mode, a far jump is executed to +# transfer to PEI using the newly loaded GDT. +# +# Return: None +# +#---------------------------------------------------------------------------- +ASM_GLOBAL ASM_PFX(_ModuleEntryPoint) +ASM_PFX(_ModuleEntryPoint): + + # + # Warm Reset (INIT#) check. + # + .byte 0xbe,0x00,0xf0 #movw $0xF000, %si + .byte 0x8e,0xde #movw %si, %ds + .byte 0xbe,0xf0,0xff #movw $0xFFF0, %si + .byte 0x80,0x3c,0xea #cmpb $0xEA, (%si) # Is it warm reset ? + jne NotWarmReset # Jump if not. + .byte 0xb0,0x08 #movb $0x08, %al + .byte 0xba,0xf9,0x0c #movw $0xcf9, %dx + .byte 0xee #outb %al, %dx + .byte 0xb0,0x55 #movb $0x55, %al + .byte 0xe6,0x80 #outb %al, $0x80 + jmp . +NotWarmReset: + .byte 0x66,0x8b,0xe8 #movl %eax, %ebp + + # + # Load the GDT table in GdtDesc + # + .byte 0x66,0xbe #movl $GdtDesc, %esi + .long GdtDesc + + .byte 0x66,0x2e,0x0f,0x01,0x14 #lgdt %cs:(%si) + + # + # Transition to 16 bit protected mode + # + .byte 0x0f,0x20,0xc0 #movl %cr0, %eax # Get control register 0 + .byte 0x66,0x83,0xc8,0x03 #orl $0x0000003, %eax # Set PE bit (bit #0) & MP bit (bit #1) + .byte 0x0f,0x22,0xc0 #movl %eax, %cr0 # Activate protected mode + + # + # Now we're in 16 bit protected mode + # Set up the selectors for 32 bit protected mode entry + # + .byte 0xb8 #movw SYS_DATA_SEL, %ax + .word SYS_DATA_SEL + + .byte 0x8e,0xd8 #movw %ax, %ds + .byte 0x8e,0xc0 #movw %ax, %es + .byte 0x8e,0xe0 #movw %ax, %fs + .byte 0x8e,0xe8 #movw %ax, %gs + .byte 0x8e,0xd0 #movw %ax, %ss + + # + # Transition to Flat 32 bit protected mode + # The jump to a far pointer causes the transition to 32 bit mode + # + .byte 0x66,0xbe #movl ProtectedModeEntryLinearAddress, %esi + .long ProtectedModeEntryLinearAddress + .byte 0x66,0x2e,0xff,0x2c #jmp %cs:(%esi) + +# +# Protected mode portion initializes stack, configures cache, and calls C entry point +# + +#---------------------------------------------------------------------------- +# +# Procedure: ProtectedModeEntryPoint +# +# Input: Executing in 32 Bit Protected (flat) mode +# cs: 0-4GB +# ds: 0-4GB +# es: 0-4GB +# fs: 0-4GB +# gs: 0-4GB +# ss: 0-4GB +# +# Output: This function never returns +# +# Destroys: +# ecx +# edi +# esi +# esp +# +# Description: +# Perform any essential early platform initilaisation +# Setup a stack +# Transfer control to EDKII code in eSRAM +# +#---------------------------------------------------------------------------- +ProtectedModeEntryPoint: + leal L0, %esp + jmp stackless_EarlyPlatformInit +L0: + + # + # Set up stack pointer + # + movl ASM_PFX(PcdGet32(PcdEsramStage1Base)), %esp + movl $QUARK_ESRAM_MEM_SIZE_BYTES, %esi + addl %esi, %esp # ESP = top of stack (stack grows downwards). + + # + # Store the the BIST value in EBP + # + movl $0, %ebp # No processor BIST on Quark + + # + # Push processor count to stack first, then BIST status (AP then BSP) + # + movl $1, %eax + cpuid + shrl $16, %ebx + andl $0x000000FF, %ebx + cmpb $1, %bl + jae PushProcessorCount + + # + # Some processors report 0 logical processors. Effectively 0 = 1. + # So we fix up the processor count + # + incl %ebx + +PushProcessorCount: + pushl %ebx + + # + # We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST + # for all processor threads + # + xorl %ecx, %ecx + movb %bl, %cl + +PushBist: + pushl %ebp + loop PushBist + + # + # Pass Control into the PEI Core + # + call PlatformSecLibStartup + + # + # PEI Core should never return to here, this is just to capture an invalid return. + # + jmp . + +#---------------------------------------------------------------------------- +# +# Procedure: stackless_EarlyPlatformInit +# +# Input: esp - Return address +# +# Output: None +# +# Destroys: Assume all registers +# +# Description: +# Any early platform initialisation required +# +# Return: +# None +# +#---------------------------------------------------------------------------- +stackless_EarlyPlatformInit: + + # + # Save return address + # + movl %esp, %ebp + + # + # Ensure cache is disabled. + # + movl %cr0, %eax + orl $(CR0_CACHE_DISABLE + CR0_NO_WRITE), %eax + invd + movl %eax, %cr0 + + # + # Disable NMI operation + # Good convention suggests you should read back RTC data port after + # accessing the RTC index port. + # + movb $(NMI_DISABLE), %al + movw $(RTC_INDEX), %dx + outb %al, %dx + movw $(RTC_DATA), %dx + inb %dx, %al + + # + # Disable SMI (Disables SMI wire, not SMI messages) + # + movl $((OPCODE_SIDEBAND_REG_READ << SB_OPCODE_FIELD) | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) | (HMISC2_OFFSET << SB_ADDR_FIELD)), %ecx + leal L1, %esp + jmp stackless_SideBand_Read +L1: + andl $(~SMI_EN), %eax + movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) | (HMISC2_OFFSET << SB_ADDR_FIELD)), %ecx + leal L2, %esp + jmp stackless_SideBand_Write +L2: + + # + # Before we get going, check SOC Unit Registers to see if we are required to issue a warm/cold reset + # + movl $((OPCODE_SIDEBAND_ALT_REG_READ << SB_OPCODE_FIELD) | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) | (CFGNONSTICKY_W1_OFFSET << SB_ADDR_FIELD)), %ecx + leal L3, %esp + jmp stackless_SideBand_Read +L3: + andl $(FORCE_WARM_RESET), %eax + jz TestForceColdReset # Zero means bit clear, we're not requested to warm reset so continue as normal + jmp IssueWarmReset + +TestForceColdReset: + movl $((OPCODE_SIDEBAND_ALT_REG_READ << SB_OPCODE_FIELD) | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) | (CFGNONSTICKY_W1_OFFSET << SB_ADDR_FIELD)), %ecx + leal L4, %esp + jmp stackless_SideBand_Read +L4: + andl $(FORCE_COLD_RESET), %eax + jz TestHmboundLock # Zero means bit clear, we're not requested to cold reset so continue as normal + jmp IssueColdReset + + # + # Before setting HMBOUND, check it's not locked + # +TestHmboundLock: + movl $((OPCODE_SIDEBAND_REG_READ << SB_OPCODE_FIELD) | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) | (HMBOUND_OFFSET << SB_ADDR_FIELD)), %ecx + leal L5, %esp + jmp stackless_SideBand_Read +L5: + andl $(HMBOUND_LOCK), %eax + jz ConfigHmbound # Zero means bit clear, we have the config we want so continue as normal + # + # Failed to config - store sticky bit debug + # + movl $((OPCODE_SIDEBAND_ALT_REG_READ << SB_OPCODE_FIELD) | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) | (CFGSTICKY_RW_OFFSET << SB_ADDR_FIELD)), %ecx + leal L6, %esp + jmp stackless_SideBand_Read +L6: + orl $(RESET_FOR_HMBOUND_LOCK), %eax + movl $((OPCODE_SIDEBAND_ALT_REG_WRITE << SB_OPCODE_FIELD) | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) | (CFGSTICKY_RW_OFFSET << SB_ADDR_FIELD)), %ecx + leal L7, %esp + jmp stackless_SideBand_Write +L7: + jmp IssueWarmReset + + # + # Set up the HMBOUND register + # +ConfigHmbound: + movl $(HMBOUND_ADDRESS), %eax # Data (Set HMBOUND location) + movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) | (HMBOUND_OFFSET << SB_ADDR_FIELD)), %ecx + leal L8, %esp + jmp stackless_SideBand_Write +L8: + + # + # Enable interrupts to Remote Management Unit when a IMR/SMM/HMBOUND violation occurs. + # + movl $(ENABLE_IMR_INTERRUPT), %eax # Data (Set interrupt enable mask) + movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) | (MEMORY_MANAGER_PORT_ID << SB_PORT_FIELD) | (BIMRVCTL_OFFSET << SB_ADDR_FIELD)), %ecx + leal L9, %esp + jmp stackless_SideBand_Write +L9: + + # + # Set eSRAM address + # + movl ASM_PFX(PcdGet32(PcdEsramStage1Base)), %eax # Data (Set eSRAM location) + shr $(0x18), %eax + addl $(BLOCK_ENABLE_PG), %eax + movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) | (MEMORY_MANAGER_PORT_ID << SB_PORT_FIELD) | (ESRAMPGCTRL_BLOCK_OFFSET << SB_ADDR_FIELD)), %ecx + leal L10, %esp + jmp stackless_SideBand_Write +L10: + + # + # Check that we're not blocked from setting the config that we want. + # + movl $((OPCODE_SIDEBAND_REG_READ << SB_OPCODE_FIELD) | (MEMORY_MANAGER_PORT_ID << SB_PORT_FIELD) | (ESRAMPGCTRL_BLOCK_OFFSET << SB_ADDR_FIELD)), %ecx + leal L11, %esp + jmp stackless_SideBand_Read +L11: + andl $(BLOCK_ENABLE_PG), %eax + jnz ConfigPci # Non-zero means bit set, we have the config we want so continue as normal + # + # Failed to config - store sticky bit debug + # + movl $((OPCODE_SIDEBAND_ALT_REG_READ << SB_OPCODE_FIELD) | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) | (CFGSTICKY_RW_OFFSET << SB_ADDR_FIELD)), %ecx + leal L12, %esp + jmp stackless_SideBand_Read +L12: + orl $(RESET_FOR_ESRAM_LOCK), %eax # Set the bit we're interested in + movl $((OPCODE_SIDEBAND_ALT_REG_WRITE << SB_OPCODE_FIELD) | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) | (CFGSTICKY_RW_OFFSET << SB_ADDR_FIELD)), %ecx + leal L13, %esp + jmp stackless_SideBand_Write +L13: + jmp IssueWarmReset + + # + # Enable PCIEXBAR + # +ConfigPci: + movl $(EC_BASE + EC_ENABLE), %eax # Data + movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) | (MEMORY_ARBITER_PORT_ID << SB_PORT_FIELD) | (AEC_CTRL_OFFSET << SB_ADDR_FIELD)), %ecx + leal L14, %esp + jmp stackless_SideBand_Write +L14: + + movl $(EC_BASE + EC_ENABLE), %eax # Data + movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) | (HECREG_OFFSET << SB_ADDR_FIELD)), %ecx + leal L15, %esp + jmp stackless_SideBand_Write +L15: + + # + # Open up full 8MB SPI decode + # + movl $(PCI_CFG | (ILB_PFA << 8) | BDE), %ebx # PCI Configuration address + movl $(DECODE_ALL_REGIONS_ENABLE), %eax + leal L16, %esp + jmp stackless_PCIConfig_Write +L16: + + # + # Enable NMI operation + # Good convention suggests you should read back RTC data port after + # accessing the RTC index port. + # + movb $(NMI_ENABLE), %al + movw $(RTC_INDEX), %dx + outb %al, %dx + movw $(RTC_DATA), %dx + inb %dx, %al + + # + # Clear Host Bridge SMI, NMI, INTR fields + # + movl $((OPCODE_SIDEBAND_REG_READ << SB_OPCODE_FIELD) | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) | (HLEGACY_OFFSET << SB_ADDR_FIELD)), %ecx + leal L21, %esp + jmp stackless_SideBand_Read +L21: + andl $~(NMI + SMI + INTR), %eax # Clear NMI, SMI, INTR fields + movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) | (HLEGACY_OFFSET << SB_ADDR_FIELD)), %ecx + leal L22, %esp + jmp stackless_SideBand_Write +L22: + + # + # Restore return address + # + movl %ebp, %esp + RET32 + +IssueWarmReset: + # + # Issue Warm Reset request to Remote Management Unit via iLB + # + movw $(CF9_WARM_RESET), %ax + movw $(ILB_RESET_REG), %dx + outw %ax, %dx + jmp . # Stay here until we are reset. + +IssueColdReset: + # + # Issue Cold Reset request to Remote Management Unit via iLB + # + movw $(CF9_COLD_RESET), %ax + movw $(ILB_RESET_REG), %dx + outw %ax, %dx + jmp . # Stay here until we are reset. + +#---------------------------------------------------------------------------- +# +# Procedure: stackless_SideBand_Read +# +# Input: esp - return address +# ecx[15:8] - Register offset +# ecx[23:16] - Port ID +# ecx[31:24] - Opcode +# +# Output: eax - Data read +# +# Destroys: +# eax +# ebx +# cl +# esi +# +# Description: +# Perform requested sideband read +# +#---------------------------------------------------------------------------- +stackless_SideBand_Read: + + movl %esp, %esi # Save the return address + + # + # Load the SideBand Packet Register to generate the transaction + # + movl $((PCI_CFG) | (HOST_BRIDGE_PFA << 8) | (MESSAGE_BUS_CONTROL_REG)), %ebx # PCI Configuration address + movb $(ALL_BYTE_EN << SB_BE_FIELD), %cl # Set all Byte Enable bits + xchgl %ecx, %eax + leal L17, %esp + jmp stackless_PCIConfig_Write +L17: + xchgl %ecx, %eax + + # + # Read the SideBand Data Register + # + movl $((PCI_CFG) | (HOST_BRIDGE_PFA << 8) | (MESSAGE_DATA_REG)), %ebx # PCI Configuration address + leal L18, %esp + jmp stackless_PCIConfig_Read +L18: + + movl %esi, %esp # Restore the return address + RET32 + + +#---------------------------------------------------------------------------- +# +# Procedure: stackless_SideBand_Write +# +# Input: esp - return address +# eax - Data +# ecx[15:8] - Register offset +# ecx[23:16] - Port ID +# ecx[31:24] - Opcode +# +# Output: None +# +# Destroys: +# ebx +# cl +# esi +# +# Description: +# Perform requested sideband write +# +# +#---------------------------------------------------------------------------- +stackless_SideBand_Write: + + movl %esp, %esi # Save the return address + + # + # Load the SideBand Data Register with the data + # + movl $((PCI_CFG) | (HOST_BRIDGE_PFA << 8) | (MESSAGE_DATA_REG)), %ebx # PCI Configuration address + leal L19, %esp + jmp stackless_PCIConfig_Write +L19: + + # + # Load the SideBand Packet Register to generate the transaction + # + movl $((PCI_CFG) | (HOST_BRIDGE_PFA << 8) | (MESSAGE_BUS_CONTROL_REG)), %ebx # PCI Configuration address + movb $(ALL_BYTE_EN << SB_BE_FIELD), %cl # Set all Byte Enable bits + xchgl %ecx, %eax + leal L20, %esp + jmp stackless_PCIConfig_Write +L20: + xchgl %ecx, %eax + + movl %esi, %esp # Restore the return address + RET32 + + +#---------------------------------------------------------------------------- +# +# Procedure: stackless_PCIConfig_Write +# +# Input: esp - return address +# eax - Data to write +# ebx - PCI Config Address +# +# Output: None +# +# Destroys: +# dx +# +# Description: +# Perform a DWORD PCI Configuration write +# +#---------------------------------------------------------------------------- +stackless_PCIConfig_Write: + + # + # Write the PCI Config Address to the address port + # + xchgl %ebx, %eax + movw $(PCI_ADDRESS_PORT), %dx + outl %eax, %dx + xchgl %ebx, %eax + + # + # Write the PCI DWORD Data to the data port + # + movw $(PCI_DATA_PORT), %dx + outl %eax, %dx + + RET32 + + +#---------------------------------------------------------------------------- +# +# Procedure: stackless_PCIConfig_Read +# +# Input: esp - return address +# ebx - PCI Config Address +# +# Output: eax - Data read +# +# Destroys: +# eax +# dx +# +# Description: +# Perform a DWORD PCI Configuration read +# +#---------------------------------------------------------------------------- +stackless_PCIConfig_Read: + + # + # Write the PCI Config Address to the address port + # + xchgl %ebx, %eax + movw $(PCI_ADDRESS_PORT), %dx + outl %eax, %dx + xchgl %ebx, %eax + + # + # Read the PCI DWORD Data from the data port + # + movw $(PCI_DATA_PORT), %dx + inl %dx, %eax + + RET32 + + +# +# ROM-based Global-Descriptor Table for the Tiano PEI Phase +# +.align 16 +# +# GDT[0]: 000h: Null entry, never used. +# + +GDT_BASE: +BootGdtTable: +# null descriptor +.equ NULL_SEL, . - GDT_BASE # Selector [0] + .word 0 # limit 15:0 + .word 0 # base 15:0 + .byte 0 # base 23:16 + .byte 0 # type + .byte 0 # limit 19:16, flags + .byte 0 # base 31:24 + +# linear data segment descriptor +.equ LINEAR_SEL, . - GDT_BASE # Selector [0x8] + .word 0xFFFF # limit 0xFFFFF + .word 0 # base 0 + .byte 0 + .byte 0x92 # present, ring 0, data, expand-up, writable + .byte 0xCF # page-granular, 32-bit + .byte 0 + +# linear code segment descriptor +.equ LINEAR_CODE_SEL, . - GDT_BASE # Selector [0x10] + .word 0xFFFF # limit 0xFFFFF + .word 0 # base 0 + .byte 0 + .byte 0x9A # present, ring 0, data, expand-up, writable + .byte 0xCF # page-granular, 32-bit + .byte 0 + +# system data segment descriptor +.equ SYS_DATA_SEL, . - GDT_BASE # Selector [0x18] + .word 0xFFFF # limit 0xFFFFF + .word 0 # base 0 + .byte 0 + .byte 0x92 # present, ring 0, data, expand-up, writable + .byte 0xCF # page-granular, 32-bit + .byte 0 + +# system code segment descriptor +.equ SYS_CODE_SEL, . - GDT_BASE + .word 0xFFFF # limit 0xFFFFF + .word 0 # base 0 + .byte 0 + .byte 0x9A # present, ring 0, data, expand-up, writable + .byte 0xCF # page-granular, 32-bit + .byte 0 + +# spare segment descriptor +.equ SYS16_CODE_SEL, . - GDT_BASE + .word 0xffff # limit 0xFFFFF + .word 0 # base 0 + .byte 0x0f + .byte 0x9b # present, ring 0, data, expand-up, writable + .byte 0 # page-granular, 32-bit + .byte 0 + +# spare segment descriptor +.equ SYS16_DATA_SEL, . - GDT_BASE + .word 0xffff # limit 0xFFFFF + .word 0 # base 0 + .byte 0 + .byte 0x93 # present, ring 0, data, expand-up, not-writable + .byte 0 # page-granular, 32-bit + .byte 0 + +# spare segment descriptor +.equ SPARE5_SEL, . - GDT_BASE + .word 0 # limit 0xFFFFF + .word 0 # base 0 + .byte 0 + .byte 0 # present, ring 0, data, expand-up, writable + .byte 0 # page-granular, 32-bit + .byte 0 +.equ GDT_SIZE, . - GDT_BASE + +# +# GDT Descriptor +# +GdtDesc: # GDT descriptor + .word GDT_SIZE - 1 + .long BootGdtTable + +ProtectedModeEntryLinearAddress: +ProtectedModeEntryLinearOffset: + .long ProtectedModeEntryPoint + .word LINEAR_CODE_SEL diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/Ia32/Flat32.asm b/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/Ia32/Flat32.asm new file mode 100644 index 0000000000..45e9e6a84a --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/Ia32/Flat32.asm @@ -0,0 +1,685 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2013-2015 Intel Corporation. +; +; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; Flat32.asm +; +; Abstract: +; +; This is the code that goes from real-mode to protected mode. +; It consumes the reset vector, configures the stack. +; +; +;------------------------------------------------------------------------------ + + +; +; Define assembler characteristics +; +.586p +.model flat, c + +; +; Include processor definitions +; + +INCLUDE Platform.inc + + +; +; CR0 cache control bit definition +; +CR0_CACHE_DISABLE EQU 040000000h +CR0_NO_WRITE EQU 020000000h + +; +; External and public declarations +; TopOfStack is used by C code +; SecStartup is the entry point to the C code +; Neither of these names can be modified without +; updating the C code. +; +EXTRN PlatformSecLibStartup: NEAR +EXTERNDEF C PcdGet32 (PcdEsramStage1Base):DWORD + +; +; Contrary to the name, this file contains 16 bit code as well. +; +_TEXT_REALMODE SEGMENT PARA PUBLIC USE16 'CODE' + ASSUME CS:_TEXT_REALMODE, DS:_TEXT_REALMODE + +;---------------------------------------------------------------------------- +; +; Procedure: _ModuleEntryPoint +; +; Input: None +; +; Output: None +; +; Destroys: Assume all registers +; +; Description: +; +; Transition to non-paged flat-model protected mode from a +; hard-coded GDT that provides exactly two descriptors. +; This is a bare bones transition to protected mode only +; used for a while in PEI and possibly DXE. +; +; After enabling protected mode, a far jump is executed to +; transfer to PEI using the newly loaded GDT. +; +; Return: None +; +;---------------------------------------------------------------------------- +align 16 +_ModuleEntryPoint PROC C PUBLIC + + ; + ; Warm Reset (INIT#) check. + ; + mov si, 0F000h + mov ds, si + mov si, 0FFF0h + cmp BYTE PTR [si], 0EAh ; Is it warm reset ? + jne NotWarmReset ; JIf not. + + mov al, 08 + mov dx, 0cf9h + out dx, al + mov al, 055h + out 080h, al; + jmp $ +NotWarmReset: + + ; + ; Load the GDT table in GdtDesc + ; + mov esi, OFFSET GdtDesc + db 66h + lgdt fword ptr cs:[si] + + ; + ; Transition to 16 bit protected mode + ; + mov eax, cr0 ; Get control register 0 + or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1) + mov cr0, eax ; Activate protected mode + + ; + ; Now we're in 16 bit protected mode + ; Set up the selectors for 32 bit protected mode entry + ; + mov ax, SYS_DATA_SEL + mov ds, ax + mov es, ax + mov fs, ax + mov gs, ax + mov ss, ax + + ; + ; Transition to Flat 32 bit protected mode + ; The jump to a far pointer causes the transition to 32 bit mode + ; + mov esi, offset ProtectedModeEntryLinearAddress + jmp fword ptr cs:[si] + +_ModuleEntryPoint ENDP + +_TEXT_REALMODE ENDS + +.code +; +; Protected mode portion initializes stack, configures cache, and calls C entry point +; + +;---------------------------------------------------------------------------- +; +; Procedure: ProtectedModeEntryPoint +; +; Input: Executing in 32 Bit Protected (flat) mode +; cs: 0-4GB +; ds: 0-4GB +; es: 0-4GB +; fs: 0-4GB +; gs: 0-4GB +; ss: 0-4GB +; +; Output: This function never returns +; +; Destroys: +; ecx +; edi +; esi +; esp +; +; Description: +; Perform any essential early platform initilaisation +; Setup a stack +; Call the main EDKII Sec C code +; +;---------------------------------------------------------------------------- + +ProtectedModeEntryPoint PROC NEAR C PUBLIC + + JMP32 stackless_EarlyPlatformInit + + ; + ; Set up stack pointer + ; + mov esp, PcdGet32(PcdEsramStage1Base) + mov esi, QUARK_ESRAM_MEM_SIZE_BYTES + add esp, esi ; ESP = top of stack (stack grows downwards). + + ; + ; Store the the BIST value in EBP + ; + mov ebp, 00h ; No processor BIST on Quark + + ; + ; Push processor count to stack first, then BIST status (AP then BSP) + ; + mov eax, 1 + cpuid + shr ebx, 16 + and ebx, 0000000FFh + cmp bl, 1 + jae PushProcessorCount + + ; + ; Some processors report 0 logical processors. Effectively 0 = 1. + ; So we fix up the processor count + ; + inc ebx + +PushProcessorCount: + push ebx + + ; + ; We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST + ; for all processor threads + ; + xor ecx, ecx + mov cl, bl +PushBist: + push ebp + loop PushBist + + ; + ; Pass Control into the PEI Core + ; + call PlatformSecLibStartup + + ; + ; PEI Core should never return to here, this is just to capture an invalid return. + ; + jmp $ + +ProtectedModeEntryPoint ENDP + +;---------------------------------------------------------------------------- +; +; Procedure: stackless_EarlyPlatformInit +; +; Input: esp - Return address +; +; Output: None +; +; Destroys: +; eax +; ecx +; dx +; ebp +; +; Description: +; Any essential early platform initialisation required: +; (1) Disable Cache +; (2) Disable NMI's/SMI's +; (3) Setup HMBOUND (defines what memory accesses go to MMIO/RAM) +; (4) Setup eSRAM (provide early memory to the system) +; (5) Setup PCIEXBAR access mechanism +; (6) Open up full SPI flash decode +; +;---------------------------------------------------------------------------- +stackless_EarlyPlatformInit PROC NEAR C PUBLIC + + ; + ; Save return address + ; + mov ebp, esp + + ; + ; Ensure cache is disabled. + ; + mov eax, cr0 + or eax, CR0_CACHE_DISABLE + CR0_NO_WRITE + invd + mov cr0, eax + + ; + ; Disable NMI + ; Good convention suggests you should read back RTC data port after + ; accessing the RTC index port. + ; + mov al, NMI_DISABLE + mov dx, RTC_INDEX + out dx, al + mov dx, RTC_DATA + in al, dx + + ; + ; Disable SMI (Disables SMI wire, not SMI messages) + ; + mov ecx, (OPCODE_SIDEBAND_REG_READ SHL SB_OPCODE_FIELD) OR (HOST_BRIDGE_PORT_ID SHL SB_PORT_FIELD) OR (HMISC2_OFFSET SHL SB_ADDR_FIELD) + JMP32 stackless_SideBand_Read + and eax, NOT (SMI_EN) + mov ecx, (OPCODE_SIDEBAND_REG_WRITE SHL SB_OPCODE_FIELD) OR (HOST_BRIDGE_PORT_ID SHL SB_PORT_FIELD) OR (HMISC2_OFFSET SHL SB_ADDR_FIELD) + JMP32 stackless_SideBand_Write + + ; + ; Before we get going, check SOC Unit Registers to see if we are required to issue a warm/cold reset + ; + mov ecx, (OPCODE_SIDEBAND_ALT_REG_READ SHL SB_OPCODE_FIELD) OR (SOC_UNIT_PORT_ID SHL SB_PORT_FIELD) OR (CFGNONSTICKY_W1_OFFSET SHL SB_ADDR_FIELD) + JMP32 stackless_SideBand_Read + and eax, FORCE_WARM_RESET + jz TestForceColdReset ; Zero means bit clear, we're not requested to warm reset so continue as normal + jmp IssueWarmReset + +TestForceColdReset: + mov ecx, (OPCODE_SIDEBAND_ALT_REG_READ SHL SB_OPCODE_FIELD) OR (SOC_UNIT_PORT_ID SHL SB_PORT_FIELD) OR (CFGSTICKY_W1_OFFSET SHL SB_ADDR_FIELD) + JMP32 stackless_SideBand_Read + and eax, FORCE_COLD_RESET + jz TestHmboundLock ; Zero means bit clear, we're not requested to cold reset so continue as normal + jmp IssueColdReset + + ; + ; Before setting HMBOUND, check it's not locked + ; +TestHmboundLock: + mov ecx, (OPCODE_SIDEBAND_REG_READ SHL SB_OPCODE_FIELD) OR (HOST_BRIDGE_PORT_ID SHL SB_PORT_FIELD) OR (HMBOUND_OFFSET SHL SB_ADDR_FIELD) + JMP32 stackless_SideBand_Read + and eax, HMBOUND_LOCK + jz ConfigHmbound ; Zero means bit clear, we have the config we want so continue as normal + ; + ; Failed to config - store sticky bit debug + ; + mov ecx, (OPCODE_SIDEBAND_ALT_REG_READ SHL SB_OPCODE_FIELD) OR (SOC_UNIT_PORT_ID SHL SB_PORT_FIELD) OR (CFGSTICKY_RW_OFFSET SHL SB_ADDR_FIELD) + JMP32 stackless_SideBand_Read + or eax, RESET_FOR_HMBOUND_LOCK ; Set the bit we're interested in + mov ecx, (OPCODE_SIDEBAND_ALT_REG_WRITE SHL SB_OPCODE_FIELD) OR (SOC_UNIT_PORT_ID SHL SB_PORT_FIELD) OR (CFGSTICKY_RW_OFFSET SHL SB_ADDR_FIELD) + JMP32 stackless_SideBand_Write + jmp IssueWarmReset + + ; + ; Set up the HMBOUND register + ; +ConfigHmbound: + mov eax, HMBOUND_ADDRESS ; Data (Set HMBOUND location) + mov ecx, (OPCODE_SIDEBAND_REG_WRITE SHL SB_OPCODE_FIELD) OR (HOST_BRIDGE_PORT_ID SHL SB_PORT_FIELD) OR (HMBOUND_OFFSET SHL SB_ADDR_FIELD) + JMP32 stackless_SideBand_Write + + ; + ; Enable interrupts to Remote Management Unit when a IMR/SMM/HMBOUND violation occurs. + ; + mov eax, ENABLE_IMR_INTERRUPT ; Data (Set interrupt enable mask) + mov ecx, (OPCODE_SIDEBAND_REG_WRITE SHL SB_OPCODE_FIELD) OR (MEMORY_MANAGER_PORT_ID SHL SB_PORT_FIELD) OR (BIMRVCTL_OFFSET SHL SB_ADDR_FIELD) + JMP32 stackless_SideBand_Write + + ; + ; Set eSRAM address + ; + mov eax, PcdGet32 (PcdEsramStage1Base) ; Data (Set eSRAM location) + shr eax, 18h ; Data (Set eSRAM location) + add eax, BLOCK_ENABLE_PG + mov ecx, (OPCODE_SIDEBAND_REG_WRITE SHL SB_OPCODE_FIELD) OR (MEMORY_MANAGER_PORT_ID SHL SB_PORT_FIELD) OR (ESRAMPGCTRL_BLOCK_OFFSET SHL SB_ADDR_FIELD) + JMP32 stackless_SideBand_Write + ; + ; Check that we're not blocked from setting the config that we want. + ; + mov ecx, (OPCODE_SIDEBAND_REG_READ SHL SB_OPCODE_FIELD) OR (MEMORY_MANAGER_PORT_ID SHL SB_PORT_FIELD) OR (ESRAMPGCTRL_BLOCK_OFFSET SHL SB_ADDR_FIELD) + JMP32 stackless_SideBand_Read + and eax, BLOCK_ENABLE_PG + jnz ConfigPci ; Non-zero means bit set, we have the config we want so continue as normal + ; + ; Failed to config - store sticky bit debug + ; + mov ecx, (OPCODE_SIDEBAND_ALT_REG_READ SHL SB_OPCODE_FIELD) OR (SOC_UNIT_PORT_ID SHL SB_PORT_FIELD) OR (CFGSTICKY_RW_OFFSET SHL SB_ADDR_FIELD) + JMP32 stackless_SideBand_Read + or eax, RESET_FOR_ESRAM_LOCK ; Set the bit we're interested in + mov ecx, (OPCODE_SIDEBAND_ALT_REG_WRITE SHL SB_OPCODE_FIELD) OR (SOC_UNIT_PORT_ID SHL SB_PORT_FIELD) OR (CFGSTICKY_RW_OFFSET SHL SB_ADDR_FIELD) + JMP32 stackless_SideBand_Write + jmp IssueWarmReset + + ; + ; Enable PCIEXBAR + ; +ConfigPci: + mov eax, (EC_BASE + EC_ENABLE) ; Data + mov ecx, (OPCODE_SIDEBAND_REG_WRITE SHL SB_OPCODE_FIELD) OR (MEMORY_ARBITER_PORT_ID SHL SB_PORT_FIELD) OR (AEC_CTRL_OFFSET SHL SB_ADDR_FIELD) + JMP32 stackless_SideBand_Write + + mov eax, (EC_BASE + EC_ENABLE) ; Data + mov ecx, (OPCODE_SIDEBAND_REG_WRITE SHL SB_OPCODE_FIELD) OR (HOST_BRIDGE_PORT_ID SHL SB_PORT_FIELD) OR (HECREG_OFFSET SHL SB_ADDR_FIELD) + JMP32 stackless_SideBand_Write + + ; + ; Open up full 8MB SPI decode + ; + mov ebx, PCI_CFG OR (ILB_PFA SHL 8) OR BDE ; PCI Configuration address + mov eax, DECODE_ALL_REGIONS_ENABLE + JMP32 stackless_PCIConfig_Write + + ; + ; Enable NMI operation + ; Good convention suggests you should read back RTC data port after + ; accessing the RTC index port. + ; + mov al, NMI_ENABLE + mov dx, RTC_INDEX + out dx, al + mov dx, RTC_DATA + in al, dx + + ; + ; Clear Host Bridge SMI, NMI, INTR fields + ; + mov ecx, (OPCODE_SIDEBAND_REG_READ SHL SB_OPCODE_FIELD) OR (HOST_BRIDGE_PORT_ID SHL SB_PORT_FIELD) OR (HLEGACY_OFFSET SHL SB_ADDR_FIELD) + JMP32 stackless_SideBand_Read + and eax, NOT(NMI + SMI + INTR) ; Clear NMI, SMI, INTR fields + mov ecx, (OPCODE_SIDEBAND_REG_WRITE SHL SB_OPCODE_FIELD) OR (HOST_BRIDGE_PORT_ID SHL SB_PORT_FIELD) OR (HLEGACY_OFFSET SHL SB_ADDR_FIELD) + JMP32 stackless_SideBand_Write + + ; + ; Restore return address + ; + mov esp, ebp + RET32 + +IssueWarmReset: + ; + ; Issue Warm Reset request to Remote Management Unit via iLB + ; + mov ax, CF9_WARM_RESET + mov dx, ILB_RESET_REG + out dx, ax + jmp $ ; Stay here until we are reset. + +IssueColdReset: + ; + ; Issue Cold Reset request to Remote Management Unit via iLB + ; + mov ax, CF9_COLD_RESET + mov dx, ILB_RESET_REG + out dx, ax + jmp $ ; Stay here until we are reset. + +stackless_EarlyPlatformInit ENDP + +;---------------------------------------------------------------------------- +; +; Procedure: stackless_SideBand_Read +; +; Input: esp - return address +; ecx[15:8] - Register offset +; ecx[23:16] - Port ID +; ecx[31:24] - Opcode +; +; Output: eax - Data read +; +; Destroys: +; eax +; ebx +; cl +; esi +; +; Description: +; Perform requested sideband read +; +;---------------------------------------------------------------------------- +stackless_SideBand_Read PROC NEAR C PUBLIC + + mov esi, esp ; Save the return address + + ; + ; Load the SideBand Packet Register to generate the transaction + ; + mov ebx, PCI_CFG OR (HOST_BRIDGE_PFA SHL 8) OR MESSAGE_BUS_CONTROL_REG ; PCI Configuration address + mov cl, (ALL_BYTE_EN SHL SB_BE_FIELD) ; Set all Byte Enable bits + xchg eax, ecx + JMP32 stackless_PCIConfig_Write + xchg eax, ecx + + ; + ; Read the SideBand Data Register + ; + mov ebx, PCI_CFG OR (HOST_BRIDGE_PFA SHL 8) OR MESSAGE_DATA_REG ; PCI Configuration address + JMP32 stackless_PCIConfig_Read + + mov esp, esi ; Restore the return address + RET32 + +stackless_SideBand_Read ENDP + +;---------------------------------------------------------------------------- +; +; Procedure: stackless_SideBand_Write +; +; Input: esp - return address +; eax - Data +; ecx[15:8] - Register offset +; ecx[23:16] - Port ID +; ecx[31:24] - Opcode +; +; Output: None +; +; Destroys: +; ebx +; cl +; esi +; +; Description: +; Perform requested sideband write +; +; +;---------------------------------------------------------------------------- +stackless_SideBand_Write PROC NEAR C PUBLIC + + mov esi, esp ; Save the return address + + ; + ; Load the SideBand Data Register with the data + ; + mov ebx, PCI_CFG OR (HOST_BRIDGE_PFA SHL 8) OR MESSAGE_DATA_REG ; PCI Configuration address + JMP32 stackless_PCIConfig_Write + + ; + ; Load the SideBand Packet Register to generate the transaction + ; + mov ebx, PCI_CFG OR (HOST_BRIDGE_PFA SHL 8) OR MESSAGE_BUS_CONTROL_REG ; PCI Configuration address + mov cl, (ALL_BYTE_EN SHL SB_BE_FIELD) ; Set all Byte Enable bits + xchg eax, ecx + JMP32 stackless_PCIConfig_Write + xchg eax, ecx + + mov esp, esi ; Restore the return address + RET32 + +stackless_SideBand_Write ENDP + +;---------------------------------------------------------------------------- +; +; Procedure: stackless_PCIConfig_Write +; +; Input: esp - return address +; eax - Data to write +; ebx - PCI Config Address +; +; Output: None +; +; Destroys: +; dx +; +; Description: +; Perform a DWORD PCI Configuration write +; +;---------------------------------------------------------------------------- +stackless_PCIConfig_Write PROC NEAR C PUBLIC + + ; + ; Write the PCI Config Address to the address port + ; + xchg eax, ebx + mov dx, PCI_ADDRESS_PORT + out dx, eax + xchg eax, ebx + + ; + ; Write the PCI DWORD Data to the data port + ; + mov dx, PCI_DATA_PORT + out dx, eax + + RET32 + +stackless_PCIConfig_Write ENDP + +;---------------------------------------------------------------------------- +; +; Procedure: stackless_PCIConfig_Read +; +; Input: esp - return address +; ebx - PCI Config Address +; +; Output: eax - Data read +; +; Destroys: +; eax +; dx +; +; Description: +; Perform a DWORD PCI Configuration read +; +;---------------------------------------------------------------------------- +stackless_PCIConfig_Read PROC NEAR C PUBLIC + + ; + ; Write the PCI Config Address to the address port + ; + xchg eax, ebx + mov dx, PCI_ADDRESS_PORT + out dx, eax + xchg eax, ebx + + ; + ; Read the PCI DWORD Data from the data port + ; + mov dx, PCI_DATA_PORT + in eax, dx + + RET32 + +stackless_PCIConfig_Read ENDP + +; +; ROM-based Global-Descriptor Table for the Tiano PEI Phase +; +align 16 +PUBLIC BootGdtTable + +; +; GDT[0]: 0x00: Null entry, never used. +; +NULL_SEL equ $ - GDT_BASE ; Selector [0] +GDT_BASE: +BootGdtTable DD 0 + DD 0 +; +; Linear data segment descriptor +; +LINEAR_SEL equ $ - GDT_BASE ; Selector [0x8] + DW 0FFFFh ; limit 0xFFFF + DW 0 ; base 0 + DB 0 + DB 092h ; present, ring 0, data, expand-up, writable + DB 0CFh ; page-granular, 32-bit + DB 0 +; +; Linear code segment descriptor +; +LINEAR_CODE_SEL equ $ - GDT_BASE ; Selector [0x10] + DW 0FFFFh ; limit 0xFFFF + DW 0 ; base 0 + DB 0 + DB 09Bh ; present, ring 0, data, expand-up, not-writable + DB 0CFh ; page-granular, 32-bit + DB 0 +; +; System data segment descriptor +; +SYS_DATA_SEL equ $ - GDT_BASE ; Selector [0x18] + DW 0FFFFh ; limit 0xFFFF + DW 0 ; base 0 + DB 0 + DB 093h ; present, ring 0, data, expand-up, not-writable + DB 0CFh ; page-granular, 32-bit + DB 0 + +; +; System code segment descriptor +; +SYS_CODE_SEL equ $ - GDT_BASE ; Selector [0x20] + DW 0FFFFh ; limit 0xFFFF + DW 0 ; base 0 + DB 0 + DB 09Ah ; present, ring 0, data, expand-up, writable + DB 0CFh ; page-granular, 32-bit + DB 0 +; +; Spare segment descriptor +; +SYS16_CODE_SEL equ $ - GDT_BASE ; Selector [0x28] + DW 0FFFFh ; limit 0xFFFF + DW 0 ; base 0 + DB 0Fh + DB 09Bh ; present, ring 0, code, expand-up, writable + DB 00h ; byte-granular, 16-bit + DB 0 +; +; Spare segment descriptor +; +SYS16_DATA_SEL equ $ - GDT_BASE ; Selector [0x30] + DW 0FFFFh ; limit 0xFFFF + DW 0 ; base 0 + DB 0 + DB 093h ; present, ring 0, data, expand-up, not-writable + DB 00h ; byte-granular, 16-bit + DB 0 + +; +; Spare segment descriptor +; +SPARE5_SEL equ $ - GDT_BASE ; Selector [0x38] + DW 0 ; limit 0xFFFF + DW 0 ; base 0 + DB 0 + DB 0 ; present, ring 0, data, expand-up, writable + DB 0 ; page-granular, 32-bit + DB 0 +GDT_SIZE EQU $ - BootGDTtable ; Size, in bytes + +; +; GDT Descriptor +; +GdtDesc: ; GDT descriptor + DW GDT_SIZE - 1 ; GDT limit + DD OFFSET BootGdtTable ; GDT base address + +ProtectedModeEntryLinearAddress LABEL FWORD +ProtectedModeEntryLinearOffset LABEL DWORD + DD OFFSET ProtectedModeEntryPoint ; Offset of our 32 bit code + DW LINEAR_CODE_SEL + +END diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/Ia32/Platform.inc b/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/Ia32/Platform.inc new file mode 100644 index 0000000000..d3ba5f0cea --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/Ia32/Platform.inc @@ -0,0 +1,134 @@ +; +; Copyright (c) 2013-2015 Intel Corporation. +; +; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;------------------------------------------------------------------------------ +; +; Module Name: +; +; Platform.inc +; +; Abstract: +; +; Quark A0 Platform Specific Definitions +; +;------------------------------------------------------------------------------ + +JMP32 MACRO FunctionName + lea esp, @F + jmp FunctionName +@@: +ENDM + +RET32 MACRO + jmp esp +ENDM + +; +; ROM/SPI/MEMORY Definitions +; +QUARK_DDR3_MEM_BASE_ADDRESS EQU 000000000h ; Memory Base Address = 0 +QUARK_MAX_DDR3_MEM_SIZE_BYTES EQU 080000000h ; DDR3 Memory Size = 2GB +QUARK_ESRAM_MEM_SIZE_BYTES EQU 000080000h ; eSRAM Memory Size = 512K +QUARK_STACK_SIZE_BYTES EQU 008000h ; Quark stack size = 32K + +; +; RTC/CMOS definitions +; +RTC_INDEX EQU 070h + NMI_DISABLE EQU 080h ; Bit7=1 disables NMI + NMI_ENABLE EQU 000h ; Bit7=0 disables NMI +RTC_DATA EQU 071h + +; +; PCI Configuration definitions +; +PCI_CFG EQU 1 SHL 01Fh ; PCI configuration access mechanism +PCI_ADDRESS_PORT EQU 0CF8h +PCI_DATA_PORT EQU 0CFCh + +; +; Quark PCI devices +; +HOST_BRIDGE_PFA EQU 0000h ; B0:D0:F0 (Host Bridge) +ILB_PFA EQU 00F8h ; B0:D31:F0 (Legacy Block) + +; +; ILB PCI Config Registers +; +BDE EQU 0D4h ; BIOS Decode Enable register + DECODE_ALL_REGIONS_ENABLE EQU 0FF000000h ; Decode all BIOS decode ranges + + +; +; iLB Reset Register +; +ILB_RESET_REG EQU 0CF9h + CF9_WARM_RESET EQU 02h + CF9_COLD_RESET EQU 08h + +; +; Host Bridge PCI Config Registers +; +MESSAGE_BUS_CONTROL_REG EQU 0D0h ; Message Bus Control Register + SB_OPCODE_FIELD EQU 018h ; Bit location of Opcode field + OPCODE_SIDEBAND_REG_READ EQU 010h ; Read opcode + OPCODE_SIDEBAND_REG_WRITE EQU 011h ; Write opcode + OPCODE_SIDEBAND_ALT_REG_READ EQU 06h ; Alternate Read opcode + OPCODE_SIDEBAND_ALT_REG_WRITE EQU 07h ; Alternate Write opcode + OPCODE_WARM_RESET_REQUEST EQU 0F4h ; Reset Warm + OPCODE_COLD_RESET_REQUEST EQU 0F5h ; Reset Cold + SB_PORT_FIELD EQU 010h ; Bit location of Port ID field + MEMORY_ARBITER_PORT_ID EQU 00h + HOST_BRIDGE_PORT_ID EQU 03h + RMU_PORT_ID EQU 04h + MEMORY_MANAGER_PORT_ID EQU 05h + SOC_UNIT_PORT_ID EQU 031h + SB_ADDR_FIELD EQU 008h ; Bit location of Register field + SB_BE_FIELD EQU 004h ; Bit location of Byte Enables field + ALL_BYTE_EN EQU 00Fh ; All Byte Enables +MESSAGE_DATA_REG EQU 0D4h ; Message Data Register + +; +; Memory Arbiter Config Registers +; +AEC_CTRL_OFFSET EQU 00h + +; +; Host Bridge Config Registers +; +HMISC2_OFFSET EQU 03h + OR_PM_FIELD EQU 010h + SMI_EN EQU 1 SHL 13h + +HMBOUND_OFFSET EQU 08h + HMBOUND_ADDRESS EQU (QUARK_DDR3_MEM_BASE_ADDRESS + QUARK_MAX_DDR3_MEM_SIZE_BYTES + QUARK_ESRAM_MEM_SIZE_BYTES) + HMBOUND_LOCK EQU 00000001h +HECREG_OFFSET EQU 09h + EC_BASE EQU 0E0000000h + EC_ENABLE EQU 01h +HLEGACY_OFFSET EQU 0Ah + NMI EQU 1 SHL 0Eh ; Pin 14 + SMI EQU 1 SHL 0Ch ; Pin 12 + INTR EQU 1 SHL 0Ah ; Pin 10 + + +; +; Memory Manager Config Registers +; +ESRAMPGCTRL_BLOCK_OFFSET EQU 082h + BLOCK_ENABLE_PG EQU 010000000h +BIMRVCTL_OFFSET EQU 019h + ENABLE_IMR_INTERRUPT EQU 080000000h + +; +; SOC UNIT Debug Registers +; +CFGSTICKY_W1_OFFSET EQU 050h + FORCE_COLD_RESET EQU 00000001h +CFGSTICKY_RW_OFFSET EQU 051h + RESET_FOR_ESRAM_LOCK EQU 00000020h + RESET_FOR_HMBOUND_LOCK EQU 00000040h +CFGNONSTICKY_W1_OFFSET EQU 052h + FORCE_WARM_RESET EQU 00000001h diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/PlatformSecLib.c b/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/PlatformSecLib.c new file mode 100644 index 0000000000..9383d3dfbf --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/PlatformSecLib.c @@ -0,0 +1,207 @@ +/** @file +Platform SEC Library for Quark. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + + Entry point to the C language phase of SEC. After the SEC assembly + code has initialized some temporary memory and set up the stack, + the control is transferred to this function. + + @param SizeOfRam Size of the temporary memory available for use. + @param TempRamBase Base address of temporary ram + @param BootFirmwareVolume Base address of the Boot Firmware Volume. + +**/ +VOID +EFIAPI +SecStartup ( + IN UINT32 SizeOfRam, + IN UINT32 TempRamBase, + IN VOID *BootFirmwareVolume + ); + +/** + Auto-generated function that calls the library constructors for all of the module's + dependent libraries. This function must be called by the SEC Core once a stack has + been established. + +**/ +VOID +EFIAPI +ProcessLibraryConstructorList ( + VOID + ); + +/** + + Entry point to the C language phase of PlatformSecLib. After the SEC assembly + code has initialized some temporary memory and set up the stack, control is + transferred to this function. + +**/ +VOID +EFIAPI +PlatformSecLibStartup ( + VOID + ) +{ + // + // Process all library constructor functions linked to SecCore. + // This function must be called before any library functions are called + // + ProcessLibraryConstructorList (); + + // + // Set write back cache attribute for SPI FLASH + // + MtrrSetMemoryAttribute ( + PcdGet32 (PcdFlashAreaBaseAddress), + PcdGet32 (PcdFlashAreaSize), + CacheWriteBack + ); + + // + // Set write back cache attribute for 512KB Embedded SRAM + // + MtrrSetMemoryAttribute ( + PcdGet32 (PcdEsramStage1Base), + SIZE_512KB, + CacheWriteBack + ); + + // + // Pass control to SecCore module passing in the size of the temporary RAM in + // Embedded SRAM, the base address of the temporary RAM in Embedded SRAM, and + // the base address of the boot firmware volume. The top 32KB of the 512 KB + // embedded SRAM are used as temporary RAM. + // + SecStartup ( + SIZE_32KB, + PcdGet32 (PcdEsramStage1Base) + SIZE_512KB - SIZE_32KB, + (VOID *)(UINTN)PcdGet32 (PcdFlashFvRecoveryBase) + ); +} + +/** + A developer supplied function to perform platform specific operations. + + It's a developer supplied function to perform any operations appropriate to a + given platform. It's invoked just before passing control to PEI core by SEC + core. Platform developer may modify the SecCoreData and PPI list that is + passed to PEI Core. + + @param SecCoreData The same parameter as passing to PEI core. It + could be overridden by this function. + @param PpiList The default PPI list passed from generic SEC + part. + + @return The final PPI list that platform wishes to passed to PEI core. + +**/ +EFI_PEI_PPI_DESCRIPTOR * +EFIAPI +SecPlatformMain ( + IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData, + IN EFI_PEI_PPI_DESCRIPTOR *PpiList + ) +{ + return NULL; +} + +/** + This interface conveys state information out of the Security (SEC) phase into PEI. + + @param PeiServices Pointer to the PEI Services Table. + @param StructureSize Pointer to the variable describing size of the input buffer. + @param PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD. + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_BUFFER_TOO_SMALL The buffer was too small. + +**/ +EFI_STATUS +EFIAPI +SecPlatformInformation ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *StructureSize, + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord + ) +{ + UINT32 *BIST; + UINT32 Size; + UINT32 Count; + EFI_HOB_GUID_TYPE *GuidHob; + UINT32 *TopOfStack; + + // + // Top of the stack is the top of the 512KB Embedded SRAM region + // + TopOfStack = (UINT32 *)(UINTN)(PcdGet32 (PcdEsramStage1Base) + SIZE_512KB); + + GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformationPpiGuid); + if (GuidHob != NULL) { + Size = GET_GUID_HOB_DATA_SIZE (GuidHob); + BIST = GET_GUID_HOB_DATA (GuidHob); + } else { + // + // The entries of BIST information, together with the number of them, + // reside in the bottom of stack, left untouched by normal stack operation. + // This routine copies the BIST information to the buffer pointed by + // PlatformInformationRecord for output. + // + Count = *(TopOfStack - 1); + Size = Count * sizeof (IA32_HANDOFF_STATUS); + BIST = (UINT32 *) ((UINT32) TopOfStack - sizeof (UINT32) - Size); + + // + // Copy Data from Stack to Hob to avoid data is lost after memory is ready. + // + BuildGuidDataHob ( + &gEfiSecPlatformInformationPpiGuid, + BIST, + (UINTN)Size + ); + GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformationPpiGuid); + Size = GET_GUID_HOB_DATA_SIZE (GuidHob); + BIST = GET_GUID_HOB_DATA (GuidHob); + } + + if ((*StructureSize) < (UINT64) Size) { + *StructureSize = Size; + return EFI_BUFFER_TOO_SMALL; + } + + *StructureSize = Size; + CopyMem (PlatformInformationRecord, BIST, Size); + + return EFI_SUCCESS; +} + +/** + This interface disables temporary memory in SEC Phase. +**/ +VOID +EFIAPI +SecPlatformDisableTemporaryMemory ( + VOID + ) +{ +} diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/PlatformSecLib.inf b/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/PlatformSecLib.inf new file mode 100644 index 0000000000..a246a38564 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/PlatformSecLib.inf @@ -0,0 +1,54 @@ +#/** @file +# Platform SEC Library for Quark. +# +# Copyright (c) 2013-2015 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformSecLib + FILE_GUID = 8DE4221F-A9CC-4c78-85B9-D863681F0C01 + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformSecLib + MODULE_UNI_FILE = PlatformSecLibModStrs.uni + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 +# + +[Sources] + PlatformSecLib.c + +[Sources.IA32] + Ia32/Flat32.asm | MSFT + Ia32/Flat32.asm | INTEL + Ia32/Flat32.S | GCC + +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + +[LibraryClasses] + DebugLib + BaseLib + BaseMemoryLib + PciLib + PcdLib + HobLib + MtrrLib + +[Pcd] + gQuarkPlatformTokenSpaceGuid.PcdEsramStage1Base ## CONSUMES + gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoveryBase ## CONSUMES + gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES + gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES + +[Ppis] + gEfiSecPlatformInformationPpiGuid ## UNDEFINED # it is used as GUIDED HOB diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/PlatformSecLibModStrs.uni b/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/PlatformSecLibModStrs.uni new file mode 100644 index 0000000000..fb16f0f320 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecLib/PlatformSecLibModStrs.uni @@ -0,0 +1,18 @@ +// /** @file +// PlatformSecLib Localized Abstract and Description Content +// +// Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_MODULE_ABSTRACT +#language en-US +"SEC Platform Library " + +#string STR_MODULE_DESCRIPTION +#language en-US +"Provides a platform-specific function to be used during the SEC stage of POST. " + + diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecureLib/PlatformSecureLib.c b/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecureLib/PlatformSecureLib.c new file mode 100644 index 0000000000..8105a11d52 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecureLib/PlatformSecureLib.c @@ -0,0 +1,164 @@ +/** @file +Provides a secure platform-specific method to detect physically present user. + +Copyright (c) 2013 - 2016 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +#include +#include +#include + +// +// Global variable to cache pointer to I2C protocol. +// +EFI_PLATFORM_TYPE mPlatformType = TypeUnknown; + +BOOLEAN +CheckResetButtonState ( + VOID + ) +{ + EFI_STATUS Status; + EFI_I2C_DEVICE_ADDRESS I2CSlaveAddress; + UINTN Length; + UINTN ReadLength; + UINT8 Buffer[2]; + + DEBUG ((EFI_D_INFO, "CheckResetButtonState(): mPlatformType == %d\n", mPlatformType)); + if (mPlatformType == GalileoGen2) { + // + // Read state of Reset Button - EXP2.P1_7 + // This GPIO is pulled high when the button is not pressed + // This GPIO reads low when button is pressed + // + return PlatformPcal9555GpioGetState ( + GALILEO_GEN2_IOEXP2_7BIT_SLAVE_ADDR, // IO Expander 2. + 15 // P1-7. + ); + } + if (mPlatformType == Galileo) { + // + // Detect the I2C Slave Address of the GPIO Expander + // + if (PlatformLegacyGpioGetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)) { + I2CSlaveAddress.I2CDeviceAddress = GALILEO_IOEXP_J2HI_7BIT_SLAVE_ADDR; + } else { + I2CSlaveAddress.I2CDeviceAddress = GALILEO_IOEXP_J2LO_7BIT_SLAVE_ADDR; + } + DEBUG ((EFI_D_INFO, "Galileo GPIO Expender Slave Address = %02x\n", I2CSlaveAddress.I2CDeviceAddress)); + + // + // Read state of RESET_N_SHLD (GPORT5_BIT0) + // + Buffer[1] = 5; + Length = 1; + ReadLength = 1; + Status = I2cReadMultipleByte ( + I2CSlaveAddress, + EfiI2CSevenBitAddrMode, + &Length, + &ReadLength, + &Buffer[1] + ); + ASSERT_EFI_ERROR (Status); + + // + // Return the state of GPORT5_BIT0 + // + return ((Buffer[1] & BIT0) != 0); + } + return TRUE; +} + +/** + + This function provides a platform-specific method to detect whether the platform + is operating by a physically present user. + + Programmatic changing of platform security policy (such as disable Secure Boot, + or switch between Standard/Custom Secure Boot mode) MUST NOT be possible during + Boot Services or after exiting EFI Boot Services. Only a physically present user + is allowed to perform these operations. + + NOTE THAT: This function cannot depend on any EFI Variable Service since they are + not available when this function is called in AuthenticateVariable driver. + + @retval TRUE The platform is operated by a physically present user. + @retval FALSE The platform is NOT operated by a physically present user. + +**/ +BOOLEAN +EFIAPI +UserPhysicalPresent ( + VOID + ) +{ + EFI_STATUS Status; + + // + // If user has already been detected as present, then return TRUE + // + if (PcdGetBool (PcdUserIsPhysicallyPresent)) { + return TRUE; + } + + // + // Check to see if user is present now + // + if (CheckResetButtonState ()) { + // + // User is still not present, then return FALSE + // + return FALSE; + } + + // + // User has gone from not present to present state, so set + // PcdUserIsPhysicallyPresent to TRUE + // + Status = PcdSetBoolS (PcdUserIsPhysicallyPresent, TRUE); + ASSERT_EFI_ERROR (Status); + + return TRUE; +} + +/** + Determines if a user is physically present by reading the reset button state. + + @param ImageHandle The image handle of this driver. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS Install the Secure Boot Helper Protocol successfully. + +**/ +EFI_STATUS +EFIAPI +PlatformSecureLibInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + // + // Get the platform type + // + mPlatformType = (EFI_PLATFORM_TYPE)PcdGet16 (PcdPlatformType); + + // + // Read the state of the reset button when the library is initialized + // + Status = PcdSetBoolS (PcdUserIsPhysicallyPresent, !CheckResetButtonState ()); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecureLib/PlatformSecureLib.inf b/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecureLib/PlatformSecureLib.inf new file mode 100644 index 0000000000..ef7b21faf5 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/PlatformSecureLib/PlatformSecureLib.inf @@ -0,0 +1,41 @@ +## @file +# Provides a secure platform-specific method to detect physically present user. +# +# Copyright (c) 2013 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformSecureLib + FILE_GUID = 38BB5221-F685-469f-846E-F1C508FC5F4A + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformSecureLib|DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_DRIVER + CONSTRUCTOR = PlatformSecureLibInitialize + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 +# + +[Sources] + PlatformSecureLib.c + +[Packages] + MdePkg/MdePkg.dec + QuarkSocPkg/QuarkSocPkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + +[LibraryClasses] + DebugLib + PlatformHelperLib + UefiBootServicesTableLib + I2cLib + +[Pcd] + gQuarkPlatformTokenSpaceGuid.PcdPlatformType + gQuarkPlatformTokenSpaceGuid.PcdUserIsPhysicallyPresent diff --git a/Platform/Intel/QuarkPlatformPkg/Library/Tpm12DeviceLibAtmelI2c/TisPc.c b/Platform/Intel/QuarkPlatformPkg/Library/Tpm12DeviceLibAtmelI2c/TisPc.c new file mode 100644 index 0000000000..dcec86aa83 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/Tpm12DeviceLibAtmelI2c/TisPc.c @@ -0,0 +1,408 @@ +/** @file + Basic TIS (TPM Interface Specification) functions for Atmel I2C TPM. + + Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +// +// Atmel I2C TPM slave address +// +#define ATMEL_I2C_TPM_SLAVE_ADDRESS 0x29 + +// +// Maximum I2C transfer size for Atmel I2C TPM +// +#define ATMEL_I2C_TPM_MAX_TRANSFER_SIZE 0x10 + +// +// Default TimeOut values in microseconds +// +#define TIS_TIMEOUT_A ( 750 * 1000) // 750ms +#define TIS_TIMEOUT_B (2000 * 1000) // 2s +#define TIS_TIMEOUT_C ( 750 * 1000) // 750ms +#define TIS_TIMEOUT_D ( 750 * 1000) // 750ms + +/** + Send command to Atmel I2c TPM breaking request up into multiple I2C transfers + if required. + + @param[in] Buffer Pointer to TPM command data. + @param[in] Length Number of bytes of TPM command data. + + @retval EFI_SUCCESS TPM command sent. + @retval EFI_NOT_FOUND TPM chip doesn't exit. + @retval EFI_TIMEOUT Can't get the TPM control in time. +**/ +EFI_STATUS +WriteTpmBufferMultiple ( + IN UINT8 *Buffer, + IN UINTN Length + ) +{ + EFI_STATUS Status; + EFI_I2C_DEVICE_ADDRESS I2CDeviceAddr; + UINTN Index; + UINTN PartialLength; + + Status = EFI_SUCCESS; + + I2CDeviceAddr.I2CDeviceAddress = ATMEL_I2C_TPM_SLAVE_ADDRESS; + + DEBUG ((EFI_D_VERBOSE, "WriteTpmBufferMultiple: Addr=%02x Length=%02x\n", I2CDeviceAddr.I2CDeviceAddress, Length)); + + for (PartialLength = 0; Length > 0; Length -= PartialLength, Buffer += PartialLength) { + // + // Write data to TPM. + // + PartialLength = MIN (Length, ATMEL_I2C_TPM_MAX_TRANSFER_SIZE); + Status = I2cWriteMultipleByte ( + I2CDeviceAddr, + EfiI2CSevenBitAddrMode, + &PartialLength, + Buffer + ); + DEBUG ((EFI_D_VERBOSE, " ")); + for (Index = 0; Index < PartialLength; Index++) { + DEBUG ((EFI_D_VERBOSE, "%02x ", Buffer[Index])); + } + DEBUG ((EFI_D_VERBOSE, "\n")); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_VERBOSE, " Status = %r\n", Status)); + return Status; + } + } + + DEBUG ((EFI_D_VERBOSE, " Status = %r\n", Status)); + return Status; +} + +/** + Receive a response to a command from Atmel I2c TPM breaking response into + multiple I2C transfers if required. + + @param[out] Buffer Pointer to TPM response data. + @param[in] Length Maximum number of bytes to receive. + + @retval EFI_SUCCESS TPM response received. + @retval EFI_NOT_FOUND TPM chip doesn't exit. + @retval EFI_TIMEOUT Can't get the TPM control in time. +**/ +EFI_STATUS +ReadTpmBufferMultiple ( + OUT UINT8 *Buffer, + IN UINTN Length + ) +{ + EFI_STATUS Status; + EFI_I2C_DEVICE_ADDRESS I2CDeviceAddr; + UINTN WriteLength; + UINTN Index; + UINTN PartialLength; + + Status = EFI_SUCCESS; + + I2CDeviceAddr.I2CDeviceAddress = ATMEL_I2C_TPM_SLAVE_ADDRESS; + WriteLength = 0; + + DEBUG ((EFI_D_VERBOSE, "ReadTpmBufferMultiple: Addr=%02x Length=%02x\n", I2CDeviceAddr.I2CDeviceAddress, Length)); + + for (PartialLength = 0; Length > 0; Length -= PartialLength, Buffer += PartialLength) { + // + // Read data from TPM. + // + PartialLength = MIN (Length, ATMEL_I2C_TPM_MAX_TRANSFER_SIZE); + Status = I2cReadMultipleByte ( + I2CDeviceAddr, + EfiI2CSevenBitAddrMode, + &WriteLength, + &PartialLength, + Buffer + ); + if (!EFI_ERROR (Status)) { + DEBUG ((EFI_D_VERBOSE, " ")); + for (Index = 0; Index < PartialLength; Index++) { + DEBUG ((EFI_D_VERBOSE, "%02x ", Buffer[Index])); + } + DEBUG ((EFI_D_VERBOSE, "\n")); + } + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_VERBOSE, " Status = %r\n", Status)); + return Status; + } + } + + DEBUG ((EFI_D_VERBOSE, " Status = %r\n", Status)); + return Status; +} + +/** + This service requests use TPM12. + + @retval EFI_SUCCESS Get the control of TPM12 chip. + @retval EFI_NOT_FOUND TPM12 not found. + @retval EFI_DEVICE_ERROR Unexpected device behavior. +**/ +EFI_STATUS +EFIAPI +Tpm12RequestUseTpm ( + VOID + ) +{ + EFI_STATUS Status; + UINT8 Data; + UINT64 Current; + UINT64 Previous; + UINT64 Total; + UINT64 Start; + UINT64 End; + UINT64 Timeout; + INT64 Cycle; + INT64 Delta; + + // + // Get the current timer value + // + Current = GetPerformanceCounter(); + + // + // Initialize local variables + // + Start = 0; + End = 0; + Total = 0; + + // + // Retrieve the performance counter properties and compute the number of + // performance counter ticks required to reach the maximum TIS timeout of + // TIS_TIMEOUT_A. TIS_TIMEOUT_A is in microseconds. + // + Timeout = DivU64x32 ( + MultU64x32 ( + GetPerformanceCounterProperties (&Start, &End), + TIS_TIMEOUT_A + ), + 1000000 + ); + Cycle = End - Start; + if (Cycle < 0) { + Cycle = -Cycle; + } + Cycle++; + + // + // Attempt to read a byte from the Atmel I2C TPM + // + do { + Status = ReadTpmBufferMultiple (&Data, sizeof(Data)); + + Previous = Current; + Current = GetPerformanceCounter(); + Delta = (INT64) (Current - Previous); + if (Start > End) { + Delta = -Delta; + } + if (Delta < 0) { + Delta += Cycle; + } + Total += Delta; + if (Total >= Timeout) { + Status = EFI_TIMEOUT; + DEBUG ((EFI_D_ERROR, "Atmel I2C TPM failed to read: %r\n", Status)); + return Status; + } + } while (EFI_ERROR (Status)); + + return EFI_SUCCESS; +} + +/** + This service enables the sending of commands to the TPM12. + + @param[in] InputParameterBlockSize Size of the TPM12 input parameter block. + @param[in] InputParameterBlock Pointer to the TPM12 input parameter block. + @param[in,out] OutputParameterBlockSize Size of the TPM12 output parameter block. + @param[in] OutputParameterBlock Pointer to the TPM12 output parameter block. + + @retval EFI_SUCCESS The command byte stream was successfully sent to + the device and a response was successfully received. + @retval EFI_DEVICE_ERROR The command was not successfully sent to the + device or a response was not successfully received + from the device. + @retval EFI_BUFFER_TOO_SMALL The output parameter block is too small. +**/ +EFI_STATUS +EFIAPI +Tpm12SubmitCommand ( + IN UINT32 InputParameterBlockSize, + IN UINT8 *InputParameterBlock, + IN OUT UINT32 *OutputParameterBlockSize, + IN UINT8 *OutputParameterBlock + ) +{ + EFI_STATUS Status; + UINT32 TpmOutSize; + TPM_RSP_COMMAND_HDR *ResponseHeader; + UINT64 Current; + UINT64 Previous; + UINT64 Total; + UINT64 Start; + UINT64 End; + UINT64 Timeout; + INT64 Cycle; + INT64 Delta; + + // + // Initialize local variables + // + Start = 0; + End = 0; + Total = 0; + + // + // Make sure response buffer is big enough to hold a response header + // + if (*OutputParameterBlockSize < sizeof (TPM_RSP_COMMAND_HDR)) { + Status = EFI_BUFFER_TOO_SMALL; + goto Done; + } + + // + // Get the current timer value + // + Current = GetPerformanceCounter(); + + // + // Retrieve the performance counter properties and compute the number of + // performance counter ticks required to reach the maximum TIS timeout of + // TIS_TIMEOUT_A. TIS_TIMEOUT_A is in microseconds. + // + Timeout = DivU64x32 ( + MultU64x32 ( + GetPerformanceCounterProperties (&Start, &End), + TIS_TIMEOUT_A + ), + 1000000 + ); + Cycle = End - Start; + if (Cycle < 0) { + Cycle = -Cycle; + } + Cycle++; + + // + // Send command + // + do { + Status = WriteTpmBufferMultiple (InputParameterBlock, InputParameterBlockSize); + + Previous = Current; + Current = GetPerformanceCounter(); + Delta = (INT64) (Current - Previous); + if (Start > End) { + Delta = -Delta; + } + if (Delta < 0) { + Delta += Cycle; + } + Total += Delta; + if (Total >= Timeout) { + Status = EFI_TIMEOUT; + goto Done; + } + } while (EFI_ERROR (Status)); + + // + // Receive response header + // + do { + Status = ReadTpmBufferMultiple (OutputParameterBlock, sizeof (TPM_RSP_COMMAND_HDR)); + + Previous = Current; + Current = GetPerformanceCounter(); + Delta = (INT64) (Current - Previous); + if (Start > End) { + Delta = -Delta; + } + if (Delta < 0) { + Delta += Cycle; + } + Total += Delta; + if (Total >= Timeout) { + Status = EFI_TIMEOUT; + goto Done; + } + } while (EFI_ERROR (Status)); + + // + // Check the response data header (tag, parasize and returncode) + // + ResponseHeader = (TPM_RSP_COMMAND_HDR *)OutputParameterBlock; + if (SwapBytes16 (ReadUnaligned16 (&ResponseHeader->tag)) != TPM_TAG_RSP_COMMAND) { + Status = EFI_DEVICE_ERROR; + goto Done; + } + + TpmOutSize = SwapBytes32 (ReadUnaligned32 (&ResponseHeader->paramSize)); + if (TpmOutSize == sizeof (TPM_RSP_COMMAND_HDR)) { + *OutputParameterBlockSize = TpmOutSize; + Status = EFI_SUCCESS; + goto Done; + } + if (TpmOutSize < sizeof (TPM_RSP_COMMAND_HDR)) { + Status = EFI_DEVICE_ERROR; + goto Done; + } + if (*OutputParameterBlockSize < TpmOutSize) { + Status = EFI_BUFFER_TOO_SMALL; + goto Done; + } + *OutputParameterBlockSize = TpmOutSize; + + // + // Receive the remaining data in the response header + // + do { + Status = ReadTpmBufferMultiple ( + OutputParameterBlock + sizeof (TPM_RSP_COMMAND_HDR), + TpmOutSize - sizeof (TPM_RSP_COMMAND_HDR) + ); + + Previous = Current; + Current = GetPerformanceCounter(); + Delta = (INT64) (Current - Previous); + if (Start > End) { + Delta = -Delta; + } + if (Delta < 0) { + Delta += Cycle; + } + Total += Delta; + if (Total >= Timeout) { + Status = EFI_TIMEOUT; + goto Done; + } + } while (EFI_ERROR (Status)); + +Done: + DEBUG (( + EFI_D_VERBOSE, + "Tpm12SubmitCommand() Status = %r Time = %ld ms\n", + Status, + DivU64x64Remainder ( + MultU64x32 (Total, 1000), + GetPerformanceCounterProperties (NULL, NULL), + NULL + ) + )); + + return Status; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Library/Tpm12DeviceLibAtmelI2c/Tpm12DeviceLibAtmelI2c.inf b/Platform/Intel/QuarkPlatformPkg/Library/Tpm12DeviceLibAtmelI2c/Tpm12DeviceLibAtmelI2c.inf new file mode 100644 index 0000000000..99117064bf --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/Tpm12DeviceLibAtmelI2c/Tpm12DeviceLibAtmelI2c.inf @@ -0,0 +1,39 @@ +## @file +# Provides some common functions for the TCG feature for Atmel I2C TPM. +# +# This instance provides basic TPM Interface Specification (TIS) functions +# or Atmel I2C TPM. +# +# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = Tpm12DeviceLibAtmelI2c + MODULE_UNI_FILE = Tpm12DeviceLibAtmelI2c.uni + FILE_GUID = A0C0B7EF-99FF-417F-8B9F-5AD4701D90D6 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = Tpm12DeviceLib|PEIM DXE_DRIVER DXE_SMM_DRIVER UEFI_DRIVER + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 +# + +[Sources] + TisPc.c + +[Packages] + MdePkg/MdePkg.dec + SecurityPkg/SecurityPkg.dec + QuarkSocPkg/QuarkSocPkg.dec + +[LibraryClasses] + BaseLib + TimerLib + DebugLib + I2cLib diff --git a/Platform/Intel/QuarkPlatformPkg/Library/Tpm12DeviceLibAtmelI2c/Tpm12DeviceLibAtmelI2c.uni b/Platform/Intel/QuarkPlatformPkg/Library/Tpm12DeviceLibAtmelI2c/Tpm12DeviceLibAtmelI2c.uni new file mode 100644 index 0000000000..7eb8b1d945 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/Tpm12DeviceLibAtmelI2c/Tpm12DeviceLibAtmelI2c.uni @@ -0,0 +1,16 @@ +// /** @file +// Provides some common functions for the TCG feature for Atmel I2C TPM. +// +// This instance provides basic TPM Interface Specification (TIS) functions +// for Atmel I2C TPM. +// +// Copyright (c) 2016, Intel Corporation. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_MODULE_ABSTRACT #language en-US "Provides some common functions for the TCG feature for Atmel I2C TPM." + +#string STR_MODULE_DESCRIPTION #language en-US "This instance provides basic TPM Interface Specification (TIS) functions for Atmel I2C TPM." + diff --git a/Platform/Intel/QuarkPlatformPkg/Library/Tpm12DeviceLibInfineonI2c/TisPc.c b/Platform/Intel/QuarkPlatformPkg/Library/Tpm12DeviceLibInfineonI2c/TisPc.c new file mode 100644 index 0000000000..c7862a0def --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/Tpm12DeviceLibInfineonI2c/TisPc.c @@ -0,0 +1,612 @@ +/** @file + Basic TIS (TPM Interface Specification) functions for Infineon I2C TPM. + + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +// +// Default TPM (Infineon SLB9645) I2C Slave Device Address on Crosshill board. +// +#define TPM_I2C_SLAVE_DEVICE_ADDRESS 0x20 + +// +// Default Infineon SLB9645 TPM I2C mapped registers (SLB9645 I2C Comm. Protocol Application Note). +// +#define INFINEON_TPM_ACCESS_0_ADDRESS_DEFAULT 0x0 +#define INFINEON_TPM_STS_0_ADDRESS_DEFAULT 0x01 +#define INFINEON_TPM_BURST0_COUNT_0_DEFAULT 0x02 +#define INFINEON_TPM_BURST1_COUNT_0_DEFAULT 0x03 +#define INFINEON_TPM_DATA_FIFO_0_ADDRESS_DEFAULT 0x05 +#define INFINEON_TPM_DID_VID_0_DEFAULT 0x09 + +// +// Max. retry count for read transfers (as recommended by Infineon). +// +#define READ_RETRY 3 + +// +// Guard time of 250us between I2C read and next I2C write transfer (as recommended by Infineon). +// +#define GUARD_TIME 250 + +// +// Define bits of ACCESS and STATUS registers +// + +/// +/// This bit is a 1 to indicate that the other bits in this register are valid. +/// +#define TIS_PC_VALID BIT7 +/// +/// Indicate that this locality is active. +/// +#define TIS_PC_ACC_ACTIVE BIT5 +/// +/// Set to 1 to indicate that this locality had the TPM taken away while +/// this locality had the TIS_PC_ACC_ACTIVE bit set. +/// +#define TIS_PC_ACC_SEIZED BIT4 +/// +/// Set to 1 to indicate that TPM MUST reset the +/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the +/// locality that is writing this bit. +/// +#define TIS_PC_ACC_SEIZE BIT3 +/// +/// When this bit is 1, another locality is requesting usage of the TPM. +/// +#define TIS_PC_ACC_PENDIND BIT2 +/// +/// Set to 1 to indicate that this locality is requesting to use TPM. +/// +#define TIS_PC_ACC_RQUUSE BIT1 +/// +/// A value of 1 indicates that a T/OS has not been established on the platform +/// +#define TIS_PC_ACC_ESTABLISH BIT0 + +/// +/// When this bit is 1, TPM is in the Ready state, +/// indicating it is ready to receive a new command. +/// +#define TIS_PC_STS_READY BIT6 +/// +/// Write a 1 to this bit to cause the TPM to execute that command. +/// +#define TIS_PC_STS_GO BIT5 +/// +/// This bit indicates that the TPM has data available as a response. +/// +#define TIS_PC_STS_DATA BIT4 +/// +/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command. +/// +#define TIS_PC_STS_EXPECT BIT3 +/// +/// Writes a 1 to this bit to force the TPM to re-send the response. +/// +#define TIS_PC_STS_RETRY BIT1 + +// +// Default TimeOut values in microseconds +// +#define TIS_TIMEOUT_A (750 * 1000) // 750ms +#define TIS_TIMEOUT_B (2000 * 1000) // 2s +#define TIS_TIMEOUT_C (750 * 1000) // 750ms +#define TIS_TIMEOUT_D (750 * 1000) // 750ms + +// +// Global variable to indicate if TPM I2C Read Transfer has previously occurred. +// NOTE: Given the GUARD_TIME requirement (TpmAccess.h), if this library loaded +// by PEI Drivers this global variable required to be resident in R/W memory +// +BOOLEAN mI2CPrevReadTransfer = FALSE; + +/** + Writes single byte data to TPM specified by I2C register address. + + @param[in] TpmAddress The register to write. + @param[in] Data The data to write to the register. + +**/ +VOID +TpmWriteByte ( + IN UINTN TpmAddress, + IN UINT8 Data + ) +{ + EFI_STATUS Status; + UINTN WriteLength; + UINT8 WriteData[2]; + EFI_I2C_DEVICE_ADDRESS I2CDeviceAddr; + + // + // Setup I2C Slave device address and address mode (7-bit). + // + I2CDeviceAddr.I2CDeviceAddress = TPM_I2C_SLAVE_DEVICE_ADDRESS; + + // + // As recommended by Infineon (SLB9645 I2C Communication protocol application + // note revision 1.0) wait 250 microseconds between a read and a write transfer. + // + if (mI2CPrevReadTransfer) { + MicroSecondDelay (GUARD_TIME); + } + + // + // Write to TPM register. + // + WriteLength = 2; + WriteData[0] = (UINT8)TpmAddress; + WriteData[1] = Data; + + Status = I2cWriteMultipleByte ( + I2CDeviceAddr, + EfiI2CSevenBitAddrMode, + &WriteLength, + &WriteData + ); + if (EFI_ERROR(Status)) { + DEBUG ((EFI_D_ERROR, "TpmWriteByte(): I2C Write to TPM address %0x failed (%r)\n", TpmAddress, Status)); + ASSERT (FALSE); // Writes to TPM should always succeed. + } + + mI2CPrevReadTransfer = FALSE; +} + +/** + Reads single byte data from TPM specified by I2C register address. + + Due to stability issues when using I2C combined write/read transfers (with + RESTART) to TPM (specifically read from status register), a single write is + performed followed by single read (with STOP condition in between). + + @param[in] TpmAddress Address of register to read. + + @return The value register read. + +**/ +UINT8 +TpmReadByte ( + IN UINTN TpmAddress + ) +{ + UINT8 Data[1]; + UINT8 ReadData; + UINT8 ReadCount; + + EFI_I2C_DEVICE_ADDRESS I2CDeviceAddr; + EFI_I2C_ADDR_MODE I2CAddrMode; + + EFI_STATUS Status; + + Status = EFI_SUCCESS; + ReadData = 0xFF; + ReadCount = 0; + + // + // Locate I2C protocol for TPM I2C access. + // + I2CDeviceAddr.I2CDeviceAddress = TPM_I2C_SLAVE_DEVICE_ADDRESS; + I2CAddrMode = EfiI2CSevenBitAddrMode; + + // + // As recommended by Infineon (SLB9645 I2C Communication protocol application + // note revision 1.0) retry up to 3 times if TPM status, access or burst count + // registers return 0xFF. + // + while ((ReadData == 0xFF) && (ReadCount < READ_RETRY)) { + // + // As recommended by Infineon (SLB9645 I2C Communication protocol application + // note revision 1.0) wait 250 microseconds between a read and a write transfer. + // + if (mI2CPrevReadTransfer) { + MicroSecondDelay (GUARD_TIME); + } + + // + // Write address to TPM. + // + Data[0] = (UINT8)TpmAddress; + Status = I2cWriteByte ( + I2CDeviceAddr, + I2CAddrMode, + &Data + ); + + if (EFI_ERROR(Status)) { + DEBUG ((EFI_D_INFO, "TpmReadByte(): write to TPM address %0x failed (%r)\n", TpmAddress, Status)); + } + + mI2CPrevReadTransfer = FALSE; + + // + // Read data from TPM. + // + Data[0] = (UINT8)TpmAddress; + Status = I2cReadByte ( + I2CDeviceAddr, + I2CAddrMode, + &Data + ); + + if (EFI_ERROR(Status)) { + DEBUG ((EFI_D_INFO, "TpmReadByte(): read from TPM address %0x failed (%r)\n", TpmAddress, Status)); + ReadData = 0xFF; + } else { + ReadData = Data[0]; + } + + // + // Only need to retry 3 times for TPM status, access, and burst count registers. + // If read transfer is to TPM Data FIFO, do not retry, exit loop. + // + if (TpmAddress == INFINEON_TPM_DATA_FIFO_0_ADDRESS_DEFAULT) { + ReadCount = READ_RETRY; + } else { + ReadCount++; + } + + mI2CPrevReadTransfer = TRUE; + } + + if (EFI_ERROR(Status)) { + // + // Only reads to access register allowed to fail. + // + if (TpmAddress != INFINEON_TPM_ACCESS_0_ADDRESS_DEFAULT) { + DEBUG ((EFI_D_ERROR, "TpmReadByte(): read from TPM address %0x failed\n", TpmAddress)); + ASSERT_EFI_ERROR (Status); + } + } + return ReadData; +} + +/** + Check whether the value of a TPM chip register satisfies the input BIT setting. + + @param[in] Register TPM register to be checked. + @param[in] BitSet Check these data bits are set. + @param[in] BitClear Check these data bits are clear. + @param[in] TimeOut The max wait time (unit MicroSecond) when checking register. + + @retval EFI_SUCCESS The register satisfies the check bit. + @retval EFI_TIMEOUT The register can't run into the expected status in time. +**/ +EFI_STATUS +TisPcWaitRegisterBits ( + IN UINTN Register, + IN UINT8 BitSet, + IN UINT8 BitClear, + IN UINT32 TimeOut + ) +{ + UINT8 RegRead; + UINT32 WaitTime; + + for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){ + RegRead = TpmReadByte (Register); + if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0) + return EFI_SUCCESS; + MicroSecondDelay (30); + } + return EFI_TIMEOUT; +} + +/** + Get BurstCount by reading the burstCount field of a TIS register + in the time of default TIS_TIMEOUT_D. + + @param[out] BurstCount Pointer to a buffer to store the got BurstConut. + + @retval EFI_SUCCESS Get BurstCount. + @retval EFI_INVALID_PARAMETER BurstCount is NULL. + @retval EFI_TIMEOUT BurstCount can't be got in time. +**/ +EFI_STATUS +TisPcReadBurstCount ( + OUT UINT16 *BurstCount + ) +{ + UINT32 WaitTime; + UINT8 DataByte0; + UINT8 DataByte1; + + if (BurstCount == NULL) { + return EFI_INVALID_PARAMETER; + } + + WaitTime = 0; + do { + // + // BurstCount is UINT16, but it is not 2bytes aligned, + // so it needs to use TpmReadByte to read two times + // + DataByte0 = TpmReadByte (INFINEON_TPM_BURST0_COUNT_0_DEFAULT); + DataByte1 = TpmReadByte (INFINEON_TPM_BURST1_COUNT_0_DEFAULT); + *BurstCount = (UINT16)((DataByte1 << 8) + DataByte0); + if (*BurstCount != 0) { + return EFI_SUCCESS; + } + MicroSecondDelay (30); + WaitTime += 30; + } while (WaitTime < TIS_TIMEOUT_D); + + return EFI_TIMEOUT; +} + +/** + Set TPM chip to ready state by sending ready command TIS_PC_STS_READY + to Status Register in time. + + @retval EFI_SUCCESS TPM chip enters into ready state. + @retval EFI_TIMEOUT TPM chip can't be set to ready state in time. +**/ +EFI_STATUS +TisPcPrepareCommand ( + VOID + ) +{ + EFI_STATUS Status; + + TpmWriteByte (INFINEON_TPM_STS_0_ADDRESS_DEFAULT, TIS_PC_STS_READY); + Status = TisPcWaitRegisterBits ( + INFINEON_TPM_STS_0_ADDRESS_DEFAULT, + TIS_PC_STS_READY, + 0, + TIS_TIMEOUT_B + ); + return Status; +} + +/** + This service requests use TPM12. + + @retval EFI_SUCCESS Get the control of TPM12 chip. + @retval EFI_NOT_FOUND TPM12 not found. + @retval EFI_DEVICE_ERROR Unexpected device behavior. +**/ +EFI_STATUS +EFIAPI +Tpm12RequestUseTpm ( + VOID + ) +{ + EFI_STATUS Status; + + // + // Check to see if TPM exists + // + if (TpmReadByte (INFINEON_TPM_ACCESS_0_ADDRESS_DEFAULT) == 0xFF) { + return EFI_NOT_FOUND; + } + + TpmWriteByte (INFINEON_TPM_ACCESS_0_ADDRESS_DEFAULT, TIS_PC_ACC_RQUUSE); + + // + // No locality set before, ACCESS_X.activeLocality MUST be valid within TIMEOUT_A + // + Status = TisPcWaitRegisterBits ( + INFINEON_TPM_ACCESS_0_ADDRESS_DEFAULT, + (UINT8)(TIS_PC_ACC_ACTIVE |TIS_PC_VALID), + 0, + TIS_TIMEOUT_A + ); + return Status; +} + +/** + Send command to TPM for execution. + + @param[in] TpmBuffer Buffer for TPM command data. + @param[in] DataLength TPM command data length. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_TIMEOUT The register can't run into the expected status in time. + +**/ +EFI_STATUS +TisPcSend ( + IN UINT8 *TpmBuffer, + IN UINT32 DataLength + ) +{ + UINT16 BurstCount; + UINT32 Index; + EFI_STATUS Status; + + Status = TisPcPrepareCommand (); + if (EFI_ERROR (Status)){ + DEBUG ((DEBUG_ERROR, "The TPM is not ready!\n")); + goto Done; + } + Index = 0; + while (Index < DataLength) { + Status = TisPcReadBurstCount (&BurstCount); + if (EFI_ERROR (Status)) { + Status = EFI_TIMEOUT; + goto Done; + } + for (; BurstCount > 0 && Index < DataLength; BurstCount--) { + TpmWriteByte (INFINEON_TPM_DATA_FIFO_0_ADDRESS_DEFAULT, *(TpmBuffer + Index)); + Index++; + } + } + // + // Ensure the TPM status STS_EXPECT change from 1 to 0 + // + Status = TisPcWaitRegisterBits ( + INFINEON_TPM_STS_0_ADDRESS_DEFAULT, + (UINT8) TIS_PC_VALID, + TIS_PC_STS_EXPECT, + TIS_TIMEOUT_C + ); + if (EFI_ERROR (Status)) { + goto Done; + } + + // + // Start the command + // + TpmWriteByte (INFINEON_TPM_STS_0_ADDRESS_DEFAULT, TIS_PC_STS_GO); + +Done: + if (EFI_ERROR (Status)) { + // + // Ensure the TPM state change from "Reception" to "Idle/Ready" + // + TpmWriteByte (INFINEON_TPM_STS_0_ADDRESS_DEFAULT, TIS_PC_STS_READY); + } + + return Status; +} + +/** + Receive response data of last command from TPM. + + @param[out] TpmBuffer Buffer for response data. + @param[out] RespSize Response data length. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_TIMEOUT The register can't run into the expected status in time. + @retval EFI_DEVICE_ERROR Unexpected device status. + @retval EFI_BUFFER_TOO_SMALL Response data is too long. + +**/ +EFI_STATUS +TisPcReceive ( + OUT UINT8 *TpmBuffer, + OUT UINT32 *RespSize + ) +{ + EFI_STATUS Status; + UINT16 BurstCount; + UINT32 Index; + UINT32 ResponseSize; + TPM_RSP_COMMAND_HDR *ResponseHeader; + + // + // Wait for the command completion + // + Status = TisPcWaitRegisterBits ( + INFINEON_TPM_STS_0_ADDRESS_DEFAULT, + (UINT8) (TIS_PC_VALID | TIS_PC_STS_DATA), + 0, + TIS_TIMEOUT_B + ); + if (EFI_ERROR (Status)) { + Status = EFI_TIMEOUT; + goto Done; + } + // + // Read the response data header and check it + // + Index = 0; + BurstCount = 0; + while (Index < sizeof (TPM_RSP_COMMAND_HDR)) { + Status = TisPcReadBurstCount (&BurstCount); + if (EFI_ERROR (Status)) { + Status = EFI_TIMEOUT; + goto Done; + } + for (; BurstCount > 0 ; BurstCount--) { + *(TpmBuffer + Index) = TpmReadByte (INFINEON_TPM_DATA_FIFO_0_ADDRESS_DEFAULT); + Index++; + if (Index == sizeof (TPM_RSP_COMMAND_HDR)) + break; + } + } + + // + // Check the response data header (tag, parasize and returncode) + // + ResponseHeader = (TPM_RSP_COMMAND_HDR *)TpmBuffer; + if (SwapBytes16 (ReadUnaligned16 (&ResponseHeader->tag)) != TPM_TAG_RSP_COMMAND) { + Status = EFI_DEVICE_ERROR; + goto Done; + } + + ResponseSize = SwapBytes32 (ReadUnaligned32 (&ResponseHeader->paramSize)); + if (ResponseSize == sizeof (TPM_RSP_COMMAND_HDR)) { + Status = EFI_SUCCESS; + goto Done; + } + if (ResponseSize < sizeof (TPM_RSP_COMMAND_HDR)) { + Status = EFI_DEVICE_ERROR; + goto Done; + } + if (*RespSize < ResponseSize) { + Status = EFI_BUFFER_TOO_SMALL; + goto Done; + } + *RespSize = ResponseSize; + + // + // Continue reading the remaining data + // + while (Index < ResponseSize) { + for (; BurstCount > 0 ; BurstCount--) { + *(TpmBuffer + Index) = TpmReadByte (INFINEON_TPM_DATA_FIFO_0_ADDRESS_DEFAULT); + Index++; + if (Index == ResponseSize) { + Status = EFI_SUCCESS; + goto Done; + } + } + Status = TisPcReadBurstCount (&BurstCount); + if (EFI_ERROR (Status) && (Index < ResponseSize)) { + Status = EFI_DEVICE_ERROR; + goto Done; + } + } + +Done: + // + // Ensure the TPM state change from "Execution" or "Completion" to "Idle/Ready" + // + TpmWriteByte (INFINEON_TPM_STS_0_ADDRESS_DEFAULT, TIS_PC_STS_READY); + + return Status; +} + +/** + This service enables the sending of commands to the TPM12. + + @param[in] InputParameterBlockSize Size of the TPM12 input parameter block. + @param[in] InputParameterBlock Pointer to the TPM12 input parameter block. + @param[in,out] OutputParameterBlockSize Size of the TPM12 output parameter block. + @param[in] OutputParameterBlock Pointer to the TPM12 output parameter block. + + @retval EFI_SUCCESS The command byte stream was successfully sent to + the device and a response was successfully received. + @retval EFI_DEVICE_ERROR The command was not successfully sent to the + device or a response was not successfully received + from the device. + @retval EFI_BUFFER_TOO_SMALL The output parameter block is too small. +**/ +EFI_STATUS +EFIAPI +Tpm12SubmitCommand ( + IN UINT32 InputParameterBlockSize, + IN UINT8 *InputParameterBlock, + IN OUT UINT32 *OutputParameterBlockSize, + IN UINT8 *OutputParameterBlock + ) +{ + EFI_STATUS Status; + + Status = TisPcSend (InputParameterBlock, InputParameterBlockSize); + if (!EFI_ERROR (Status)) { + Status = TisPcReceive (OutputParameterBlock, OutputParameterBlockSize); + } + return Status; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Library/Tpm12DeviceLibInfineonI2c/Tpm12DeviceLibInfineonI2c.inf b/Platform/Intel/QuarkPlatformPkg/Library/Tpm12DeviceLibInfineonI2c/Tpm12DeviceLibInfineonI2c.inf new file mode 100644 index 0000000000..26c12a4b6d --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/Tpm12DeviceLibInfineonI2c/Tpm12DeviceLibInfineonI2c.inf @@ -0,0 +1,39 @@ +## @file +# Provides some common functions for the TCG feature for Infineon I2C TPM. +# +# This instance provides basic TPM Interface Specification (TIS) functions +# for Infineon I2C TPM. +# +# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = Tpm12DeviceLibInfineonI2c + MODULE_UNI_FILE = Tpm12DeviceLibInfineonI2c.uni + FILE_GUID = DBE37563-AFEF-4B41-BDCE-B01B6D1E8690 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = Tpm12DeviceLib|PEIM DXE_DRIVER DXE_SMM_DRIVER UEFI_DRIVER + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 +# + +[Sources] + TisPc.c + +[Packages] + MdePkg/MdePkg.dec + SecurityPkg/SecurityPkg.dec + QuarkSocPkg/QuarkSocPkg.dec + +[LibraryClasses] + BaseLib + TimerLib + DebugLib + I2cLib diff --git a/Platform/Intel/QuarkPlatformPkg/Library/Tpm12DeviceLibInfineonI2c/Tpm12DeviceLibInfineonI2c.uni b/Platform/Intel/QuarkPlatformPkg/Library/Tpm12DeviceLibInfineonI2c/Tpm12DeviceLibInfineonI2c.uni new file mode 100644 index 0000000000..efc07ea39d --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Library/Tpm12DeviceLibInfineonI2c/Tpm12DeviceLibInfineonI2c.uni @@ -0,0 +1,16 @@ +// /** @file +// Provides some common functions for the TCG feature for Infineon I2C TPM. +// +// This instance provides basic TPM Interface Specification (TIS) functions +// for Infineon I2C TPM. +// +// Copyright (c) 2016, Intel Corporation. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_MODULE_ABSTRACT #language en-US "Provides some common functions for the TCG feature for Infineon I2C TPM" + +#string STR_MODULE_DESCRIPTION #language en-US "This instance provides basic TPM Interface Specification (TIS) functions for Infineon I2C TPM." + diff --git a/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.c b/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.c new file mode 100644 index 0000000000..be41a8595c --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.c @@ -0,0 +1,1397 @@ +/** @file +Pci Host Bridge driver for a simple IIO. There is only one PCI Root Bridge in the system. +Provides the basic interfaces to abstract a PCI Host Bridge Resource Allocation. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#include "PciHostBridge.h" +#include + +// +// We can hardcode the following for a Simple IIO - +// Root Bridge Count within the host bridge +// Root Bridge's device path +// Root Bridge's resource appeture +// +EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[ROOT_BRIDGE_COUNT] = { + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), + (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) + } + }, + EISA_PNP_ID (0x0A03), + 0 + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + } +}; + +EFI_HANDLE mDriverImageHandle; +PCI_ROOT_BRIDGE_RESOURCE_APERTURE *mResAperture; + +// +// Implementation +// +EFI_STATUS +EFIAPI +InitializePciHostBridge ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +/*++ + +Routine Description: + + Entry point of this driver. + +Arguments: + + ImageHandle - Image handle of this driver. + SystemTable - Pointer to standard EFI system table. + +Returns: + + EFI_SUCCESS - Succeed. + EFI_DEVICE_ERROR - Fail to install PCI_ROOT_BRIDGE_IO protocol. + +--*/ +{ + EFI_STATUS Status; + UINTN TotalRootBridgeFound; + PCI_HOST_BRIDGE_INSTANCE *HostBridge; + PCI_ROOT_BRIDGE_INSTANCE *PrivateData; + UINT64 AllocAttributes; + EFI_PHYSICAL_ADDRESS BaseAddress; + + PrivateData = NULL; + + mDriverImageHandle = ImageHandle; + + // + // Most systems in the world including complex servers + // have only one Host Bridge. Create Host Bridge Device Handle + // + Status = gBS->AllocatePool(EfiBootServicesData, sizeof(PCI_HOST_BRIDGE_INSTANCE), (VOID **) &HostBridge); + ASSERT_EFI_ERROR (Status); + ZeroMem (HostBridge, sizeof (PCI_HOST_BRIDGE_INSTANCE)); + + HostBridge->Signature = PCI_HOST_BRIDGE_SIGNATURE; + HostBridge->RootBridgeCount = 1; + HostBridge->ResourceSubmited = FALSE; + HostBridge->CanRestarted = TRUE; + // + // InitializeListHead (&HostBridge->Head); + // + HostBridge->ResAlloc.NotifyPhase = NotifyPhase; + HostBridge->ResAlloc.GetNextRootBridge = GetNextRootBridge; + HostBridge->ResAlloc.GetAllocAttributes = GetAttributes; + HostBridge->ResAlloc.StartBusEnumeration = StartBusEnumeration; + HostBridge->ResAlloc.SetBusNumbers = SetBusNumbers; + HostBridge->ResAlloc.SubmitResources = SubmitResources; + HostBridge->ResAlloc.GetProposedResources = GetProposedResources; + HostBridge->ResAlloc.PreprocessController = PreprocessController; + + Status = gBS->InstallProtocolInterface ( + &HostBridge->HostBridgeHandle, + &gEfiPciHostBridgeResourceAllocationProtocolGuid, + EFI_NATIVE_INTERFACE, + &HostBridge->ResAlloc + ); + if (EFI_ERROR (Status)) { + gBS->FreePool (HostBridge); + return EFI_DEVICE_ERROR; + } + + Status = gBS->AllocatePool (EfiBootServicesData, + HostBridge->RootBridgeCount * sizeof(PCI_ROOT_BRIDGE_RESOURCE_APERTURE), + (VOID **) &mResAperture); + ASSERT_EFI_ERROR (Status); + ZeroMem (mResAperture, HostBridge->RootBridgeCount * sizeof(PCI_ROOT_BRIDGE_RESOURCE_APERTURE)); + + DEBUG ((EFI_D_INFO, "Address of resource Aperture: %x\n", mResAperture)); + + // + // Create Root Bridge Device Handle in this Host Bridge + // + InitializeListHead (&HostBridge->Head); + + TotalRootBridgeFound = 0; + + Status = gBS->AllocatePool ( EfiBootServicesData,sizeof (PCI_ROOT_BRIDGE_INSTANCE), (VOID **) &PrivateData); + ASSERT_EFI_ERROR (Status); + ZeroMem (PrivateData, sizeof (PCI_ROOT_BRIDGE_INSTANCE)); + + PrivateData->Signature = PCI_ROOT_BRIDGE_SIGNATURE; + PrivateData->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) &mEfiPciRootBridgeDevicePath[TotalRootBridgeFound]; + AllocAttributes = GetAllocAttributes (TotalRootBridgeFound); + + SimpleIioRootBridgeConstructor ( + &PrivateData->Io, + HostBridge->HostBridgeHandle, + &(mResAperture[TotalRootBridgeFound]), + AllocAttributes + ); + // + // Update Root Bridge with UDS resource information + // + PrivateData->Aperture.BusBase = QNC_PCI_HOST_BRIDGE_RESOURCE_APPETURE_BUSBASE; + PrivateData->Aperture.BusLimit = QNC_PCI_HOST_BRIDGE_RESOURCE_APPETURE_BUSLIMIT; + PrivateData->Aperture.Mem32Base = PcdGet32 (PcdPciHostBridgeMemory32Base); + PrivateData->Aperture.Mem32Limit = PcdGet32 (PcdPciHostBridgeMemory32Base) + (PcdGet32 (PcdPciHostBridgeMemory32Size) - 1); + PrivateData->Aperture.IoBase = PcdGet16 (PcdPciHostBridgeIoBase); + PrivateData->Aperture.IoLimit = PcdGet16 (PcdPciHostBridgeIoBase) + (PcdGet16 (PcdPciHostBridgeIoSize) - 1); + + DEBUG ((EFI_D_INFO, "PCI Host Bridge BusBase: %x\n", QNC_PCI_HOST_BRIDGE_RESOURCE_APPETURE_BUSBASE)); + DEBUG ((EFI_D_INFO, "PCI Host Bridge BusLimit: %x\n", QNC_PCI_HOST_BRIDGE_RESOURCE_APPETURE_BUSLIMIT)); + DEBUG ((EFI_D_INFO, "PCI Host Bridge PciResourceMem32Base: %x\n", PcdGet32 (PcdPciHostBridgeMemory32Base))); + DEBUG ((EFI_D_INFO, "PCI Host Bridge PciResourceMem32Limit: %x\n", PcdGet32 (PcdPciHostBridgeMemory32Base) + (PcdGet32 (PcdPciHostBridgeMemory32Size) - 1))); + DEBUG ((EFI_D_INFO, "PCI Host Bridge PciResourceMem64Base: %lX\n", PcdGet64 (PcdPciHostBridgeMemory64Base))); + DEBUG ((EFI_D_INFO, "PCI Host Bridge PciResourceMem64Limit: %lX\n", PcdGet64 (PcdPciHostBridgeMemory64Base) + (PcdGet64 (PcdPciHostBridgeMemory64Size) - 1))); + DEBUG ((EFI_D_INFO, "PCI Host Bridge PciResourceIoBase: %x\n", PcdGet16 (PcdPciHostBridgeIoBase))); + DEBUG ((EFI_D_INFO, "PCI Host Bridge PciResourceIoLimit: %x\n", PcdGet16 (PcdPciHostBridgeIoBase) + (PcdGet16 (PcdPciHostBridgeIoSize) - 1))); + + PrivateData->Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces ( + &PrivateData->Handle, + &gEfiDevicePathProtocolGuid, + PrivateData->DevicePath, + &gEfiPciRootBridgeIoProtocolGuid, + &PrivateData->Io, + NULL + ); + ASSERT_EFI_ERROR (Status); + + InsertTailList (&HostBridge->Head, &PrivateData->Link); + TotalRootBridgeFound++; // This is a valid rootbridge so imcrement total root bridges found + + // + // Add PCIE base into Runtime memory so that it can be reported in E820 table + // + Status = gDS->AddMemorySpace ( + EfiGcdMemoryTypeMemoryMappedIo, + PcdGet64 (PcdPciExpressBaseAddress), + PcdGet64 (PcdPciExpressSize), + EFI_MEMORY_RUNTIME | EFI_MEMORY_UC + ); + ASSERT_EFI_ERROR(Status); + + BaseAddress = PcdGet64 (PcdPciExpressBaseAddress); + + Status = gDS->AllocateMemorySpace ( + EfiGcdAllocateAddress, + EfiGcdMemoryTypeMemoryMappedIo, + 0, + PcdGet64 (PcdPciExpressSize), + &BaseAddress, + ImageHandle, + NULL + ); + ASSERT_EFI_ERROR(Status); + + Status = gDS->SetMemorySpaceAttributes ( + PcdGet64 (PcdPciExpressBaseAddress), + PcdGet64 (PcdPciExpressSize), + EFI_MEMORY_RUNTIME + ); + ASSERT_EFI_ERROR (Status); + + if (PcdGet16 (PcdPciHostBridgeIoSize) > 0) { + // + // At present, we use up the first 4k for fixed ranges like + // ICH GPIO, ACPI and ISA devices. The first 4k is not + // tracked through GCD. It should be. + // + Status = gDS->AddIoSpace ( + EfiGcdIoTypeIo, + PcdGet16(PcdPciHostBridgeIoBase), + PcdGet16(PcdPciHostBridgeIoSize) + ); + ASSERT_EFI_ERROR (Status); + } + + if (PcdGet32(PcdPciHostBridgeMemory32Size) > 0) { + // + // Shouldn't the capabilities be UC? + // + Status = gDS->AddMemorySpace ( + EfiGcdMemoryTypeMemoryMappedIo, + PcdGet32(PcdPciHostBridgeMemory32Base), + PcdGet32(PcdPciHostBridgeMemory32Size), + 0 + ); + ASSERT_EFI_ERROR (Status); + } + + return Status; +} + +EFI_STATUS +EFIAPI +NotifyPhase ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase + ) +/*++ + +Routine Description: + + Enter a certain phase of the PCI enumeration process. + +Arguments: + + This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance. + Phase - The phase during enumeration. + +Returns: + + EFI_SUCCESS - Succeed. + EFI_INVALID_PARAMETER - Wrong phase parameter passed in. + EFI_NOT_READY - Resources have not been submitted yet. + +--*/ +{ + PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; + PCI_RESOURCE_TYPE Index; + EFI_LIST_ENTRY *List; + EFI_PHYSICAL_ADDRESS BaseAddress; + UINT64 AddrLen; + UINTN BitsOfAlignment; + UINT64 Alignment; + EFI_STATUS Status; + EFI_STATUS ReturnStatus; + PCI_RESOURCE_TYPE Index1; + PCI_RESOURCE_TYPE Index2; + BOOLEAN ResNodeHandled[TypeMax]; + UINT64 MaxAlignment; + + HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); + + switch (Phase) { + case EfiPciHostBridgeBeginEnumeration: + if (HostBridgeInstance->CanRestarted) { + // + // Reset Root Bridge + // + List = HostBridgeInstance->Head.ForwardLink; + + while (List != &HostBridgeInstance->Head) { + RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + for (Index = TypeIo; Index < TypeMax; Index++) { + RootBridgeInstance->ResAllocNode[Index].Type = Index; + RootBridgeInstance->ResAllocNode[Index].Base = 0; + RootBridgeInstance->ResAllocNode[Index].Length = 0; + RootBridgeInstance->ResAllocNode[Index].Status = ResNone; + } // for + + List = List->ForwardLink; + } // while + + HostBridgeInstance->ResourceSubmited = FALSE; + HostBridgeInstance->CanRestarted = TRUE; + } else { + // + // Can not restart + // + return EFI_NOT_READY; + } // if + break; + + case EfiPciHostBridgeEndEnumeration: + return EFI_SUCCESS; + break; + + case EfiPciHostBridgeBeginBusAllocation: + // + // No specific action is required here, can perform any chipset specific programing + // + HostBridgeInstance->CanRestarted = FALSE; + return EFI_SUCCESS; + break; + + case EfiPciHostBridgeEndBusAllocation: + // + // No specific action is required here, can perform any chipset specific programing + // + // HostBridgeInstance->CanRestarted = FALSE; + // + return EFI_SUCCESS; + break; + + case EfiPciHostBridgeBeginResourceAllocation: + // + // No specific action is required here, can perform any chipset specific programing + // + // HostBridgeInstance->CanRestarted = FALSE; + // + return EFI_SUCCESS; + break; + + case EfiPciHostBridgeAllocateResources: + ReturnStatus = EFI_SUCCESS; + if (HostBridgeInstance->ResourceSubmited) { + List = HostBridgeInstance->Head.ForwardLink; + while (List != &HostBridgeInstance->Head) { + for (Index1 = TypeIo; Index1 < TypeBus; Index1++) { + ResNodeHandled[Index1] = FALSE; + } + + RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + DEBUG ((EFI_D_INFO, "Address of RootBridgeInstance: %x)\n", RootBridgeInstance)); + DEBUG ((EFI_D_INFO, " Signature: %x\n", RootBridgeInstance->Signature)); + DEBUG ((EFI_D_INFO, " Bus Number Assigned: %x\n", RootBridgeInstance->BusNumberAssigned)); + DEBUG ((EFI_D_INFO, " Bus Scan Count: %x\n", RootBridgeInstance->BusScanCount)); + + for (Index1 = TypeIo; Index1 < TypeBus; Index1++) { + if (RootBridgeInstance->ResAllocNode[Index1].Status == ResNone) { + ResNodeHandled[Index1] = TRUE; + } else { + // + // Allocate the resource node with max alignment at first + // + MaxAlignment = 0; + Index = TypeMax; + for (Index2 = TypeIo; Index2 < TypeBus; Index2++) { + if (ResNodeHandled[Index2]) { + continue; + } + if (MaxAlignment <= RootBridgeInstance->ResAllocNode[Index2].Alignment) { + MaxAlignment = RootBridgeInstance->ResAllocNode[Index2].Alignment; + Index = Index2; + } + } // for + + if (Index < TypeMax) { + ResNodeHandled[Index] = TRUE; + } else { + ASSERT (FALSE); + } + + Alignment = RootBridgeInstance->ResAllocNode[Index].Alignment; + + // + // Get the number of '1' in Alignment. + // + for (BitsOfAlignment = 0; Alignment != 0; BitsOfAlignment++) { + Alignment = RShiftU64 (Alignment, 1); + } + + AddrLen = RootBridgeInstance->ResAllocNode[Index].Length; + Alignment = RootBridgeInstance->ResAllocNode[Index].Alignment; + + DEBUG ((EFI_D_INFO, "\n\nResource Type to assign : %x\n", Index)); + DEBUG ((EFI_D_INFO, " Length to allocate: %x\n", RootBridgeInstance->ResAllocNode[Index].Length)); + DEBUG ((EFI_D_INFO, " Aligment: %x\n", Alignment)); + + switch (Index) { + case TypeIo: + if (RootBridgeInstance->Aperture.IoBase < RootBridgeInstance->Aperture.IoLimit) { + // + // It is impossible for 0xFFFF Alignment for IO16 + // + if (BitsOfAlignment >= 16) + Alignment = 0; + + BaseAddress = RootBridgeInstance->Aperture.IoBase; + + // + // Have to make sure Aligment is handled seeing we are doing direct address allocation + // + if ((BaseAddress & ~(Alignment)) != BaseAddress) + BaseAddress = ((BaseAddress + Alignment) & ~(Alignment)); + + while((BaseAddress + AddrLen) <= RootBridgeInstance->Aperture.IoLimit + 1) { + + Status = gDS->AllocateIoSpace ( EfiGcdAllocateAddress, EfiGcdIoTypeIo, BitsOfAlignment, + AddrLen, &BaseAddress, mDriverImageHandle, NULL ); + + if (!EFI_ERROR (Status)) { + RootBridgeInstance->ResAllocNode[Index].Base = (UINT64) BaseAddress; + RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated; + goto TypeIoFound; + } + + BaseAddress += (Alignment + 1); + } // while + + } // if + + TypeIoFound: + if (RootBridgeInstance->ResAllocNode[Index].Status != ResAllocated) { + // + // No Room at the Inn for this resources request + // + ReturnStatus = EFI_OUT_OF_RESOURCES; + } // if + + break; + + case TypeMem32: + if (RootBridgeInstance->Aperture.Mem32Base < RootBridgeInstance->Aperture.Mem32Limit) { + + BaseAddress = RootBridgeInstance->Aperture.Mem32Base; + // + // Have to make sure Aligment is handled seeing we are doing direct address allocation + // + if ((BaseAddress & ~(Alignment)) != BaseAddress) + BaseAddress = ((BaseAddress + Alignment) & ~(Alignment)); + + while((BaseAddress + AddrLen) <= RootBridgeInstance->Aperture.Mem32Limit + 1) { + + Status = gDS->AllocateMemorySpace ( EfiGcdAllocateAddress, EfiGcdMemoryTypeMemoryMappedIo, + BitsOfAlignment, AddrLen, &BaseAddress, mDriverImageHandle, NULL); + + if (!EFI_ERROR (Status)) { + RootBridgeInstance->ResAllocNode[Index].Base = (UINT64) BaseAddress; + RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated; + goto TypeMem32Found; + } // if + + BaseAddress += (Alignment + 1); + } // while + } // if + + TypeMem32Found: + if (RootBridgeInstance->ResAllocNode[Index].Status != ResAllocated) { + // + // No Room at the Inn for this resources request + // + ReturnStatus = EFI_OUT_OF_RESOURCES; + } + + break; + + case TypePMem32: + StartTypePMem32: + if (RootBridgeInstance->Aperture.Mem32Base < RootBridgeInstance->Aperture.Mem32Limit) { + + BaseAddress = RootBridgeInstance->Aperture.Mem32Limit + 1; + BaseAddress -= AddrLen; + + // + // Have to make sure Aligment is handled seeing we are doing direct address allocation + // + if ((BaseAddress & ~(Alignment)) != BaseAddress) + BaseAddress = ((BaseAddress) & ~(Alignment)); + + while(RootBridgeInstance->Aperture.Mem32Base <= BaseAddress) { + + DEBUG ((EFI_D_INFO, " Attempting %x allocation at 0x%lx .....", Index, BaseAddress)); + Status = gDS->AllocateMemorySpace ( EfiGcdAllocateAddress, EfiGcdMemoryTypeMemoryMappedIo, + BitsOfAlignment, AddrLen, &BaseAddress, mDriverImageHandle, NULL); + + if (!EFI_ERROR (Status)) { + RootBridgeInstance->ResAllocNode[Index].Base = (UINT64) BaseAddress; + RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated; + DEBUG ((EFI_D_INFO, "... Passed!!\n")); + goto TypePMem32Found; + } + DEBUG ((EFI_D_INFO, "... Failed!!\n")); + BaseAddress -= (Alignment + 1); + } // while + } // if + + TypePMem32Found: + if (RootBridgeInstance->ResAllocNode[Index].Status != ResAllocated) { + // + // No Room at the Inn for this resources request + // + ReturnStatus = EFI_OUT_OF_RESOURCES; + } + + break; + + case TypeMem64: + case TypePMem64: + if (RootBridgeInstance->ResAllocNode[Index].Status != ResAllocated) { + // + // If 64-bit resourcing is not available, then try as PMem32 + // + goto StartTypePMem32; + } + + break; + + default: + break; + } // End switch (Index) + + DEBUG ((EFI_D_INFO, "Resource Type Assigned: %x\n", Index)); + if (RootBridgeInstance->ResAllocNode[Index].Status == ResAllocated) { + DEBUG ((EFI_D_INFO, " Base Address Assigned: %x\n", RootBridgeInstance->ResAllocNode[Index].Base)); + DEBUG ((EFI_D_INFO, " Length Assigned: %x\n", RootBridgeInstance->ResAllocNode[Index].Length)); + } else { + DEBUG ((DEBUG_ERROR, " Resource Allocation failed! There was no room at the inn\n")); + } + + } + } + + List = List->ForwardLink; + } + + if (ReturnStatus == EFI_OUT_OF_RESOURCES) { + DEBUG ((DEBUG_ERROR, "Resource allocation Failed. Continue booting the system.\n")); + } + + // + // Set resource to zero for nodes where allocation fails + // + List = HostBridgeInstance->Head.ForwardLink; + while (List != &HostBridgeInstance->Head) { + RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + for (Index = TypeIo; Index < TypeBus; Index++) { + if (RootBridgeInstance->ResAllocNode[Index].Status != ResAllocated) { + RootBridgeInstance->ResAllocNode[Index].Length = 0; + } + } + List = List->ForwardLink; + } + return ReturnStatus; + } else { + return EFI_NOT_READY; + } + // + // HostBridgeInstance->CanRestarted = FALSE; + // + break; + + case EfiPciHostBridgeSetResources: + // + // HostBridgeInstance->CanRestarted = FALSE; + // + break; + + case EfiPciHostBridgeFreeResources: + // + // HostBridgeInstance->CanRestarted = FALSE; + // + ReturnStatus = EFI_SUCCESS; + List = HostBridgeInstance->Head.ForwardLink; + while (List != &HostBridgeInstance->Head) { + RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + for (Index = TypeIo; Index < TypeBus; Index++) { + if (RootBridgeInstance->ResAllocNode[Index].Status == ResAllocated) { + AddrLen = RootBridgeInstance->ResAllocNode[Index].Length; + BaseAddress = (EFI_PHYSICAL_ADDRESS) RootBridgeInstance->ResAllocNode[Index].Base; + switch (Index) { + case TypeIo: + Status = gDS->FreeIoSpace (BaseAddress, AddrLen); + if (EFI_ERROR (Status)) { + ReturnStatus = Status; + } + break; + + case TypeMem32: + Status = gDS->FreeMemorySpace (BaseAddress, AddrLen); + if (EFI_ERROR (Status)) { + ReturnStatus = Status; + } + break; + + case TypePMem32: + break; + + case TypeMem64: + break; + + case TypePMem64: + Status = gDS->FreeMemorySpace (BaseAddress, AddrLen); + if (EFI_ERROR (Status)) { + ReturnStatus = Status; + } + break; + + default: + break; + } // end switch (Index) + + RootBridgeInstance->ResAllocNode[Index].Type = Index; + RootBridgeInstance->ResAllocNode[Index].Base = 0; + RootBridgeInstance->ResAllocNode[Index].Length = 0; + RootBridgeInstance->ResAllocNode[Index].Status = ResNone; + } + } + + List = List->ForwardLink; + } + + HostBridgeInstance->ResourceSubmited = FALSE; + HostBridgeInstance->CanRestarted = TRUE; + return ReturnStatus; + break; + + case EfiPciHostBridgeEndResourceAllocation: + // + // Resource enumeration is done. Perform any activities that + // must wait until that time. + // + break; + + default: + return EFI_INVALID_PARAMETER; + } // End switch (Phase) + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +GetNextRootBridge ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN OUT EFI_HANDLE *RootBridgeHandle + ) +/*++ + +Routine Description: + Return the device handle of the next PCI root bridge that is associated with + this Host Bridge. + +Arguments: + + This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance. + RootBridgeHandle - Returns the device handle of the next PCI Root Bridge. + On input, it holds the RootBridgeHandle returned by the most + recent call to GetNextRootBridge().The handle for the first + PCI Root Bridge is returned if RootBridgeHandle is NULL on input. + +Returns: + + EFI_SUCCESS - Succeed. + EFI_NOT_FOUND - Next PCI root bridge not found. + EFI_INVALID_PARAMETER - Wrong parameter passed in. + +--*/ +{ + BOOLEAN NoRootBridge; + EFI_LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; + + NoRootBridge = TRUE; + HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); + List = HostBridgeInstance->Head.ForwardLink; + + while (List != &HostBridgeInstance->Head) { + NoRootBridge = FALSE; + RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + if (*RootBridgeHandle == NULL) { + // + // Return the first Root Bridge Handle of the Host Bridge + // + *RootBridgeHandle = RootBridgeInstance->Handle; + return EFI_SUCCESS; + } else { + if (*RootBridgeHandle == RootBridgeInstance->Handle) { + // + // Get next if have + // + List = List->ForwardLink; + if (List != &HostBridgeInstance->Head) { + RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + *RootBridgeHandle = RootBridgeInstance->Handle; + return EFI_SUCCESS; + } else { + return EFI_NOT_FOUND; + } + } + } + + List = List->ForwardLink; + // + // end while + // + } + + if (NoRootBridge) { + return EFI_NOT_FOUND; + } else { + return EFI_INVALID_PARAMETER; + } +} + +EFI_STATUS +EFIAPI +GetAttributes ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT UINT64 *Attributes + ) +/*++ + +Routine Description: + Returns the attributes of a PCI Root Bridge. + +Arguments: + + This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance. + RootBridgeHandle - The device handle of the PCI Root Bridge + that the caller is interested in. + Attributes - The pointer to attributes of the PCI Root Bridge. + +Returns: + + EFI_SUCCESS - Succeed. + EFI_INVALID_PARAMETER - Attributes parameter passed in is NULL or + RootBridgeHandle is not an EFI_HANDLE + that was returned on a previous call to + GetNextRootBridge(). + +--*/ +{ + EFI_LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; + + if (Attributes == NULL) { + return EFI_INVALID_PARAMETER; + } + + HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); + List = HostBridgeInstance->Head.ForwardLink; + + while (List != &HostBridgeInstance->Head) { + RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + if (RootBridgeHandle == RootBridgeInstance->Handle) { + *Attributes = RootBridgeInstance->RootBridgeAllocAttrib; + return EFI_SUCCESS; + } + + List = List->ForwardLink; + } + // + // RootBridgeHandle is not an EFI_HANDLE + // that was returned on a previous call to GetNextRootBridge() + // + return EFI_INVALID_PARAMETER; +} + +EFI_STATUS +EFIAPI +StartBusEnumeration ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT VOID **Configuration + ) +/*++ + +Routine Description: + This is the request from the PCI enumerator to set up + the specified PCI Root Bridge for bus enumeration process. + +Arguments: + + This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance. + RootBridgeHandle - The PCI Root Bridge to be set up. + Configuration - Pointer to the pointer to the PCI bus resource descriptor. + +Returns: + + EFI_SUCCESS - Succeed. + EFI_OUT_OF_RESOURCES - Not enough pool to be allocated. + EFI_INVALID_PARAMETER - RootBridgeHandle is not a valid handle. + +--*/ +{ + EFI_LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; + VOID *Buffer; + UINT8 *Temp; + EFI_STATUS Status; + UINTN BusStart; + UINTN BusEnd; + UINT64 BusReserve; + + HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); + List = HostBridgeInstance->Head.ForwardLink; + + while (List != &HostBridgeInstance->Head) { + RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + if (RootBridgeHandle == RootBridgeInstance->Handle) { + // + // Set up the Root Bridge for Bus Enumeration + // + BusStart = RootBridgeInstance->Aperture.BusBase; + BusEnd = RootBridgeInstance->Aperture.BusLimit; + BusReserve = RootBridgeInstance->Aperture.BusReserve; + // + // Program the Hardware(if needed) if error return EFI_DEVICE_ERROR + // + Status = gBS->AllocatePool ( + EfiBootServicesData, + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR), + &Buffer + ); + if (EFI_ERROR (Status)) { + return EFI_OUT_OF_RESOURCES; + } + + Temp = (UINT8 *) Buffer; + + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->Len = 0x2B; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->GenFlag = 0; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->SpecificFlag = 0; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->AddrSpaceGranularity = 0; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->AddrRangeMin = BusStart; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->AddrRangeMax = BusReserve; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->AddrTranslationOffset = 0; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->AddrLen = BusEnd - BusStart + 1; + + Temp = Temp + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); + ((EFI_ACPI_END_TAG_DESCRIPTOR *) Temp)->Desc = ACPI_END_TAG_DESCRIPTOR; + ((EFI_ACPI_END_TAG_DESCRIPTOR *) Temp)->Checksum = 0x0; + + *Configuration = Buffer; + return EFI_SUCCESS; + } + + List = List->ForwardLink; + } + + return EFI_INVALID_PARAMETER; +} + +EFI_STATUS +EFIAPI +SetBusNumbers ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN VOID *Configuration + ) +/*++ + +Routine Description: + This function programs the PCI Root Bridge hardware so that + it decodes the specified PCI bus range. + +Arguments: + + This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance. + RootBridgeHandle - The PCI Root Bridge whose bus range is to be programmed. + Configuration - The pointer to the PCI bus resource descriptor. + +Returns: + + EFI_SUCCESS - Succeed. + EFI_INVALID_PARAMETER - Wrong parameters passed in. + +--*/ +{ + EFI_LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; + UINT8 *Ptr; + UINTN BusStart; + UINTN BusEnd; + UINTN BusLen; + + if (Configuration == NULL) { + return EFI_INVALID_PARAMETER; + } + + Ptr = Configuration; + + // + // Check the Configuration is valid + // + if (*Ptr != ACPI_ADDRESS_SPACE_DESCRIPTOR) { + return EFI_INVALID_PARAMETER; + } + + if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Ptr)->ResType != ACPI_ADDRESS_SPACE_TYPE_BUS) { + return EFI_INVALID_PARAMETER; + } + + Ptr += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); + if (*Ptr != ACPI_END_TAG_DESCRIPTOR) { + return EFI_INVALID_PARAMETER; + } + + HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); + List = HostBridgeInstance->Head.ForwardLink; + + Ptr = Configuration; + + while (List != &HostBridgeInstance->Head) { + RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + if (RootBridgeHandle == RootBridgeInstance->Handle) { + BusStart = (UINTN) ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Ptr)->AddrRangeMin; + BusLen = (UINTN) ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Ptr)->AddrLen; + BusEnd = BusStart + BusLen - 1; + + if (BusStart > BusEnd) { + return EFI_INVALID_PARAMETER; + } + + if ((BusStart < RootBridgeInstance->Aperture.BusBase) || (BusEnd > RootBridgeInstance->Aperture.BusLimit)) { + return EFI_INVALID_PARAMETER; + } + // + // Update the Bus Range + // + RootBridgeInstance->ResAllocNode[TypeBus].Base = BusStart; + RootBridgeInstance->ResAllocNode[TypeBus].Length = BusLen; + RootBridgeInstance->ResAllocNode[TypeBus].Status = ResAllocated; + RootBridgeInstance->BusScanCount++; + if (RootBridgeInstance->BusScanCount > 0) { + // + // Only care about the 2nd PCI bus scanning + // + RootBridgeInstance->BusNumberAssigned = TRUE; + } + + return EFI_SUCCESS; + } + + List = List->ForwardLink; + } + + return EFI_INVALID_PARAMETER; +} + +EFI_STATUS +EFIAPI +SubmitResources ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN VOID *Configuration + ) +/*++ + +Routine Description: + + Submits the I/O and memory resource requirements for the specified PCI Root Bridge. + +Arguments: + This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance. + RootBridgeHandle - The PCI Root Bridge whose I/O and memory resource requirements. + are being submitted. + Configuration - The pointer to the PCI I/O and PCI memory resource descriptor. + +Returns: + + EFI_SUCCESS - Succeed. + EFI_INVALID_PARAMETER - Wrong parameters passed in. + +--*/ +{ + EFI_LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; + UINT8 *Temp; + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ptr; + UINT64 AddrLen; + UINT64 Alignment; + UINT64 Value; + + // + // Check the input parameter: Configuration + // + if (Configuration == NULL) { + return EFI_INVALID_PARAMETER; + } + + HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); + List = HostBridgeInstance->Head.ForwardLink; + + Temp = (UINT8 *) Configuration; + while (List != &HostBridgeInstance->Head) { + RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + if (RootBridgeHandle == RootBridgeInstance->Handle) { + // + // Check the resource descriptors. + // If the Configuration includes one or more invalid resource descriptors, all the resource + // descriptors are ignored and the function returns EFI_INVALID_PARAMETER. + // + while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) { + ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp; + DEBUG ((EFI_D_INFO, " ptr->ResType:%x \n",ptr->ResType)); + DEBUG ((EFI_D_INFO, " ptr->AddrLen:0x%lx AddrRangeMin:0x%lx AddrRangeMax:0x%lx\n\n",ptr->AddrLen,ptr->AddrRangeMin,ptr->AddrRangeMax)); + + switch (ptr->ResType) { + case ACPI_ADDRESS_SPACE_TYPE_MEM: + if (ptr->AddrSpaceGranularity != 32 && ptr->AddrSpaceGranularity != 64) { + return EFI_INVALID_PARAMETER; + } + if (ptr->AddrSpaceGranularity == 32 && ptr->AddrLen > 0xffffffff) { + return EFI_INVALID_PARAMETER; + } + // + // If the PCI root bridge does not support separate windows for nonprefetchable and + // prefetchable memory, then the PCI bus driver needs to include requests for + // prefetchable memory in the nonprefetchable memory pool. + // + if ((RootBridgeInstance->RootBridgeAllocAttrib & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0 && + ((ptr->SpecificFlag & (BIT2 | BIT1)) != 0)) { + return EFI_INVALID_PARAMETER; + } + case ACPI_ADDRESS_SPACE_TYPE_IO: + // + // Check aligment, it should be of the form 2^n-1 + // + Value = Power2MaxMemory (ptr->AddrRangeMax + 1); + if (Value != (ptr->AddrRangeMax + 1)) { + CpuDeadLoop(); + return EFI_INVALID_PARAMETER; + } + break; + case ACPI_ADDRESS_SPACE_TYPE_BUS: + default: + return EFI_INVALID_PARAMETER; + } + Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ; + } + if (*Temp != ACPI_END_TAG_DESCRIPTOR) { + return EFI_INVALID_PARAMETER; + } + + Temp = (UINT8 *) Configuration; + while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) { + ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp; + + switch (ptr->ResType) { + case ACPI_ADDRESS_SPACE_TYPE_MEM: + AddrLen = (UINT64) ptr->AddrLen; + Alignment = (UINT64) ptr->AddrRangeMax; + if (ptr->AddrSpaceGranularity == 32) { + if (ptr->SpecificFlag == 0x06) { + // + // Apply from GCD + // + RootBridgeInstance->ResAllocNode[TypePMem32].Status = ResSubmitted; + } else { + RootBridgeInstance->ResAllocNode[TypeMem32].Length = AddrLen; + RootBridgeInstance->ResAllocNode[TypeMem32].Alignment = Alignment; + RootBridgeInstance->ResAllocNode[TypeMem32].Status = ResRequested; + HostBridgeInstance->ResourceSubmited = TRUE; + } + } + + if (ptr->AddrSpaceGranularity == 64) { + if (ptr->SpecificFlag == 0x06) { + RootBridgeInstance->ResAllocNode[TypePMem64].Status = ResSubmitted; + } else { + RootBridgeInstance->ResAllocNode[TypeMem64].Length = AddrLen; + RootBridgeInstance->ResAllocNode[TypeMem64].Alignment = Alignment; + RootBridgeInstance->ResAllocNode[TypeMem64].Status = ResSubmitted; + HostBridgeInstance->ResourceSubmited = TRUE; + } + } + break; + + case ACPI_ADDRESS_SPACE_TYPE_IO: + AddrLen = (UINT64) ptr->AddrLen; + Alignment = (UINT64) ptr->AddrRangeMax; + RootBridgeInstance->ResAllocNode[TypeIo].Length = AddrLen; + RootBridgeInstance->ResAllocNode[TypeIo].Alignment = Alignment; + RootBridgeInstance->ResAllocNode[TypeIo].Status = ResRequested; + HostBridgeInstance->ResourceSubmited = TRUE; + break; + + default: + break; + } + + Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); + } + + return EFI_SUCCESS; + } + + List = List->ForwardLink; + } + + return EFI_INVALID_PARAMETER; +} + +EFI_STATUS +EFIAPI +GetProposedResources ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT VOID **Configuration + ) +/*++ + +Routine Description: + This function returns the proposed resource settings for the specified + PCI Root Bridge. + +Arguments: + + This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance. + RootBridgeHandle - The PCI Root Bridge handle. + Configuration - The pointer to the pointer to the PCI I/O + and memory resource descriptor. + +Returns: + + EFI_SUCCESS - Succeed. + EFI_OUT_OF_RESOURCES - Not enough pool to be allocated. + EFI_INVALID_PARAMETER - RootBridgeHandle is not a valid handle. + +--*/ +{ + EFI_LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; + UINTN Index; + UINTN Number; + VOID *Buffer; + UINT8 *Temp; + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ptr; + EFI_STATUS Status; + UINT64 ResStatus; + + Buffer = NULL; + Number = 0; + // + // Get the Host Bridge Instance from the resource allocation protocol + // + HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); + List = HostBridgeInstance->Head.ForwardLink; + + // + // Enumerate the root bridges in this host bridge + // + while (List != &HostBridgeInstance->Head) { + RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + if (RootBridgeHandle == RootBridgeInstance->Handle) { + for (Index = 0; Index < TypeBus; Index++) { + if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) { + Number++; + } + } + + if (Number > 0) { + Status = gBS->AllocatePool ( + EfiBootServicesData, + Number * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR), + &Buffer + ); + + if (EFI_ERROR (Status)) { + return EFI_OUT_OF_RESOURCES; + } + + ZeroMem (Buffer, sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * Number + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); + } + + ASSERT (Buffer != NULL); + Temp = Buffer; + for (Index = 0; Index < TypeBus; Index++) { + if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) { + ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp; + ResStatus = RootBridgeInstance->ResAllocNode[Index].Status; + + switch (Index) { + + case TypeIo: + // + // Io + // + ptr->Desc = 0x8A; + ptr->Len = 0x2B; + ptr->ResType = 1; + ptr->GenFlag = 0; + ptr->SpecificFlag = 0; + ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base; + ptr->AddrRangeMax = 0; + ptr->AddrTranslationOffset = (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; + ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length; + break; + + case TypeMem32: + // + // Memory 32 + // + ptr->Desc = 0x8A; + ptr->Len = 0x2B; + ptr->ResType = 0; + ptr->GenFlag = 0; + ptr->SpecificFlag = 0; + ptr->AddrSpaceGranularity = 32; + ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base; + ptr->AddrRangeMax = 0; + ptr->AddrTranslationOffset = (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; + ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length; + break; + + case TypePMem32: + // + // Prefetch memory 32 + // + ptr->Desc = 0x8A; + ptr->Len = 0x2B; + ptr->ResType = 0; + ptr->GenFlag = 0; + ptr->SpecificFlag = 6; + ptr->AddrSpaceGranularity = 32; + ptr->AddrRangeMin = 0; + ptr->AddrRangeMax = 0; + ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT; + ptr->AddrLen = 0; + break; + + case TypeMem64: + // + // Memory 64 + // + ptr->Desc = 0x8A; + ptr->Len = 0x2B; + ptr->ResType = 0; + ptr->GenFlag = 0; + ptr->SpecificFlag = 0; + ptr->AddrSpaceGranularity = 64; + ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base; + ptr->AddrRangeMax = 0; + ptr->AddrTranslationOffset = (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; + ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length; + break; + + case TypePMem64: + // + // Prefetch memory 64 + // + ptr->Desc = 0x8A; + ptr->Len = 0x2B; + ptr->ResType = 0; + ptr->GenFlag = 0; + ptr->SpecificFlag = 6; + ptr->AddrSpaceGranularity = 64; + ptr->AddrRangeMin = 0; + ptr->AddrRangeMax = 0; + ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT; + ptr->AddrLen = 0; + break; + } + + Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); + } + } + + ((EFI_ACPI_END_TAG_DESCRIPTOR *) Temp)->Desc = 0x79; + ((EFI_ACPI_END_TAG_DESCRIPTOR *) Temp)->Checksum = 0x0; + + *Configuration = Buffer; + + return EFI_SUCCESS; + } + + List = List->ForwardLink; + } + + return EFI_INVALID_PARAMETER; +} + +EFI_STATUS +EFIAPI +PreprocessController ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase + ) +/*++ + +Routine Description: + This function is called for all the PCI controllers that the PCI + bus driver finds. Can be used to Preprogram the controller. + +Arguments: + + This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance. + RootBridgeHandle - The PCI Root Bridge handle. + PciAddress - Address of the controller on the PCI bus. + Phase - The Phase during resource allocation. + +Returns: + + EFI_SUCCESS - Succeed. + EFI_INVALID_PARAMETER - RootBridgeHandle is not a valid handle. + +--*/ +{ + BOOLEAN RootBridgeFound; + EFI_LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; + + if (RootBridgeHandle == NULL) { + return EFI_INVALID_PARAMETER; + } + + RootBridgeFound = FALSE; + HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); + List = HostBridgeInstance->Head.ForwardLink; + + while (List != &HostBridgeInstance->Head) { + RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + + if (RootBridgeHandle == RootBridgeInstance->Handle) { + RootBridgeFound = TRUE; + break; + } + // + // Get next if have + // + List = List->ForwardLink; + } + + if (RootBridgeFound == FALSE) { + return EFI_INVALID_PARAMETER; + } + + return EFI_SUCCESS; +} + +UINT64 +Power2MaxMemory ( + IN UINT64 MemoryLength + ) +/*++ + +Routine Description: + + Calculate maximum memory length that can be fit to a mtrr. + +Arguments: + + MemoryLength - Input memory length. + +Returns: + + Returned Maximum length. + +--*/ +{ + UINT64 Result; + + if (RShiftU64 (MemoryLength, 32)) { + Result = LShiftU64 ((UINT64) GetPowerOfTwo64 ((UINT32) RShiftU64 (MemoryLength, 32)), 32); + } else { + Result = (UINT64) GetPowerOfTwo64 ((UINT32) MemoryLength); + } + + return Result; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.h b/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.h new file mode 100644 index 0000000000..3dddca2d26 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.h @@ -0,0 +1,389 @@ +/** @file +The Header file of the Pci Host Bridge Driver. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#ifndef _PCI_HOST_BRIDGE_H_ +#define _PCI_HOST_BRIDGE_H_ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32 ('e', 'h', 's', 't') +typedef struct { + UINTN Signature; + EFI_HANDLE HostBridgeHandle; + UINTN RootBridgeCount; + EFI_LIST_ENTRY Head; + BOOLEAN ResourceSubmited; + BOOLEAN CanRestarted; + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc; +} PCI_HOST_BRIDGE_INSTANCE; + +#define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) CR (a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE) + +typedef enum { + SocketResourceRatioChanged, + SocketResourceRatioNotChanged, + SocketResourceAdjustMax +} SOCKET_RESOURCE_ADJUSTMENT_RESULT; + +// +// Driver Entry Point +// +EFI_STATUS +EFIAPI +InitializePciHostBridge ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +/*++ + +Routine Description: + + Entry point of this driver. + +Arguments: + + ImageHandle - Image handle of this driver. + SystemTable - Pointer to standard EFI system table. + +Returns: + + EFI_SUCCESS - Succeed. + EFI_DEVICE_ERROR - Fail to install PCI_ROOT_BRIDGE_IO protocol. + +--*/ +; + +// +// HostBridge Resource Allocation interface +// +EFI_STATUS +EFIAPI +NotifyPhase ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase + ) +/*++ + +Routine Description: + + Enter a certain phase of the PCI enumeration process. + +Arguments: + + This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance. + Phase - The phase during enumeration. + +Returns: + + EFI_SUCCESS - Succeed. + EFI_INVALID_PARAMETER - Wrong phase parameter passed in. + EFI_NOT_READY - Resources have not been submitted yet. + +--*/ +; + +EFI_STATUS +EFIAPI +GetNextRootBridge ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN OUT EFI_HANDLE *RootBridgeHandle + ) +/*++ + +Routine Description: + + Return the device handle of the next PCI root bridge that is associated with + this Host Bridge. + +Arguments: + + This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance. + RootBridgeHandle - Returns the device handle of the next PCI Root Bridge. + On input, it holds the RootBridgeHandle returned by the most + recent call to GetNextRootBridge().The handle for the first + PCI Root Bridge is returned if RootBridgeHandle is NULL on input. + +Returns: + + EFI_SUCCESS - Succeed. + EFI_NOT_FOUND - Next PCI root bridge not found. + EFI_INVALID_PARAMETER - Wrong parameter passed in. + +--*/ +; + +EFI_STATUS +EFIAPI +GetAttributes ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT UINT64 *Attributes + ) +/*++ + +Routine Description: + + Returns the attributes of a PCI Root Bridge. + +Arguments: + + This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance + RootBridgeHandle - The device handle of the PCI Root Bridge + that the caller is interested in + Attributes - The pointer to attributes of the PCI Root Bridge + +Returns: + + EFI_SUCCESS - Succeed. + EFI_INVALID_PARAMETER - Attributes parameter passed in is NULL or + RootBridgeHandle is not an EFI_HANDLE + that was returned on a previous call to + GetNextRootBridge(). + +--*/ +; + +EFI_STATUS +EFIAPI +StartBusEnumeration ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT VOID **Configuration + ) +/*++ + +Routine Description: + + This is the request from the PCI enumerator to set up + the specified PCI Root Bridge for bus enumeration process. + +Arguments: + + This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance. + RootBridgeHandle - The PCI Root Bridge to be set up. + Configuration - Pointer to the pointer to the PCI bus resource descriptor. + +Returns: + + EFI_SUCCESS - Succeed. + EFI_OUT_OF_RESOURCES - Not enough pool to be allocated. + EFI_INVALID_PARAMETER - RootBridgeHandle is not a valid handle. + +--*/ +; + +EFI_STATUS +EFIAPI +SetBusNumbers ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN VOID *Configuration + ) +/*++ + +Routine Description: + + This function programs the PCI Root Bridge hardware so that + it decodes the specified PCI bus range. + +Arguments: + + This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance. + RootBridgeHandle - The PCI Root Bridge whose bus range is to be programmed. + Configuration - The pointer to the PCI bus resource descriptor. + +Returns: + + EFI_SUCCESS - Succeed. + EFI_INVALID_PARAMETER - Wrong parameters passed in. + +--*/ +; + +EFI_STATUS +EFIAPI +SubmitResources ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN VOID *Configuration + ) +/*++ + +Routine Description: + + Submits the I/O and memory resource requirements for the specified PCI Root Bridge. + +Arguments: + + This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance + RootBridgeHandle - The PCI Root Bridge whose I/O and memory resource requirements + are being submitted + Configuration - The pointer to the PCI I/O and PCI memory resource descriptor + +Returns: + + EFI_SUCCESS - Succeed. + EFI_INVALID_PARAMETER - Wrong parameters passed in. + +--*/ +; + +EFI_STATUS +EFIAPI +GetProposedResources ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT VOID **Configuration + ) +/*++ + +Routine Description: + + This function returns the proposed resource settings for the specified + PCI Root Bridge. + +Arguments: + + This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance. + RootBridgeHandle - The PCI Root Bridge handle. + Configuration - The pointer to the pointer to the PCI I/O + and memory resource descriptor. + +Returns: + + EFI_SUCCESS - Succeed. + EFI_OUT_OF_RESOURCES - Not enough pool to be allocated. + EFI_INVALID_PARAMETER - RootBridgeHandle is not a valid handle. + +--*/ +; + +EFI_STATUS +EFIAPI +PreprocessController ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase + ) +/*++ + +Routine Description: + + This function is called for all the PCI controllers that the PCI + bus driver finds. Can be used to Preprogram the controller. + +Arguments: + + This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance. + RootBridgeHandle - The PCI Root Bridge handle. + PciAddress - Address of the controller on the PCI bus. + Phase - The Phase during resource allocation. + +Returns: + + EFI_SUCCESS - Succeed. + EFI_INVALID_PARAMETER - RootBridgeHandle is not a valid handle. + +--*/ +; + +// +// Host Bridge Silicon specific hooks +// +UINT64 +GetAllocAttributes ( + IN UINTN RootBridgeIndex + ) +/*++ + +Routine Description: + + Returns the Allocation attributes for the BNB Root Bridge. + +Arguments: + + RootBridgeIndex - The root bridge number. 0 based. + +Returns: + + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | EFI_PCI_HOST_BRIDGE_MEM64_DECODE + +--*/ +; + +EFI_STATUS +GetHostBridgeMemApertures ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, + OUT UINT32 *Mem32Base, + OUT UINT32 *Mem32Limit, + OUT UINT64 *Mem64Base, + OUT UINT64 *Mem64Limit + ) +/*++ + +Routine Description: + + Returns memory apertures for the BNB Root Bridge. + +Arguments: + + PciRootBridgeIo - Pointer to Efi Pci root bridge Io protocol interface instance. + Mem32Base - Pointer to 32 bit memory base. This is the lowest 32 bit memory address + that is decoded by the Host Bridge. + Mem32Limit - Pointer to 32 bit memory limit.This is the highest 32 bit memory address + that is decoded by the Host Bridge. The size of the 32 bit window is + (Mem32Limit - Mem32base + 1). + Mem64Base - Pointer to 64 bit memory base. This is the lowest 64 bit memory address + that is decoded by the Host Bridge. + Mem64Limit - Pointer to 64 bit memory limit.This is the highest 64 bit memory address + that is decoded by the Host Bridge. The size of the 64 bit window is + (Mem64Limit - Mem64base + 1). Set Mem64Limit < Mem64Base if the host bridge + does not support 64 bit memory addresses. + +Returns: + + EFI_SUCCESS - Success. + +--*/ +; + +UINT64 +Power2MaxMemory ( + IN UINT64 MemoryLength + ) +/*++ + +Routine Description: + + Calculate maximum memory length that can be fit to a mtrr. + +Arguments: + + MemoryLength - Input memory length. + +Returns: + + Returned Maximum length. + +--*/ +; + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.inf b/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.inf new file mode 100644 index 0000000000..adf36f6632 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.inf @@ -0,0 +1,61 @@ +## @file +# Component description file for PciHostBridge module +# +# Copyright (c) 2013-2015 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PciHostBridge + FILE_GUID = D58EBCE1-AF26-488d-BE66-C164417F8C13 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InitializePciHostBridge + +[Sources] + PciHostBridge.h + PciRootBridge.h + PciHostBridge.c + PciRootBridgeIo.c + PciHostBridgeSupport.c + PciHostResource.h + +[Packages] + MdePkg/MdePkg.dec + QuarkSocPkg/QuarkSocPkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + UefiBootServicesTableLib + DebugLib + UefiLib + DxeServicesTableLib + UefiRuntimeServicesTableLib + DevicePathLib + BaseMemoryLib + BaseLib + +[Protocols] + gEfiMetronomeArchProtocolGuid + gEfiCpuIo2ProtocolGuid + gEfiDevicePathProtocolGuid + gEfiPciRootBridgeIoProtocolGuid + gEfiPciHostBridgeResourceAllocationProtocolGuid + +[Pcd] + gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeIoBase + gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeIoSize + gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory32Base + gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory32Size + gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory64Base + gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory64Size + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciExpressSize + +[Depex] + gEfiCpuIo2ProtocolGuid AND gEfiMetronomeArchProtocolGuid diff --git a/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridgeSupport.c b/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridgeSupport.c new file mode 100644 index 0000000000..774d658f3a --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridgeSupport.c @@ -0,0 +1,140 @@ +/** @file +Do platform initialization for PCI bridge. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#include "PciHostBridge.h" + +EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo; + +EFI_STATUS +ChipsetPreprocessController ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase + ) +/*++ + +Routine Description: + This function is called for all the PCI controllers that the PCI + bus driver finds. Can be used to Preprogram the controller. + +Arguments: + This -- The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance + RootBridgeHandle -- The PCI Root Bridge handle + PciBusAddress -- Address of the controller on the PCI bus + Phase -- The Phase during resource allocation + +Returns: + EFI_SUCCESS + +--*/ + +// GC_TODO: PciAddress - add argument and description to function comment +// +// GC_TODO: PciAddress - add argument and description to function comment +// +// GC_TODO: PciAddress - add argument and description to function comment +// +// GC_TODO: PciAddress - add argument and description to function comment +// +{ + + EFI_STATUS Status; + UINT8 Latency; + UINT8 CacheLineSize; + + if (mPciRootBridgeIo == NULL) { + // + // Get root bridge in the system. + // + Status = gBS->HandleProtocol (RootBridgeHandle, &gEfiPciRootBridgeIoProtocolGuid, (VOID **) &mPciRootBridgeIo); + ASSERT_EFI_ERROR (Status); + } + + if (Phase == EfiPciBeforeResourceCollection) { + // + // Program the latency register, CLS register + // + PciAddress.Register = PCI_LATENCY_TIMER_OFFSET; + mPciRootBridgeIo->Pci.Read ( + mPciRootBridgeIo, + EfiPciWidthUint8, + *((UINT64 *) &PciAddress), + 1, + &Latency + ); + + // + // PCI-x cards come up with a default latency of 0x40. Don't touch them. + // + if (Latency == 0) { + Latency = DEFAULT_PCI_LATENCY; + mPciRootBridgeIo->Pci.Write ( + mPciRootBridgeIo, + EfiPciWidthUint8, + *((UINT64 *) &PciAddress), + 1, + &Latency + ); + } + // + // Program Cache Line Size as 64bytes + // 16 of DWORDs = 64bytes (0x10) + // + PciAddress.Register = PCI_CACHELINE_SIZE_OFFSET; + CacheLineSize = 0x10; + mPciRootBridgeIo->Pci.Write ( + mPciRootBridgeIo, + EfiPciWidthUint8, + *((UINT64 *) &PciAddress), + 1, + &CacheLineSize + ); + + } + + return EFI_SUCCESS; +} + +UINT64 +GetAllocAttributes ( + IN UINTN RootBridgeIndex + ) +/*++ + +Routine Description: + + Returns the Allocation attributes for the BNB Root Bridge. + +Arguments: + + RootBridgeIndex - The root bridge number. 0 based. + +Returns: + + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | EFI_PCI_HOST_BRIDGE_MEM64_DECODE + +--*/ +{ + // + // Cannot have more than one Root bridge + // + //ASSERT (RootBridgeIndex == 0); + + // + // PCI Root Bridge does not support separate windows for Non-prefetchable + // and Prefetchable memory. A PCI bus driver needs to include requests for + // Prefetchable memory in the Non-prefetchable memory pool. + // Further TNB does not support 64 bit memory apertures for PCI. BNB + // can only have system memory above 4 GB, + // + + return EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | EFI_PCI_HOST_BRIDGE_MEM64_DECODE; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostResource.h b/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostResource.h new file mode 100644 index 0000000000..da7d55d503 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostResource.h @@ -0,0 +1,60 @@ +/** @file +The Header file of the Pci Host Bridge Driver. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#ifndef _PCI_HOST_RESOURCE_H_ +#define _PCI_HOST_RESOURCE_H_ + +#include + +#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL +#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL + +typedef struct { + UINTN BusBase; + UINTN BusLimit; + UINTN BusReserve; + + UINT32 Mem32Base; + UINT32 Mem32Limit; + + UINT64 Mem64Base; + UINT64 Mem64Limit; + + UINTN IoBase; + UINTN IoLimit; +} PCI_ROOT_BRIDGE_RESOURCE_APERTURE; + +typedef enum { + TypeIo = 0, + TypeMem32, + TypePMem32, + TypeMem64, + TypePMem64, + TypeBus, + TypeMax +} PCI_RESOURCE_TYPE; + +typedef enum { + ResNone = 0, + ResSubmitted, + ResRequested, + ResAllocated, + ResStatusMax +} RES_STATUS; + +typedef struct { + PCI_RESOURCE_TYPE Type; + UINT64 Base; + UINT64 Length; + UINT64 Alignment; + RES_STATUS Status; +} PCI_RES_NODE; + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciRootBridge.h b/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciRootBridge.h new file mode 100644 index 0000000000..613265d2ff --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciRootBridge.h @@ -0,0 +1,693 @@ +/** @file +The PCI Root Bridge header file. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#ifndef _PCI_ROOT_BRIDGE_H_ +#define _PCI_ROOT_BRIDGE_H_ + +#include +#include +#include +#include + +// +// Driver Consumed Protocol Prototypes +// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +// +// Define the region of memory used for DMA memory +// +#define DMA_MEMORY_TOP 0x0000000001FFFFFFULL + +// +// The number of PCI root bridges +// +#define ROOT_BRIDGE_COUNT 1 + +// +// The default latency for controllers +// +#define DEFAULT_PCI_LATENCY 0x20 + +// +// Define resource status constant +// +typedef struct { + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation; + UINTN NumberOfBytes; + UINTN NumberOfPages; + EFI_PHYSICAL_ADDRESS HostAddress; + EFI_PHYSICAL_ADDRESS MappedHostAddress; +} MAP_INFO; + +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; + +#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('e', '2', 'p', 'b') + +typedef struct { + UINT32 Signature; + EFI_LIST_ENTRY Link; + EFI_HANDLE Handle; + UINT64 RootBridgeAllocAttrib; + UINT64 Attributes; + UINT64 Supports; + PCI_RES_NODE ResAllocNode[6]; + PCI_ROOT_BRIDGE_RESOURCE_APERTURE Aperture; + EFI_LOCK PciLock; + UINTN PciAddress; + UINTN PciData; + UINT32 HecBase; + UINT32 HecLen; + UINTN BusScanCount; + BOOLEAN BusNumberAssigned; + VOID *ConfigBuffer; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io; +} PCI_ROOT_BRIDGE_INSTANCE; + +// +// Driver Instance Data Macros +// +#define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE) + +#define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE) + +EFI_STATUS +SimpleIioRootBridgeConstructor ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol, + IN EFI_HANDLE HostBridgeHandle, + IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAppeture, + IN UINT64 AllocAttributes + ) +/*++ + +Routine Description: + + Construct the Pci Root Bridge Io protocol. + +Arguments: + + Protocol - Protocol to initialize. + HostBridgeHandle - Handle to the HostBridge. + ResAppeture - Resource apperture of the root bridge. + AllocAttributes - Attribute of resouce allocated. + +Returns: + + EFI_SUCCESS - Success. + Others - Fail. + +--*/ +; + +// +// Protocol Member Function Prototypes +// +EFI_STATUS +EFIAPI +RootBridgeIoPollMem ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ) +/*++ + +Routine Description: + + Poll an address in memory mapped space until an exit condition is met + or a timeout occurs. + +Arguments: + + This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + Width - Width of the memory operation. + Address - The base address of the memory operation. + Mask - Mask used for polling criteria. + Value - Comparison value used for polling exit criteria. + Delay - Number of 100ns units to poll. + Result - Pointer to the last value read from memory location. + +Returns: + + EFI_SUCCESS - Success. + EFI_INVALID_PARAMETER - Invalid parameter found. + EFI_TIMEOUT - Delay expired before a match occurred. + EFI_OUT_OF_RESOURCES - Fail due to lack of resources. + +--*/ +; + +EFI_STATUS +EFIAPI +RootBridgeIoPollIo ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ) +/*++ + +Routine Description: + + Poll an address in I/O space until an exit condition is met + or a timeout occurs. + +Arguments: + + This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + Width - Width of I/O operation. + Address - The base address of the I/O operation. + Mask - Mask used for polling criteria. + Value - Comparison value used for polling exit criteria. + Delay - Number of 100ns units to poll. + Result - Pointer to the last value read from memory location. + +Returns: + + EFI_SUCCESS - Success. + EFI_INVALID_PARAMETER - Invalid parameter found. + EFI_TIMEOUT - Delay expired before a match occurred. + EFI_OUT_OF_RESOURCES - Fail due to lack of resources. + +--*/ +; + +EFI_STATUS +EFIAPI +RootBridgeIoMemRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +/*++ + +Routine Description: + + Allow read from memory mapped I/O space. + +Arguments: + + This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + Width - The width of memory operation. + Address - Base address of the memory operation. + Count - Number of memory opeartion to perform. + Buffer - The destination buffer to store data. + +Returns: + + EFI_SUCCESS - Success. + EFI_INVALID_PARAMETER - Invalid parameter found. + EFI_OUT_OF_RESOURCES - Fail due to lack of resources. + +--*/ +; + +EFI_STATUS +EFIAPI +RootBridgeIoMemWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +/*++ + +Routine Description: + + Allow write to memory mapped I/O space. + +Arguments: + + This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + Width - The width of memory operation. + Address - Base address of the memory operation. + Count - Number of memory opeartion to perform. + Buffer - The source buffer to write data from. + +Returns: + + EFI_SUCCESS - Success. + EFI_INVALID_PARAMETER - Invalid parameter found. + EFI_OUT_OF_RESOURCES - Fail due to lack of resources. + +--*/ +; + +EFI_STATUS +EFIAPI +RootBridgeIoIoRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 UserAddress, + IN UINTN Count, + IN OUT VOID *UserBuffer + ) +/*++ + +Routine Description: + + Enable a PCI driver to read PCI controller registers in the + PCI root bridge I/O space. + +Arguments: + + This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + Width - Signifies the width of the memory operation. + UserAddress - The base address of the I/O operation. + Count - The number of I/O operations to perform. + UserBuffer - The destination buffer to store the results. + +Returns: + + EFI_SUCCESS - The data was read from the PCI root bridge. + EFI_INVALID_PARAMETER - Invalid parameters found. + EFI_OUT_OF_RESOURCES - The request could not be completed due to a lack of + resources. +--*/ +; + +EFI_STATUS +EFIAPI +RootBridgeIoIoWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 UserAddress, + IN UINTN Count, + IN OUT VOID *UserBuffer + ) +/*++ + +Routine Description: + + Enable a PCI driver to write to PCI controller registers in the + PCI root bridge I/O space. + +Arguments: + + This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + Width - Signifies the width of the memory operation. + UserAddress - The base address of the I/O operation. + Count - The number of I/O operations to perform. + UserBuffer - The source buffer to write data from. + +Returns: + + EFI_SUCCESS - The data was written to the PCI root bridge. + EFI_INVALID_PARAMETER - Invalid parameters found. + EFI_OUT_OF_RESOURCES - The request could not be completed due to a lack of + resources. +--*/ +; + +EFI_STATUS +EFIAPI +RootBridgeIoCopyMem ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 DestAddress, + IN UINT64 SrcAddress, + IN UINTN Count + ) +/*++ + +Routine Description: + + Copy one region of PCI root bridge memory space to be copied to + another region of PCI root bridge memory space. + +Arguments: + + This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + Width - Signifies the width of the memory operation. + DestAddress - Destination address of the memory operation. + SrcAddress - Source address of the memory operation. + Count - Number of memory operations to perform. + +Returns: + + EFI_SUCCESS - The data was copied successfully. + EFI_INVALID_PARAMETER - Invalid parameters found. + EFI_OUT_OF_RESOURCES - The request could not be completed due to a lack of + resources. +--*/ +; + +EFI_STATUS +EFIAPI +RootBridgeIoPciRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +/*++ + +Routine Description: + + Allows read from PCI configuration space. + +Arguments: + + This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + Width - Signifies the width of the memory operation. + Address - The address within the PCI configuration space + for the PCI controller. + Count - The number of PCI configuration operations + to perform. + Buffer - The destination buffer to store the results. + +Returns: + + EFI_SUCCESS - The data was read from the PCI root bridge. + EFI_INVALID_PARAMETER - Invalid parameters found. + EFI_OUT_OF_RESOURCES - The request could not be completed due to a lack of + resources. +--*/ +; + +EFI_STATUS +EFIAPI +RootBridgeIoPciWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +/*++ + +Routine Description: + + Allows write to PCI configuration space. + +Arguments: + + This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + Width - Signifies the width of the memory operation. + Address - The address within the PCI configuration space + for the PCI controller. + Count - The number of PCI configuration operations + to perform. + Buffer - The source buffer to get the results. + +Returns: + + EFI_SUCCESS - The data was written to the PCI root bridge. + EFI_INVALID_PARAMETER - Invalid parameters found. + EFI_OUT_OF_RESOURCES - The request could not be completed due to a lack of + resources. +--*/ +; + +EFI_STATUS +EFIAPI +RootBridgeIoMap ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ) +/*++ + +Routine Description: + + Provides the PCI controller-specific address needed to access + system memory for DMA. + +Arguments: + + This - A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + Operation - Indicate if the bus master is going to read or write + to system memory. + HostAddress - The system memory address to map on the PCI controller. + NumberOfBytes - On input the number of bytes to map. + On output the number of bytes that were mapped. + DeviceAddress - The resulting map address for the bus master PCI + controller to use to access the system memory's HostAddress. + Mapping - The value to pass to Unmap() when the bus master DMA + operation is complete. + +Returns: + + EFI_SUCCESS - Success. + EFI_INVALID_PARAMETER - Invalid parameters found. + EFI_UNSUPPORTED - The HostAddress cannot be mapped as a common + buffer. + EFI_DEVICE_ERROR - The System hardware could not map the requested + address. + EFI_OUT_OF_RESOURCES - The request could not be completed due to + lack of resources. + +--*/ +; + +EFI_STATUS +EFIAPI +RootBridgeIoUnmap ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN VOID *Mapping + ) +/*++ + +Routine Description: + + Completes the Map() operation and releases any corresponding resources. + +Arguments: + + This - Pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + Mapping - The value returned from Map() operation. + +Returns: + + EFI_SUCCESS - The range was unmapped successfully. + EFI_INVALID_PARAMETER - Mapping is not a value that was returned + by Map operation. + EFI_DEVICE_ERROR - The data was not committed to the target + system memory. + +--*/ +; + +EFI_STATUS +EFIAPI +RootBridgeIoAllocateBuffer ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_ALLOCATE_TYPE Type, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + OUT VOID **HostAddress, + IN UINT64 Attributes + ) +/*++ + +Routine Description: + + Allocates pages that are suitable for a common buffer mapping. + +Arguments: + + This - Pointer to EFI_ROOT_BRIDGE_IO_PROTOCOL instance. + Type - Not used and can be ignored. + MemoryType - Type of memory to allocate. + Pages - Number of pages to allocate. + HostAddress - Pointer to store the base system memory address + of the allocated range. + Attributes - Requested bit mask of attributes of the allocated + range. + +Returns: + + EFI_SUCCESS - The requested memory range were allocated. + EFI_INVALID_PARAMETER - Invalid parameter found. + EFI_UNSUPPORTED - Attributes is unsupported. + +--*/ +; + +EFI_STATUS +EFIAPI +RootBridgeIoFreeBuffer ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN UINTN Pages, + OUT VOID *HostAddress + ) +/*++ + +Routine Description: + + Free memory allocated in AllocateBuffer. + +Arguments: + + This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + instance. + Pages - Number of pages to free. + HostAddress - The base system memory address of the + allocated range. + +Returns: + + EFI_SUCCESS - Requested memory pages were freed. + EFI_INVALID_PARAMETER - Invalid parameter found. + +--*/ +; + +EFI_STATUS +EFIAPI +RootBridgeIoFlush ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This + ) +/*++ + +Routine Description: + + Flushes all PCI posted write transactions from a PCI host + bridge to system memory. + +Arguments: + + This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + +Returns: + + EFI_SUCCESS - PCI posted write transactions were flushed + from PCI host bridge to system memory. + EFI_DEVICE_ERROR - Fail due to hardware error. + +--*/ +; + +EFI_STATUS +EFIAPI +RootBridgeIoGetAttributes ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + OUT UINT64 *Supported, + OUT UINT64 *Attributes + ) +/*++ + +Routine Description: + + Get the attributes that a PCI root bridge supports and + the attributes the PCI root bridge is currently using. + +Arguments: + + This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + instance. + Supports - A pointer to the mask of attributes that + this PCI root bridge supports. + Attributes - A pointer to the mask of attributes that + this PCI root bridge is currently using. +Returns: + + EFI_SUCCESS - Success. + EFI_INVALID_PARAMETER - Invalid parameter found. + +--*/ + +// GC_TODO: Supported - add argument and description to function comment +// +// GC_TODO: Supported - add argument and description to function comment +// +// GC_TODO: Supported - add argument and description to function comment +// +; + +EFI_STATUS +EFIAPI +RootBridgeIoSetAttributes ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN UINT64 Attributes, + IN OUT UINT64 *ResourceBase, + IN OUT UINT64 *ResourceLength + ) +/*++ + +Routine Description: + + Sets the attributes for a resource range on a PCI root bridge. + +Arguments: + + This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + Attributes - The mask of attributes to set. + ResourceBase - Pointer to the base address of the resource range + to be modified by the attributes specified by Attributes. + ResourceLength - Pointer to the length of the resource range to be modified. + +Returns: + EFI_SUCCESS - Success. + EFI_INVALID_PARAMETER - Invalid parameter found. + EFI_OUT_OF_RESOURCES - Not enough resources to set the attributes upon. + +--*/ +; + +EFI_STATUS +EFIAPI +RootBridgeIoConfiguration ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + OUT VOID **Resources + ) +/*++ + +Routine Description: + + Retrieves the current resource settings of this PCI root bridge + in the form of a set of ACPI 2.0 resource descriptor. + +Arguments: + + This - Pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + Resources - Pointer to the ACPI 2.0 resource descriptor that + describe the current configuration of this PCI root + bridge. + +Returns: + + EFI_SUCCESS - Success. + EFI_UNSUPPORTED - Current configuration of the PCI root bridge + could not be retrieved. + +--*/ +; + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciRootBridgeIo.c b/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciRootBridgeIo.c new file mode 100644 index 0000000000..12b2e18720 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciRootBridgeIo.c @@ -0,0 +1,1610 @@ +/** @file +IIO PCI Root Bridge Io Protocol code. Generic enough to work for all IIOs. +Does not support configuration accesses to the extended PCI Express registers yet. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#include "PciRootBridge.h" + +// +// Define PCI express offse +// +#define PCIE_OFF(Bus, Device, Function, Register) \ + ((UINT64) ((UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) (Function << 12) + (UINTN) (Register))) + +// +// Pci Root Bridge Io Module Variables +// +EFI_METRONOME_ARCH_PROTOCOL *mMetronome; +EFI_CPU_IO2_PROTOCOL *mCpuIo; + +EFI_STATUS +SimpleIioRootBridgeConstructor ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol, + IN EFI_HANDLE HostBridgeHandle, + IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture, + UINT64 AllocAttributes + ) +/*++ + +Routine Description: + + Construct the Pci Root Bridge Io protocol. + +Arguments: + + Protocol - Protocol to initialize. + HostBridgeHandle - Handle to the HostBridge. + ResAperture - Resource apperture of the root bridge. + AllocAttributes - Attribute of resouce allocated. + +Returns: + + EFI_SUCCESS - Success. + Others - Fail. + +--*/ +{ + EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *PrivateData; + PCI_RESOURCE_TYPE Index; + UINT32 HecBase; + UINT32 HecSize; + + PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (Protocol); + + // + // Initialize the apertures with default values + // + CopyMem ( + &PrivateData->Aperture, + ResAperture, + sizeof (PCI_ROOT_BRIDGE_RESOURCE_APERTURE) + ); + + for (Index = TypeIo; Index < TypeMax; Index++) { + PrivateData->ResAllocNode[Index].Type = Index; + PrivateData->ResAllocNode[Index].Base = 0; + PrivateData->ResAllocNode[Index].Length = 0; + PrivateData->ResAllocNode[Index].Status = ResNone; + } + + EfiInitializeLock (&PrivateData->PciLock, TPL_HIGH_LEVEL); + PrivateData->PciAddress = 0xCF8; + PrivateData->PciData = 0xCFC; + + PrivateData->RootBridgeAllocAttrib = AllocAttributes; + PrivateData->Attributes = 0; + PrivateData->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | + EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | + EFI_PCI_ATTRIBUTE_ISA_IO_16 | + EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 | + EFI_PCI_ATTRIBUTE_VGA_MEMORY | + EFI_PCI_ATTRIBUTE_VGA_IO_16; + + // + // Don't support BASE above 4GB currently + // Position to bit 39:28 + // + HecBase = (UINT32) PcdGet64 (PcdPciExpressBaseAddress); + HecSize = (UINT32) PcdGet64 (PcdPciExpressSize); + + ASSERT ((HecBase & (HecSize - 1)) == 0); + ASSERT (HecBase != 0); + + PrivateData->HecBase = HecBase; + PrivateData->HecLen = HecSize; + + PrivateData->BusNumberAssigned = FALSE; + PrivateData->BusScanCount = 0; + + Protocol->ParentHandle = HostBridgeHandle; + + Protocol->PollMem = RootBridgeIoPollMem; + Protocol->PollIo = RootBridgeIoPollIo; + + Protocol->Mem.Read = RootBridgeIoMemRead; + Protocol->Mem.Write = RootBridgeIoMemWrite; + + Protocol->Io.Read = RootBridgeIoIoRead; + Protocol->Io.Write = RootBridgeIoIoWrite; + + Protocol->CopyMem = RootBridgeIoCopyMem; + + Protocol->Pci.Read = RootBridgeIoPciRead; + Protocol->Pci.Write = RootBridgeIoPciWrite; + + Protocol->Map = RootBridgeIoMap; + Protocol->Unmap = RootBridgeIoUnmap; + + Protocol->AllocateBuffer = RootBridgeIoAllocateBuffer; + Protocol->FreeBuffer = RootBridgeIoFreeBuffer; + + Protocol->Flush = RootBridgeIoFlush; + + Protocol->GetAttributes = RootBridgeIoGetAttributes; + Protocol->SetAttributes = RootBridgeIoSetAttributes; + + Protocol->Configuration = RootBridgeIoConfiguration; + + Protocol->SegmentNumber = 0; + + Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **) &mMetronome); + ASSERT_EFI_ERROR (Status); + + Status = gBS->LocateProtocol ( + &gEfiCpuIo2ProtocolGuid, + NULL, + (VOID **) &mCpuIo + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +RootBridgeIoPollMem ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ) +/*++ + +Routine Description: + + Poll an address in memory mapped space until an exit condition is met + or a timeout occurs. + +Arguments: + + This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + Width - Width of the memory operation. + Address - The base address of the memory operation. + Mask - Mask used for polling criteria. + Value - Comparison value used for polling exit criteria. + Delay - Number of 100ns units to poll. + Result - Pointer to the last value read from memory location. + +Returns: + + EFI_SUCCESS - Success. + EFI_INVALID_PARAMETER - Invalid parameter found. + EFI_TIMEOUT - Delay expired before a match occurred. + EFI_OUT_OF_RESOURCES - Fail due to lack of resources. + +--*/ +{ + EFI_STATUS Status; + UINT64 NumberOfTicks; + UINT32 Remainder; + + if (Result == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (Width < 0 || Width > EfiPciWidthUint64) { + return EFI_INVALID_PARAMETER; + } + // + // No matter what, always do a single poll. + // + Status = This->Mem.Read ( + This, + Width, + Address, + 1, + Result + ); + if (EFI_ERROR (Status)) { + return Status; + } + + if ((*Result & Mask) == Value) { + return EFI_SUCCESS; + } + + if (Delay != 0) { + // + // Determine the proper # of metronome ticks to wait for polling the + // location. The nuber of ticks is Roundup (Delay / mMetronome->TickPeriod)+1 + // The "+1" to account for the possibility of the first tick being short + // because we started in the middle of a tick. + // + // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome + // protocol definition is updated. + // + NumberOfTicks = DivU64x32Remainder ( + Delay, + (UINT32) mMetronome->TickPeriod, + &Remainder + ); + if (Remainder != 0) { + NumberOfTicks += 1; + } + + NumberOfTicks += 1; + + while (NumberOfTicks) { + + mMetronome->WaitForTick (mMetronome, 1); + + Status = This->Mem.Read ( + This, + Width, + Address, + 1, + Result + ); + if (EFI_ERROR (Status)) { + return Status; + } + + if ((*Result & Mask) == Value) { + return EFI_SUCCESS; + } + + NumberOfTicks -= 1; + } + } + + return EFI_TIMEOUT; +} + +EFI_STATUS +EFIAPI +RootBridgeIoPollIo ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ) +/*++ + +Routine Description: + + Poll an address in I/O space until an exit condition is met + or a timeout occurs. + +Arguments: + + This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + Width - Width of I/O operation. + Address - The base address of the I/O operation. + Mask - Mask used for polling criteria. + Value - Comparison value used for polling exit criteria. + Delay - Number of 100ns units to poll. + Result - Pointer to the last value read from memory location. + +Returns: + + EFI_SUCCESS - Success. + EFI_INVALID_PARAMETER - Invalid parameter found. + EFI_TIMEOUT - Delay expired before a match occurred. + EFI_OUT_OF_RESOURCES - Fail due to lack of resources. + +--*/ +{ + EFI_STATUS Status; + UINT64 NumberOfTicks; + UINT32 Remainder; + + // + // No matter what, always do a single poll. + // + if (Result == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (Width < 0 || Width > EfiPciWidthUint64) { + return EFI_INVALID_PARAMETER; + } + + Status = This->Io.Read ( + This, + Width, + Address, + 1, + Result + ); + if (EFI_ERROR (Status)) { + return Status; + } + + if ((*Result & Mask) == Value) { + return EFI_SUCCESS; + } + + if (Delay != 0) { + // + // Determine the proper # of metronome ticks to wait for polling the + // location. The number of ticks is Roundup (Delay / mMetronome->TickPeriod)+1 + // The "+1" to account for the possibility of the first tick being short + // because we started in the middle of a tick. + // + NumberOfTicks = DivU64x32Remainder ( + Delay, + (UINT32) mMetronome->TickPeriod, + &Remainder + ); + if (Remainder != 0) { + NumberOfTicks += 1; + } + + NumberOfTicks += 1; + + while (NumberOfTicks) { + + mMetronome->WaitForTick (mMetronome, 1); + + Status = This->Io.Read ( + This, + Width, + Address, + 1, + Result + ); + if (EFI_ERROR (Status)) { + return Status; + } + + if ((*Result & Mask) == Value) { + return EFI_SUCCESS; + } + + NumberOfTicks -= 1; + } + } + + return EFI_TIMEOUT; +} + +EFI_STATUS +EFIAPI +RootBridgeIoMemRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +/*++ + +Routine Description: + + Allow read from memory mapped I/O space. + +Arguments: + + This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + Width - The width of memory operation. + Address - Base address of the memory operation. + Count - Number of memory opeartion to perform. + Buffer - The destination buffer to store data. + +Returns: + + EFI_SUCCESS - Success. + EFI_INVALID_PARAMETER - Invalid parameter found. + EFI_OUT_OF_RESOURCES - Fail due to lack of resources. + +--*/ +{ + PCI_ROOT_BRIDGE_INSTANCE *PrivateData; + if (Buffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (Width < 0 || + Width == EfiPciWidthUint64 || + Width == EfiPciWidthFifoUint64 || + Width == EfiPciWidthFillUint64 || + Width >= EfiPciWidthMaximum + ) { + return EFI_INVALID_PARAMETER; + } + + PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + // + // Check memory access limit + // + if (PrivateData->Aperture.Mem64Limit > PrivateData->Aperture.Mem64Base) { + if (Address > PrivateData->Aperture.Mem64Limit) { + return EFI_INVALID_PARAMETER; + } + } else { + if (Address > PrivateData->Aperture.Mem32Limit) { + return EFI_INVALID_PARAMETER; + } + } + + return mCpuIo->Mem.Read ( + mCpuIo, + (EFI_CPU_IO_PROTOCOL_WIDTH) Width, + Address, + Count, + Buffer + ); +} + +EFI_STATUS +EFIAPI +RootBridgeIoMemWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +/*++ + +Routine Description: + + Allow write to memory mapped I/O space. + +Arguments: + + This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + Width - The width of memory operation. + Address - Base address of the memory operation. + Count - Number of memory opeartion to perform. + Buffer - The source buffer to write data from. + +Returns: + + EFI_SUCCESS - Success. + EFI_INVALID_PARAMETER - Invalid parameter found. + EFI_OUT_OF_RESOURCES - Fail due to lack of resources. + +--*/ +{ + PCI_ROOT_BRIDGE_INSTANCE *PrivateData; + + if (Buffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (Width < 0 || + Width == EfiPciWidthUint64 || + Width == EfiPciWidthFifoUint64 || + Width == EfiPciWidthFillUint64 || + Width >= EfiPciWidthMaximum + ) { + return EFI_INVALID_PARAMETER; + } + + PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + + // + // Check memory access limit + // + if (PrivateData->Aperture.Mem64Limit > PrivateData->Aperture.Mem64Base) { + if (Address > PrivateData->Aperture.Mem64Limit) { + return EFI_INVALID_PARAMETER; + } + } else { + if (Address > PrivateData->Aperture.Mem32Limit) { + return EFI_INVALID_PARAMETER; + } + } + + return mCpuIo->Mem.Write ( + mCpuIo, + (EFI_CPU_IO_PROTOCOL_WIDTH) Width, + Address, + Count, + Buffer + ); +} + +EFI_STATUS +EFIAPI +RootBridgeIoIoRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +/*++ + +Routine Description: + + Enable a PCI driver to read PCI controller registers in the + PCI root bridge I/O space. + +Arguments: + + This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + Width - Signifies the width of the memory operation. + Address - The base address of the I/O operation. + Count - The number of I/O operations to perform. + Buffer - The destination buffer to store the results. + +Returns: + + EFI_SUCCESS - The data was read from the PCI root bridge. + EFI_INVALID_PARAMETER - Invalid parameters found. + EFI_OUT_OF_RESOURCES - The request could not be completed due to a lack of + resources. +--*/ +{ + + UINTN AlignMask; + PCI_ROOT_BRIDGE_INSTANCE *PrivateData; + + if (Buffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (Width < 0 || + Width == EfiPciWidthUint64 || + Width == EfiPciWidthFifoUint64 || + Width == EfiPciWidthFillUint64 || + Width >= EfiPciWidthMaximum + ) { + return EFI_INVALID_PARAMETER; + } + + PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + + // + // AlignMask = (1 << Width) - 1; + // + AlignMask = (1 << (Width & 0x03)) - 1; + + // + // check Io access limit + // + if (Address > PrivateData->Aperture.IoLimit) { + return EFI_INVALID_PARAMETER; + } + + if (Address & AlignMask) { + return EFI_INVALID_PARAMETER; + } + + return mCpuIo->Io.Read ( + mCpuIo, + (EFI_CPU_IO_PROTOCOL_WIDTH) Width, + Address, + Count, + Buffer + ); + +} + +EFI_STATUS +EFIAPI +RootBridgeIoIoWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +/*++ + +Routine Description: + + Enable a PCI driver to write to PCI controller registers in the + PCI root bridge I/O space. + +Arguments: + + This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + Width - Signifies the width of the memory operation. + Address - The base address of the I/O operation. + Count - The number of I/O operations to perform. + Buffer - The source buffer to write data from. + +Returns: + + EFI_SUCCESS - The data was written to the PCI root bridge. + EFI_INVALID_PARAMETER - Invalid parameters found. + EFI_OUT_OF_RESOURCES - The request could not be completed due to a lack of + resources. +--*/ +{ + UINTN AlignMask; + PCI_ROOT_BRIDGE_INSTANCE *PrivateData; + + if (Buffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (Width < 0 || + Width == EfiPciWidthUint64 || + Width == EfiPciWidthFifoUint64 || + Width == EfiPciWidthFillUint64 || + Width >= EfiPciWidthMaximum + ) { + return EFI_INVALID_PARAMETER; + } + + PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + + // + // AlignMask = (1 << Width) - 1; + // + AlignMask = (1 << (Width & 0x03)) - 1; + + // + // Check Io access limit + // + if (Address > PrivateData->Aperture.IoLimit) { + return EFI_INVALID_PARAMETER; + } + + if (Address & AlignMask) { + return EFI_INVALID_PARAMETER; + } + + return mCpuIo->Io.Write ( + mCpuIo, + (EFI_CPU_IO_PROTOCOL_WIDTH) Width, + Address, + Count, + Buffer + ); + +} + +EFI_STATUS +EFIAPI +RootBridgeIoCopyMem ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 DestAddress, + IN UINT64 SrcAddress, + IN UINTN Count + ) +/*++ + +Routine Description: + + Copy one region of PCI root bridge memory space to be copied to + another region of PCI root bridge memory space. + +Arguments: + + This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + Width - Signifies the width of the memory operation. + DestAddress - Destination address of the memory operation. + SrcAddress - Source address of the memory operation. + Count - Number of memory operations to perform. + +Returns: + + EFI_SUCCESS - The data was copied successfully. + EFI_INVALID_PARAMETER - Invalid parameters found. + EFI_OUT_OF_RESOURCES - The request could not be completed due to a lack of + resources. +--*/ +{ + EFI_STATUS Status; + BOOLEAN Direction; + UINTN Stride; + UINTN Index; + UINT64 Result; + + if (Width < 0 || Width > EfiPciWidthUint64) { + return EFI_INVALID_PARAMETER; + } + + if (DestAddress == SrcAddress) { + return EFI_SUCCESS; + } + + Stride = (UINTN)1 << Width; + + Direction = TRUE; + if ((DestAddress > SrcAddress) && (DestAddress < (SrcAddress + Count * Stride))) { + Direction = FALSE; + SrcAddress = SrcAddress + (Count - 1) * Stride; + DestAddress = DestAddress + (Count - 1) * Stride; + } + + for (Index = 0; Index < Count; Index++) { + Status = RootBridgeIoMemRead ( + This, + Width, + SrcAddress, + 1, + &Result + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = RootBridgeIoMemWrite ( + This, + Width, + DestAddress, + 1, + &Result + ); + if (EFI_ERROR (Status)) { + return Status; + } + + if (Direction) { + SrcAddress += Stride; + DestAddress += Stride; + } else { + SrcAddress -= Stride; + DestAddress -= Stride; + } + } + + return EFI_SUCCESS; +} + +EFI_STATUS +RootBridgeIoPciRW ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN BOOLEAN Write, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 UserAddress, + IN UINTN Count, + IN OUT VOID *UserBuffer + ) +/*++ + +Routine Description: + +Arguments: + +Returns: + +--*/ +{ + PCI_CONFIG_ACCESS_CF8 Pci; + PCI_CONFIG_ACCESS_CF8 PciAligned; + UINT32 Stride; + UINTN PciData; + UINTN PciDataStride; + PCI_ROOT_BRIDGE_INSTANCE *PrivateData; + + if (Width >= EfiPciWidthMaximum) { + return EFI_INVALID_PARAMETER; + } + + PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This); + + ASSERT (((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*)&UserAddress)->ExtendedRegister == 0x00); + + Stride = 1 << Width; + + Pci.Bits.Reg = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &UserAddress)->Register; + Pci.Bits.Func = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &UserAddress)->Function; + Pci.Bits.Dev = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &UserAddress)->Device; + Pci.Bits.Bus = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &UserAddress)->Bus; + Pci.Bits.Reserved = 0; + Pci.Bits.Enable = 1; + + // + // PCI Configure access are all 32-bit aligned, but by accessing the + // CONFIG_DATA_REGISTER (0xcfc) with different widths more cycle types + // are possible on PCI. + // + // To read a byte of PCI configuration space you load 0xcf8 and + // read 0xcfc, 0xcfd, 0xcfe, 0xcff + // + PciDataStride = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &UserAddress)->Register & 0x03; + + while (Count) { + PciAligned = Pci; + PciAligned.Bits.Reg &= 0xfc; + PciData = PrivateData->PciData + PciDataStride; + EfiAcquireLock(&PrivateData->PciLock); + This->Io.Write (This, EfiPciWidthUint32, \ + PrivateData->PciAddress, 1, &PciAligned); + if (Write) { + This->Io.Write (This, Width, PciData, 1, UserBuffer); + } else { + This->Io.Read (This, Width, PciData, 1, UserBuffer); + } + EfiReleaseLock(&PrivateData->PciLock); + UserBuffer = ((UINT8 *)UserBuffer) + Stride; + PciDataStride = (PciDataStride + Stride) % 4; + Count -= 1; + + // + // Only increment the PCI address if Width is not a FIFO. + // + if (Width >= EfiPciWidthUint8 && Width <= EfiPciWidthUint64) { + Pci.Bits.Reg += Stride; + } + } + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +RootBridgeIoPciRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +/*++ + +Routine Description: + + Allows read from PCI configuration space. + +Arguments: + + This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + Width - Signifies the width of the memory operation. + Address - The address within the PCI configuration space + for the PCI controller. + Count - The number of PCI configuration operations + to perform. + Buffer - The destination buffer to store the results. + +Returns: + + EFI_SUCCESS - The data was read from the PCI root bridge. + EFI_INVALID_PARAMETER - Invalid parameters found. + EFI_OUT_OF_RESOURCES - The request could not be completed due to a lack of + resources. +--*/ +{ + PCI_ROOT_BRIDGE_INSTANCE *PrivateData; + UINT32 PciBus; + UINT32 PciDev; + UINT32 PciFn; + UINT32 PciExtReg; + UINT64 ExtConfigAdd; + + if (Buffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (Width < 0 || + Width == EfiPciWidthUint64 || + Width == EfiPciWidthFifoUint64 || + Width == EfiPciWidthFillUint64 || + Width >= EfiPciWidthMaximum + ) { + return EFI_INVALID_PARAMETER; + } + + // + // Read Pci configuration space + // + PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + + if (PrivateData->HecBase == 0) { + return RootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer); + } + + if (!((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->ExtendedRegister) { + PciExtReg = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->Register; + } else { + PciExtReg = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->ExtendedRegister & 0x0FFF; + } + + PciBus = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->Bus; + PciDev = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->Device; + PciFn = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->Function; + + ExtConfigAdd = (UINT64) PrivateData->HecBase + PCIE_OFF (PciBus, PciDev, PciFn, PciExtReg); + + return mCpuIo->Mem.Read ( + mCpuIo, + (EFI_CPU_IO_PROTOCOL_WIDTH) Width, + ExtConfigAdd, + Count, + Buffer + ); +} + +EFI_STATUS +EFIAPI +RootBridgeIoPciWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +/*++ + +Routine Description: + + Allows write to PCI configuration space. + +Arguments: + + This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + Width - Signifies the width of the memory operation. + Address - The address within the PCI configuration space + for the PCI controller. + Count - The number of PCI configuration operations + to perform. + Buffer - The source buffer to get the results. + +Returns: + + EFI_SUCCESS - The data was written to the PCI root bridge. + EFI_INVALID_PARAMETER - Invalid parameters found. + EFI_OUT_OF_RESOURCES - The request could not be completed due to a lack of + resources. +--*/ +{ + PCI_ROOT_BRIDGE_INSTANCE *PrivateData; + UINT32 PciBus; + UINT32 PciDev; + UINT32 PciFn; + UINT32 PciExtReg; + UINT64 ExtConfigAdd; + + if (Buffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (Width < 0 || Width >= EfiPciWidthMaximum) { + return EFI_INVALID_PARAMETER; + } + + // + // Write Pci configuration space + // + PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + + if (PrivateData->HecBase == 0) { + return RootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer); + } + + if (!((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->ExtendedRegister) { + PciExtReg = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->Register; + } else { + PciExtReg = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->ExtendedRegister & 0x0FFF; + } + + PciBus = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->Bus; + PciDev = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->Device; + PciFn = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->Function; + + ExtConfigAdd = (UINT64) PrivateData->HecBase + PCIE_OFF (PciBus, PciDev, PciFn, PciExtReg); + + return mCpuIo->Mem.Write ( + mCpuIo, + (EFI_CPU_IO_PROTOCOL_WIDTH) Width, + ExtConfigAdd, + Count, + Buffer + ); +} + +EFI_STATUS +EFIAPI +RootBridgeIoMap ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ) +/*++ + +Routine Description: + + Provides the PCI controller-specific address needed to access + system memory for DMA. + +Arguments: + + This - A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + Operation - Indicate if the bus master is going to read or write + to system memory. + HostAddress - The system memory address to map on the PCI controller. + NumberOfBytes - On input the number of bytes to map. + On output the number of bytes that were mapped. + DeviceAddress - The resulting map address for the bus master PCI + controller to use to access the system memory's HostAddress. + Mapping - The value to pass to Unmap() when the bus master DMA + operation is complete. + +Returns: + + EFI_SUCCESS - Success. + EFI_INVALID_PARAMETER - Invalid parameters found. + EFI_UNSUPPORTED - The HostAddress cannot be mapped as a common + buffer. + EFI_DEVICE_ERROR - The System hardware could not map the requested + address. + EFI_OUT_OF_RESOURCES - The request could not be completed due to + lack of resources. + +--*/ +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS PhysicalAddress; + MAP_INFO *MapInfo; + + if (NumberOfBytes == NULL || Mapping == NULL || DeviceAddress == NULL || HostAddress == NULL) { + return EFI_INVALID_PARAMETER; + } + // + // Initialize the return values to their defaults + // + *Mapping = NULL; + + // + // Make sure that Operation is valid + // + if ((Operation < 0) || (Operation > EfiPciOperationBusMasterCommonBuffer64)) { + return EFI_INVALID_PARAMETER; + } + // + // Most PCAT like chipsets can not handle performing DMA above 4GB. + // If any part of the DMA transfer being mapped is above 4GB, then + // map the DMA transfer to a buffer below 4GB. + // + PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress; + if ((PhysicalAddress +*NumberOfBytes) > 0x100000000ULL) { + // + // Common Buffer operations can not be remapped. If the common buffer + // if above 4GB, then it is not possible to generate a mapping, so return + // an error. + // + if (Operation == EfiPciOperationBusMasterCommonBuffer || Operation == EfiPciOperationBusMasterCommonBuffer64) { + return EFI_INVALID_PARAMETER; + } + } + + if ((PhysicalAddress + *NumberOfBytes) > (DMA_MEMORY_TOP+1)) { + + // + // Common Buffer operations can not be remapped. + // + if (Operation == EfiPciOperationBusMasterCommonBuffer || Operation == EfiPciOperationBusMasterCommonBuffer64) { + *DeviceAddress = PhysicalAddress; + return EFI_SUCCESS; + } + // + // Allocate a MAP_INFO structure to remember the mapping when Unmap() is + // called later. + // + Status = gBS->AllocatePool ( + EfiBootServicesData, + sizeof (MAP_INFO), + (VOID **) &MapInfo + ); + if (EFI_ERROR (Status)) { + *NumberOfBytes = 0; + return Status; + } + // + // Return a pointer to the MAP_INFO structure in Mapping + // + *Mapping = MapInfo; + + // + // Initialize the MAP_INFO structure + // + MapInfo->Operation = Operation; + MapInfo->NumberOfBytes = *NumberOfBytes; + MapInfo->NumberOfPages = EFI_SIZE_TO_PAGES (*NumberOfBytes); + MapInfo->HostAddress = PhysicalAddress; + MapInfo->MappedHostAddress = DMA_MEMORY_TOP; + + // + // Allocate a buffer below DMA_MEMORY_TOP to map the transfer to. + // + Status = gBS->AllocatePages ( + AllocateMaxAddress, + EfiBootServicesData, + MapInfo->NumberOfPages, + &MapInfo->MappedHostAddress + ); + if (EFI_ERROR (Status)) { + gBS->FreePool (MapInfo); + *NumberOfBytes = 0; + return Status; + } + // + // If this is a read operation from the Bus Master's point of view, + // then copy the contents of the real buffer into the mapped buffer + // so the Bus Master can read the contents of the real buffer. + // + if (Operation == EfiPciOperationBusMasterRead || Operation == EfiPciOperationBusMasterRead64) { + CopyMem ( + (VOID *) (UINTN) MapInfo->MappedHostAddress, + (VOID *) (UINTN) MapInfo->HostAddress, + MapInfo->NumberOfBytes + ); + } + // + // The DeviceAddress is the address of the maped buffer below DMA_MEMORY_TOP + // + *DeviceAddress = MapInfo->MappedHostAddress; + } else { + // + // The transfer is below DMA_MEMORY_TOP, so the DeviceAddress is simply the HostAddress + // + *DeviceAddress = PhysicalAddress; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +RootBridgeIoUnmap ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN VOID *Mapping + ) +/*++ + +Routine Description: + + Completes the Map() operation and releases any corresponding resources. + +Arguments: + + This - Pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + Mapping - The value returned from Map() operation. + +Returns: + + EFI_SUCCESS - The range was unmapped successfully. + EFI_INVALID_PARAMETER - Mapping is not a value that was returned + by Map operation. + EFI_DEVICE_ERROR - The data was not committed to the target + system memory. + +--*/ +{ + MAP_INFO *MapInfo; + + // + // See if the Map() operation associated with this Unmap() required a mapping buffer. + // If a mapping buffer was not required, then this function simply returns EFI_SUCCESS. + // + if (Mapping != NULL) { + // + // Get the MAP_INFO structure from Mapping + // + MapInfo = (MAP_INFO *) Mapping; + + // + // If this is a write operation from the Bus Master's point of view, + // then copy the contents of the mapped buffer into the real buffer + // so the processor can read the contents of the real buffer. + // + if ((MapInfo->Operation == EfiPciOperationBusMasterWrite) || + (MapInfo->Operation == EfiPciOperationBusMasterWrite64) + ) { + CopyMem ( + (VOID *) (UINTN) MapInfo->HostAddress, + (VOID *) (UINTN) MapInfo->MappedHostAddress, + MapInfo->NumberOfBytes + ); + } + // + // Free the mapped buffer and the MAP_INFO structure. + // + gBS->FreePages (MapInfo->MappedHostAddress, MapInfo->NumberOfPages); + gBS->FreePool (Mapping); + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +RootBridgeIoAllocateBuffer ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_ALLOCATE_TYPE Type, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + OUT VOID **HostAddress, + IN UINT64 Attributes + ) +/*++ + +Routine Description: + + Allocates pages that are suitable for a common buffer mapping. + +Arguments: + + This - Pointer to EFI_ROOT_BRIDGE_IO_PROTOCOL instance. + Type - Not used and can be ignored. + MemoryType - Type of memory to allocate. + Pages - Number of pages to allocate. + HostAddress - Pointer to store the base system memory address + of the allocated range. + Attributes - Requested bit mask of attributes of the allocated + range. + +Returns: + + EFI_SUCCESS - The requested memory range were allocated. + EFI_INVALID_PARAMETER - Invalid parameter found. + EFI_UNSUPPORTED - Attributes is unsupported. + +--*/ +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS PhysicalAddress; + + // + // Validate Attributes + // + if ((Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) != 0) { + return EFI_UNSUPPORTED; + } + // + // Check for invalid inputs + // + if (HostAddress == NULL) { + return EFI_INVALID_PARAMETER; + } + // + // The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData + // + if ((MemoryType != EfiBootServicesData) && (MemoryType != EfiRuntimeServicesData)) { + return EFI_INVALID_PARAMETER; + } + // + // Limit allocations to memory below DMA_MEMORY_TOP + // + PhysicalAddress = DMA_MEMORY_TOP; + + Status = gBS->AllocatePages ( + AllocateMaxAddress, + MemoryType, + Pages, + &PhysicalAddress + ); + if (EFI_ERROR (Status)) { + return Status; + } + + *HostAddress = (VOID *) (UINTN) PhysicalAddress; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +RootBridgeIoFreeBuffer ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN UINTN Pages, + OUT VOID *HostAddress + ) +/*++ + +Routine Description: + + Free memory allocated in AllocateBuffer. + +Arguments: + + This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + instance. + Pages - Number of pages to free. + HostAddress - The base system memory address of the + allocated range. + +Returns: + + EFI_SUCCESS - Requested memory pages were freed. + EFI_INVALID_PARAMETER - Invalid parameter found. + +--*/ +{ + return gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress, Pages); +} + +EFI_STATUS +EFIAPI +RootBridgeIoFlush ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This + ) +/*++ + +Routine Description: + + Flushes all PCI posted write transactions from a PCI host + bridge to system memory. + +Arguments: + + This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + +Returns: + + EFI_SUCCESS - PCI posted write transactions were flushed + from PCI host bridge to system memory. + EFI_DEVICE_ERROR - Fail due to hardware error. + +--*/ +{ + // + // not supported yet + // + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +RootBridgeIoGetAttributes ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + OUT UINT64 *Supported, + OUT UINT64 *Attributes + ) +/*++ + +Routine Description: + + Get the attributes that a PCI root bridge supports and + the attributes the PCI root bridge is currently using. + +Arguments: + + This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + instance. + Supports - A pointer to the mask of attributes that + this PCI root bridge supports. + Attributes - A pointer to the mask of attributes that + this PCI root bridge is currently using. +Returns: + + EFI_SUCCESS - Success. + EFI_INVALID_PARAMETER - Invalid parameter found. + +--*/ + +// GC_TODO: Supported - add argument and description to function comment +// +// GC_TODO: Supported - add argument and description to function comment +// +// GC_TODO: Supported - add argument and description to function comment +// +{ + PCI_ROOT_BRIDGE_INSTANCE *PrivateData; + + PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + + if (Attributes == NULL && Supported == NULL) { + return EFI_INVALID_PARAMETER; + } + // + // Set the return value for Supported and Attributes + // + if (Supported) { + *Supported = PrivateData->Supports; + } + + if (Attributes) { + *Attributes = PrivateData->Attributes; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +RootBridgeIoSetAttributes ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN UINT64 Attributes, + IN OUT UINT64 *ResourceBase, + IN OUT UINT64 *ResourceLength + ) +/*++ + +Routine Description: + + Sets the attributes for a resource range on a PCI root bridge. + +Arguments: + + This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + Attributes - The mask of attributes to set. + ResourceBase - Pointer to the base address of the resource range + to be modified by the attributes specified by Attributes. + ResourceLength - Pointer to the length of the resource range to be modified. + +Returns: + EFI_SUCCESS - Success. + EFI_INVALID_PARAMETER - Invalid parameter found. + EFI_OUT_OF_RESOURCES - Not enough resources to set the attributes upon. + +--*/ + +// +// GC_TODO: EFI_UNSUPPORTED - add return value to function comment +// +{ + PCI_ROOT_BRIDGE_INSTANCE *PrivateData; + + PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + + if (Attributes != 0) { + Attributes &= (PrivateData->Supports); + if (Attributes == 0) { + return EFI_UNSUPPORTED; + } + } + + if (Attributes == PrivateData->Attributes) { + return EFI_SUCCESS; + } + // + // It is just a trick for some attribute can only be enabled or disabled + // otherwise it can impact on other devices + // + PrivateData->Attributes = Attributes; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +RootBridgeIoConfiguration ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + OUT VOID **Resources + ) +/*++ + +Routine Description: + + Retrieves the current resource settings of this PCI root bridge + in the form of a set of ACPI 2.0 resource descriptor. + +Arguments: + + This - Pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + Resources - Pointer to the ACPI 2.0 resource descriptor that + describe the current configuration of this PCI root + bridge. + +Returns: + + EFI_SUCCESS - Success. + EFI_UNSUPPORTED - Current configuration of the PCI root bridge + could not be retrieved. + +--*/ + +// +// GC_TODO: EFI_OUT_OF_RESOURCES - add return value to function comment +// +{ + EFI_STATUS Status; + UINTN Idx; + + PCI_ROOT_BRIDGE_INSTANCE *RbPrivateData; + PCI_RES_NODE *ResAllocNode; + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Config; + + // + // Get this instance of the Root Bridge. + // + RbPrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + + // + // If the pointer is not NULL, it points to a buffer already allocated. + // + if (RbPrivateData->ConfigBuffer == NULL) { + Status = gBS->AllocatePool ( + EfiBootServicesData, + TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR), + &RbPrivateData->ConfigBuffer + ); + if (EFI_ERROR (Status)) { + return EFI_OUT_OF_RESOURCES; + } + } + + Config = RbPrivateData->ConfigBuffer; + + ZeroMem (Config, TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); + + for (Idx = 0; Idx < TypeMax; Idx++) { + + ResAllocNode = &RbPrivateData->ResAllocNode[Idx]; + + if (ResAllocNode->Status != ResAllocated) { + continue; + } + + switch (ResAllocNode->Type) { + + case TypeIo: + Config->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; + Config->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3; + Config->ResType = ACPI_ADDRESS_SPACE_TYPE_IO; + Config->AddrRangeMin = ResAllocNode->Base; + Config->AddrRangeMax = ResAllocNode->Base + ResAllocNode->Length - 1; + Config->AddrLen = ResAllocNode->Length; + break; + + case TypeMem32: + Config->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; + Config->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3; + Config->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; + Config->AddrSpaceGranularity = 32; + Config->AddrRangeMin = ResAllocNode->Base; + Config->AddrRangeMax = ResAllocNode->Base + ResAllocNode->Length - 1; + Config->AddrLen = ResAllocNode->Length; + break; + + case TypePMem32: + Config->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; + Config->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3; + Config->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; + Config->SpecificFlag = 6; + Config->AddrSpaceGranularity = 32; + Config->AddrRangeMin = ResAllocNode->Base; + Config->AddrRangeMax = ResAllocNode->Base + ResAllocNode->Length - 1; + Config->AddrLen = ResAllocNode->Length; + break; + + case TypeMem64: + Config->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; + Config->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3; + Config->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; + Config->SpecificFlag = 6; + Config->AddrSpaceGranularity = 64; + Config->AddrRangeMin = ResAllocNode->Base; + Config->AddrRangeMax = ResAllocNode->Base + ResAllocNode->Length - 1; + Config->AddrLen = ResAllocNode->Length; + break; + + case TypePMem64: + Config->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; + Config->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3; + Config->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; + Config->SpecificFlag = 6; + Config->AddrSpaceGranularity = 64; + Config->AddrRangeMin = ResAllocNode->Base; + Config->AddrRangeMax = ResAllocNode->Base + ResAllocNode->Length - 1; + Config->AddrLen = ResAllocNode->Length; + break; + + case TypeBus: + Config->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; + Config->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3; + Config->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS; + Config->AddrRangeMin = ResAllocNode->Base; + Config->AddrRangeMax = ResAllocNode->Base + ResAllocNode->Length - 1; + Config->AddrLen = ResAllocNode->Length; + break; + + default: + break; + } + + Config++; + } + // + // Terminate the entries. + // + ((EFI_ACPI_END_TAG_DESCRIPTOR *) Config)->Desc = ACPI_END_TAG_DESCRIPTOR; + ((EFI_ACPI_END_TAG_DESCRIPTOR *) Config)->Checksum = 0x0; + + *Resources = RbPrivateData->ConfigBuffer; + return EFI_SUCCESS; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciPlatform/CommonHeader.h b/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciPlatform/CommonHeader.h new file mode 100644 index 0000000000..2ca6dc8eef --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciPlatform/CommonHeader.h @@ -0,0 +1,31 @@ +/** @file +Common header file shared by all source files. + +This file includes package header files, library classes and protocol, PPI & GUID definitions. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __COMMON_HEADER_H_ +#define __COMMON_HEADER_H_ + + + +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.c b/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.c new file mode 100644 index 0000000000..bb993fc9d3 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.c @@ -0,0 +1,194 @@ +/** @file +Registers onboard PCI ROMs with PCI.IO + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#include "CommonHeader.h" + +#include "PciPlatform.h" + + +PCI_OPTION_ROM_TABLE mPciOptionRomTable[] = { + { NULL_ROM_FILE_GUID, 0, 0, 0, 0, 0xffff, 0xffff } +}; +EFI_PCI_PLATFORM_PROTOCOL mPciPlatform = { + PhaseNotify, + PlatformPrepController, + GetPlatformPolicy, + GetPciRom +}; + +EFI_HANDLE mPciPlatformHandle = NULL; +EFI_HANDLE mImageHandle = NULL; + + +EFI_STATUS +PhaseNotify ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +{ + UINT8 UsbHostBusNumber = IOH_BUS; + if (Phase == EfiPciHostBridgeEndResourceAllocation) { + // Required for QuarkSouthCluster. + // Enable USB controller memory, io and bus master before Ehci driver. + EnableUsbMemIoBusMaster (UsbHostBusNumber); + return EFI_SUCCESS; + } + return EFI_UNSUPPORTED; +} + + +EFI_STATUS +PlatformPrepController ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_HANDLE RootBridge, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +{ + return EFI_UNSUPPORTED; +} + +EFI_STATUS +GetPlatformPolicy ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy + ) +{ + if (PciPolicy == NULL) { + return EFI_INVALID_PARAMETER; + } + + return EFI_UNSUPPORTED; +} + +EFI_STATUS +GetPciRom ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + OUT VOID **RomImage, + OUT UINTN *RomSize + ) +/*++ + + Routine Description: + Return a PCI ROM image for the onboard device represented by PciHandle + + Arguments: + This - Protocol instance pointer. + PciHandle - PCI device to return the ROM image for. + RomImage - PCI Rom Image for onboard device + RomSize - Size of RomImage in bytes + + Returns: + EFI_SUCCESS - RomImage is valid + EFI_NOT_FOUND - No RomImage + +--*/ +{ + EFI_STATUS Status; + EFI_PCI_IO_PROTOCOL *PciIo; + UINTN Segment; + UINTN Bus; + UINTN Device; + UINTN Function; + UINT16 VendorId; + UINT16 DeviceId; + UINT16 DeviceClass; + UINTN TableIndex; + + Status = gBS->HandleProtocol ( + PciHandle, + &gEfiPciIoProtocolGuid, + (VOID **) &PciIo + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + PciIo->GetLocation (PciIo, &Segment, &Bus, &Device, &Function); + + PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, 0x0A, 1, &DeviceClass); + + PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, 0, 1, &VendorId); + + PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, 2, 1, &DeviceId); + + // + // Loop through table of video option rom descriptions + // + for (TableIndex = 0; mPciOptionRomTable[TableIndex].VendorId != 0xffff; TableIndex++) { + + // + // See if the PCI device specified by PciHandle matches at device in mPciOptionRomTable + // + if (VendorId != mPciOptionRomTable[TableIndex].VendorId || + DeviceId != mPciOptionRomTable[TableIndex].DeviceId || + Segment != mPciOptionRomTable[TableIndex].Segment || + Bus != mPciOptionRomTable[TableIndex].Bus || + Device != mPciOptionRomTable[TableIndex].Device || + Function != mPciOptionRomTable[TableIndex].Function) { + continue; + } + + Status = GetSectionFromFv ( + &mPciOptionRomTable[TableIndex].FileName, + EFI_SECTION_RAW, + 0, + RomImage, + RomSize + ); + + if (EFI_ERROR (Status)) { + continue; + } + + return EFI_SUCCESS; + } + + return EFI_NOT_FOUND; +} + +EFI_STATUS +PciPlatformDriverEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +/*++ + +Routine Description: + +Arguments: + (Standard EFI Image entry - EFI_IMAGE_ENTRY_POINT) + +Returns: + EFI_STATUS + +--*/ +{ + EFI_STATUS Status; + + mImageHandle = ImageHandle; + + // + // Install on a new handle + // + Status = gBS->InstallProtocolInterface ( + &mPciPlatformHandle, + &gEfiPciPlatformProtocolGuid, + EFI_NATIVE_INTERFACE, + &mPciPlatform + ); + + return Status; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.h b/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.h new file mode 100644 index 0000000000..baa5d48d22 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.h @@ -0,0 +1,82 @@ +/** @file +This code supports a the private implementation +of the Legacy BIOS Platform protocol + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#ifndef PCI_PLATFORM_H_ +#define PCI_PLATFORM_H_ + +#include +#include +// +// Global variables for Option ROMs +// +#define NULL_ROM_FILE_GUID \ +{ 0x00000000, 0x0000, 0x0000, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }} + +#define ONBOARD_VIDEO_OPTION_ROM_FILE_GUID \ +{ 0x8dfae5d4, 0xb50e, 0x4c10, {0x96, 0xe6, 0xf2, 0xc2, 0x66, 0xca, 0xcb, 0xb6 }} + +#define IDE_RAID_OPTION_ROM_FILE_GUID \ +{ 0x3392A8E1, 0x1881, 0x4398, {0x83, 0xa6, 0x53, 0xd3, 0x87, 0xdb, 0x20, 0x20 }} + +#define TANX_UNDI_OPTION_ROM_FILE_GUID \ +{ 0x84c24ab0, 0x124e, 0x4aed, {0x8e, 0xfe, 0xf9, 0x1b, 0xb9, 0x73, 0x69, 0xf4 }} + +#define PXE_UNDI_OPTION_ROM_FILE_GUID \ +{ 0xea34cd48, 0x5fdf, 0x46f0, {0xb5, 0xfa, 0xeb, 0xe0, 0x76, 0xa4, 0xf1, 0x2c }} + + +typedef struct { + EFI_GUID FileName; + UINTN Segment; + UINTN Bus; + UINTN Device; + UINTN Function; + UINT16 VendorId; + UINT16 DeviceId; +} PCI_OPTION_ROM_TABLE; + + +EFI_STATUS +PhaseNotify ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ); + + +EFI_STATUS +PlatformPrepController ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_HANDLE RootBridge, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ); + +EFI_STATUS +GetPlatformPolicy ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy + ); + +EFI_STATUS +GetPciRom ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + OUT VOID **RomImage, + OUT UINTN *RomSize + ); + +#endif + + diff --git a/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.inf b/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.inf new file mode 100644 index 0000000000..02cde7d431 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.inf @@ -0,0 +1,54 @@ +## @file +# Component description file for PciPlatform module. +# +# This driver installs pciplatform protocol to provide access interfaces to the onboard pci roms. +# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PciPlatform + FILE_GUID = 2E8CD01A-BDB7-40b4-8376-E7C26EAC21FF + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PciPlatformDriverEntry + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 EBC +# + +[Sources] + PciPlatform.c + PciPlatform.h + CommonHeader.h + +[Packages] + MdePkg/MdePkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + QuarkSocPkg/QuarkSocPkg.dec + +[LibraryClasses] + PciLib + PcdLib + IohLib + DebugLib + UefiRuntimeServicesTableLib + UefiBootServicesTableLib + UefiDriverEntryPoint + DxeServicesLib + +[Guids] + +[Protocols] + gEfiPciIoProtocolGuid # PROTOCOL ALWAYS_CONSUMED + gEfiPciPlatformProtocolGuid # PROTOCOL ALWAYS_PRODUCED + +[Pcd] + +[Depex] + TRUE diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClass.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClass.c new file mode 100644 index 0000000000..fb11f5f8c4 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClass.c @@ -0,0 +1,435 @@ +/** @file +This is the driver that locates the MemoryConfigurationData Variable, if it +exists, and reports the data to the DataHub. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MemorySubClass.h" + +extern UINT8 MemorySubClassStrings[]; + +EFI_GUID gEfiMemorySubClassDriverGuid = EFI_MEMORY_SUBCLASS_DRIVER_GUID; + +EFI_STATUS +MemorySubClassEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +/*++ + + Routine Description: + This is the standard EFI driver point that detects whether there is a + MemoryConfigurationData Variable and, if so, reports memory configuration info + to the DataHub. + + Arguments: + ImageHandle - Handle for the image of this driver + SystemTable - Pointer to the EFI System Table + + Returns: + EFI_SUCCESS if the data is successfully reported + EFI_NOT_FOUND if the HOB list could not be located. + +--*/ +{ +// UINT8 Index; + UINTN DataSize; + UINT8 Dimm; + UINTN StringBufferSize; + UINT8 NumSlots; + UINTN DevLocStrLen; + UINTN BankLocStrLen; + UINTN ManuStrLen; + UINTN SerialNumStrLen; + UINTN AssertTagStrLen; + UINTN PartNumStrLen; + UINTN MemoryDeviceSize; + CHAR8* OptionalStrStart; + UINT16 ArrayInstance; + UINT64 DimmMemorySize; + UINT64 TotalMemorySize; + UINT32 Data; + UINT32 MemoryCapacity; + BOOLEAN MemoryDeviceSizeUnitMega; + EFI_STATUS Status; + EFI_STRING StringBuffer; + EFI_STRING DevLocStr; + EFI_STRING BankLocStr; + EFI_STRING ManuStr; + EFI_STRING SerialNumStr; + EFI_STRING AssertTagStr; + EFI_STRING PartNumStr; + EFI_HII_HANDLE HiiHandle; + EFI_SMBIOS_HANDLE MemArraySmbiosHandle; + EFI_SMBIOS_HANDLE MemArrayMappedAddrSmbiosHandle; + EFI_SMBIOS_HANDLE MemDevSmbiosHandle; + EFI_SMBIOS_HANDLE MemDevMappedAddrSmbiosHandle; + EFI_SMBIOS_HANDLE MemModuleInfoSmbiosHandle; + SMBIOS_TABLE_TYPE6 *Type6Record; + SMBIOS_TABLE_TYPE16 *Type16Record; + SMBIOS_TABLE_TYPE17 *Type17Record; + SMBIOS_TABLE_TYPE19 *Type19Record; + SMBIOS_TABLE_TYPE20 *Type20Record; + EFI_SMBIOS_PROTOCOL *Smbios; + EFI_MEMORY_ARRAY_LINK_DATA ArrayLink; + EFI_MEMORY_ARRAY_LOCATION_DATA ArrayLocationData; + EFI_MEMORY_DEVICE_START_ADDRESS_DATA DeviceStartAddress; + + + DataSize = 0; + Dimm = 0; + + + // + // Allocate Buffers + // + StringBufferSize = (sizeof (CHAR16)) * 100; + StringBuffer = AllocateZeroPool (StringBufferSize); + ASSERT (StringBuffer != NULL); + + // + // Locate dependent protocols + // + Status = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID**)&Smbios); + ASSERT_EFI_ERROR (Status); + + + // + // Add our default strings to the HII database. They will be modified later. + // + HiiHandle = HiiAddPackages ( + &gEfiMemorySubClassDriverGuid, + NULL, + MemorySubClassStrings, + NULL + ); + ASSERT (HiiHandle != NULL); + + // + // Create physical array and associated data for all mainboard memory + // This will translate into a Type 16 SMBIOS Record + // + ArrayInstance = 1; + + McD0PciCfg32 (QNC_ACCESS_PORT_MCR) = MESSAGE_READ_DW (0x3, 0x8); + TotalMemorySize = McD0PciCfg32 (QNC_ACCESS_PORT_MDR); + + ArrayLocationData.MemoryArrayLocation = EfiMemoryArrayLocationSystemBoard; + ArrayLocationData.MemoryArrayUse = EfiMemoryArrayUseSystemMemory; + + ArrayLocationData.MemoryErrorCorrection = EfiMemoryErrorCorrectionNone; + + Data = 0x40000000;//(UINT32) RShiftU64(MemConfigData->RowInfo.MaxMemory, 10); + + ArrayLocationData.MaximumMemoryCapacity.Exponent = (UINT16) LowBitSet32 (Data); + ArrayLocationData.MaximumMemoryCapacity.Value = (UINT16) (Data >> ArrayLocationData.MaximumMemoryCapacity.Exponent); + + NumSlots = 2;// (UINT8)(MemConfigData->RowInfo.MaxRows >> 1); + ArrayLocationData.NumberMemoryDevices = (UINT16)(NumSlots); + + // + // Report top level physical array to Type 16 SMBIOS Record + // + Type16Record = AllocatePool(sizeof(SMBIOS_TABLE_TYPE16) + 1 + 1); + ZeroMem(Type16Record, sizeof(SMBIOS_TABLE_TYPE16) + 1 + 1); + + Type16Record->Hdr.Type = EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY; + Type16Record->Hdr.Length = sizeof(SMBIOS_TABLE_TYPE16); + Type16Record->Hdr.Handle = 0; + + Type16Record->Location = (UINT8)ArrayLocationData.MemoryArrayLocation; + + Type16Record->Use = (UINT8)ArrayLocationData.MemoryArrayUse; + + Type16Record->MemoryErrorCorrection = (UINT8)ArrayLocationData.MemoryErrorCorrection; + + MemoryCapacity = (UINT32) ArrayLocationData.MaximumMemoryCapacity.Value * (1 << ((UINT32) ArrayLocationData.MaximumMemoryCapacity.Exponent - 10)); + Type16Record->MaximumCapacity = MemoryCapacity; + + Type16Record->MemoryErrorInformationHandle = 0xfffe; + + Type16Record->NumberOfMemoryDevices = ArrayLocationData.NumberMemoryDevices; + // + // Don't change it. This handle will be referenced by type 17 records + // + MemArraySmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios->Add (Smbios, NULL, &MemArraySmbiosHandle, (EFI_SMBIOS_TABLE_HEADER*) Type16Record); + FreePool(Type16Record); + ASSERT_EFI_ERROR (Status); + + // Do associated data for each DIMM + //RowConfArray = &MemConfigData->RowConfArray; + + // + // Get total memory size for the construction of smbios record type 19 + // + //TotalMemorySize = 0;// MSG_BUS_READ(0x0208); + + // + // Generate Memory Array Mapped Address info + // + Type19Record = AllocatePool(sizeof (SMBIOS_TABLE_TYPE19)); + ZeroMem(Type19Record, sizeof(SMBIOS_TABLE_TYPE19)); + Type19Record->Hdr.Type = EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS; + Type19Record->Hdr.Length = sizeof(SMBIOS_TABLE_TYPE19); + Type19Record->Hdr.Handle = 0; + Type19Record->StartingAddress = 0; + Type19Record->EndingAddress = (UINT32)RShiftU64(TotalMemorySize, 10) - 1; + Type19Record->MemoryArrayHandle = MemArraySmbiosHandle; + Type19Record->PartitionWidth = (UINT8)(NumSlots); + + // + // Generate Memory Array Mapped Address info (TYPE 19) + // + MemArrayMappedAddrSmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios->Add (Smbios, NULL, &MemArrayMappedAddrSmbiosHandle, (EFI_SMBIOS_TABLE_HEADER*) Type19Record); + FreePool(Type19Record); + ASSERT_EFI_ERROR (Status); + + + // Use SPD data to generate Device Type info + ZeroMem (&ArrayLink, sizeof (EFI_MEMORY_ARRAY_LINK_DATA)); + ArrayLink.MemoryDeviceLocator = STRING_TOKEN(STR_MEMORY_SUBCLASS_DEVICE_LOCATOR_0); + ArrayLink.MemoryBankLocator = STRING_TOKEN(STR_MEMORY_SUBCLASS_DEVICE_LOCATOR_0); + ArrayLink.MemoryAssetTag = STRING_TOKEN(STR_MEMORY_SUBCLASS_UNKNOWN); + ArrayLink.MemoryArrayLink.ProducerName = gEfiMemorySubClassDriverGuid; + ArrayLink.MemoryArrayLink.Instance = ArrayInstance; + ArrayLink.MemoryArrayLink.SubInstance = EFI_SUBCLASS_INSTANCE_NON_APPLICABLE; + ArrayLink.MemorySubArrayLink.ProducerName = gEfiMemorySubClassDriverGuid; + ArrayLink.MemorySubArrayLink.SubInstance = EFI_SUBCLASS_INSTANCE_NON_APPLICABLE; + ArrayLink.MemoryFormFactor = EfiMemoryFormFactorChip; + ArrayLink.MemoryType = EfiMemoryTypeDdr2; + + + StrCpy (StringBuffer, L"NO DIMM,MEMROY DOWN"); + ArrayLink.MemoryManufacturer = HiiSetString ( + HiiHandle, + 0, + StringBuffer, + NULL + ); + ArrayLink.MemorySerialNumber = HiiSetString ( + HiiHandle, + 0, + StringBuffer, + NULL + ); + + ArrayLink.MemoryPartNumber = HiiSetString ( + HiiHandle, + 0, + StringBuffer, + NULL + ); + + // + // Hardcode value. Need to revise for different configuration. + // + ArrayLink.MemoryTotalWidth = 64; + ArrayLink.MemoryDataWidth = 64; + + DimmMemorySize = TotalMemorySize;// MSG_BUS_READ(0x0208); + + ArrayLink.MemoryDeviceSize.Exponent = (UINT16) LowBitSet64 (DimmMemorySize); + ArrayLink.MemoryDeviceSize.Value = (UINT16) RShiftU64(DimmMemorySize, ArrayLink.MemoryDeviceSize.Exponent); + ArrayLink.MemoryTypeDetail.Synchronous = 1; + Data = 800; + ArrayLink.MemorySpeed = *((EFI_EXP_BASE10_DATA *) &Data); + + + + DevLocStr = HiiGetPackageString(&gEfiMemorySubClassDriverGuid, ArrayLink.MemoryDeviceLocator, NULL); + DevLocStrLen = StrLen(DevLocStr); + ASSERT(DevLocStrLen <= SMBIOS_STRING_MAX_LENGTH); + + BankLocStr = HiiGetPackageString(&gEfiMemorySubClassDriverGuid, ArrayLink.MemoryBankLocator, NULL); + BankLocStrLen = StrLen(BankLocStr); + ASSERT(BankLocStrLen <= SMBIOS_STRING_MAX_LENGTH); + + ManuStr = HiiGetPackageString(&gEfiMemorySubClassDriverGuid, ArrayLink.MemoryManufacturer, NULL); + ManuStrLen = StrLen(ManuStr); + ASSERT(ManuStrLen <= SMBIOS_STRING_MAX_LENGTH); + + SerialNumStr = HiiGetPackageString(&gEfiMemorySubClassDriverGuid, ArrayLink.MemorySerialNumber, NULL); + SerialNumStrLen = StrLen(SerialNumStr); + ASSERT(SerialNumStrLen <= SMBIOS_STRING_MAX_LENGTH); + + AssertTagStr = HiiGetPackageString(&gEfiMemorySubClassDriverGuid, ArrayLink.MemoryAssetTag, NULL); + AssertTagStrLen = StrLen(AssertTagStr); + ASSERT(AssertTagStrLen <= SMBIOS_STRING_MAX_LENGTH); + + PartNumStr = HiiGetPackageString(&gEfiMemorySubClassDriverGuid, ArrayLink.MemoryPartNumber, NULL); + PartNumStrLen = StrLen(PartNumStr); + ASSERT(PartNumStrLen <= SMBIOS_STRING_MAX_LENGTH); + + // + // Report DIMM level memory module information to smbios (Type 6) + // + DataSize = sizeof(SMBIOS_TABLE_TYPE6) + DevLocStrLen + 1 + 1; + Type6Record = AllocatePool(DataSize); + ZeroMem(Type6Record, DataSize); + Type6Record->Hdr.Type = EFI_SMBIOS_TYPE_MEMORY_MODULE_INFORMATON; + Type6Record->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE6); + Type6Record->Hdr.Handle = 0; + Type6Record->SocketDesignation = 1; + if (ArrayLink.MemorySpeed.Value == 0) { + Type6Record->CurrentSpeed = 0; + } else { + // + // Memory speed is in ns unit + // + Type6Record->CurrentSpeed = (UINT8)(1000 / (ArrayLink.MemorySpeed.Value)); + } + // + // Device Size + // + MemoryDeviceSize = (UINTN)(ArrayLink.MemoryDeviceSize.Value) * (UINTN)(1 << ArrayLink.MemoryDeviceSize.Exponent); + if (MemoryDeviceSize == 0) { + *(UINT8*)&(Type6Record->InstalledSize) = 0x7F; + *(UINT8*)&(Type6Record->EnabledSize) = 0x7F; + } else { + MemoryDeviceSize = (UINTN) RShiftU64 ((UINT64) MemoryDeviceSize, 21); + while (MemoryDeviceSize != 0) { + (*(UINT8*)&(Type6Record->InstalledSize))++; + (*(UINT8*)&(Type6Record->EnabledSize))++; + MemoryDeviceSize = (UINTN) RShiftU64 ((UINT64) MemoryDeviceSize,1); + } + } + + if (ArrayLink.MemoryFormFactor == EfiMemoryFormFactorDimm || + ArrayLink.MemoryFormFactor == EfiMemoryFormFactorFbDimm) { + *(UINT16*)&Type6Record->CurrentMemoryType |= 1<<8; + } + if (ArrayLink.MemoryFormFactor == EfiMemoryFormFactorSimm) { + *(UINT16*)&Type6Record->CurrentMemoryType |= 1<<7; + } + if (ArrayLink.MemoryType == EfiMemoryTypeSdram) { + *(UINT16*)&Type6Record->CurrentMemoryType |= 1<<10; + } + if (ArrayLink.MemoryTypeDetail.Edo == 1) { + *(UINT16*)&Type6Record->CurrentMemoryType |= 1<<4; + } + if (ArrayLink.MemoryTypeDetail.FastPaged == 1) { + *(UINT16*)&Type6Record->CurrentMemoryType |= 1<<3; + } + OptionalStrStart = (CHAR8 *)(Type6Record + 1); + UnicodeStrToAsciiStr(DevLocStr, OptionalStrStart); + MemModuleInfoSmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios->Add (Smbios, NULL, &MemModuleInfoSmbiosHandle, (EFI_SMBIOS_TABLE_HEADER*) Type6Record); + FreePool(Type6Record); + ASSERT_EFI_ERROR (Status); + // + // Report DIMM level Device Type to smbios (Type 17) + // + DataSize = sizeof (SMBIOS_TABLE_TYPE17) + DevLocStrLen + 1 + BankLocStrLen + 1 + ManuStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen + 1 + PartNumStrLen + 1 + 1; + Type17Record = AllocatePool(DataSize); + ZeroMem(Type17Record, DataSize); + Type17Record->Hdr.Type = EFI_SMBIOS_TYPE_MEMORY_DEVICE; + Type17Record->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE17); + Type17Record->Hdr.Handle = 0; + + Type17Record->MemoryArrayHandle = MemArraySmbiosHandle; + Type17Record->MemoryErrorInformationHandle = 0xfffe; + Type17Record->TotalWidth = ArrayLink.MemoryTotalWidth; + Type17Record->DataWidth = ArrayLink.MemoryDataWidth; + // + // Device Size + // + MemoryDeviceSize = ((UINTN) ArrayLink.MemoryDeviceSize.Value) << (ArrayLink.MemoryDeviceSize.Exponent - 10); + MemoryDeviceSizeUnitMega = FALSE; + // + // kilo as unit + // + if (MemoryDeviceSize > 0xffff) { + MemoryDeviceSize = MemoryDeviceSize >> 10; + // + // Mega as unit + // + MemoryDeviceSizeUnitMega = TRUE; + } + + MemoryDeviceSize = MemoryDeviceSize & 0x7fff; + if (MemoryDeviceSize != 0 && MemoryDeviceSizeUnitMega == FALSE) { + MemoryDeviceSize |= 0x8000; + } + Type17Record->Size = (UINT16)MemoryDeviceSize; + + Type17Record->FormFactor = (UINT8)ArrayLink.MemoryFormFactor; + Type17Record->DeviceLocator = 1; + Type17Record->BankLocator = 2; + Type17Record->MemoryType = (UINT8)ArrayLink.MemoryType; + CopyMem ( + (UINT8 *) &Type17Record->TypeDetail, + &ArrayLink.MemoryTypeDetail, + 2 + ); + + Type17Record->Speed = ArrayLink.MemorySpeed.Value; + Type17Record->Manufacturer = 3; + Type17Record->SerialNumber = 4; + Type17Record->AssetTag = 5; + Type17Record->PartNumber = 6; + // + // temporary solution for save device label information. + // + Type17Record->Attributes = (UINT8)(Dimm + 1); + + OptionalStrStart = (CHAR8 *)(Type17Record + 1); + UnicodeStrToAsciiStr(DevLocStr, OptionalStrStart); + UnicodeStrToAsciiStr(BankLocStr, OptionalStrStart + DevLocStrLen + 1); + UnicodeStrToAsciiStr(ManuStr, OptionalStrStart + DevLocStrLen + 1 + BankLocStrLen + 1); + UnicodeStrToAsciiStr(SerialNumStr, OptionalStrStart + DevLocStrLen + 1 + BankLocStrLen + 1 + ManuStrLen + 1); + UnicodeStrToAsciiStr(AssertTagStr, OptionalStrStart + DevLocStrLen + 1 + BankLocStrLen + 1 + ManuStrLen + 1 + SerialNumStrLen + 1); + UnicodeStrToAsciiStr(PartNumStr, OptionalStrStart + DevLocStrLen + 1 + BankLocStrLen + 1 + ManuStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen + 1); + MemDevSmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios->Add (Smbios, NULL, &MemDevSmbiosHandle, (EFI_SMBIOS_TABLE_HEADER*) Type17Record); + FreePool(Type17Record); + ASSERT_EFI_ERROR (Status); + + // + // Generate Memory Device Mapped Address info + // + ZeroMem(&DeviceStartAddress, sizeof(EFI_MEMORY_DEVICE_START_ADDRESS_DATA)); + DeviceStartAddress.MemoryDeviceStartAddress = 0; + DeviceStartAddress.MemoryDeviceEndAddress = DeviceStartAddress.MemoryDeviceStartAddress + DimmMemorySize-1; + DeviceStartAddress.PhysicalMemoryDeviceLink.ProducerName = gEfiMemorySubClassDriverGuid; + DeviceStartAddress.PhysicalMemoryDeviceLink.Instance = ArrayInstance; + DeviceStartAddress.PhysicalMemoryDeviceLink.SubInstance = (UINT16)(Dimm + 1); + DeviceStartAddress.PhysicalMemoryArrayLink.ProducerName = gEfiMemorySubClassDriverGuid; + DeviceStartAddress.PhysicalMemoryArrayLink.Instance = ArrayInstance; + DeviceStartAddress.PhysicalMemoryArrayLink.SubInstance = EFI_SUBCLASS_INSTANCE_NON_APPLICABLE; + + // + // Single channel mode + // + DeviceStartAddress.MemoryDevicePartitionRowPosition = 0x01; + DeviceStartAddress.MemoryDeviceInterleavePosition = 0x00; + DeviceStartAddress.MemoryDeviceInterleaveDataDepth = 0x00; + + // + // Generate Memory Device Mapped Address info (TYPE 20) + // + Type20Record = AllocatePool(sizeof (SMBIOS_TABLE_TYPE20)); + ZeroMem(Type20Record, sizeof (SMBIOS_TABLE_TYPE20)); + Type20Record->Hdr.Type = EFI_SMBIOS_TYPE_MEMORY_DEVICE_MAPPED_ADDRESS; + Type20Record->Hdr.Length = sizeof(SMBIOS_TABLE_TYPE20); + Type20Record->Hdr.Handle = 0; + + Type20Record->StartingAddress = (UINT32)RShiftU64 (DeviceStartAddress.MemoryDeviceStartAddress, 10); + Type20Record->EndingAddress = (UINT32)RShiftU64 (DeviceStartAddress.MemoryDeviceEndAddress, 10); + Type20Record->MemoryDeviceHandle = MemDevSmbiosHandle; + Type20Record->MemoryArrayMappedAddressHandle = MemArrayMappedAddrSmbiosHandle; + Type20Record->PartitionRowPosition = DeviceStartAddress.MemoryDevicePartitionRowPosition; + Type20Record->InterleavePosition = DeviceStartAddress.MemoryDeviceInterleavePosition; + Type20Record->InterleavedDataDepth = DeviceStartAddress.MemoryDeviceInterleaveDataDepth; + MemDevMappedAddrSmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios->Add (Smbios, NULL, &MemDevMappedAddrSmbiosHandle, (EFI_SMBIOS_TABLE_HEADER*) Type20Record); + FreePool(Type20Record); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClass.h b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClass.h new file mode 100644 index 0000000000..2343070707 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClass.h @@ -0,0 +1,65 @@ +/** @file +Header file for MemorySubClass Driver. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MEMORY_SUB_CLASS_H +#define _MEMORY_SUB_CLASS_H + +// +// The package level header files this module uses +// +#include +// +// The protocols, PPI and GUID definitions for this module +// +#include +#include +#include +#include +#include +#include +#include +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "QNCAccess.h" + + + +// +// This is the generated header file which includes whatever needs to be exported (strings + IFR) +// + +#define EFI_MEMORY_SUBCLASS_DRIVER_GUID \ + { 0xef17cee7, 0x267d, 0x4bfd, { 0xa2, 0x57, 0x4a, 0x6a, 0xb3, 0xee, 0x85, 0x91 }} + +// +// Prototypes +// +EFI_STATUS +MemorySubClassEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClass.inf b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClass.inf new file mode 100644 index 0000000000..720dfc15f9 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClass.inf @@ -0,0 +1,60 @@ +## @file +# Component description file for MemorySubClass module. +# +# This is the driver that locates the MemoryConfigurationData Variable, if it +# exists, and reports the data to the DataHub. +# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = MemorySubClass + FILE_GUID = EF17CEE7-267D-4BFD-A257-4A6AB3EE8591 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = MemorySubClassEntryPoint + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 EBC +# + +[Sources] + MemorySubClass.c + MemorySubClass.h + MemorySubClassStrings.uni + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFrameworkPkg/IntelFrameworkPkg.dec + QuarkSocPkg/QuarkSocPkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + +[LibraryClasses] + MemoryAllocationLib + HiiLib + PrintLib + BaseMemoryLib + DebugLib + UefiRuntimeServicesTableLib + UefiBootServicesTableLib + UefiDriverEntryPoint + BaseLib + HobLib + PciLib + QNCAccessLib + +[Guids] + gEfiMemoryConfigDataGuid # ALWAYS_CONSUMED + +[Protocols] + gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED + gEfiSmbusHcProtocolGuid # PROTOCOL ALWAYS_CONSUMED + +[Depex] + gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiSmbiosProtocolGuid AND gEfiSmbusHcProtocolGuid diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClassStrings.uni b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClassStrings.uni new file mode 100644 index 0000000000..29ba9df8d8 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClassStrings.uni @@ -0,0 +1,29 @@ +// /** @file +// String definitions for Smbios Memory SubClass data. +// +// Copyright (c) 2013-2015 Intel Corporation. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// +// **/ + + +/=# + +#langdef en-US "English" + +// +// Begin English Language Strings +// +#string STR_MEMORY_SUBCLASS_UNKNOWN #language en-US "Unknown" +#string STR_MEMORY_SUBCLASS_DEVICE_LOCATOR_0 #language en-US "SOLDER DOWN" +#string STR_MEMORY_SUBCLASS_MANUFACTURER #language en-US "Manufacturer: " +#string STR_MEMORY_SUBCLASS_SERIAL_NUMBER #language en-US "Serial Number: " +#string STR_MEMORY_SUBCLASS_ASSET_TAG #language en-US "Asset Tag: " +#string STR_MEMORY_SUBCLASS_PART_NUMBER #language en-US "PartNumber: " +// +// End English Language Strings +// + + diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformConfig.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformConfig.c new file mode 100644 index 0000000000..a0642fe31a --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformConfig.c @@ -0,0 +1,443 @@ +/** @file +Essential platform configuration. + +Copyright (c) 2013 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#include "PlatformInitDxe.h" + +// +// The protocols, PPI and GUID defintions for this module +// + +// +// The Library classes this module consumes +// + +// +// RTC:28208 - System hang/crash when entering probe mode(ITP) when relocating SMBASE +// Workaround to make default SMRAM UnCachable +// +#define SMM_DEFAULT_SMBASE 0x30000 // Default SMBASE address +#define SMM_DEFAULT_SMBASE_SIZE_BYTES 0x10000 // Size in bytes of default SMRAM + +BOOLEAN mMemCfgDone = FALSE; +UINT8 ChipsetDefaultMac [6] = {0xff,0xff,0xff,0xff,0xff,0xff}; + +VOID +EFIAPI +PlatformInitializeUart0MuxGalileo ( + VOID + ) +/*++ + + +Routine Description: + + This is the routine to initialize UART0 for DBG2 support. The hardware used in this process is a + Legacy Bridge (Legacy GPIO), I2C controller, a bi-directional MUX and a Cypress CY8C9540A chip. + +Arguments: + + None. + +Returns: + + None. + +--*/ +{ + EFI_STATUS Status; + EFI_I2C_DEVICE_ADDRESS I2CSlaveAddress; + UINTN Length; + UINT8 Buffer[2]; + + if (PlatformLegacyGpioGetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)) { + I2CSlaveAddress.I2CDeviceAddress = GALILEO_IOEXP_J2HI_7BIT_SLAVE_ADDR; + } else { + I2CSlaveAddress.I2CDeviceAddress = GALILEO_IOEXP_J2LO_7BIT_SLAVE_ADDR; + } + + // + // Set GPIO_SUS<2> as an output, raise voltage to Vdd. + // + PlatformLegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, 2, TRUE); + + // + // Select Port 3 + // + Length = 2; + Buffer[0] = 0x18; //sub-address + Buffer[1] = 0x03; //data + + Status = I2cWriteMultipleByte ( + I2CSlaveAddress, + EfiI2CSevenBitAddrMode, + &Length, + &Buffer + ); + ASSERT_EFI_ERROR (Status); + + // + // Set "Pin Direction" bit4 and bit5 as outputs + // + Length = 2; + Buffer[0] = 0x1C; //sub-address + Buffer[1] = 0xCF; //data + + Status = I2cWriteMultipleByte ( + I2CSlaveAddress, + EfiI2CSevenBitAddrMode, + &Length, + &Buffer + ); + ASSERT_EFI_ERROR (Status); + + // + // Lower GPORT3 bit4 and bit5 to Vss + // + Length = 2; + Buffer[0] = 0x0B; //sub-address + Buffer[1] = 0xCF; //data + + Status = I2cWriteMultipleByte ( + I2CSlaveAddress, + EfiI2CSevenBitAddrMode, + &Length, + &Buffer + ); + ASSERT_EFI_ERROR (Status); +} + +VOID +EFIAPI +PlatformInitializeUart0MuxGalileoGen2 ( + VOID + ) +/*++ + + +Routine Description: + + This is the routine to initialize UART0 on GalileoGen2. The hardware used in this process is + I2C controller and the configuring the following IO Expander signal. + + EXP1.P1_5 should be configured as an output & driven high. + EXP1.P0_0 should be configured as an output & driven high. + EXP0.P1_4 should be configured as an output, driven low. + EXP1.P0_1 pullup should be disabled. + EXP0.P1_5 Pullup should be disabled. + +Arguments: + + None. + +Returns: + + None. + +--*/ + +{ + // + // EXP1.P1_5 should be configured as an output & driven high. + // + PlatformPcal9555GpioSetDir ( + GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1. + 13, // P1-5. + TRUE + ); + PlatformPcal9555GpioSetLevel ( + GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1. + 13, // P1-5. + TRUE + ); + + // + // EXP1.P0_0 should be configured as an output & driven high. + // + PlatformPcal9555GpioSetDir ( + GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0. + 0, // P0_0. + TRUE + ); + PlatformPcal9555GpioSetLevel ( + GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0. + 0, // P0_0. + TRUE + ); + + // + // EXP0.P1_4 should be configured as an output, driven low. + // + PlatformPcal9555GpioSetDir ( + GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0. + 12, // P1-4. + FALSE + ); + PlatformPcal9555GpioSetLevel ( // IO Expander 0. + GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // P1-4 + 12, + FALSE + ); + + // + // EXP1.P0_1 pullup should be disabled. + // + PlatformPcal9555GpioDisablePull ( + GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1. + 1 // P0-1. + ); + + // + // EXP0.P1_5 Pullup should be disabled. + // + PlatformPcal9555GpioDisablePull ( + GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0. + 13 // P1-5. + ); +} + +VOID +EFIAPI +PlatformConfigOnSmmConfigurationProtocol ( + IN EFI_EVENT Event, + IN VOID *Context + ) +/*++ + +Routine Description: + + Function runs in PI-DXE to perform platform specific config when + SmmConfigurationProtocol is installed. + +Arguments: + Event - The event that occured. + Context - For EFI compatiblity. Not used. + +Returns: + None. +--*/ + +{ + EFI_STATUS Status; + UINT32 NewValue; + UINT64 BaseAddress; + UINT64 SmramLength; + VOID *SmmCfgProt; + + Status = gBS->LocateProtocol (&gEfiSmmConfigurationProtocolGuid, NULL, &SmmCfgProt); + if (Status != EFI_SUCCESS){ + DEBUG ((DEBUG_INFO, "gEfiSmmConfigurationProtocolGuid triggered but not valid.\n")); + return; + } + if (mMemCfgDone) { + DEBUG ((DEBUG_INFO, "Platform DXE Mem config already done.\n")); + return; + } + + // + // Disable eSram block (this will also clear/zero eSRAM) + // We only use eSRAM in the PEI phase. Disable now that we are in the DXE phase + // + NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK); + NewValue |= BLOCK_DISABLE_PG; + QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK, NewValue); + + // + // Update HMBOUND to top of DDR3 memory and LOCK + // We disabled eSRAM so now we move HMBOUND down to top of DDR3 + // + QNCGetTSEGMemoryRange (&BaseAddress, &SmramLength); + NewValue = (UINT32)(BaseAddress + SmramLength); + DEBUG ((EFI_D_INFO,"Locking HMBOUND at: = 0x%8x\n",NewValue)); + QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_HMBOUND_REG, (NewValue | HMBOUND_LOCK)); + + // + // Lock IMR5 now that HMBOUND is locked (legacy S3 region) + // + NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR5+QUARK_NC_MEMORY_MANAGER_IMRXL); + NewValue |= IMR_LOCK; + QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR5+QUARK_NC_MEMORY_MANAGER_IMRXL, NewValue); + + // + // Lock IMR6 now that HMBOUND is locked (ACPI Reclaim/ACPI/Runtime services/Reserved) + // + NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR6+QUARK_NC_MEMORY_MANAGER_IMRXL); + NewValue |= IMR_LOCK; + QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR6+QUARK_NC_MEMORY_MANAGER_IMRXL, NewValue); + + // + // Disable IMR2 memory protection (RMU Main Binary) + // + QncImrWrite ( + QUARK_NC_MEMORY_MANAGER_IMR2, + (UINT32)(IMRL_RESET & ~IMR_EN), + (UINT32)IMRH_RESET, + (UINT32)IMRX_ALL_ACCESS, + (UINT32)IMRX_ALL_ACCESS + ); + + // + // Disable IMR3 memory protection (Default SMRAM) + // + QncImrWrite ( + QUARK_NC_MEMORY_MANAGER_IMR3, + (UINT32)(IMRL_RESET & ~IMR_EN), + (UINT32)IMRH_RESET, + (UINT32)IMRX_ALL_ACCESS, + (UINT32)IMRX_ALL_ACCESS + ); + + // + // Disable IMR4 memory protection (eSRAM). + // + QncImrWrite ( + QUARK_NC_MEMORY_MANAGER_IMR4, + (UINT32)(IMRL_RESET & ~IMR_EN), + (UINT32)IMRH_RESET, + (UINT32)IMRX_ALL_ACCESS, + (UINT32)IMRX_ALL_ACCESS + ); + + // + // RTC:28208 - System hang/crash when entering probe mode(ITP) when relocating SMBASE + // Workaround to make default SMRAM UnCachable + // + Status = gDS->SetMemorySpaceAttributes ( + (EFI_PHYSICAL_ADDRESS) SMM_DEFAULT_SMBASE, + SMM_DEFAULT_SMBASE_SIZE_BYTES, + EFI_MEMORY_WB + ); + ASSERT_EFI_ERROR (Status); + + mMemCfgDone = TRUE; +} + +VOID +EFIAPI +PlatformConfigOnSpiReady ( + IN EFI_EVENT Event, + IN VOID *Context + ) +/*++ + +Routine Description: + + Function runs in PI-DXE to perform platform specific config when SPI + interface is ready. + +Arguments: + Event - The event that occured. + Context - For EFI compatiblity. Not used. + +Returns: + None. + +--*/ +{ + EFI_STATUS Status; + VOID *SpiReadyProt = NULL; + EFI_PLATFORM_TYPE Type; + EFI_BOOT_MODE BootMode; + + BootMode = GetBootModeHob (); + + Status = gBS->LocateProtocol (&gEfiSmmSpiReadyProtocolGuid, NULL, &SpiReadyProt); + if (Status != EFI_SUCCESS){ + DEBUG ((DEBUG_INFO, "gEfiSmmSpiReadyProtocolGuid triggered but not valid.\n")); + return; + } + + // + // Lock regions SPI flash. + // + PlatformFlashLockPolicy (FALSE); + + // + // Configurations and checks to be done when DXE tracing available. + // + + // + // Platform specific Signal routing. + // + + // + // Skip any signal not needed for recovery and flash update. + // + if (BootMode != BOOT_ON_FLASH_UPDATE && BootMode != BOOT_IN_RECOVERY_MODE) { + + // + // Galileo Platform UART0 support. + // + Type = (EFI_PLATFORM_TYPE)PcdGet16 (PcdPlatformType); + if (Type == Galileo) { + // + // Use MUX to connect out UART0 pins. + // + PlatformInitializeUart0MuxGalileo (); + } + + // + // GalileoGen2 Platform UART0 support. + // + if (Type == GalileoGen2) { + // + // Use route out UART0 pins. + // + PlatformInitializeUart0MuxGalileoGen2 (); + } + } +} + +EFI_STATUS +EFIAPI +CreateConfigEvents ( + VOID + ) +/*++ + +Routine Description: + +Arguments: + None + +Returns: + EFI_STATUS + +--*/ +{ + EFI_EVENT EventSmmCfg; + EFI_EVENT EventSpiReady; + VOID *RegistrationSmmCfg; + VOID *RegistrationSpiReady; + + // + // Schedule callback for when SmmConfigurationProtocol installed. + // + EventSmmCfg = EfiCreateProtocolNotifyEvent ( + &gEfiSmmConfigurationProtocolGuid, + TPL_CALLBACK, + PlatformConfigOnSmmConfigurationProtocol, + NULL, + &RegistrationSmmCfg + ); + ASSERT (EventSmmCfg != NULL); + + // + // Schedule callback to setup SPI Flash Policy when SPI interface ready. + // + EventSpiReady = EfiCreateProtocolNotifyEvent ( + &gEfiSmmSpiReadyProtocolGuid, + TPL_CALLBACK, + PlatformConfigOnSpiReady, + NULL, + &RegistrationSpiReady + ); + ASSERT (EventSpiReady != NULL); + return EFI_SUCCESS; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.c new file mode 100644 index 0000000000..c0cde2c32c --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.c @@ -0,0 +1,87 @@ +/** @file +Platform init DXE driver for this platform. + +Copyright (c) 2013 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// Statements that include other files +// +#include "PlatformInitDxe.h" +#include +#include + +VOID +GetQncName ( + VOID + ) +{ + DEBUG ((EFI_D_INFO, "QNC Name: ")); + switch (PciRead16 (PCI_LIB_ADDRESS (MC_BUS, MC_DEV, MC_FUN, PCI_DEVICE_ID_OFFSET))) { + case QUARK_MC_DEVICE_ID: + DEBUG ((EFI_D_INFO, "Quark")); + break; + case QUARK2_MC_DEVICE_ID: + DEBUG ((EFI_D_INFO, "Quark2")); + break; + default: + DEBUG ((EFI_D_INFO, "Unknown")); + } + + // + // Revision + // + switch (PciRead8 (PCI_LIB_ADDRESS (MC_BUS, MC_DEV, MC_FUN, PCI_REVISION_ID_OFFSET))) { + case QNC_MC_REV_ID_A0: + DEBUG ((EFI_D_INFO, " - A0 stepping\n")); + break; + default: + DEBUG ((EFI_D_INFO, " - xx\n")); + } + + return; +} + +EFI_STATUS +EFIAPI +PlatformInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +/*++ + +Routine Description: + Entry point for the driver. + +Arguments: + + ImageHandle - Image Handle. + SystemTable - EFI System Table. + +Returns: + + EFI_SUCCESS - Function has completed successfully. + +--*/ +{ + EFI_STATUS Status; + + GetQncName(); + + // + // Create events for configuration callbacks. + // + CreateConfigEvents (); + + // + // Init Platform LEDs. + // + Status = PlatformLedInit ((EFI_PLATFORM_TYPE)PcdGet16 (PcdPlatformType)); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.h b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.h new file mode 100644 index 0000000000..603d6050f2 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.h @@ -0,0 +1,58 @@ +/** @file +Platform init DXE driver header file. + +Copyright (c) 2013 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PLATFORM_TYPES_H_ +#define _PLATFORM_TYPES_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BLOCK_SIZE_32KB 0x8000 +#define BLOCK_SIZE_64KB 0x10000 + +// +// Function prototypes for routines private to this driver. +// +EFI_STATUS +EFIAPI +CreateConfigEvents ( + VOID + ); + +EFI_STATUS +EFIAPI +PlatformPcal9555Config ( + IN CONST EFI_PLATFORM_TYPE PlatformType + ); + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.inf b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.inf new file mode 100644 index 0000000000..2605050612 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.inf @@ -0,0 +1,56 @@ +## @file +# Component description file for Quark Platform Init DXE module. +# +# Copyright (c) 2013 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformInitDxe + FILE_GUID = 2E6A521C-F697-402d-9774-98B2B7E140F3 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PlatformInit + +[Sources] + PlatformInitDxe.h + PlatformInitDxe.c + PlatformConfig.c + +[Packages] + MdePkg/MdePkg.dec + QuarkSocPkg/QuarkSocPkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + +[LibraryClasses] + BaseLib + HobLib + DebugLib + UefiDriverEntryPoint + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + DxeServicesTableLib + PlatformHelperLib + PlatformPcieHelperLib + DxeServicesLib + IntelQNCLib + QNCAccessLib + BaseMemoryLib + I2cLib + +[Protocols] + gEfiFirmwareVolumeBlockProtocolGuid + gEfiCpuArchProtocolGuid + gEfiSmmConfigurationProtocolGuid + gEfiSmmSpiReadyProtocolGuid + +[Pcd] + gQuarkPlatformTokenSpaceGuid.PcdPlatformType + +[Depex] + TRUE + diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SaveMemoryConfig/SaveMemoryConfig.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SaveMemoryConfig/SaveMemoryConfig.c new file mode 100644 index 0000000000..e6455acd63 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SaveMemoryConfig/SaveMemoryConfig.c @@ -0,0 +1,118 @@ +/** @file +This is the driver that locates the MemoryConfigurationData HOB, if it +exists, and saves the data to nvRAM. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +EFI_STATUS +EFIAPI +SaveMemoryConfigEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +/*++ + + Routine Description: + This is the standard EFI driver point that detects whether there is a + MemoryConfigurationData HOB and, if so, saves its data to nvRAM. + + Arguments: + ImageHandle - Handle for the image of this driver + SystemTable - Pointer to the EFI System Table + + Returns: + EFI_SUCCESS - if the data is successfully saved or there was no data + EFI_NOT_FOUND - if the HOB list could not be located. + EFI_UNLOAD_IMAGE - It is not success + +--*/ +{ + EFI_STATUS Status; + VOID *HobList; + EFI_HOB_GUID_TYPE *GuidHob; + VOID *HobData; + VOID *VariableData; + UINTN DataSize; + UINTN BufferSize; + + DataSize = 0; + VariableData = NULL; + GuidHob = NULL; + HobList = NULL; + HobData = NULL; + Status = EFI_UNSUPPORTED; + + // + // Get the HOB list. If it is not present, then ASSERT. + // + HobList = GetHobList (); + ASSERT (HobList != NULL); + + // + // Search for the Memory Configuration GUID HOB. If it is not present, then + // there's nothing we can do. It may not exist on the update path. + // + GuidHob = GetNextGuidHob (&gEfiMemoryConfigDataGuid, HobList); + if (GuidHob != NULL) { + HobData = GET_GUID_HOB_DATA (GuidHob); + DataSize = GET_GUID_HOB_DATA_SIZE (GuidHob); + // + // Use the HOB to save Memory Configuration Data + // + BufferSize = DataSize; + VariableData = AllocatePool (BufferSize); + ASSERT (VariableData != NULL); + Status = gRT->GetVariable ( + EFI_MEMORY_CONFIG_DATA_NAME, + &gEfiMemoryConfigDataGuid, + NULL, + &BufferSize, + VariableData + ); + if (Status == EFI_BUFFER_TOO_SMALL) { + gBS->FreePool (VariableData); + VariableData = AllocatePool (BufferSize); + ASSERT (VariableData != NULL); + Status = gRT->GetVariable ( + EFI_MEMORY_CONFIG_DATA_NAME, + &gEfiMemoryConfigDataGuid, + NULL, + &BufferSize, + VariableData + ); + } + + if (EFI_ERROR(Status) || BufferSize != DataSize || CompareMem (HobData, VariableData, DataSize) != 0) { + Status = gRT->SetVariable ( + EFI_MEMORY_CONFIG_DATA_NAME, + &gEfiMemoryConfigDataGuid, + (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS), + DataSize, + HobData + ); + ASSERT((Status == EFI_SUCCESS) || (Status == EFI_OUT_OF_RESOURCES)); + } + + gBS->FreePool (VariableData); + } + + // + // This driver does not produce any protocol services, so always unload it. + // + return Status; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SaveMemoryConfig/SaveMemoryConfig.inf b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SaveMemoryConfig/SaveMemoryConfig.inf new file mode 100644 index 0000000000..c980a3cd8c --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SaveMemoryConfig/SaveMemoryConfig.inf @@ -0,0 +1,44 @@ +## @file +# Component description file for SaveMemoryConfig module +# +# Copyright (c) 2013-2015 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SaveMemoryConfig + FILE_GUID = 0F99E33C-CA0C-4aa2-887D-B57EC9050278 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = SaveMemoryConfigEntryPoint + +[sources] + SaveMemoryConfig.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + +[LibraryClasses] + DebugLib + MemoryAllocationLib + BaseMemoryLib + UefiRuntimeServicesTableLib + UefiBootServicesTableLib + UefiDriverEntryPoint + HobLib + +[Protocols] + +[Guids] + gEfiGenericVariableGuid + gEfiMemoryConfigDataGuid + +[Depex] + gEdkiiVariableLockProtocolGuid AND + gEfiVariableArchProtocolGuid AND + gEfiVariableWriteArchProtocolGuid diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/CommonHeader.h b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/CommonHeader.h new file mode 100644 index 0000000000..e863a41ff4 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/CommonHeader.h @@ -0,0 +1,55 @@ +/** @file +Common header file shared by all source files. + +This file includes package header files, library classes and protocol, PPI & GUID definitions. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __COMMON_HEADER_H_ +#define __COMMON_HEADER_H_ + + + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/DxePlatform.inf b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/DxePlatform.inf new file mode 100644 index 0000000000..fb59706c70 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/DxePlatform.inf @@ -0,0 +1,76 @@ +## @file +# Component description file for DxePlatform module. +# +# This driver initializes platform configuration setting and installs several platform policy potocols. +# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = DxePlatform + FILE_GUID = DAA55048-BC3F-4dd9-999B-F58ABF2BBFCC + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = DxePlatformDriverEntry + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 EBC +# + +[Sources] + KeyboardLayout.c + QNCRegTable.c + processor.c + SetupPlatform.c + SetupPlatform.h + Strings.uni + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + QuarkSocPkg/QuarkSocPkg.dec + +[LibraryClasses] + IoLib + IntelQNCLib + PcdLib + PrintLib + MemoryAllocationLib + BaseMemoryLib + S3BootScriptLib + DebugLib + UefiRuntimeServicesTableLib + UefiBootServicesTableLib + UefiDriverEntryPoint + BaseLib + S3IoLib + S3PciLib + HiiLib + HobLib + PciLib + UefiLib + +[Guids] + +[Protocols] + gEfiPlatformPolicyProtocolGuid # PROTOCOL ALWAYS_PRODUCED + gEfiHiiDatabaseProtocolGuid # PROTOCOL ALWAYS_CONSUMED + gEfiHiiConfigAccessProtocolGuid # PROTOCOL ALWAYS_CONSUMED + gEfiHiiConfigRoutingProtocolGuid # PROTOCOL ALWAYS_CONSUMED + +[Pcd] + gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioBaseAddress + gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent0IR + gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent1IR + gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent2IR + gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent3IR + +[Depex] + # AND EFI_SDRAM_MEMORY_SETUP_PROTOCOL_GUID AND + gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiHiiDatabaseProtocolGuid AND gPcdProtocolGuid diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/KeyboardLayout.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/KeyboardLayout.c new file mode 100644 index 0000000000..01dad5d34b --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/KeyboardLayout.c @@ -0,0 +1,262 @@ +/** @file +Example code to register customized keyboard layout to HII database. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "CommonHeader.h" + +// +// Define "`" as Non-spacing key to switch "a","u","i","o","e" +// +#define ENABLE_NS_KEY 1 + +#ifdef ENABLE_NS_KEY +#define KEYBOARD_KEY_COUNT (104 + 5) +#else +#define KEYBOARD_KEY_COUNT 104 +#endif + +#pragma pack (1) +typedef struct { + // + // This 4-bytes total array length is required by PreparePackageList() + // + UINT32 Length; + + // + // Keyboard Layout package definition + // + EFI_HII_PACKAGE_HEADER PackageHeader; + UINT16 LayoutCount; + + // + // EFI_HII_KEYBOARD_LAYOUT + // + UINT16 LayoutLength; + EFI_GUID Guid; + UINT32 LayoutDescriptorStringOffset; + UINT8 DescriptorCount; + EFI_KEY_DESCRIPTOR KeyDescriptor[KEYBOARD_KEY_COUNT]; + UINT16 DescriptionCount; // EFI_DESCRIPTION_STRING_BUNDLE + CHAR16 Language[5]; // RFC4646 Language Code: "en-US" + CHAR16 Space; + CHAR16 DescriptionString[17]; // Description: "English Keyboard" +} KEYBOARD_LAYOUT_PACK_BIN; +#pragma pack() + +#define KEYBOARD_LAYOUT_PACKAGE_GUID \ + { \ + 0xd66f7b7a, 0x5e06, 0x49f3, { 0xa1, 0xcf, 0x12, 0x8d, 0x4, 0x86, 0xc2, 0x7c } \ + } + +#define KEYBOARD_LAYOUT_KEY_GUID \ + { \ + 0xd9db96f4, 0xff47, 0x4eb6, { 0x8a, 0x4, 0x79, 0x5b, 0x56, 0x87, 0xb, 0x4e } \ + } + +EFI_GUID mKeyboardLayoutPackageGuid = KEYBOARD_LAYOUT_PACKAGE_GUID; +EFI_GUID mKeyboardLayoutKeyGuid = KEYBOARD_LAYOUT_KEY_GUID; + +KEYBOARD_LAYOUT_PACK_BIN mKeyboardLayoutBin = { + sizeof (KEYBOARD_LAYOUT_PACK_BIN), // Binary size + + // + // EFI_HII_PACKAGE_HEADER + // + { + sizeof (KEYBOARD_LAYOUT_PACK_BIN) - sizeof (UINT32), + EFI_HII_PACKAGE_KEYBOARD_LAYOUT + }, + 1, // LayoutCount + sizeof (KEYBOARD_LAYOUT_PACK_BIN) - sizeof (UINT32) - sizeof (EFI_HII_PACKAGE_HEADER) - sizeof (UINT16), // LayoutLength + KEYBOARD_LAYOUT_KEY_GUID, // KeyGuid + sizeof (UINT16) + sizeof (EFI_GUID) + sizeof (UINT32) + sizeof (UINT8) + (KEYBOARD_KEY_COUNT * sizeof (EFI_KEY_DESCRIPTOR)), // LayoutDescriptorStringOffset + KEYBOARD_KEY_COUNT, // DescriptorCount + { + // + // EFI_KEY_DESCRIPTOR + // + {EfiKeyC1, 'a', 'A', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyB5, 'b', 'B', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyB3, 'c', 'C', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyC3, 'd', 'D', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyD3, 'e', 'E', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyC4, 'f', 'F', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyC5, 'g', 'G', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyC6, 'h', 'H', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyD8, 'i', 'I', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyC7, 'j', 'J', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyC8, 'k', 'K', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyC9, 'l', 'L', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyB7, 'm', 'M', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyB6, 'n', 'N', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyD9, 'o', 'O', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyD10, 'p', 'P', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyD1, 'q', 'Q', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyD4, 'r', 'R', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyC2, 's', 'S', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyD5, 't', 'T', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyD7, 'u', 'U', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyB4, 'v', 'V', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyD2, 'w', 'W', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyB2, 'x', 'X', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyD6, 'y', 'Y', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyB1, 'z', 'Z', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyE1, '1', '!', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT}, + {EfiKeyE2, '2', '@', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT}, + {EfiKeyE3, '3', '#', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT}, + {EfiKeyE4, '4', '$', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT}, + {EfiKeyE5, '5', '%', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT}, + {EfiKeyE6, '6', '^', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT}, + {EfiKeyE7, '7', '&', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT}, + {EfiKeyE8, '8', '*', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT}, + {EfiKeyE9, '9', '(', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT}, + {EfiKeyE10, '0', ')', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT}, + {EfiKeyEnter, 0x0d, 0x0d, 0, 0, EFI_NULL_MODIFIER, 0}, + {EfiKeyEsc, 0x1b, 0x1b, 0, 0, EFI_NULL_MODIFIER, 0}, + {EfiKeyBackSpace, 0x08, 0x08, 0, 0, EFI_NULL_MODIFIER, 0}, + {EfiKeyTab, 0x09, 0x09, 0, 0, EFI_NULL_MODIFIER, 0}, + {EfiKeySpaceBar, ' ', ' ', 0, 0, EFI_NULL_MODIFIER, 0}, + {EfiKeyE11, '-', '_', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT}, + {EfiKeyE12, '=', '+', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT}, + {EfiKeyD11, '[', '{', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT}, + {EfiKeyD12, ']', '}', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT}, + {EfiKeyD13, '\\', '|', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT}, + {EfiKeyC10, ';', ':', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT}, + {EfiKeyC11, '\'', '"', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT}, + +#ifdef ENABLE_NS_KEY + // + // Non-Spacing key example + // + {EfiKeyE0, 0, 0, 0, 0, EFI_NS_KEY_MODIFIER, 0}, + {EfiKeyC1, 0x00E2, 0x00C2, 0, 0, EFI_NS_KEY_DEPENDENCY_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyD3, 0x00EA, 0x00CA, 0, 0, EFI_NS_KEY_DEPENDENCY_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyD8, 0x00EC, 0x00CC, 0, 0, EFI_NS_KEY_DEPENDENCY_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyD9, 0x00F4, 0x00D4, 0, 0, EFI_NS_KEY_DEPENDENCY_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, + {EfiKeyD7, 0x00FB, 0x00CB, 0, 0, EFI_NS_KEY_DEPENDENCY_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK}, +#else + {EfiKeyE0, '`', '~', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT}, +#endif + + {EfiKeyB8, ',', '<', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT}, + {EfiKeyB9, '.', '>', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT}, + {EfiKeyB10, '/', '?', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT}, + {EfiKeyCapsLock, 0x00, 0x00, 0, 0, EFI_CAPS_LOCK_MODIFIER, 0}, + {EfiKeyF1, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_ONE_MODIFIER, 0}, + {EfiKeyF2, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_TWO_MODIFIER, 0}, + {EfiKeyF3, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_THREE_MODIFIER, 0}, + {EfiKeyF4, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_FOUR_MODIFIER, 0}, + {EfiKeyF5, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_FIVE_MODIFIER, 0}, + {EfiKeyF6, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_SIX_MODIFIER, 0}, + {EfiKeyF7, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_SEVEN_MODIFIER, 0}, + {EfiKeyF8, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_EIGHT_MODIFIER, 0}, + {EfiKeyF9, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_NINE_MODIFIER, 0}, + {EfiKeyF10, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_TEN_MODIFIER, 0}, + {EfiKeyF11, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_ELEVEN_MODIFIER, 0}, + {EfiKeyF12, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_TWELVE_MODIFIER, 0}, + {EfiKeyPrint, 0x00, 0x00, 0, 0, EFI_PRINT_MODIFIER, 0}, + {EfiKeySLck, 0x00, 0x00, 0, 0, EFI_SCROLL_LOCK_MODIFIER, 0}, + {EfiKeyPause, 0x00, 0x00, 0, 0, EFI_PAUSE_MODIFIER, 0}, + {EfiKeyIns, 0x00, 0x00, 0, 0, EFI_INSERT_MODIFIER, 0}, + {EfiKeyHome, 0x00, 0x00, 0, 0, EFI_HOME_MODIFIER, 0}, + {EfiKeyPgUp, 0x00, 0x00, 0, 0, EFI_PAGE_UP_MODIFIER, 0}, + {EfiKeyDel, 0x00, 0x00, 0, 0, EFI_DELETE_MODIFIER, 0}, + {EfiKeyEnd, 0x00, 0x00, 0, 0, EFI_END_MODIFIER, 0}, + {EfiKeyPgDn, 0x00, 0x00, 0, 0, EFI_PAGE_DOWN_MODIFIER, 0}, + {EfiKeyRightArrow, 0x00, 0x00, 0, 0, EFI_RIGHT_ARROW_MODIFIER, 0}, + {EfiKeyLeftArrow, 0x00, 0x00, 0, 0, EFI_LEFT_ARROW_MODIFIER, 0}, + {EfiKeyDownArrow, 0x00, 0x00, 0, 0, EFI_DOWN_ARROW_MODIFIER, 0}, + {EfiKeyUpArrow, 0x00, 0x00, 0, 0, EFI_UP_ARROW_MODIFIER, 0}, + {EfiKeyNLck, 0x00, 0x00, 0, 0, EFI_NUM_LOCK_MODIFIER, 0}, + {EfiKeySlash, '/', '/', 0, 0, EFI_NULL_MODIFIER, 0}, + {EfiKeyAsterisk, '*', '*', 0, 0, EFI_NULL_MODIFIER, 0}, + {EfiKeyMinus, '-', '-', 0, 0, EFI_NULL_MODIFIER, 0}, + {EfiKeyPlus, '+', '+', 0, 0, EFI_NULL_MODIFIER, 0}, + {EfiKeyEnter, 0x0d, 0x0d, 0, 0, EFI_NULL_MODIFIER, 0}, + {EfiKeyOne, '1', '1', 0, 0, EFI_END_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_NUM_LOCK}, + {EfiKeyTwo, '2', '2', 0, 0, EFI_DOWN_ARROW_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_NUM_LOCK}, + {EfiKeyThree, '3', '3', 0, 0, EFI_PAGE_DOWN_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_NUM_LOCK}, + {EfiKeyFour, '4', '4', 0, 0, EFI_LEFT_ARROW_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_NUM_LOCK}, + {EfiKeyFive, '5', '5', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_NUM_LOCK}, + {EfiKeySix, '6', '6', 0, 0, EFI_RIGHT_ARROW_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_NUM_LOCK}, + {EfiKeySeven, '7', '7', 0, 0, EFI_HOME_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_NUM_LOCK}, + {EfiKeyEight, '8', '8', 0, 0, EFI_UP_ARROW_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_NUM_LOCK}, + {EfiKeyNine, '9', '9', 0, 0, EFI_PAGE_UP_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_NUM_LOCK}, + {EfiKeyZero, '0', '0', 0, 0, EFI_INSERT_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_NUM_LOCK}, + {EfiKeyPeriod, '.', '.', 0, 0, EFI_DELETE_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_NUM_LOCK}, + {EfiKeyA4, 0x00, 0x00, 0, 0, EFI_MENU_MODIFIER, 0}, + {EfiKeyLCtrl, 0, 0, 0, 0, EFI_LEFT_CONTROL_MODIFIER, 0}, + {EfiKeyLShift, 0, 0, 0, 0, EFI_LEFT_SHIFT_MODIFIER, 0}, + {EfiKeyLAlt, 0, 0, 0, 0, EFI_LEFT_ALT_MODIFIER, 0}, + {EfiKeyA0, 0, 0, 0, 0, EFI_LEFT_LOGO_MODIFIER, 0}, + {EfiKeyRCtrl, 0, 0, 0, 0, EFI_RIGHT_CONTROL_MODIFIER, 0}, + {EfiKeyRShift, 0, 0, 0, 0, EFI_RIGHT_SHIFT_MODIFIER, 0}, + {EfiKeyA2, 0, 0, 0, 0, EFI_RIGHT_ALT_MODIFIER, 0}, + {EfiKeyA3, 0, 0, 0, 0, EFI_RIGHT_LOGO_MODIFIER, 0}, + }, + 1, // DescriptionCount + {'e', 'n', '-', 'U', 'S'}, // RFC4646 language code + ' ', // Space + {'E', 'n', 'g', 'l', 'i', 's', 'h', ' ', 'K', 'e', 'y', 'b', 'o', 'a', 'r', 'd', '\0'}, // DescriptionString[17] +}; + +extern EFI_HANDLE mImageHandle; + +EFI_STATUS +InitKeyboardLayout ( + VOID + ) +/*++ + + Routine Description: + Install keyboard layout package and set current keyboard layout. + + Arguments: + None. + + Returns: + EFI_STATUS + +--*/ +{ + EFI_STATUS Status; + EFI_HII_DATABASE_PROTOCOL *HiiDatabase; + EFI_HII_HANDLE HiiHandle; + + // + // Locate Hii database protocol + // + Status = gBS->LocateProtocol ( + &gEfiHiiDatabaseProtocolGuid, + NULL, + (VOID**)&HiiDatabase + ); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Install Keyboard Layout package to HII database + // + HiiHandle = HiiAddPackages ( + &mKeyboardLayoutPackageGuid, + mImageHandle, + &mKeyboardLayoutBin, + NULL + ); + if (HiiHandle == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + // + // Set current keyboard layout + // + Status = HiiDatabase->SetKeyboardLayout (HiiDatabase, &mKeyboardLayoutKeyGuid); + + return Status; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/QNCRegTable.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/QNCRegTable.c new file mode 100644 index 0000000000..cc677e896f --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/QNCRegTable.c @@ -0,0 +1,80 @@ +/** @file +Register initialization table for Ich. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + + +#include "CommonHeader.h" + +VOID +PlatformInitQNCRegs ( + VOID + ) +{ + // + // All devices on bus 0. + // Device 0: + // FNC 0: Host Bridge + // Device 20: + // FNC 0: IOSF2AHB Bridge + // Device 21: + // FNC 0: IOSF2AHB Bridge + // Device 23: + // FNC 0: PCIe Port 0 + // Device 24: + // FNC 0: PCIe Port 1 + + // Device 31: + // FNC 0: PCI-LPC Bridge + // + S3PciWrite32 (PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, R_QNC_LPC_FWH_BIOS_DEC), + B_QNC_LPC_FWH_BIOS_DEC_F0 | B_QNC_LPC_FWH_BIOS_DEC_F8 | + B_QNC_LPC_FWH_BIOS_DEC_E0 | B_QNC_LPC_FWH_BIOS_DEC_E8 | + B_QNC_LPC_FWH_BIOS_DEC_D0 | B_QNC_LPC_FWH_BIOS_DEC_D8 | + B_QNC_LPC_FWH_BIOS_DEC_C0 | B_QNC_LPC_FWH_BIOS_DEC_C8 + ); + + // + // Program SCI Interrupt for IRQ9 + // + S3PciWrite8 (PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, R_QNC_LPC_ACTL), + V_QNC_LPC_ACTL_SCIS_IRQ9 + ); + + // + // Program Quark Interrupt Route Registers + // + S3MmioWrite16 ((UINTN)PcdGet64(PcdRcbaMmioBaseAddress) + R_QNC_RCRB_AGENT0IR, + PcdGet16(PcdQuarkAgent0IR) + ); + S3MmioWrite16 ((UINTN)PcdGet64(PcdRcbaMmioBaseAddress) + R_QNC_RCRB_AGENT1IR, + PcdGet16(PcdQuarkAgent1IR) + ); + S3MmioWrite16 ((UINTN)PcdGet64(PcdRcbaMmioBaseAddress) + R_QNC_RCRB_AGENT2IR, + PcdGet16(PcdQuarkAgent2IR) + ); + S3MmioWrite16 ((UINTN)PcdGet64(PcdRcbaMmioBaseAddress) + R_QNC_RCRB_AGENT3IR, + PcdGet16(PcdQuarkAgent3IR) + ); + + // + // Program SVID and SID for QNC PCI devices. In order to boost performance, we + // combine two 16 bit PCI_WRITE into one 32 bit PCI_WRITE. The programmed LPC SVID + // will reflect on all internal devices's SVID registers + // + S3PciWrite32 (PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, R_EFI_PCI_SVID), + (UINT32)(V_INTEL_VENDOR_ID + (QUARK_V_LPC_DEVICE_ID_0 << 16)) + ); + + // + // Write once on Element Self Description Register before OS boot + // + QNCMmio32And (PcdGet64(PcdRcbaMmioBaseAddress), 0x04, 0xFF00FFFF); + + return; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/SetupPlatform.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/SetupPlatform.c new file mode 100644 index 0000000000..7e36fdfcef --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/SetupPlatform.c @@ -0,0 +1,97 @@ +/** @file +Platform Initialization Driver. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "CommonHeader.h" + +#include "SetupPlatform.h" +#include + +EFI_HANDLE mImageHandle = NULL; + +EFI_HII_DATABASE_PROTOCOL *mHiiDataBase = NULL; +EFI_HII_CONFIG_ROUTING_PROTOCOL *mHiiConfigRouting = NULL; + +UINT8 mSmbusRsvdAddresses[PLATFORM_NUM_SMBUS_RSVD_ADDRESSES] = { + SMBUS_ADDR_CH_A_1, + SMBUS_ADDR_CK505, + SMBUS_ADDR_THERMAL_SENSOR1, + SMBUS_ADDR_THERMAL_SENSOR2 +}; + +EFI_PLATFORM_POLICY_PROTOCOL mPlatformPolicyData = { + PLATFORM_NUM_SMBUS_RSVD_ADDRESSES, + mSmbusRsvdAddresses +}; + +EFI_STATUS +DxePlatformDriverEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +/*++ + + Routine Description: + This is the standard EFI driver point for the D845GRgPlatform Driver. This + driver is responsible for setting up any platform specific policy or + initialization information. + + Arguments: + ImageHandle - Handle for the image of this driver + SystemTable - Pointer to the EFI System Table + + Returns: + EFI_SUCCESS - Policy decisions set + +--*/ +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + S3BootScriptSaveInformationAsciiString ( + "SetupDxeEntryBegin" + ); + + mImageHandle = ImageHandle; + + Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL, (VOID**)&mHiiDataBase); + ASSERT_EFI_ERROR (Status); + + Status = gBS->LocateProtocol (&gEfiHiiConfigRoutingProtocolGuid, NULL, (VOID**)&mHiiConfigRouting); + ASSERT_EFI_ERROR (Status); + + // + // Initialize keyboard layout + // + Status = InitKeyboardLayout (); + + // + // Initialize ICH registers + // + PlatformInitQNCRegs(); + + ProducePlatformCpuData (); + + // + // Install protocol to to allow access to this Policy. + // + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEfiPlatformPolicyProtocolGuid, &mPlatformPolicyData, + NULL + ); + ASSERT_EFI_ERROR(Status); + + S3BootScriptSaveInformationAsciiString ( + "SetupDxeEntryEnd" + ); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/SetupPlatform.h b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/SetupPlatform.h new file mode 100644 index 0000000000..a0ea25ca90 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/SetupPlatform.h @@ -0,0 +1,71 @@ +/** @file +Header file for Platform Initialization Driver. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SETUP_PLATFORM_H +#define _SETUP_PLATFORM_H + +// +// Data +// +#define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES 4 +#define VAR_OFFSET(Field) ((UINT16) ((UINTN) &(((SYSTEM_CONFIGURATION *) 0)->Field))) +#define QUESTION_ID(Field) (VAR_OFFSET (Field) + 1) + +#define SMBUS_ADDR_CH_A_1 0xA0 +#define SMBUS_ADDR_CK505 0xD2 +#define SMBUS_ADDR_THERMAL_SENSOR1 0x4C +#define SMBUS_ADDR_THERMAL_SENSOR2 0x4D + +/// +/// HII specific Vendor Device Path Node definition. +/// +#pragma pack(1) + +typedef struct { + VENDOR_DEVICE_PATH VendorDevicePath; + UINT16 UniqueId; +} HII_VENDOR_DEVICE_PATH_NODE; + +/// +/// HII specific Vendor Device Path definition. +/// +typedef struct { + HII_VENDOR_DEVICE_PATH_NODE Node; + EFI_DEVICE_PATH_PROTOCOL End; +} HII_VENDOR_DEVICE_PATH; + +#pragma pack() + +// +// Prototypes +// +VOID +ProducePlatformCpuData ( + VOID + ); + +VOID +PlatformInitQNCRegs ( + VOID + ); + +EFI_STATUS +InitKeyboardLayout ( + VOID + ); + +// +// Global externs +// +extern UINT8 UefiSetupDxeStrings[]; + +extern EFI_HII_DATABASE_PROTOCOL *mHiiDataBase; +extern EFI_HII_CONFIG_ROUTING_PROTOCOL *mHiiConfigRouting; + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/Strings.uni b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/Strings.uni new file mode 100644 index 0000000000..69d497d69a --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/Strings.uni @@ -0,0 +1,47 @@ +// /** @file +// String definitions for Sample Setup formset. +// +// Copyright (c) 2013-2015 Intel Corporation. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// +// **/ + +/=# + +#langdef en-US "English" +#langdef fr-FR "Français" +#langdef es-ES "Español" + +#string STR_LGA775 #language en-US "L775" +#string STR_LGA775 #language fr-FR "L775" +#string STR_LGA775 #language es-ES "L775" + + +// Enable or Disable +#string STR_ENABLE #language en-US "Enable" +#string STR_ENABLE #language fr-FR "Activé" +#string STR_ENABLE #language es-ES "Activada" + +#string STR_DISABLE #language en-US "Disable" +#string STR_DISABLE #language fr-FR "Désactivé" +#string STR_DISABLE #language es-ES "Desactivada" + +#string STR_AUTO #language en-US "Auto" +#string STR_AUTO #language fr-FR "Auto" +#string STR_AUTO #language es-ES "Auto" + +// Unknown +#string STR_UNKNOWN #language en-US "Unknown" +#string STR_UNKNOWN #language fr-FR "Unknown" +#string STR_UNKNOWN #language es-ES "Unknown" + + +// NULL String +#string STR_NULL_STRING #language en-US "" + +#string STR_VAR_TOTAL_MEMORY_SIZE #language en-US "54" + +#string VAR_EQ_CONFIG_MODE_NAME #language en-US "67" +// End of file diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/processor.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/processor.c new file mode 100644 index 0000000000..e86901f9b6 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/Setup/processor.c @@ -0,0 +1,40 @@ +/** @file +Platform CPU Data + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "CommonHeader.h" + +#include "SetupPlatform.h" + + +#define NUMBER_OF_PACKAGES 1 + +CHAR16 *SocketNames[NUMBER_OF_PACKAGES]; +CHAR16 *AssetTags[NUMBER_OF_PACKAGES]; + +CHAR16 EmptyString[] = L" "; +CHAR16 SocketString[] = L"LGA775"; + +VOID +ProducePlatformCpuData ( + VOID + ) +{ + UINTN Index; + + for (Index = 0; Index < NUMBER_OF_PACKAGES; Index++) { + + // + // The String Package of a module is registered together with all IFR packages. + // So we just arbitrarily pick a package GUID that is always installed to get the string. + // + AssetTags[Index] = EmptyString; + SocketNames[Index] = SocketString; + } +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/CommonHeader.h b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/CommonHeader.h new file mode 100644 index 0000000000..a21de76efd --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/CommonHeader.h @@ -0,0 +1,34 @@ +/** @file +Common header file shared by all source files. + +This file includes package header files, library classes and protocol, PPI & GUID definitions. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __COMMON_HEADER_H_ +#define __COMMON_HEADER_H_ + + + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern EFI_HII_HANDLE gHiiHandle; +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBaseBoardManufacturer.uni b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBaseBoardManufacturer.uni new file mode 100644 index 0000000000..c51183ef4e --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBaseBoardManufacturer.uni @@ -0,0 +1,19 @@ +// /** @file +// System Manufacturer Information +// +// Copyright (c) 2013-2015 Intel Corporation. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// +// **/ + +/=# + +#string STR_MISC_BASE_BOARD_MANUFACTURER #language en-US "Intel Corp." +#string STR_MISC_BASE_BOARD_PRODUCT_NAME #language en-US "QUARK" +#string STR_MISC_BASE_BOARD_VERSION #language en-US "FAB-D" +#string STR_MISC_BASE_BOARD_SERIAL_NUMBER #language en-US "XXXXXXXXXXXX" +#string STR_MISC_BASE_BOARD_ASSET_TAG #language en-US "Base Board Asset Tag" +#string STR_MISC_BASE_BOARD_CHASSIS_LOCATION #language en-US "Part Component" + diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBaseBoardManufacturerData.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBaseBoardManufacturerData.c new file mode 100644 index 0000000000..18f4624cf9 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBaseBoardManufacturerData.c @@ -0,0 +1,45 @@ +/** @file +Type 2: Base Board Information. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "CommonHeader.h" +#include "SmbiosMisc.h" + +// +// Static (possibly build generated) Bios Vendor data. +// +MISC_SMBIOS_TABLE_DATA(EFI_MISC_BASE_BOARD_MANUFACTURER_DATA, MiscBaseBoardManufacturer) += { + STRING_TOKEN(STR_MISC_BASE_BOARD_MANUFACTURER), + STRING_TOKEN(STR_MISC_BASE_BOARD_PRODUCT_NAME), + STRING_TOKEN(STR_MISC_BASE_BOARD_VERSION), + STRING_TOKEN(STR_MISC_BASE_BOARD_SERIAL_NUMBER), + STRING_TOKEN(STR_MISC_BASE_BOARD_ASSET_TAG), + STRING_TOKEN(STR_MISC_BASE_BOARD_CHASSIS_LOCATION), + { // BaseBoardFeatureFlags + 1, // Motherboard + 0, // RequiresDaughterCard + 0, // Removable + 1, // Replaceable, + 0, // HotSwappable + 0, // Reserved + }, + EfiBaseBoardTypeUnknown, // BaseBoardType + { // BaseBoardChassisLink + EFI_MISC_SUBCLASS_GUID, // ProducerName + 1, // Instance + 1, // SubInstance + }, + 0, // BaseBoardNumberLinks + { // LinkN + EFI_MISC_SUBCLASS_GUID, // ProducerName + 1, // Instance + 1, // SubInstance + }, +}; diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBaseBoardManufacturerFunction.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBaseBoardManufacturerFunction.c new file mode 100644 index 0000000000..a9597ebcc2 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBaseBoardManufacturerFunction.c @@ -0,0 +1,181 @@ +/** @file +Base Board Information boot time changes. +Misc. subclass type 4. +SMBIOS type 2. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "CommonHeader.h" +#include "SmbiosMisc.h" + +/** + This function makes boot time changes to the contents of the + MiscBaseBoardManufacturer (Type 2). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscBaseBoardManufacturer) +{ + CHAR8 *OptionalStrStart; + UINTN ManuStrLen; + UINTN ProductStrLen; + UINTN VerStrLen; + UINTN AssertTagStrLen; + UINTN SerialNumStrLen; + UINTN ChassisStrLen; + EFI_STATUS Status; + EFI_STRING Manufacturer; + EFI_STRING Product; + EFI_STRING Version; + EFI_STRING SerialNumber; + EFI_STRING AssertTag; + EFI_STRING Chassis; + STRING_REF TokenToGet; + STRING_REF TokenToUpdate; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE2 *SmbiosRecord; + EFI_MISC_BASE_BOARD_MANUFACTURER *ForType2InputData; + UINTN TypeStringSize; + CHAR16 TypeString[SMBIOS_STRING_MAX_LENGTH]; + + ForType2InputData = (EFI_MISC_BASE_BOARD_MANUFACTURER *)RecordData; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER); + Manufacturer = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + ManuStrLen = StrLen(Manufacturer); + if (ManuStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + StrCpy (TypeString, L""); + TypeStringSize = PcdGetSize (PcdPlatformTypeName); + if (TypeStringSize > 0 && TypeStringSize <= sizeof (TypeString)) { + CopyMem (TypeString, PcdGetPtr (PcdPlatformTypeName), TypeStringSize); + } + if (StrLen (TypeString) == 0) { + StrCpy (TypeString, L"Unknown"); + } + TokenToUpdate = STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME); + HiiSetString (mHiiHandle, TokenToUpdate, TypeString, NULL); + + TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME); + Product = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + ProductStrLen = StrLen(TypeString); + if (ProductStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_VERSION); + Version = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + VerStrLen = StrLen(Version); + if (VerStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER); + SerialNumber = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + SerialNumStrLen = StrLen(SerialNumber); + if (SerialNumStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_ASSET_TAG); + AssertTag = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + AssertTagStrLen = StrLen(AssertTag); + if (AssertTagStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_CHASSIS_LOCATION); + Chassis = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + ChassisStrLen = StrLen(Chassis); + if (ChassisStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE3) + ManuStrLen + 1 + ProductStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen + 1 + ChassisStrLen +1 + 1); + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE3) + ManuStrLen + 1 + ProductStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen + 1 + ChassisStrLen +1 + 1); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION; + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE2); + // + // Make handle chosen by smbios protocol.add automatically. + // + SmbiosRecord->Hdr.Handle = 0; + // + // Manu will be the 1st optional string following the formatted structure. + // + SmbiosRecord->Manufacturer = 1; + // + // ProductName will be the 2st optional string following the formatted structure. + // + SmbiosRecord->ProductName = 2; + // + // Version will be the 3rd optional string following the formatted structure. + // + SmbiosRecord->Version = 3; + // + // SerialNumber will be the 4th optional string following the formatted structure. + // + SmbiosRecord->SerialNumber = 4; + // + // AssertTag will be the 5th optional string following the formatted structure. + // + SmbiosRecord->AssetTag = 5; + + // + // LocationInChassis will be the 6th optional string following the formatted structure. + // + SmbiosRecord->LocationInChassis = 6; + SmbiosRecord->FeatureFlag = (*(BASE_BOARD_FEATURE_FLAGS*)&(ForType2InputData->BaseBoardFeatureFlags)); + SmbiosRecord->ChassisHandle = 0; + SmbiosRecord->BoardType = (UINT8)ForType2InputData->BaseBoardType; + SmbiosRecord->NumberOfContainedObjectHandles = 0; + + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); + // + // Since we fill NumberOfContainedObjectHandles = 0 for simple, just after this filed to fill string + // + //OptionalStrStart -= 2; + UnicodeStrToAsciiStr(Manufacturer, OptionalStrStart); + UnicodeStrToAsciiStr(Product, OptionalStrStart + ManuStrLen + 1); + UnicodeStrToAsciiStr(Version, OptionalStrStart + ManuStrLen + 1 + ProductStrLen + 1); + UnicodeStrToAsciiStr(SerialNumber, OptionalStrStart + ManuStrLen + 1 + ProductStrLen + 1 + VerStrLen + 1); + UnicodeStrToAsciiStr(AssertTag, OptionalStrStart + ManuStrLen + 1 + ProductStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1); + UnicodeStrToAsciiStr(Chassis, OptionalStrStart + ManuStrLen + 1 + ProductStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen + 1); + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios-> Add( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + + FreePool(SmbiosRecord); + return Status; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBiosVendor.uni b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBiosVendor.uni new file mode 100644 index 0000000000..b71b2b0947 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBiosVendor.uni @@ -0,0 +1,18 @@ +// /** @file +// BIOS vendor information. +// Misc. subclass type 2. +// SMBIOS type 0. +// +// Copyright (c) 2013-2015 Intel Corporation. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// +// **/ + + +/=# + +#string STR_MISC_BIOS_VENDOR #language en-US "Intel Corp." +#string STR_MISC_BIOS_VERSION #language en-US "BIOS Version" +#string STR_MISC_BIOS_RELEASE_DATE #language en-US "11/03/2015" diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBiosVendorData.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBiosVendorData.c new file mode 100644 index 0000000000..aee8d48487 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBiosVendorData.c @@ -0,0 +1,92 @@ +/** @file +BIOS vendor information static data. +Misc. subclass type 2. +SMBIOS type 0. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + + +#include "CommonHeader.h" + +#include "SmbiosMisc.h" + + +// +// Static (possibly build generated) Bios Vendor data. +// +MISC_SMBIOS_TABLE_DATA(EFI_MISC_BIOS_VENDOR, MiscBiosVendor) = { + STRING_TOKEN (STR_MISC_BIOS_VENDOR), // BiosVendor + STRING_TOKEN (STR_MISC_BIOS_VERSION), // BiosVersion + STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE), // BiosReleaseDate + 0xE0000, // BiosStartingAddress + { // BiosPhysicalDeviceSize + 2, // Value + 20, // Exponent + }, + { // BiosCharacteristics1 + 0, // Reserved1 :2 + 0, // Unknown :1 + 0, // BiosCharacteristicsNotSupported :1 + 0, // IsaIsSupported :1 + 0, // McaIsSupported :1 + + 0, // EisaIsSupported :1 + 1, // PciIsSupported :1 + 0, // PcmciaIsSupported :1 + 0, // PlugAndPlayIsSupported :1 + 0, // ApmIsSupported :1 + + 1, // BiosIsUpgradable :1 + 1, // BiosShadowingAllowed :1 + 0, // VlVesaIsSupported :1 + 0, // EscdSupportIsAvailable :1 + 1, // BootFromCdIsSupported :1 + + 1, // SelectableBootIsSupported :1 + 0, // RomBiosIsSocketed :1 + 0, // BootFromPcmciaIsSupported :1 + 1, // EDDSpecificationIsSupported :1 + 0, // JapaneseNecFloppyIsSupported :1 + + 0, // JapaneseToshibaFloppyIsSupported :1 + 0, // Floppy525_360IsSupported :1 + 0, // Floppy525_12IsSupported :1 + 0, // Floppy35_720IsSupported :1 + 0, // Floppy35_288IsSupported :1 + + 1, // PrintScreenIsSupported :1 + 1, // Keyboard8042IsSupported :1 + 1, // SerialIsSupported :1 + 1, // PrinterIsSupported :1 + 1, // CgaMonoIsSupported :1 + + 0, // NecPc98 :1 + 1, // AcpiIsSupported :1 + 1, // UsbLegacyIsSupported :1 + 0, // AgpIsSupported :1 + 0, // I20BootIsSupported :1 + + 0, // Ls120BootIsSupported :1 + 0, // AtapiZipDriveBootIsSupported :1 + 0, // Boot1394IsSupported :1 + 0, // SmartBatteryIsSupported :1 + 1, // BiosBootSpecIsSupported :1 + + 1, // FunctionKeyNetworkBootIsSupported :1 + 0 // Reserved :22 + }, + { // BiosCharacteristics2 + 0, // BiosReserved :16 + 0, // SystemReserved :16 + 0 // Reserved :32 + }, + 0x1, // System BIOS Major Release + 0x0, // System BIOS Minor Release + 0xFF, // Embedded controller firmware major Release + 0xFF, // Embedded controller firmware minor Release +}; diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBiosVendorFunction.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBiosVendorFunction.c new file mode 100644 index 0000000000..a27e704302 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBiosVendorFunction.c @@ -0,0 +1,222 @@ +/** @file +BIOS vendor information boot time changes. +Misc. subclass type 2. +SMBIOS type 0. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + + +#include "CommonHeader.h" + +#include "SmbiosMisc.h" + +/** + This function returns the value & exponent to Base2 for a given + Hex value. This is used to calculate the BiosPhysicalDeviceSize. + + @param Value The hex value which is to be converted into value-exponent form + @param Exponent The exponent out of the conversion + + @retval EFI_SUCCESS All parameters were valid and *Value & *Exponent have been set. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +EFI_STATUS +GetValueExponentBase2( + IN OUT UINTN *Value, + OUT UINTN *Exponent + ) +{ + if ((Value == NULL) || (Exponent == NULL)) { + return EFI_INVALID_PARAMETER; + } + + while ((*Value % 2) == 0) { + *Value=*Value/2; + (*Exponent)++; + } + + return EFI_SUCCESS; +} + +/** + Field Filling Function. Transform an EFI_EXP_BASE2_DATA to a byte, with '64k' + as the unit. + + @param Base2Data Pointer to Base2_Data + + @retval EFI_SUCCESS Transform successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +UINT16 +Base2ToByteWith64KUnit ( + IN EFI_EXP_BASE2_DATA *Base2Data + ) +{ + UINT16 Value; + UINT16 Exponent; + + Value = Base2Data->Value; + Exponent = Base2Data->Exponent; + Exponent -= 16; + Value <<= Exponent; + + return Value; +} + + +/** + This function makes boot time changes to the contents of the + MiscBiosVendor (Type 0). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscBiosVendor) +{ + CHAR8 *OptionalStrStart; + UINTN VendorStrLen; + UINTN VerStrLen; + UINTN DateStrLen; + UINTN BiosPhysicalSizeHexValue; + UINTN BiosPhysicalSizeExponent; + CHAR16 Version[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 Vendor[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 ReleaseDate[SMBIOS_STRING_MAX_LENGTH]; + EFI_STRING VersionPtr; + EFI_STRING VendorPtr; + EFI_STRING ReleaseDatePtr; + EFI_STATUS Status; + STRING_REF TokenToGet; + STRING_REF TokenToUpdate; + SMBIOS_TABLE_TYPE0 *SmbiosRecord; + EFI_SMBIOS_HANDLE SmbiosHandle; + EFI_MISC_BIOS_VENDOR *ForType0InputData; + + BiosPhysicalSizeHexValue = 0x0; + BiosPhysicalSizeExponent = 0x0; + ForType0InputData = (EFI_MISC_BIOS_VENDOR *)RecordData; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + // + // Now update the BiosPhysicalSize + // + BiosPhysicalSizeHexValue = PcdGet32 (PcdFlashAreaSize); + Status= GetValueExponentBase2 ( + &BiosPhysicalSizeHexValue, + &BiosPhysicalSizeExponent + ); + if(Status == EFI_SUCCESS){ + ForType0InputData->BiosPhysicalDeviceSize.Value = (UINT16)BiosPhysicalSizeHexValue; + ForType0InputData->BiosPhysicalDeviceSize.Exponent = (UINT16)BiosPhysicalSizeExponent; + } + // + // Update strings from PCD + // + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr (PcdSMBIOSBiosVendor), Vendor); + if (StrLen (Vendor) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VENDOR); + HiiSetString (mHiiHandle, TokenToUpdate, Vendor, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VENDOR); + VendorPtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + VendorStrLen = StrLen(VendorPtr); + if (VendorStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + UnicodeSPrint (Version, sizeof (Version), L"0x%08x", PcdGet32 (PcdFirmwareRevision)); + if (StrLen (Version) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VERSION); + HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VERSION); + VersionPtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + VerStrLen = StrLen(VersionPtr); + if (VerStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr (PcdSMBIOSBiosReleaseDate), ReleaseDate); + if (StrLen (ReleaseDate) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE); + HiiSetString (mHiiHandle, TokenToUpdate, ReleaseDate, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE); + ReleaseDatePtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + DateStrLen = StrLen(ReleaseDatePtr); + if (DateStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE0) + VendorStrLen + 1 + VerStrLen + 1 + DateStrLen + 1 + 1); + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE0) + VendorStrLen + 1 + VerStrLen + 1 + DateStrLen + 1 + 1); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_BIOS_INFORMATION; + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE0); + // + // Make handle chosen by smbios protocol.add automatically. + // + SmbiosRecord->Hdr.Handle = 0; + // + // Vendor will be the 1st optional string following the formatted structure. + // + SmbiosRecord->Vendor = 1; + // + // Version will be the 2nd optional string following the formatted structure. + // + SmbiosRecord->BiosVersion = 2; + SmbiosRecord->BiosSegment = PcdGet16 (PcdSMBIOSBiosStartAddress); + // + // ReleaseDate will be the 3rd optional string following the formatted structure. + // + SmbiosRecord->BiosReleaseDate = 3; + SmbiosRecord->BiosSize = (UINT8)(Base2ToByteWith64KUnit(&ForType0InputData->BiosPhysicalDeviceSize) - 1); + *(UINT64 *)&SmbiosRecord->BiosCharacteristics = PcdGet64 (PcdSMBIOSBiosChar); + // + // CharacterExtensionBytes also store in ForType0InputData->BiosCharacteristics1 later two bytes to save size. + // + SmbiosRecord->BIOSCharacteristicsExtensionBytes[0] = PcdGet8 (PcdSMBIOSBiosCharEx1); + SmbiosRecord->BIOSCharacteristicsExtensionBytes[1] = PcdGet8 (PcdSMBIOSBiosCharEx2); + + SmbiosRecord->SystemBiosMajorRelease = ForType0InputData->BiosMajorRelease; + SmbiosRecord->SystemBiosMinorRelease = ForType0InputData->BiosMinorRelease; + SmbiosRecord->EmbeddedControllerFirmwareMajorRelease = ForType0InputData->BiosEmbeddedFirmwareMajorRelease; + SmbiosRecord->EmbeddedControllerFirmwareMinorRelease = ForType0InputData->BiosEmbeddedFirmwareMinorRelease; + + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); + UnicodeStrToAsciiStr(VendorPtr, OptionalStrStart); + UnicodeStrToAsciiStr(VersionPtr, OptionalStrStart + VendorStrLen + 1); + UnicodeStrToAsciiStr(ReleaseDatePtr, OptionalStrStart + VendorStrLen + 1 + VerStrLen + 1); + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios-> Add( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + + FreePool(SmbiosRecord); + return Status; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBootInformationData.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBootInformationData.c new file mode 100644 index 0000000000..2c2c038bc8 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBootInformationData.c @@ -0,0 +1,24 @@ +/** @file +This driver parses the mMiscSubclassDataTable structure and reports +any generated data to the DataHub. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + + +#include "CommonHeader.h" + +#include "SmbiosMisc.h" + + +// +// Static (possibly build generated) Bios Vendor data. SMBIOS TYPE 32 +// +MISC_SMBIOS_TABLE_DATA(EFI_MISC_BOOT_INFORMATION_STATUS, MiscBootInfoStatus) = { + EfiBootInformationStatusNoError, // BootInformationStatus + {0} // BootInformationData +}; diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBootInformationFunction.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBootInformationFunction.c new file mode 100644 index 0000000000..841d592314 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBootInformationFunction.c @@ -0,0 +1,71 @@ +/** @file +boot information boot time changes. +SMBIOS type 32. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + + +#include "CommonHeader.h" +#include "SmbiosMisc.h" + + +/** + This function makes boot time changes to the contents of the + MiscBootInformation (Type 32). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ + +MISC_SMBIOS_TABLE_FUNCTION(MiscBootInfoStatus) +{ + EFI_STATUS Status; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE32 *SmbiosRecord; + EFI_MISC_BOOT_INFORMATION_STATUS* ForType32InputData; + + ForType32InputData = (EFI_MISC_BOOT_INFORMATION_STATUS *)RecordData; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE32) + 1 + 1); + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE32) + 1 + 1); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION; + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE32); + // + // Make handle chosen by smbios protocol.add automatically. + // + SmbiosRecord->Hdr.Handle = 0; + SmbiosRecord->BootStatus = (UINT8)ForType32InputData->BootInformationStatus; + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios-> Add( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + FreePool(SmbiosRecord); + return Status; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscChassisManufacturer.uni b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscChassisManufacturer.uni new file mode 100644 index 0000000000..a1b930ee22 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscChassisManufacturer.uni @@ -0,0 +1,17 @@ +// /** @file +// Miscellaneous chassis manufacturer information +// +// Copyright (c) 2013-2015 Intel Corporation. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// +// **/ + + +/=# + +#string STR_MISC_CHASSIS_MANUFACTURER #language en-US "Chassis Manufacturer" +#string STR_MISC_CHASSIS_VERSION #language en-US "Chassis Version" +#string STR_MISC_CHASSIS_SERIAL_NUMBER #language en-US "Chassis Serial Number" +#string STR_MISC_CHASSIS_ASSET_TAG #language en-US "Chassis Asset Tag" diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscChassisManufacturerData.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscChassisManufacturerData.c new file mode 100644 index 0000000000..527086305c --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscChassisManufacturerData.c @@ -0,0 +1,36 @@ +/** @file +This driver parses the mMiscSubclassDataTable structure and reports +any generated data to the DataHub. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + + +#include "CommonHeader.h" + +#include "SmbiosMisc.h" + + +// +// Static (possibly build generated) Chassis Manufacturer data. +// +MISC_SMBIOS_TABLE_DATA(EFI_MISC_CHASSIS_MANUFACTURER, MiscChassisManufacturer) = { + STRING_TOKEN(STR_MISC_CHASSIS_MANUFACTURER), // ChassisManufactrurer + STRING_TOKEN(STR_MISC_CHASSIS_VERSION), // ChassisVersion + STRING_TOKEN(STR_MISC_CHASSIS_SERIAL_NUMBER), // ChassisSerialNumber + STRING_TOKEN(STR_MISC_CHASSIS_ASSET_TAG), // ChassisAssetTag + { // ChassisTypeStatus + EfiMiscChassisTypeDeskTop, // ChassisType + 0, // ChassisLockPresent + 0 // Reserved + }, + EfiChassisStateSafe, // ChassisBootupState + EfiChassisStateSafe, // ChassisPowerSupplyState + EfiChassisStateOther, // ChassisThermalState + EfiChassisSecurityStatusOther, // ChassisSecurityState + 0 // ChassisOemDefined +}; diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscChassisManufacturerFunction.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscChassisManufacturerFunction.c new file mode 100644 index 0000000000..5d6c32ef32 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscChassisManufacturerFunction.c @@ -0,0 +1,168 @@ +/** @file +Chassis manufacturer information boot time changes. +SMBIOS type 3. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + + +#include "CommonHeader.h" + +#include "SmbiosMisc.h" + +/** + This function makes boot time changes to the contents of the + MiscChassisManufacturer (Type 3). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscChassisManufacturer) +{ + CHAR8 *OptionalStrStart; + UINTN ManuStrLen; + UINTN VerStrLen; + UINTN AssertTagStrLen; + UINTN SerialNumStrLen; + EFI_STATUS Status; + CHAR16 Manufacturer[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 Version[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 SerialNumber[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 AssertTag[SMBIOS_STRING_MAX_LENGTH]; + EFI_STRING ManufacturerPtr; + EFI_STRING VersionPtr; + EFI_STRING SerialNumberPtr; + EFI_STRING AssertTagPtr; + STRING_REF TokenToGet; + STRING_REF TokenToUpdate; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE3 *SmbiosRecord; + EFI_MISC_CHASSIS_MANUFACTURER *ForType3InputData; + + ForType3InputData = (EFI_MISC_CHASSIS_MANUFACTURER *)RecordData; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Update strings from PCD + // + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSChassisManufacturer), Manufacturer); + if (StrLen (Manufacturer) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_CHASSIS_MANUFACTURER); + HiiSetString (mHiiHandle, TokenToUpdate, Manufacturer, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_MANUFACTURER); + ManufacturerPtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + ManuStrLen = StrLen(ManufacturerPtr); + if (ManuStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSChassisVersion), Version); + if (StrLen (Version) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_CHASSIS_VERSION); + HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_VERSION); + VersionPtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + VerStrLen = StrLen(VersionPtr); + if (VerStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSChassisSerialNumber), SerialNumber); + if (StrLen (SerialNumber) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_CHASSIS_SERIAL_NUMBER); + HiiSetString (mHiiHandle, TokenToUpdate, SerialNumber, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_SERIAL_NUMBER); + SerialNumberPtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + SerialNumStrLen = StrLen(SerialNumberPtr); + if (SerialNumStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSChassisAssetTag), AssertTag); + if (StrLen (AssertTag) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_CHASSIS_ASSET_TAG); + HiiSetString (mHiiHandle, TokenToUpdate, AssertTag, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_ASSET_TAG); + AssertTagPtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + AssertTagStrLen = StrLen(AssertTagPtr); + if (AssertTagStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE3) + ManuStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen + 1 + 1); + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE3) + ManuStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen + 1 + 1); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE; + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE3); + // + // Make handle chosen by smbios protocol.add automatically. + // + SmbiosRecord->Hdr.Handle = 0; + // + // Manu will be the 1st optional string following the formatted structure. + // + SmbiosRecord->Manufacturer = 1; + SmbiosRecord->Type = PcdGet8 (PcdSMBIOSChassisType); + // + // Version will be the 2nd optional string following the formatted structure. + // + SmbiosRecord->Version = 2; + // + // SerialNumber will be the 3rd optional string following the formatted structure. + // + SmbiosRecord->SerialNumber = 3; + // + // AssertTag will be the 4th optional string following the formatted structure. + // + SmbiosRecord->AssetTag = 4; + SmbiosRecord->BootupState = PcdGet8 (PcdSMBIOSChassisBootupState); + SmbiosRecord->PowerSupplyState = PcdGet8 (PcdSMBIOSChassisPowerSupplyState); + SmbiosRecord->ThermalState = (UINT8)ForType3InputData->ChassisThermalState; + SmbiosRecord->SecurityStatus = PcdGet8 (PcdSMBIOSChassisSecurityState); + *(UINT32 *)&SmbiosRecord->OemDefined = PcdGet32 (PcdSMBIOSChassisOemDefined); + SmbiosRecord->Height = PcdGet8 (PcdSMBIOSChassisHeight); + SmbiosRecord->NumberofPowerCords = PcdGet8 (PcdSMBIOSChassisNumberPowerCords); + SmbiosRecord->ContainedElementCount = PcdGet8 (PcdSMBIOSChassisElementCount); + SmbiosRecord->ContainedElementRecordLength = PcdGet8 (PcdSMBIOSChassisElementRecordLength); + + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); + UnicodeStrToAsciiStr(ManufacturerPtr, OptionalStrStart); + UnicodeStrToAsciiStr(VersionPtr, OptionalStrStart + ManuStrLen + 1); + UnicodeStrToAsciiStr(SerialNumberPtr, OptionalStrStart + ManuStrLen + 1 + VerStrLen + 1); + UnicodeStrToAsciiStr(AssertTagPtr, OptionalStrStart + ManuStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1); + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios-> Add( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + + FreePool(SmbiosRecord); + return Status; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscDevicePath.h b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscDevicePath.h new file mode 100644 index 0000000000..8641e58fca --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscDevicePath.h @@ -0,0 +1,42 @@ +/** @file +Misc class required EFI Device Path definitions (Ports, slots & +onboard devices) + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#ifndef _MISC_DEVICE_PATH_H +#define _MISC_DEVICE_PATH_H + +#pragma pack(1) + +//USB +/* For reference: +#define USB1_1_STR "ACPI(PNP0A03,0)/PCI(1D,0)." +#define USB1_2_STR "ACPI(PNP0A03,0)/PCI(1D,1)." +#define USB1_3_STR "ACPI(PNP0A03,0)/PCI(1D,2)." +#define USB2_1_STR "ACPI(PNP0A03,0)/PCI(1D,7)." +*/ + +#define DP_ACPI { ACPI_DEVICE_PATH,\ + ACPI_DP, (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)),\ + (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8), EISA_PNP_ID(0x0A03), 0 } +#define DP_PCI( device,function) { HARDWARE_DEVICE_PATH,\ + HW_PCI_DP, (UINT8) (sizeof (PCI_DEVICE_PATH)),\ + (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8), function, device } +#define DP_END { END_DEVICE_PATH_TYPE, \ + END_ENTIRE_DEVICE_PATH_SUBTYPE, {END_DEVICE_PATH_LENGTH, 0 }} + +#define DP_LPC(eisaid,function ){ ACPI_DEVICE_PATH, \ +ACPI_DP,(UINT8) (sizeof (ACPI_HID_DEVICE_PATH)),\ +(UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8),EISA_PNP_ID(eisaid), function } + + +#pragma pack() + + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscNumberOfInstallableLanguagesData.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscNumberOfInstallableLanguagesData.c new file mode 100644 index 0000000000..c1c8f61447 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscNumberOfInstallableLanguagesData.c @@ -0,0 +1,28 @@ +/** @file +This driver parses the mSmbiosMiscDataTable structure and reports +any generated data to SMBIOS. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + + +#include "CommonHeader.h" + +#include "SmbiosMisc.h" + + +// +// Static (possibly build generated) Bios Vendor data. +// +MISC_SMBIOS_TABLE_DATA(EFI_MISC_NUMBER_OF_INSTALLABLE_LANGUAGES, NumberOfInstallableLanguages) = { + 2, // NumberOfInstallableLanguages + { // LanguageFlags + 0, // AbbreviatedLanguageFormat + 0 // Reserved + }, + 1, // CurrentLanguageNumber +}; diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscNumberOfInstallableLanguagesFunction.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscNumberOfInstallableLanguagesFunction.c new file mode 100644 index 0000000000..977ee57b24 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscNumberOfInstallableLanguagesFunction.c @@ -0,0 +1,240 @@ +/** @file +This driver parses the mSmbiosMiscDataTable structure and reports +any generated data. + +Copyright (c) 2013-2016 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + + +#include "CommonHeader.h" + +#include "SmbiosMisc.h" +/*++ + Check whether the language is supported for given HII handle + + @param HiiHandle The HII package list handle. + @param Offset The offest of current lanague in the supported languages. + @param CurrentLang The language code. + + @retval TRUE Supported. + @retval FALSE Not Supported. + +--*/ +BOOLEAN +EFIAPI +CurrentLanguageMatch ( + IN EFI_HII_HANDLE HiiHandle, + OUT UINT16 *Offset, + OUT CHAR8 *CurrentLang + ) +{ + CHAR8 *DefaultLang; + CHAR8 *BestLanguage; + CHAR8 *Languages; + CHAR8 *MatchLang; + CHAR8 *EndMatchLang; + UINTN CompareLength; + BOOLEAN LangMatch; + + Languages = HiiGetSupportedLanguages (HiiHandle); + if (Languages == NULL) { + return FALSE; + } + + LangMatch = FALSE; + CurrentLang = GetEfiGlobalVariable (L"PlatformLang"); + DefaultLang = (CHAR8 *) PcdGetPtr (PcdUefiVariableDefaultPlatformLang); + BestLanguage = GetBestLanguage ( + Languages, + FALSE, + (CurrentLang != NULL) ? CurrentLang : "", + DefaultLang, + NULL + ); + if (BestLanguage != NULL) { + // + // Find the best matching RFC 4646 language, compute the offset. + // + LangMatch = TRUE; + CompareLength = AsciiStrLen (BestLanguage); + for (MatchLang = Languages, (*Offset) = 0; *MatchLang != '\0'; (*Offset)++) { + // + // Seek to the end of current match language. + // + for (EndMatchLang = MatchLang; *EndMatchLang != '\0' && *EndMatchLang != ';'; EndMatchLang++); + + if ((EndMatchLang == MatchLang + CompareLength) && AsciiStrnCmp(MatchLang, BestLanguage, CompareLength) == 0) { + // + // Find the current best Language in the supported languages + // + break; + } + // + // best language match be in the supported language. + // + ASSERT (*EndMatchLang == ';'); + MatchLang = EndMatchLang + 1; + } + FreePool (BestLanguage); + } + + FreePool (Languages); + if (CurrentLang != NULL) { + FreePool (CurrentLang); + } + return LangMatch; +} + + +/** + Get next language from language code list (with separator ';'). + + @param LangCode Input: point to first language in the list. On + Otput: point to next language in the list, or + NULL if no more language in the list. + @param Lang The first language in the list. + +**/ +VOID +EFIAPI +GetNextLanguage ( + IN OUT CHAR8 **LangCode, + OUT CHAR8 *Lang + ) +{ + UINTN Index; + CHAR8 *StringPtr; + + ASSERT (LangCode != NULL); + ASSERT (*LangCode != NULL); + ASSERT (Lang != NULL); + + Index = 0; + StringPtr = *LangCode; + while (StringPtr[Index] != 0 && StringPtr[Index] != ';') { + Index++; + } + + CopyMem (Lang, StringPtr, Index); + Lang[Index] = 0; + + if (StringPtr[Index] == ';') { + Index++; + } + *LangCode = StringPtr + Index; +} + +/** + This function returns the number of supported languages on HiiHandle. + + @param HiiHandle The HII package list handle. + + @retval The number of supported languages. + +**/ +UINT16 +EFIAPI +GetSupportedLanguageNumber ( + IN EFI_HII_HANDLE HiiHandle + ) +{ + CHAR8 *Lang; + CHAR8 *Languages; + CHAR8 *LanguageString; + UINT16 LangNumber; + + Languages = HiiGetSupportedLanguages (HiiHandle); + if (Languages == NULL) { + return 0; + } + + LangNumber = 0; + Lang = AllocatePool (AsciiStrSize (Languages)); + if (Lang != NULL) { + LanguageString = Languages; + while (*LanguageString != 0) { + GetNextLanguage (&LanguageString, Lang); + LangNumber++; + } + FreePool (Lang); + } + FreePool (Languages); + return LangNumber; +} + + +/** + This function makes boot time changes to the contents of the + MiscNumberOfInstallableLanguages (Type 13). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(NumberOfInstallableLanguages) +{ + UINTN LangStrLen; + CHAR8 CurrentLang[SMBIOS_STRING_MAX_LENGTH + 1]; + CHAR8 *OptionalStrStart; + UINT16 Offset; + EFI_STATUS Status; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE13 *SmbiosRecord; + EFI_MISC_NUMBER_OF_INSTALLABLE_LANGUAGES *ForType13InputData; + + ForType13InputData = (EFI_MISC_NUMBER_OF_INSTALLABLE_LANGUAGES *)RecordData; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + ForType13InputData->NumberOfInstallableLanguages = GetSupportedLanguageNumber (mHiiHandle); + + // + // Try to check if current langcode matches with the langcodes in installed languages + // + ZeroMem(CurrentLang, SMBIOS_STRING_MAX_LENGTH + 1); + CurrentLanguageMatch (mHiiHandle, &Offset, CurrentLang); + LangStrLen = AsciiStrLen(CurrentLang); + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE13) + LangStrLen + 1 + 1); + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE13) + LangStrLen + 1 + 1); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION; + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE13); + // + // Make handle chosen by smbios protocol.add automatically. + // + SmbiosRecord->Hdr.Handle = 0; + + SmbiosRecord->InstallableLanguages = (UINT8)ForType13InputData->NumberOfInstallableLanguages; + SmbiosRecord->Flags = (UINT8)ForType13InputData->LanguageFlags.AbbreviatedLanguageFormat; + SmbiosRecord->CurrentLanguages = 1; + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); + AsciiStrCpy(OptionalStrStart, CurrentLang); + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios-> Add( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + FreePool(SmbiosRecord); + return Status; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOemString.uni b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOemString.uni new file mode 100644 index 0000000000..d039948561 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOemString.uni @@ -0,0 +1,12 @@ +// /** @file +// Unicode string used for SMBIOS type 11 record (OEM string) +// +// Copyright (c) 2013-2015 Intel Corporation. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +/=# + +#string STR_MISC_OEM_EN_US #language en-US "Intel SSG" diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOemStringData.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOemStringData.c new file mode 100644 index 0000000000..469a6321da --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOemStringData.c @@ -0,0 +1,20 @@ +/** @file +This driver parses the mMiscSubclassDataTable structure and reports +any generated data to smbios. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "CommonHeader.h" + +#include "SmbiosMisc.h" + +// +// Static (possibly build generated) OEM String data. +// +MISC_SMBIOS_TABLE_DATA(EFI_MISC_OEM_STRING, MiscOemString) += { {STRING_TOKEN(STR_MISC_OEM_EN_US) }}; diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOemStringFunction.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOemStringFunction.c new file mode 100644 index 0000000000..f3f61366fc --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOemStringFunction.c @@ -0,0 +1,78 @@ +/** @file +boot information boot time changes. +SMBIOS type 11. + +Copyright (c) 2013-2016 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "CommonHeader.h" +#include "SmbiosMisc.h" + +/** + This function makes boot time changes to the contents of the + MiscOemString (Type 11). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscOemString) +{ + UINTN OemStrLen; + CHAR8 *OptionalStrStart; + EFI_STATUS Status; + EFI_STRING OemStr; + STRING_REF TokenToGet; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE11 *SmbiosRecord; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + TokenToGet = STRING_TOKEN (STR_MISC_OEM_EN_US); + OemStr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + OemStrLen = StrLen(OemStr); + if (OemStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE11) + OemStrLen + 1 + 1); + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE11) + OemStrLen + 1 + 1); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_OEM_STRINGS; + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE11); + // + // Make handle chosen by smbios protocol.add automatically. + // + SmbiosRecord->Hdr.Handle = 0; + SmbiosRecord->StringCount = 1; + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); + UnicodeStrToAsciiStr(OemStr, OptionalStrStart); + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios-> Add( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + FreePool(SmbiosRecord); + return Status; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOnboardDevice.uni b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOnboardDevice.uni new file mode 100644 index 0000000000..c88dd9f57a --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOnboardDevice.uni @@ -0,0 +1,18 @@ +// /** @file +// Miscellaneous Onboard Device +// +// Copyright (c) 2013-2015 Intel Corporation. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// +// MiscOnboardDevice.Vfr +// +// **/ + + +/=# + +#string STR_MISC_ONBOARD_DEVICE_VIDEO #language en-US "Intel(R) Extreme Graphics 3 Controller" +#string STR_MISC_ONBOARD_DEVICE_NETWORK #language en-US "Gigabit Ethernet" +#string STR_MISC_ONBOARD_DEVICE_AUDIO #language en-US "Intel(R) High Definition Audio Device" diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOnboardDeviceData.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOnboardDeviceData.c new file mode 100644 index 0000000000..a729ad7c9a --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOnboardDeviceData.c @@ -0,0 +1,49 @@ +/** @file +This driver parses the mMiscSubclassDataTable structure and reports +any generated data to smbios. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + + +#include "CommonHeader.h" + +#include "SmbiosMisc.h" + + +// +// Static (possibly build generated) Bios Vendor data. +// +MISC_SMBIOS_TABLE_DATA(EFI_MISC_ONBOARD_DEVICE, MiscOnboardDeviceVideo) = { + STRING_TOKEN(STR_MISC_ONBOARD_DEVICE_VIDEO), // OnBoardDeviceDescription + { // OnBoardDeviceStatus + EfiOnBoardDeviceTypeVideo, // DeviceType + 1, // DeviceEnabled + 0 // Reserved + }, + {0} // OnBoardDevicePath +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_ONBOARD_DEVICE, MiscOnboardDeviceNetwork) = { + STRING_TOKEN(STR_MISC_ONBOARD_DEVICE_NETWORK), // OnBoardDeviceDescription + { // OnBoardDeviceStatus + EfiOnBoardDeviceTypeEthernet, // DeviceType + 1, // DeviceEnabled + 0 // Reserved + }, + {0} // OnBoardDevicePath +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_ONBOARD_DEVICE, MiscOnboardDeviceAudio) = { + STRING_TOKEN(STR_MISC_ONBOARD_DEVICE_AUDIO), // OnBoardDeviceDescription + { // OnBoardDeviceStatus + EfiOnBoardDeviceTypeSound, // DeviceType + 1, // DeviceEnabled + 0 // Reserved + }, + DP_END // OnBoardDevicePath +}; diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOnboardDeviceFunction.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOnboardDeviceFunction.c new file mode 100644 index 0000000000..f570184a56 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOnboardDeviceFunction.c @@ -0,0 +1,105 @@ +/** @file +Onboard device information boot time changes. +SMBIOS type 10. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + + +#include "CommonHeader.h" + +#include "SmbiosMisc.h" + + +/** + This function makes boot time changes to the contents of the + MiscOnboardDevice (Type 10). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscOnboardDevice) +{ + CHAR8 *OptionalStrStart; + UINT8 StatusAndType; + UINTN DescriptionStrLen; + EFI_STRING DeviceDescription; + STRING_REF TokenToGet; + EFI_STATUS Status; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE10 *SmbiosRecord; + EFI_MISC_ONBOARD_DEVICE *ForType10InputData; + + ForType10InputData = (EFI_MISC_ONBOARD_DEVICE *)RecordData; + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + TokenToGet = 0; + switch (ForType10InputData->OnBoardDeviceDescription) { + case STR_MISC_ONBOARD_DEVICE_VIDEO: + TokenToGet = STRING_TOKEN (STR_MISC_ONBOARD_DEVICE_VIDEO); + break; + case STR_MISC_ONBOARD_DEVICE_AUDIO: + TokenToGet = STRING_TOKEN (STR_MISC_ONBOARD_DEVICE_AUDIO); + break; + } + + DeviceDescription = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + DescriptionStrLen = StrLen(DeviceDescription); + if (DescriptionStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE10) + DescriptionStrLen + 1 + 1); + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE10) + DescriptionStrLen + 1 + 1); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION; + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE10); + // + // Make handle chosen by smbios protocol.add automatically. + // + SmbiosRecord->Hdr.Handle = 0; + + // + // Status & Type: Bit 7 Devicen Status, Bits 6:0 Type of Device + // + StatusAndType = (UINT8) ForType10InputData->OnBoardDeviceStatus.DeviceType; + if (ForType10InputData->OnBoardDeviceStatus.DeviceEnabled != 0) { + StatusAndType |= 0x80; + } else { + StatusAndType &= 0x7F; + } + + SmbiosRecord->Device[0].DeviceType = StatusAndType; + SmbiosRecord->Device[0].DescriptionString = 1; + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); + UnicodeStrToAsciiStr(DeviceDescription, OptionalStrStart); + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios-> Add( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + FreePool(SmbiosRecord); + return Status; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscPortInternalConnectorDesignator.uni b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscPortInternalConnectorDesignator.uni new file mode 100644 index 0000000000..165dcf2157 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscPortInternalConnectorDesignator.uni @@ -0,0 +1,53 @@ +// /** @file +// Miscellaneous Port Internal Connector Information +// +// Copyright (c) 2013-2015 Intel Corporation. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// +// **/ +/=# + +#string STR_MISC_PORT1_INTERNAL_DESIGN #language en-US "P1ICD" +#string STR_MISC_PORT1_EXTERNAL_DESIGN #language en-US "P1ECD" +#string STR_MISC_PORT2_INTERNAL_DESIGN #language en-US "P2ICD" +#string STR_MISC_PORT2_EXTERNAL_DESIGN #language en-US "P2ECD" +#string STR_MISC_PORT3_INTERNAL_DESIGN #language en-US "P3ICD" +#string STR_MISC_PORT3_EXTERNAL_DESIGN #language en-US "P3ECD" +#string STR_MISC_PORT4_INTERNAL_DESIGN #language en-US "P4ICD" +#string STR_MISC_PORT4_EXTERNAL_DESIGN #language en-US "P4ECD" +#string STR_MISC_PORT5_INTERNAL_DESIGN #language en-US "P5ICD" +#string STR_MISC_PORT5_EXTERNAL_DESIGN #language en-US "P5ECD" +#string STR_MISC_PORT6_INTERNAL_DESIGN #language en-US "P6ICD" +#string STR_MISC_PORT6_EXTERNAL_DESIGN #language en-US "P6ECD" +#string STR_MISC_PORT7_INTERNAL_DESIGN #language en-US "P7ICD" +#string STR_MISC_PORT7_EXTERNAL_DESIGN #language en-US "P7ECD" +#string STR_MISC_PORT8_INTERNAL_DESIGN #language en-US "P8ICD" +#string STR_MISC_PORT8_EXTERNAL_DESIGN #language en-US "P8ECD" +#string STR_MISC_PORT9_INTERNAL_DESIGN #language en-US "P9ICD" +#string STR_MISC_PORT9_EXTERNAL_DESIGN #language en-US "P9ECD" +#string STR_MISC_PORT10_INTERNAL_DESIGN #language en-US "P10ICD" +#string STR_MISC_PORT10_EXTERNAL_DESIGN #language en-US "P10ECD" +#string STR_MISC_PORT11_INTERNAL_DESIGN #language en-US "P11ICD" +#string STR_MISC_PORT11_EXTERNAL_DESIGN #language en-US "P11ECD" +#string STR_MISC_PORT12_INTERNAL_DESIGN #language en-US "P12ICD" +#string STR_MISC_PORT12_EXTERNAL_DESIGN #language en-US "P12ECD" +#string STR_MISC_PORT13_INTERNAL_DESIGN #language en-US "P13ICD" +#string STR_MISC_PORT13_EXTERNAL_DESIGN #language en-US "P13ECD" +#string STR_MISC_PORT14_INTERNAL_DESIGN #language en-US "P14ICD" +#string STR_MISC_PORT14_EXTERNAL_DESIGN #language en-US "P14ECD" +#string STR_MISC_PORT15_INTERNAL_DESIGN #language en-US "P15ICD" +#string STR_MISC_PORT15_EXTERNAL_DESIGN #language en-US "P15ECD" +#string STR_MISC_PORT16_INTERNAL_DESIGN #language en-US "P16ICD" +#string STR_MISC_PORT16_EXTERNAL_DESIGN #language en-US "P16ECD" +#string STR_MISC_PORT17_INTERNAL_DESIGN #language en-US "P17ICD" +#string STR_MISC_PORT17_EXTERNAL_DESIGN #language en-US "P17ECD" +#string STR_MISC_PORT18_INTERNAL_DESIGN #language en-US "P18ICD" +#string STR_MISC_PORT18_EXTERNAL_DESIGN #language en-US "P18ECD" +#string STR_MISC_PORT19_INTERNAL_DESIGN #language en-US "P19ICD" +#string STR_MISC_PORT19_EXTERNAL_DESIGN #language en-US "P19ECD" +#string STR_MISC_PORT20_INTERNAL_DESIGN #language en-US "P20ICD" +#string STR_MISC_PORT20_EXTERNAL_DESIGN #language en-US "P20ECD" +#string STR_MISC_PORT21_INTERNAL_DESIGN #language en-US "P21ICD" +#string STR_MISC_PORT21_EXTERNAL_DESIGN #language en-US "P21ECD" diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscPortInternalConnectorDesignatorData.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscPortInternalConnectorDesignatorData.c new file mode 100644 index 0000000000..c572288b0a --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscPortInternalConnectorDesignatorData.c @@ -0,0 +1,184 @@ +/** @file +This driver parses the mSmbiosMiscDataTable structure and reports +any generated data to the DataHub. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + + +#include "CommonHeader.h" + +#include "SmbiosMisc.h" + +// +// Static (possibly build generated) Bios Vendor data. +// +MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector1) = { + STRING_TOKEN (STR_MISC_PORT1_INTERNAL_DESIGN), // PortInternalConnectorDesignator + STRING_TOKEN (STR_MISC_PORT1_EXTERNAL_DESIGN), // PortExternalConnectorDesignator + EfiPortConnectorTypeNone, // PortInternalConnectorType + EfiPortConnectorTypePS2, // PortExternalConnectorType + EfiPortTypeKeyboard, // PortType + //mPs2KbyboardDevicePath // PortPath + {{{{0}}}} +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector2) = { + STRING_TOKEN (STR_MISC_PORT2_INTERNAL_DESIGN), // PortInternalConnectorDesignator + STRING_TOKEN (STR_MISC_PORT2_EXTERNAL_DESIGN), // PortExternalConnectorDesignator + EfiPortConnectorTypeNone, // PortInternalConnectorType + EfiPortConnectorTypePS2, // PortExternalConnectorType + EfiPortTypeMouse, // PortType + //mPs2MouseDevicePath // PortPath + {{{{0}}}} +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector3) = { + STRING_TOKEN (STR_MISC_PORT3_INTERNAL_DESIGN), + STRING_TOKEN (STR_MISC_PORT3_EXTERNAL_DESIGN), + EfiPortConnectorTypeOther, + EfiPortConnectorTypeNone, + EfiPortTypeSerial16550ACompatible, + //mCom1DevicePath + {{{{0}}}} +}; + + + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector4) = { + STRING_TOKEN (STR_MISC_PORT4_INTERNAL_DESIGN), + STRING_TOKEN (STR_MISC_PORT4_EXTERNAL_DESIGN), + EfiPortConnectorTypeNone, + EfiPortConnectorTypeRJ45, + EfiPortTypeSerial16550ACompatible, + //mCom2DevicePath + {{{{0}}}} +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector5) = { + STRING_TOKEN (STR_MISC_PORT5_INTERNAL_DESIGN), + STRING_TOKEN (STR_MISC_PORT5_EXTERNAL_DESIGN), + EfiPortConnectorTypeOther, + EfiPortConnectorTypeNone, + EfiPortTypeSerial16550ACompatible, + //mCom3DevicePath + {{{{0}}}} +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector6) = { + STRING_TOKEN (STR_MISC_PORT6_INTERNAL_DESIGN), + STRING_TOKEN (STR_MISC_PORT6_EXTERNAL_DESIGN), + EfiPortConnectorTypeNone, + EfiPortConnectorTypeRJ45, + EfiPortTypeSerial16550ACompatible, + //mCom3DevicePath + {{{{0}}}} +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector7) = { + STRING_TOKEN (STR_MISC_PORT7_INTERNAL_DESIGN), + STRING_TOKEN (STR_MISC_PORT7_EXTERNAL_DESIGN), + EfiPortConnectorTypeNone, + EfiPortConnectorTypeDB25Male, + EfiPortTypeParallelPortEcpEpp, + //mLpt1DevicePath + {{{{0}}}} +}; + + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector8) = { + STRING_TOKEN (STR_MISC_PORT8_INTERNAL_DESIGN), + STRING_TOKEN (STR_MISC_PORT8_EXTERNAL_DESIGN), + EfiPortConnectorTypeNone, + EfiPortConnectorTypeUsb, + EfiPortTypeUsb, + //mUsb0DevicePath + {{{{0}}}} +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector9) = { + STRING_TOKEN (STR_MISC_PORT9_INTERNAL_DESIGN), + STRING_TOKEN (STR_MISC_PORT9_EXTERNAL_DESIGN), + EfiPortConnectorTypeNone, + EfiPortConnectorTypeUsb, + EfiPortTypeUsb, + //mUsb1DevicePath + {{{{0}}}} +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector10) = { + STRING_TOKEN (STR_MISC_PORT10_INTERNAL_DESIGN), + STRING_TOKEN (STR_MISC_PORT10_EXTERNAL_DESIGN), + EfiPortConnectorTypeNone, + EfiPortConnectorTypeUsb, + EfiPortTypeUsb, + //mUsb2DevicePath + {{{{0}}}} +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector11) = { + STRING_TOKEN (STR_MISC_PORT11_INTERNAL_DESIGN), + STRING_TOKEN (STR_MISC_PORT11_EXTERNAL_DESIGN), + EfiPortConnectorTypeNone, + EfiPortConnectorTypeUsb, + EfiPortTypeUsb, + //mUsb3DevicePath + {{{{0}}}} +}; + + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector12) = { + STRING_TOKEN (STR_MISC_PORT12_INTERNAL_DESIGN), + STRING_TOKEN (STR_MISC_PORT12_EXTERNAL_DESIGN), + EfiPortConnectorTypeNone, + EfiPortConnectorTypeRJ45, + EfiPortTypeNetworkPort, + //mGbNicDevicePath + {{{{0}}}} +}; + + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector13) = { + STRING_TOKEN (STR_MISC_PORT13_INTERNAL_DESIGN), + STRING_TOKEN (STR_MISC_PORT13_EXTERNAL_DESIGN), + EfiPortConnectorTypeOnboardFloppy, + EfiPortConnectorTypeNone, + EfiPortTypeOther, + //mFloopyADevicePath + {{{{0}}}} +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector14) = { + STRING_TOKEN (STR_MISC_PORT14_INTERNAL_DESIGN), + STRING_TOKEN (STR_MISC_PORT14_EXTERNAL_DESIGN), + EfiPortConnectorTypeOnboardIde, + EfiPortConnectorTypeNone, + EfiPortTypeOther, + //mIdeDevicePath + {{{{0}}}} +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector15) = { + STRING_TOKEN (STR_MISC_PORT15_INTERNAL_DESIGN), + STRING_TOKEN (STR_MISC_PORT15_EXTERNAL_DESIGN), + EfiPortConnectorTypeOnboardIde, + EfiPortConnectorTypeNone, + EfiPortTypeOther, + //mSataDevicePath + {{{{0}}}} +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector16) = { + STRING_TOKEN (STR_MISC_PORT16_INTERNAL_DESIGN), + STRING_TOKEN (STR_MISC_PORT16_EXTERNAL_DESIGN), + EfiPortConnectorTypeOnboardIde, + EfiPortConnectorTypeNone, + EfiPortTypeOther, + //mSataDevicePath + {{{{0}}}} +}; + diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscPortInternalConnectorDesignatorFunction.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscPortInternalConnectorDesignatorFunction.c new file mode 100644 index 0000000000..28c05efb21 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscPortInternalConnectorDesignatorFunction.c @@ -0,0 +1,292 @@ +/** @file +Port internal connector designator information boot time changes. +SMBIOS type 8. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + + +#include "CommonHeader.h" + +#include "SmbiosMisc.h" + +//STATIC PS2_CONN_DEVICE_PATH mPs2KeyboardDevicePath = { DP_ACPI, DP_PCI( 0x1F,0x00 ),DP_LPC( 0x0303,0 ), DP_END }; +//STATIC PS2_CONN_DEVICE_PATH mPs2MouseDevicePath = { DP_ACPI, DP_PCI( 0x1F,0x00 ),DP_LPC( 0x0303,1 ), DP_END }; +//STATIC SERIAL_CONN_DEVICE_PATH mCom1DevicePath = { DP_ACPI, DP_PCI( 0x1F,0x00 ),DP_LPC( 0x0501,0 ), DP_END }; +//STATIC SERIAL_CONN_DEVICE_PATH mCom2DevicePath = { DP_ACPI, DP_PCI( 0x1F,0x00 ),DP_LPC( 0x0501,1 ), DP_END }; +//STATIC PARALLEL_CONN_DEVICE_PATH mLpt1DevicePath = { DP_ACPI, DP_PCI( 0x1F,0x00 ),DP_LPC( 0x0401,0 ), DP_END }; +//STATIC FLOOPY_CONN_DEVICE_PATH mFloopyADevicePath = { DP_ACPI, DP_PCI( 0x1F,0x00 ),DP_LPC( 0x0604,0 ), DP_END }; +//STATIC FLOOPY_CONN_DEVICE_PATH mFloopyBDevicePath = { DP_ACPI, DP_PCI( 0x1F,0x00 ),DP_LPC( 0x0604,1 ), DP_END }; +//STATIC USB_PORT_DEVICE_PATH mUsb0DevicePath = { DP_ACPI, DP_PCI( 0x1d,0x00 ), DP_END }; +//STATIC USB_PORT_DEVICE_PATH mUsb1DevicePath = { DP_ACPI, DP_PCI( 0x1d,0x01 ), DP_END }; +//STATIC USB_PORT_DEVICE_PATH mUsb2DevicePath = { DP_ACPI, DP_PCI( 0x1d,0x02 ), DP_END }; +//STATIC USB_PORT_DEVICE_PATH mUsb3DevicePath = { DP_ACPI, DP_PCI( 0x1d,0x03 ), DP_END }; +//STATIC IDE_DEVICE_PATH mIdeDevicePath = { DP_ACPI, DP_PCI( 0x1F,0x01 ), DP_END }; +//STATIC IDE_DEVICE_PATH mSata1DevicePath = { DP_ACPI, DP_PCI( 0x1F,0x02 ), DP_END }; +//STATIC GB_NIC_DEVICE_PATH mGbNicDevicePath = { DP_ACPI, DP_PCI( 0x03,0x00 ),DP_PCI( 0x1F,0x00 ),DP_PCI( 0x07,0x00 ), DP_END }; +EFI_DEVICE_PATH_PROTOCOL mEndDevicePath = DP_END; + +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector1); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector2); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector3); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector4); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector5); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector6); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector7); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector8); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector9); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector10); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector11); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector12); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector13); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector14); + + +EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR *mMiscConnectorArray[SMBIOS_PORT_CONNECTOR_MAX_NUM] = +{ + MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector1), + MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector2), + MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector3), + MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector4), + MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector5), + MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector6), + MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector7), + MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector8), + MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector9), + MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector10), + MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector11), + MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector12), + MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector13), + MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector14), +}; + +BOOLEAN PcdMiscPortIsInit = FALSE; +SMBIOS_PORT_CONNECTOR_DESIGNATOR_COFNIG SMBIOSPortConnector = {0}; + + +/** + Get Misc Port Configuration information from PCD + @param SMBIOSPortConnector Pointer to SMBIOSPortConnector table. + +**/ + +VOID +GetMiscPortConfigFromPcd () +{ + // + // Type 8 + // + SMBIOSPortConnector.SMBIOSConnectorNumber = PcdGet8 (PcdSMBIOSConnectorNumber); + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort1InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[0].PortInternalConnectorDesignator); + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort1ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[0].PortExternalConnectorDesignator); + SMBIOSPortConnector.SMBIOSPortConnector[0].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort1InternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[0].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort1ExternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[0].PortType = PcdGet8 (PcdSMBIOSPort1Type); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort2InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[1].PortInternalConnectorDesignator); + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort2ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[1].PortExternalConnectorDesignator); + SMBIOSPortConnector.SMBIOSPortConnector[1].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort2InternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[1].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort2ExternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[1].PortType = PcdGet8 (PcdSMBIOSPort2Type); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort3InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[2].PortInternalConnectorDesignator); + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort3ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[2].PortExternalConnectorDesignator); + SMBIOSPortConnector.SMBIOSPortConnector[2].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort3InternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[2].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort3ExternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[2].PortType = PcdGet8 (PcdSMBIOSPort3Type); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort4InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[3].PortInternalConnectorDesignator); + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort4ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[3].PortExternalConnectorDesignator); + SMBIOSPortConnector.SMBIOSPortConnector[3].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort4InternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[3].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort4ExternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[3].PortType = PcdGet8 (PcdSMBIOSPort4Type); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort5InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[4].PortInternalConnectorDesignator); + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort5ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[4].PortExternalConnectorDesignator); + SMBIOSPortConnector.SMBIOSPortConnector[4].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort5InternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[4].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort5ExternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[4].PortType = PcdGet8 (PcdSMBIOSPort5Type); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort6InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[5].PortInternalConnectorDesignator); + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort6ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[5].PortExternalConnectorDesignator); + SMBIOSPortConnector.SMBIOSPortConnector[5].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort6InternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[5].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort6ExternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[5].PortType = PcdGet8 (PcdSMBIOSPort6Type); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort7InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[6].PortInternalConnectorDesignator); + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort7ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[6].PortExternalConnectorDesignator); + SMBIOSPortConnector.SMBIOSPortConnector[6].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort7InternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[6].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort7ExternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[6].PortType = PcdGet8 (PcdSMBIOSPort7Type); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort8InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[7].PortInternalConnectorDesignator); + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort8ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[7].PortExternalConnectorDesignator); + SMBIOSPortConnector.SMBIOSPortConnector[7].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort8InternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[7].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort8ExternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[7].PortType = PcdGet8 (PcdSMBIOSPort8Type); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort9InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[8].PortInternalConnectorDesignator); + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort9ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[8].PortExternalConnectorDesignator); + SMBIOSPortConnector.SMBIOSPortConnector[8].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort9InternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[8].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort9ExternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[8].PortType = PcdGet8 (PcdSMBIOSPort9Type); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort10InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[9].PortInternalConnectorDesignator); + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort10ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[9].PortExternalConnectorDesignator); + SMBIOSPortConnector.SMBIOSPortConnector[9].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort10InternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[9].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort10ExternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[9].PortType = PcdGet8 (PcdSMBIOSPort10Type); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort11InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[10].PortInternalConnectorDesignator); + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort11ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[10].PortExternalConnectorDesignator); + SMBIOSPortConnector.SMBIOSPortConnector[10].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort11InternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[10].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort11ExternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[10].PortType = PcdGet8 (PcdSMBIOSPort11Type); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort12InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[11].PortInternalConnectorDesignator); + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort12ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[11].PortExternalConnectorDesignator); + SMBIOSPortConnector.SMBIOSPortConnector[11].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort12InternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[11].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort12ExternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[11].PortType = PcdGet8 (PcdSMBIOSPort12Type); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort13InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[12].PortInternalConnectorDesignator); + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort13ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[12].PortExternalConnectorDesignator); + SMBIOSPortConnector.SMBIOSPortConnector[12].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort13InternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[12].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort13ExternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[12].PortType = PcdGet8 (PcdSMBIOSPort13Type); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort14InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[13].PortInternalConnectorDesignator); + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort14ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[13].PortExternalConnectorDesignator); + SMBIOSPortConnector.SMBIOSPortConnector[13].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort14InternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[13].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort14ExternalConnectorType); + SMBIOSPortConnector.SMBIOSPortConnector[13].PortType = PcdGet8 (PcdSMBIOSPort14Type); +} +/** + This function makes boot time changes to the contents of the + MiscPortConnectorInformation (Type 8). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscPortInternalConnectorDesignator) +{ + CHAR8 *OptionalStrStart; + UINTN InternalRefStrLen; + UINTN ExternalRefStrLen; + EFI_STRING InternalRef; + EFI_STRING ExternalRef; + STRING_REF TokenForInternal; + STRING_REF TokenForExternal; + STRING_REF TokenToUpdate; + UINT8 InternalType; + UINT8 ExternalType; + UINT8 PortType; + EFI_STATUS Status; + SMBIOS_TABLE_TYPE8 *SmbiosRecord; + EFI_SMBIOS_HANDLE SmbiosHandle; + EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR *ForType8InputData; + UINT8 Index; + + ForType8InputData = (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR *)RecordData; + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + TokenForInternal = 0; + TokenForExternal = 0; + InternalType = 0; + ExternalType = 0; + PortType = 0; + + if (!PcdMiscPortIsInit) { + GetMiscPortConfigFromPcd (); + PcdMiscPortIsInit = TRUE; + } + + for (Index = 0; Index < SMBIOS_PORT_CONNECTOR_MAX_NUM; Index++) { + if (ForType8InputData->PortInternalConnectorDesignator == (mMiscConnectorArray[Index])->PortInternalConnectorDesignator) { + //DEBUG ((EFI_D_ERROR, "Found Port Connector Data %d : ", Index)); + break; + } + } + if (Index >= SMBIOSPortConnector.SMBIOSConnectorNumber) { + return EFI_SUCCESS; + } + + if (Index >= SMBIOS_PORT_CONNECTOR_MAX_NUM) { + return EFI_INVALID_PARAMETER; + } + + InternalRef = SMBIOSPortConnector.SMBIOSPortConnector[Index].PortInternalConnectorDesignator; + if (StrLen (InternalRef) > 0) { + TokenToUpdate = STRING_TOKEN ((mMiscConnectorArray[Index])->PortInternalConnectorDesignator); + HiiSetString (mHiiHandle, TokenToUpdate, InternalRef, NULL); + } + ExternalRef = SMBIOSPortConnector.SMBIOSPortConnector[Index].PortExternalConnectorDesignator; + if (StrLen (ExternalRef) > 0) { + TokenToUpdate = STRING_TOKEN ((mMiscConnectorArray[Index])->PortExternalConnectorDesignator); + HiiSetString (mHiiHandle, TokenToUpdate, ExternalRef, NULL); + } + TokenForInternal = STRING_TOKEN ((mMiscConnectorArray[Index])->PortInternalConnectorDesignator); + TokenForExternal = STRING_TOKEN ((mMiscConnectorArray[Index])->PortExternalConnectorDesignator); + InternalType = SMBIOSPortConnector.SMBIOSPortConnector[Index].PortInternalConnectorType; + ExternalType = SMBIOSPortConnector.SMBIOSPortConnector[Index].PortExternalConnectorType; + PortType = SMBIOSPortConnector.SMBIOSPortConnector[Index].PortType; + + InternalRef = HiiGetPackageString(&gEfiCallerIdGuid, TokenForInternal, NULL); + InternalRefStrLen = StrLen(InternalRef); + if (InternalRefStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + ExternalRef = HiiGetPackageString(&gEfiCallerIdGuid, TokenForExternal, NULL); + ExternalRefStrLen = StrLen(ExternalRef); + if (ExternalRefStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE8) + InternalRefStrLen + 1 + ExternalRefStrLen + 1 + 1); + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE8) + InternalRefStrLen + 1 + ExternalRefStrLen + 1 + 1); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION; + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE8); + // + // Make handle chosen by smbios protocol.add automatically. + // + SmbiosRecord->Hdr.Handle = 0; + SmbiosRecord->InternalReferenceDesignator = 1; + SmbiosRecord->InternalConnectorType = InternalType; + SmbiosRecord->ExternalReferenceDesignator = 2; + SmbiosRecord->ExternalConnectorType = ExternalType; + SmbiosRecord->PortType = PortType; + + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); + UnicodeStrToAsciiStr(InternalRef, OptionalStrStart); + UnicodeStrToAsciiStr(ExternalRef, OptionalStrStart + InternalRefStrLen + 1); + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios-> Add( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + FreePool(SmbiosRecord); + return Status; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemManufacturer.uni b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemManufacturer.uni new file mode 100644 index 0000000000..bb49db5573 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemManufacturer.uni @@ -0,0 +1,20 @@ +// /** @file +// System Manufacturer Information +// +// Copyright (c) 2013-2015 Intel Corporation. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// +// **/ + + +/=# + + +#string STR_MISC_SYSTEM_MANUFACTURER #language en-US "Intel Corp." +#string STR_MISC_SYSTEM_PRODUCT_NAME #language en-US "QUARK" +#string STR_MISC_SYSTEM_VERSION #language en-US "1.0" +#string STR_MISC_SYSTEM_SERIAL_NUMBER #language en-US "Unknown" +#string STR_MISC_SYSTEM_SKU_NUMBER #language en-US "System SKUNumber" +#string STR_MISC_SYSTEM_FAMILY #language en-US "X1000" diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemManufacturerData.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemManufacturerData.c new file mode 100644 index 0000000000..5a8b84b0ed --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemManufacturerData.c @@ -0,0 +1,32 @@ +/** @file +This driver parses the mMiscSubclassDataTable structure and reports +any generated data using smbios protocol. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + + +#include "CommonHeader.h" + +#include "SmbiosMisc.h" + + +// +// Static (possibly build generated) System Manufacturer data. +// +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_MANUFACTURER, MiscSystemManufacturer) = { + STRING_TOKEN(STR_MISC_SYSTEM_MANUFACTURER), // SystemManufactrurer + STRING_TOKEN(STR_MISC_SYSTEM_PRODUCT_NAME), // SystemProductName + STRING_TOKEN(STR_MISC_SYSTEM_VERSION), // SystemVersion + STRING_TOKEN(STR_MISC_SYSTEM_SERIAL_NUMBER), // SystemSerialNumber + { // SystemUuid + 0x13ffef23, 0x8654, 0x46da, {0xa4, 0x7, 0x39, 0xc9, 0x12, 0x2, 0xd3, 0x56} + }, + EfiSystemWakeupTypePowerSwitch, // SystemWakeupType + STRING_TOKEN(STR_MISC_SYSTEM_SKU_NUMBER), // SystemSKUNumber + STRING_TOKEN(STR_MISC_SYSTEM_FAMILY), // SystemFamily +}; diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemManufacturerFunction.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemManufacturerFunction.c new file mode 100644 index 0000000000..d7658f3d7c --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemManufacturerFunction.c @@ -0,0 +1,198 @@ +/** @file +This driver parses the mMiscSubclassDataTable structure and reports +any generated data to smbios. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + + +#include "CommonHeader.h" + +#include "SmbiosMisc.h" + +/** + This function makes boot time changes to the contents of the + MiscSystemManufacturer (Type 1). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer) +{ + CHAR8 *OptionalStrStart; + UINTN ManuStrLen; + UINTN VerStrLen; + UINTN PdNameStrLen; + UINTN SerialNumStrLen; + UINTN SKUNumStrLen; + UINTN FamilyStrLen; + EFI_STATUS Status; + CHAR16 Manufacturer[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 ProductName[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 Version[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 SerialNumber[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 SKUNumber[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 Family[SMBIOS_STRING_MAX_LENGTH]; + EFI_STRING ManufacturerPtr; + EFI_STRING ProductNamePtr; + EFI_STRING VersionPtr; + EFI_STRING SerialNumberPtr; + EFI_STRING SKUNumberPtr; + EFI_STRING FamilyPtr; + STRING_REF TokenToGet; + STRING_REF TokenToUpdate; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE1 *SmbiosRecord; + EFI_MISC_SYSTEM_MANUFACTURER *ForType1InputData; + + ForType1InputData = (EFI_MISC_SYSTEM_MANUFACTURER *)RecordData; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Update strings from PCD + // + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemManufacturer), Manufacturer); + if (StrLen (Manufacturer) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER); + HiiSetString (mHiiHandle, TokenToUpdate, Manufacturer, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER); + ManufacturerPtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + ManuStrLen = StrLen(ManufacturerPtr); + if (ManuStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemProductName), ProductName); + if (StrLen (ProductName) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME); + HiiSetString (mHiiHandle, TokenToUpdate, ProductName, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME); + ProductNamePtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + PdNameStrLen = StrLen(ProductNamePtr); + if (PdNameStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemVersion), Version); + if (StrLen (Version) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_VERSION); + HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_VERSION); + VersionPtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + VerStrLen = StrLen(VersionPtr); + if (VerStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSerialNumber), SerialNumber); + if (StrLen (SerialNumber) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER); + HiiSetString (mHiiHandle, TokenToUpdate, SerialNumber, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER); + SerialNumberPtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + SerialNumStrLen = StrLen(SerialNumberPtr); + if (SerialNumStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSKUNumber), SKUNumber); + if (StrLen (SKUNumber) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_SKU_NUMBER); + HiiSetString (mHiiHandle, TokenToUpdate, SKUNumber, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SKU_NUMBER); + SKUNumberPtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + SKUNumStrLen = StrLen(SKUNumberPtr); + if (SKUNumStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemFamily), Family); + if (StrLen (Family) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_FAMILY); + HiiSetString (mHiiHandle, TokenToUpdate, Family, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_FAMILY); + FamilyPtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + FamilyStrLen = StrLen(FamilyPtr); + if (FamilyStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE1) + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + SKUNumStrLen + 1 + FamilyStrLen + 1 + 1); + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE1) + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + SKUNumStrLen + 1 + FamilyStrLen + 1 + 1); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_INFORMATION; + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE1); + // + // Make handle chosen by smbios protocol.add automatically. + // + SmbiosRecord->Hdr.Handle = 0; + // + // Manu will be the 1st optional string following the formatted structure. + // + SmbiosRecord->Manufacturer = 1; + // + // ProductName will be the 2nd optional string following the formatted structure. + // + SmbiosRecord->ProductName = 2; + // + // Version will be the 3rd optional string following the formatted structure. + // + SmbiosRecord->Version = 3; + // + // Serial number will be the 4th optional string following the formatted structure. + // + SmbiosRecord->SerialNumber = 4; + // + // SKU number will be the 5th optional string following the formatted structure. + // + SmbiosRecord->SKUNumber = 5; + // + // Family will be the 6th optional string following the formatted structure. + // + SmbiosRecord->Family = 6; + CopyMem ((UINT8 *) (&SmbiosRecord->Uuid), (UINT8 *)PcdGetPtr(PcdSMBIOSSystemUuid),16); + SmbiosRecord->WakeUpType = (UINT8)ForType1InputData->SystemWakeupType; + + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); + UnicodeStrToAsciiStr(ManufacturerPtr, OptionalStrStart); + UnicodeStrToAsciiStr(ProductNamePtr, OptionalStrStart + ManuStrLen + 1); + UnicodeStrToAsciiStr(VersionPtr, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1); + UnicodeStrToAsciiStr(SerialNumberPtr, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1); + UnicodeStrToAsciiStr(SKUNumberPtr, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen+ 1); + UnicodeStrToAsciiStr(FamilyPtr, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + SKUNumStrLen+ 1); + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios-> Add( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + FreePool(SmbiosRecord); + return Status; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemOptionString.uni b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemOptionString.uni new file mode 100644 index 0000000000..aa5bb6fb65 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemOptionString.uni @@ -0,0 +1,14 @@ +// /** @file +// Miscellaneous System Option Strings +// +// Copyright (c) 2013-2015 Intel Corporation. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// +// **/ + + +/=# + +#string STR_MISC_SYSTEM_OPTION_STRING #language en-US "J1D4:1-2,5-6,9-10Default;2-3CMOS clr,6-7Pswd clr,10-11Recovery" diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemOptionStringData.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemOptionStringData.c new file mode 100644 index 0000000000..5e6682ec7c --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemOptionStringData.c @@ -0,0 +1,23 @@ +/** @file +This driver parses the mSmbiosMiscDataTable structure and reports +any generated data to smbios. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + + +#include "CommonHeader.h" + +#include "SmbiosMisc.h" + + +// +// Static (possibly build generated) Bios Vendor data. +// +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_OPTION_STRING, SystemOptionString) = { + {STRING_TOKEN (STR_MISC_SYSTEM_OPTION_STRING)} +}; diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemOptionStringFunction.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemOptionStringFunction.c new file mode 100644 index 0000000000..a32765f836 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemOptionStringFunction.c @@ -0,0 +1,81 @@ +/** @file +BIOS system option string boot time changes. +SMBIOS type 12. + +Copyright (c) 2013-2016 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + + +#include "CommonHeader.h" +#include "SmbiosMisc.h" + + +/** + This function makes boot time changes to the contents of the + MiscSystemOptionString (Type 12). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(SystemOptionString) +{ + CHAR8 *OptionalStrStart; + UINTN OptStrLen; + EFI_STRING OptionString; + EFI_STATUS Status; + STRING_REF TokenToGet; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE12 *SmbiosRecord; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_OPTION_STRING); + OptionString = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + OptStrLen = StrLen(OptionString); + if (OptStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE12) + OptStrLen + 1 + 1); + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE12) + OptStrLen + 1 + 1); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS; + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE12); + // + // Make handle chosen by smbios protocol.add automatically. + // + SmbiosRecord->Hdr.Handle = 0; + + SmbiosRecord->StringCount = 1; + OptionalStrStart = (CHAR8*) (SmbiosRecord + 1); + UnicodeStrToAsciiStr(OptionString, OptionalStrStart); + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios-> Add( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + + FreePool(SmbiosRecord); + return Status; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemSlotDesignation.uni b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemSlotDesignation.uni new file mode 100644 index 0000000000..e7639c9f36 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemSlotDesignation.uni @@ -0,0 +1,27 @@ +// /** @file +// Miscellaneous Port Connector Information +// +// Copyright (c) 2013-2015 Intel Corporation. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// +// **/ + + +/=# + +#string STR_MISC_SYSTEM_SLOT1 #language en-US "SLOT1" +#string STR_MISC_SYSTEM_SLOT2 #language en-US "SLOT2" +#string STR_MISC_SYSTEM_SLOT3 #language en-US "SLOT3" +#string STR_MISC_SYSTEM_SLOT4 #language en-US "SLOT4" +#string STR_MISC_SYSTEM_SLOT5 #language en-US "SLOT5" +#string STR_MISC_SYSTEM_SLOT6 #language en-US "SLOT6" +#string STR_MISC_SYSTEM_SLOT7 #language en-US "SLOT7" +#string STR_MISC_SYSTEM_SLOT8 #language en-US "SLOT8" +#string STR_MISC_SYSTEM_SLOT9 #language en-US "SLOT9" +#string STR_MISC_SYSTEM_SLOT10 #language en-US "SLOT10" +#string STR_MISC_SYSTEM_SLOT11 #language en-US "SLOT11" +#string STR_MISC_SYSTEM_SLOT12 #language en-US "SLOT12" +#string STR_MISC_SYSTEM_SLOT13 #language en-US "SLOT13" +#string STR_MISC_SYSTEM_SLOT14 #language en-US "SLOT14" diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemSlotDesignationData.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemSlotDesignationData.c new file mode 100644 index 0000000000..e60f1f8dfa --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemSlotDesignationData.c @@ -0,0 +1,357 @@ +/** @file +This driver parses the mMiscSubclassDataTable structure and reports +any generated data to the DataHub. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + + +#include "CommonHeader.h" + +#include "SmbiosMisc.h" + + +// +// Static (possibly build generated) Bios Vendor data. +// +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot1) = { + STRING_TOKEN(STR_MISC_SYSTEM_SLOT1), // SlotDesignation + EfiSlotTypePci, // SlotType + EfiSlotDataBusWidth32Bit, // SlotDataBusWidth + EfiSlotUsageAvailable, // SlotUsage + EfiSlotLengthLong , // SlotLength + 1, // SlotId + { // SlotCharacteristics + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 1, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0, // ModemRingResumeSupported:1; + 1, // PmeSignalSupported :1; + 0, // HotPlugDevicesSupported :1; + 1, // SmbusSignalSupported :1; + 0 // Reserved :21; + }, + {0} // SlotDevicePath +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot2) = { + STRING_TOKEN(STR_MISC_SYSTEM_SLOT2), // SlotDesignation + EfiSlotTypePciExpress, // SlotType + EfiSlotDataBusWidth32Bit, // SlotDataBusWidth + EfiSlotUsageAvailable, // SlotUsage + EfiSlotLengthLong , // SlotLength + 1, // SlotId + { // SlotCharacteristics + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 1, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0, // ModemRingResumeSupported:1; + 1, // PmeSignalSupported :1; + 1, // HotPlugDevicesSupported :1; + 1, // SmbusSignalSupported :1; + 0 // Reserved :21; + }, + {0} // SlotDevicePath +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot3) = { + STRING_TOKEN(STR_MISC_SYSTEM_SLOT3), // SlotDesignation + EfiSlotTypePciExpress, // SlotType + EfiSlotDataBusWidth32Bit, // SlotDataBusWidth + EfiSlotUsageAvailable, // SlotUsage + EfiSlotLengthLong , // SlotLength + 2, // SlotId + { // SlotCharacteristics + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 1, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0, // ModemRingResumeSupported:1; + 1, // PmeSignalSupported :1; + 1, // HotPlugDevicesSupported :1; + 1, // SmbusSignalSupported :1; + 0 // Reserved :21; + }, + {0} // SlotDevicePath +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot4) = { + STRING_TOKEN(STR_MISC_SYSTEM_SLOT4), // SlotDesignation + EfiSlotTypePciExpress, // SlotType + EfiSlotDataBusWidth32Bit, // SlotDataBusWidth + EfiSlotUsageAvailable, // SlotUsage + EfiSlotLengthLong , // SlotLength + 2, // SlotId + { // SlotCharacteristics + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 1, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0, // ModemRingResumeSupported:1; + 1, // PmeSignalSupported :1; + 1, // HotPlugDevicesSupported :1; + 1, // SmbusSignalSupported :1; + 0 // Reserved :21; + }, + {0} // SlotDevicePath +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot5) = { + STRING_TOKEN(STR_MISC_SYSTEM_SLOT5), // SlotDesignation + EfiSlotTypePciExpress, // SlotType + EfiSlotDataBusWidth32Bit, // SlotDataBusWidth + EfiSlotUsageAvailable, // SlotUsage + EfiSlotLengthLong , // SlotLength + 3, // SlotId + { // SlotCharacteristics + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 1, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0, // ModemRingResumeSupported:1; + 1, // PmeSignalSupported :1; + 1, // HotPlugDevicesSupported :1; + 1, // SmbusSignalSupported :1; + 0 // Reserved :21; + }, + {0} // SlotDevicePath +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot6) = { + STRING_TOKEN(STR_MISC_SYSTEM_SLOT6), // SlotDesignation + EfiSlotTypePciExpress, // SlotType + EfiSlotDataBusWidth32Bit, // SlotDataBusWidth + EfiSlotUsageAvailable, // SlotUsage + EfiSlotLengthLong , // SlotLength + 3, // SlotId + { // SlotCharacteristics + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 1, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0, // ModemRingResumeSupported:1; + 1, // PmeSignalSupported :1; + 1, // HotPlugDevicesSupported :1; + 1, // SmbusSignalSupported :1; + 0 // Reserved :21; + }, + {0} // SlotDevicePath +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot7) = { + STRING_TOKEN(STR_MISC_SYSTEM_SLOT7), // SlotDesignation + EfiSlotTypePciExpress, // SlotType + EfiSlotDataBusWidth32Bit, // SlotDataBusWidth + EfiSlotUsageAvailable, // SlotUsage + EfiSlotLengthLong , // SlotLength + 3, // SlotId + { // SlotCharacteristics + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 1, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0, // ModemRingResumeSupported:1; + 1, // PmeSignalSupported :1; + 1, // HotPlugDevicesSupported :1; + 1, // SmbusSignalSupported :1; + 0 // Reserved :21; + }, + {0} // SlotDevicePath +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot8) = { + STRING_TOKEN(STR_MISC_SYSTEM_SLOT8), // SlotDesignation + EfiSlotTypePciExpress, // SlotType + EfiSlotDataBusWidth32Bit, // SlotDataBusWidth + EfiSlotUsageAvailable, // SlotUsage + EfiSlotLengthLong , // SlotLength + 3, // SlotId + { // SlotCharacteristics + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 1, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0, // ModemRingResumeSupported:1; + 1, // PmeSignalSupported :1; + 1, // HotPlugDevicesSupported :1; + 1, // SmbusSignalSupported :1; + 0 // Reserved :21; + }, + {0} // SlotDevicePath +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot9) = { + STRING_TOKEN(STR_MISC_SYSTEM_SLOT9), // SlotDesignation + EfiSlotTypeUnknown, // SlotType + EfiSlotDataBusWidthUnknown, // SlotDataBusWidth + EfiSlotUsageUnknown, // SlotUsage + EfiSlotLengthUnknown , // SlotLength + 0, // SlotId + { // SlotCharacteristics + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 1, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0, // ModemRingResumeSupported:1; + 1, // PmeSignalSupported :1; + 1, // HotPlugDevicesSupported :1; + 1, // SmbusSignalSupported :1; + 0 // Reserved :21; + }, + {0} // SlotDevicePath +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot10) = { + STRING_TOKEN(STR_MISC_SYSTEM_SLOT10), // SlotDesignation + EfiSlotTypeUnknown, // SlotType + EfiSlotDataBusWidthUnknown, // SlotDataBusWidth + EfiSlotUsageUnknown, // SlotUsage + EfiSlotLengthUnknown , // SlotLength + 0, // SlotId + { // SlotCharacteristics + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 1, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0, // ModemRingResumeSupported:1; + 1, // PmeSignalSupported :1; + 1, // HotPlugDevicesSupported :1; + 1, // SmbusSignalSupported :1; + 0 // Reserved :21; + }, + {0} // SlotDevicePath +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot11) = { + STRING_TOKEN(STR_MISC_SYSTEM_SLOT11), // SlotDesignation + EfiSlotTypeUnknown, // SlotType + EfiSlotDataBusWidthUnknown, // SlotDataBusWidth + EfiSlotUsageUnknown, // SlotUsage + EfiSlotLengthUnknown , // SlotLength + 0, // SlotId + { // SlotCharacteristics + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 1, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0, // ModemRingResumeSupported:1; + 1, // PmeSignalSupported :1; + 1, // HotPlugDevicesSupported :1; + 1, // SmbusSignalSupported :1; + 0 // Reserved :21; + }, + {0} // SlotDevicePath +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot12) = { + STRING_TOKEN(STR_MISC_SYSTEM_SLOT12), // SlotDesignation + EfiSlotTypeUnknown, // SlotType + EfiSlotDataBusWidthUnknown, // SlotDataBusWidth + EfiSlotUsageUnknown, // SlotUsage + EfiSlotLengthUnknown , // SlotLength + 0, // SlotId + { // SlotCharacteristics + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 1, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0, // ModemRingResumeSupported:1; + 1, // PmeSignalSupported :1; + 1, // HotPlugDevicesSupported :1; + 1, // SmbusSignalSupported :1; + 0 // Reserved :21; + }, + {0} // SlotDevicePath +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot13) = { + STRING_TOKEN(STR_MISC_SYSTEM_SLOT13), // SlotDesignation + EfiSlotTypeUnknown, // SlotType + EfiSlotDataBusWidthUnknown, // SlotDataBusWidth + EfiSlotUsageUnknown, // SlotUsage + EfiSlotLengthUnknown , // SlotLength + 0, // SlotId + { // SlotCharacteristics + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 1, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0, // ModemRingResumeSupported:1; + 1, // PmeSignalSupported :1; + 1, // HotPlugDevicesSupported :1; + 1, // SmbusSignalSupported :1; + 0 // Reserved :21; + }, + {0} // SlotDevicePath +}; + +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot14) = { + STRING_TOKEN(STR_MISC_SYSTEM_SLOT14), // SlotDesignation + EfiSlotTypeUnknown, // SlotType + EfiSlotDataBusWidthUnknown, // SlotDataBusWidth + EfiSlotUsageUnknown, // SlotUsage + EfiSlotLengthUnknown , // SlotLength + 0, // SlotId + { // SlotCharacteristics + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 1, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0, // ModemRingResumeSupported:1; + 1, // PmeSignalSupported :1; + 1, // HotPlugDevicesSupported :1; + 1, // SmbusSignalSupported :1; + 0 // Reserved :21; + }, + {0} // SlotDevicePath +}; + + diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemSlotDesignationFunction.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemSlotDesignationFunction.c new file mode 100644 index 0000000000..6a7348e3df --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemSlotDesignationFunction.c @@ -0,0 +1,285 @@ +/** @file +BIOS system slot designator information boot time changes. +SMBIOS type 9. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +MiscSystemSlotDesignatorFunction.c + +**/ + + +#include "CommonHeader.h" + +#include "SmbiosMisc.h" + +// +// +// + +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot1); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot2); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot3); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot4); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot5); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot6); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot7); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot8); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot9); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot10); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot11); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot12); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot13); +MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot14); + +EFI_MISC_SYSTEM_SLOT_DESIGNATION *mMiscSlotArray[SMBIOS_SYSTEM_SLOT_MAX_NUM] = +{ + MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot1), + MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot2), + MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot3), + MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot4), + MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot5), + MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot6), + MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot7), + MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot8), + MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot9), + MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot10), + MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot11), + MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot12), + MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot13), + MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot14), +}; + +BOOLEAN PcdMiscSlotIsInit = FALSE; +SMBIOS_SLOT_COFNIG SMBIOSlotConfig = {0}; + +/** + Get Misc Slot Configuration information from PCD + @param SMBIOSPortConnector Pointer to SMBIOSPortConnector table. + +**/ + +VOID +GetMiscSLotConfigFromPcd () +{ + // + // Type 9 + // + SMBIOSlotConfig.SMBIOSSystemSlotNumber = PcdGet8 (PcdSMBIOSSystemSlotNumber); + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot1Designation), SMBIOSlotConfig.SMBIOSSystemSlot[0].SlotDesignation); + SMBIOSlotConfig.SMBIOSSystemSlot[0].SlotType = PcdGet8(PcdSMBIOSSystemSlot1Type); + SMBIOSlotConfig.SMBIOSSystemSlot[0].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot1DataBusWidth); + SMBIOSlotConfig.SMBIOSSystemSlot[0].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot1Usage); + SMBIOSlotConfig.SMBIOSSystemSlot[0].SlotLength = PcdGet8(PcdSMBIOSSystemSlot1Length); + SMBIOSlotConfig.SMBIOSSystemSlot[0].SlotId = PcdGet16(PcdSMBIOSSystemSlot1Id); + SMBIOSlotConfig.SMBIOSSystemSlot[0].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot1Characteristics); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot2Designation), SMBIOSlotConfig.SMBIOSSystemSlot[1].SlotDesignation); + SMBIOSlotConfig.SMBIOSSystemSlot[1].SlotType = PcdGet8(PcdSMBIOSSystemSlot2Type); + SMBIOSlotConfig.SMBIOSSystemSlot[1].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot2DataBusWidth); + SMBIOSlotConfig.SMBIOSSystemSlot[1].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot2Usage); + SMBIOSlotConfig.SMBIOSSystemSlot[1].SlotLength = PcdGet8(PcdSMBIOSSystemSlot2Length); + SMBIOSlotConfig.SMBIOSSystemSlot[1].SlotId = PcdGet16(PcdSMBIOSSystemSlot2Id); + SMBIOSlotConfig.SMBIOSSystemSlot[1].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot2Characteristics); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot3Designation), SMBIOSlotConfig.SMBIOSSystemSlot[2].SlotDesignation); + SMBIOSlotConfig.SMBIOSSystemSlot[2].SlotType = PcdGet8(PcdSMBIOSSystemSlot3Type); + SMBIOSlotConfig.SMBIOSSystemSlot[2].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot3DataBusWidth); + SMBIOSlotConfig.SMBIOSSystemSlot[2].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot3Usage); + SMBIOSlotConfig.SMBIOSSystemSlot[2].SlotLength = PcdGet8(PcdSMBIOSSystemSlot3Length); + SMBIOSlotConfig.SMBIOSSystemSlot[2].SlotId = PcdGet16(PcdSMBIOSSystemSlot3Id); + SMBIOSlotConfig.SMBIOSSystemSlot[2].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot3Characteristics); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot4Designation), SMBIOSlotConfig.SMBIOSSystemSlot[3].SlotDesignation); + SMBIOSlotConfig.SMBIOSSystemSlot[3].SlotType = PcdGet8(PcdSMBIOSSystemSlot4Type); + SMBIOSlotConfig.SMBIOSSystemSlot[3].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot4DataBusWidth); + SMBIOSlotConfig.SMBIOSSystemSlot[3].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot4Usage); + SMBIOSlotConfig.SMBIOSSystemSlot[3].SlotLength = PcdGet8(PcdSMBIOSSystemSlot4Length); + SMBIOSlotConfig.SMBIOSSystemSlot[3].SlotId = PcdGet16(PcdSMBIOSSystemSlot4Id); + SMBIOSlotConfig.SMBIOSSystemSlot[3].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot4Characteristics); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot5Designation), SMBIOSlotConfig.SMBIOSSystemSlot[4].SlotDesignation); + SMBIOSlotConfig.SMBIOSSystemSlot[4].SlotType = PcdGet8(PcdSMBIOSSystemSlot5Type); + SMBIOSlotConfig.SMBIOSSystemSlot[4].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot5DataBusWidth); + SMBIOSlotConfig.SMBIOSSystemSlot[4].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot5Usage); + SMBIOSlotConfig.SMBIOSSystemSlot[4].SlotLength = PcdGet8(PcdSMBIOSSystemSlot5Length); + SMBIOSlotConfig.SMBIOSSystemSlot[4].SlotId = PcdGet16(PcdSMBIOSSystemSlot5Id); + SMBIOSlotConfig.SMBIOSSystemSlot[4].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot5Characteristics); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot6Designation), SMBIOSlotConfig.SMBIOSSystemSlot[5].SlotDesignation); + SMBIOSlotConfig.SMBIOSSystemSlot[5].SlotType = PcdGet8(PcdSMBIOSSystemSlot6Type); + SMBIOSlotConfig.SMBIOSSystemSlot[5].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot6DataBusWidth); + SMBIOSlotConfig.SMBIOSSystemSlot[5].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot6Usage); + SMBIOSlotConfig.SMBIOSSystemSlot[5].SlotLength = PcdGet8(PcdSMBIOSSystemSlot6Length); + SMBIOSlotConfig.SMBIOSSystemSlot[5].SlotId = PcdGet16(PcdSMBIOSSystemSlot6Id); + SMBIOSlotConfig.SMBIOSSystemSlot[5].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot6Characteristics); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot7Designation), SMBIOSlotConfig.SMBIOSSystemSlot[6].SlotDesignation); + SMBIOSlotConfig.SMBIOSSystemSlot[6].SlotType = PcdGet8(PcdSMBIOSSystemSlot7Type); + SMBIOSlotConfig.SMBIOSSystemSlot[6].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot7DataBusWidth); + SMBIOSlotConfig.SMBIOSSystemSlot[6].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot7Usage); + SMBIOSlotConfig.SMBIOSSystemSlot[6].SlotLength = PcdGet8(PcdSMBIOSSystemSlot7Length); + SMBIOSlotConfig.SMBIOSSystemSlot[6].SlotId = PcdGet16(PcdSMBIOSSystemSlot7Id); + SMBIOSlotConfig.SMBIOSSystemSlot[6].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot7Characteristics); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot8Designation), SMBIOSlotConfig.SMBIOSSystemSlot[7].SlotDesignation); + SMBIOSlotConfig.SMBIOSSystemSlot[7].SlotType = PcdGet8(PcdSMBIOSSystemSlot8Type); + SMBIOSlotConfig.SMBIOSSystemSlot[7].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot8DataBusWidth); + SMBIOSlotConfig.SMBIOSSystemSlot[7].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot8Usage); + SMBIOSlotConfig.SMBIOSSystemSlot[7].SlotLength = PcdGet8(PcdSMBIOSSystemSlot8Length); + SMBIOSlotConfig.SMBIOSSystemSlot[7].SlotId = PcdGet16(PcdSMBIOSSystemSlot8Id); + SMBIOSlotConfig.SMBIOSSystemSlot[7].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot8Characteristics); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot9Designation), SMBIOSlotConfig.SMBIOSSystemSlot[8].SlotDesignation); + SMBIOSlotConfig.SMBIOSSystemSlot[8].SlotType = PcdGet8(PcdSMBIOSSystemSlot9Type); + SMBIOSlotConfig.SMBIOSSystemSlot[8].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot9DataBusWidth); + SMBIOSlotConfig.SMBIOSSystemSlot[8].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot9Usage); + SMBIOSlotConfig.SMBIOSSystemSlot[8].SlotLength = PcdGet8(PcdSMBIOSSystemSlot9Length); + SMBIOSlotConfig.SMBIOSSystemSlot[8].SlotId = PcdGet16(PcdSMBIOSSystemSlot9Id); + SMBIOSlotConfig.SMBIOSSystemSlot[8].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot9Characteristics); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot10Designation), SMBIOSlotConfig.SMBIOSSystemSlot[9].SlotDesignation); + SMBIOSlotConfig.SMBIOSSystemSlot[9].SlotType = PcdGet8(PcdSMBIOSSystemSlot10Type); + SMBIOSlotConfig.SMBIOSSystemSlot[9].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot10DataBusWidth); + SMBIOSlotConfig.SMBIOSSystemSlot[9].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot10Usage); + SMBIOSlotConfig.SMBIOSSystemSlot[9].SlotLength = PcdGet8(PcdSMBIOSSystemSlot10Length); + SMBIOSlotConfig.SMBIOSSystemSlot[9].SlotId = PcdGet16(PcdSMBIOSSystemSlot10Id); + SMBIOSlotConfig.SMBIOSSystemSlot[9].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot10Characteristics); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot11Designation), SMBIOSlotConfig.SMBIOSSystemSlot[10].SlotDesignation); + SMBIOSlotConfig.SMBIOSSystemSlot[10].SlotType = PcdGet8(PcdSMBIOSSystemSlot11Type); + SMBIOSlotConfig.SMBIOSSystemSlot[10].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot11DataBusWidth); + SMBIOSlotConfig.SMBIOSSystemSlot[10].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot11Usage); + SMBIOSlotConfig.SMBIOSSystemSlot[10].SlotLength = PcdGet8(PcdSMBIOSSystemSlot11Length); + SMBIOSlotConfig.SMBIOSSystemSlot[10].SlotId = PcdGet16(PcdSMBIOSSystemSlot11Id); + SMBIOSlotConfig.SMBIOSSystemSlot[10].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot11Characteristics); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot12Designation), SMBIOSlotConfig.SMBIOSSystemSlot[11].SlotDesignation); + SMBIOSlotConfig.SMBIOSSystemSlot[11].SlotType = PcdGet8(PcdSMBIOSSystemSlot12Type); + SMBIOSlotConfig.SMBIOSSystemSlot[11].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot12DataBusWidth); + SMBIOSlotConfig.SMBIOSSystemSlot[11].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot12Usage); + SMBIOSlotConfig.SMBIOSSystemSlot[11].SlotLength = PcdGet8(PcdSMBIOSSystemSlot12Length); + SMBIOSlotConfig.SMBIOSSystemSlot[11].SlotId = PcdGet16(PcdSMBIOSSystemSlot12Id); + SMBIOSlotConfig.SMBIOSSystemSlot[11].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot12Characteristics); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot13Designation), SMBIOSlotConfig.SMBIOSSystemSlot[12].SlotDesignation); + SMBIOSlotConfig.SMBIOSSystemSlot[12].SlotType = PcdGet8(PcdSMBIOSSystemSlot13Type); + SMBIOSlotConfig.SMBIOSSystemSlot[12].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot13DataBusWidth); + SMBIOSlotConfig.SMBIOSSystemSlot[12].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot13Usage); + SMBIOSlotConfig.SMBIOSSystemSlot[12].SlotLength = PcdGet8(PcdSMBIOSSystemSlot13Length); + SMBIOSlotConfig.SMBIOSSystemSlot[12].SlotId = PcdGet16(PcdSMBIOSSystemSlot13Id); + SMBIOSlotConfig.SMBIOSSystemSlot[12].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot13Characteristics); + + AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot14Designation), SMBIOSlotConfig.SMBIOSSystemSlot[13].SlotDesignation); + SMBIOSlotConfig.SMBIOSSystemSlot[13].SlotType = PcdGet8(PcdSMBIOSSystemSlot14Type); + SMBIOSlotConfig.SMBIOSSystemSlot[13].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot14DataBusWidth); + SMBIOSlotConfig.SMBIOSSystemSlot[13].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot14Usage); + SMBIOSlotConfig.SMBIOSSystemSlot[13].SlotLength = PcdGet8(PcdSMBIOSSystemSlot14Length); + SMBIOSlotConfig.SMBIOSSystemSlot[13].SlotId = PcdGet16(PcdSMBIOSSystemSlot14Id); + SMBIOSlotConfig.SMBIOSSystemSlot[13].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot14Characteristics); +} +/** + This function makes boot time changes to the contents of the + MiscSystemSlotDesignator structure (Type 9). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscSystemSlotDesignator) +{ + CHAR8 *OptionalStrStart; + UINTN SlotDesignationStrLen; + EFI_STATUS Status; + EFI_STRING SlotDesignation; + STRING_REF TokenToUpdate; + STRING_REF TokenToGet; + SMBIOS_TABLE_TYPE9 *SmbiosRecord; + EFI_SMBIOS_HANDLE SmbiosHandle; + EFI_MISC_SYSTEM_SLOT_DESIGNATION* ForType9InputData; + UINT8 Index; + + ForType9InputData = (EFI_MISC_SYSTEM_SLOT_DESIGNATION *)RecordData; + + TokenToGet = 0; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (!PcdMiscSlotIsInit) { + GetMiscSLotConfigFromPcd (); + PcdMiscSlotIsInit = TRUE; + } + + for (Index = 0; Index < SMBIOS_SYSTEM_SLOT_MAX_NUM; Index++) { + if (ForType9InputData->SlotDesignation == (mMiscSlotArray[Index])->SlotDesignation) { + //DEBUG ((EFI_D_ERROR, "Found slot Data %d : ", Index)); + break; + } + } + if (Index >= SMBIOSlotConfig.SMBIOSSystemSlotNumber) { + return EFI_SUCCESS; + } + + if (Index >= SMBIOS_SYSTEM_SLOT_MAX_NUM) { + return EFI_INVALID_PARAMETER; + } + + SlotDesignation = SMBIOSlotConfig.SMBIOSSystemSlot[Index].SlotDesignation; + TokenToGet = STRING_TOKEN ((mMiscSlotArray[Index])->SlotDesignation); + + if (StrLen (SlotDesignation) > 0) { + TokenToUpdate = STRING_TOKEN ((mMiscSlotArray[Index])->SlotDesignation); + HiiSetString (mHiiHandle, TokenToUpdate, SlotDesignation, NULL); + } + + SlotDesignation = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); + SlotDesignationStrLen = StrLen(SlotDesignation); + if (SlotDesignationStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE9) + SlotDesignationStrLen + 1 + 1); + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE9) +SlotDesignationStrLen + 1 + 1); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_SLOTS; + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE9); + SmbiosRecord->Hdr.Handle = 0; + SmbiosRecord->SlotDesignation = 1; + SmbiosRecord->SlotType = SMBIOSlotConfig.SMBIOSSystemSlot[Index].SlotType; + SmbiosRecord->SlotDataBusWidth = SMBIOSlotConfig.SMBIOSSystemSlot[Index].SlotDataBusWidth; + SmbiosRecord->CurrentUsage = SMBIOSlotConfig.SMBIOSSystemSlot[Index].SlotUsage; + SmbiosRecord->SlotLength = SMBIOSlotConfig.SMBIOSSystemSlot[Index].SlotLength; + SmbiosRecord->SlotID = SMBIOSlotConfig.SMBIOSSystemSlot[Index].SlotId; + *(UINT16 *)&SmbiosRecord->SlotCharacteristics1 = (UINT16)(SMBIOSlotConfig.SMBIOSSystemSlot[Index].SlotCharacteristics); + + // + // Slot Characteristics + // + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); + UnicodeStrToAsciiStr(SlotDesignation, OptionalStrStart); + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios-> Add( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + FreePool(SmbiosRecord); + return Status; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemSlotOnboardDevices.uni b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemSlotOnboardDevices.uni new file mode 100644 index 0000000000..ce1d9199d6 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemSlotOnboardDevices.uni @@ -0,0 +1,23 @@ +// /** @file +// System Slot onboard devices +// +// Copyright (c) 2013-2015 Intel Corporation. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// +// **/ +/=# + + + +#string STR_MISC_SYSTEM_SLOT_P64_B1 #language en-US "P64B1" +#string STR_MISC_SYSTEM_SLOT_P64_B2 #language en-US "P64B2" +#string STR_MISC_SYSTEM_SLOT_P64_B3 #language en-US "P64B3" +#string STR_MISC_SYSTEM_SLOT_P64_C1 #language en-US "P64C1" +#string STR_MISC_SYSTEM_SLOT_P64_C2 #language en-US "P64C2" +#string STR_MISC_SYSTEM_SLOT_P64_C3 #language en-US "P64C3" + + + + diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMisc.h b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMisc.h new file mode 100644 index 0000000000..b59933ba3a --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMisc.h @@ -0,0 +1,137 @@ +/** @file +Header file for the SmbiosMisc Driver. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#ifndef _SMBIOS_MISC_H +#define _SMBIOS_MISC_H + +#include "MiscDevicePath.h" +#include +#include + +/// +/// Reference SMBIOS 2.6, chapter 3.1.3. +/// Each text string is limited to 64 significant characters due to system MIF limitations. +/// +#define SMBIOS_STRING_MAX_LENGTH 64 +#define SMBIOS_PORT_CONNECTOR_MAX_NUM 14 + +typedef struct { + CHAR16 PortInternalConnectorDesignator[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 PortExternalConnectorDesignator[SMBIOS_STRING_MAX_LENGTH]; + UINT8 PortInternalConnectorType; + UINT8 PortExternalConnectorType; + UINT8 PortType; +} SMBIOS_PORT_CONNECTOR_DESIGNATOR; + +typedef struct { + UINT8 SMBIOSConnectorNumber; + SMBIOS_PORT_CONNECTOR_DESIGNATOR SMBIOSPortConnector[SMBIOS_PORT_CONNECTOR_MAX_NUM]; +} SMBIOS_PORT_CONNECTOR_DESIGNATOR_COFNIG; + +#define SMBIOS_SYSTEM_SLOT_MAX_NUM 14 + +typedef struct { + CHAR16 SlotDesignation[SMBIOS_STRING_MAX_LENGTH]; + UINT8 SlotType; + UINT8 SlotDataBusWidth; + UINT8 SlotUsage; + UINT8 SlotLength; + UINT16 SlotId; + UINT32 SlotCharacteristics; +} SMBIOS_SLOT_DESIGNATION; + +typedef struct { + UINT8 SMBIOSSystemSlotNumber; + SMBIOS_SLOT_DESIGNATION SMBIOSSystemSlot[SMBIOS_SYSTEM_SLOT_MAX_NUM]; +} SMBIOS_SLOT_COFNIG; + +// +// Data table entry update function. +// +typedef EFI_STATUS (EFIAPI EFI_MISC_SMBIOS_DATA_FUNCTION) ( + IN VOID *RecordData, + IN EFI_SMBIOS_PROTOCOL *Smbios + ); + + +// +// Data table entry definition. +// +typedef struct { + // + // intermediat input data for SMBIOS record + // + VOID *RecordData; + EFI_MISC_SMBIOS_DATA_FUNCTION *Function; +} EFI_MISC_SMBIOS_DATA_TABLE; + +// +// Data Table extern definitions. +// +#define MISC_SMBIOS_DATA_TABLE_POINTER(NAME1) \ + & NAME1 ## Data + +// +// Data Table extern definitions. +// +#define MISC_SMBIOS_DATA_TABLE_EXTERNS(NAME1, NAME2) \ +extern NAME1 NAME2 ## Data + +// +// Data and function Table extern definitions. +// +#define MISC_SMBIOS_TABLE_EXTERNS(NAME1, NAME2, NAME3) \ +extern NAME1 NAME2 ## Data; \ +extern EFI_MISC_SMBIOS_DATA_FUNCTION NAME3 ## Function + + +// +// Data Table entries +// + +#define MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(NAME1, NAME2) \ +{ \ + & NAME1 ## Data, \ + & NAME2 ## Function \ +} + + +// +// Global definition macros. +// +#define MISC_SMBIOS_TABLE_DATA(NAME1, NAME2) \ + NAME1 NAME2 ## Data + +#define MISC_SMBIOS_TABLE_FUNCTION(NAME2) \ + EFI_STATUS EFIAPI NAME2 ## Function( \ + IN VOID *RecordData, \ + IN EFI_SMBIOS_PROTOCOL *Smbios \ + ) + + +// Data Table Array +// +extern EFI_MISC_SMBIOS_DATA_TABLE mSmbiosMiscDataTable[]; + +// +// Data Table Array Entries +// +extern UINTN mSmbiosMiscDataTableEntries; +extern EFI_HII_HANDLE mHiiHandle; +// +// Prototypes +// +EFI_STATUS +PiSmbiosMiscEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscDataTable.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscDataTable.c new file mode 100644 index 0000000000..fb57e36cd1 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscDataTable.c @@ -0,0 +1,109 @@ +/** @file +This driver parses the mSmbiosMiscDataTable structure and reports +any generated data using SMBIOS protocol. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + + +#include "CommonHeader.h" + +#include "SmbiosMisc.h" + + +// +// External definitions referenced by Data Table entries. +// + +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_BIOS_VENDOR, MiscBiosVendor, MiscBiosVendor); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_MANUFACTURER, MiscSystemManufacturer, MiscSystemManufacturer); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_MANUFACTURER, MiscBaseBoardManufacturer, MiscBaseBoardManufacturer); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_CHASSIS_MANUFACTURER, MiscChassisManufacturer, MiscChassisManufacturer); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_BOOT_INFORMATION_STATUS, MiscBootInfoStatus, MiscBootInfoStatus); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_NUMBER_OF_INSTALLABLE_LANGUAGES, NumberOfInstallableLanguages, NumberOfInstallableLanguages); +MISC_SMBIOS_TABLE_EXTERNS (EFI_MISC_SYSTEM_OPTION_STRING, SystemOptionString, SystemOptionString); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_ONBOARD_DEVICE, MiscOnboardDeviceVideo, MiscOnboardDevice); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_OEM_STRING,MiscOemString, MiscOemString); + +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector1, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector2, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector3, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector4, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector5, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector6, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector7, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector8, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector9, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector10, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector11, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector12, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector13, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector14, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot1, MiscSystemSlotDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot2, MiscSystemSlotDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot3, MiscSystemSlotDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot4, MiscSystemSlotDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot5, MiscSystemSlotDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot6, MiscSystemSlotDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot7, MiscSystemSlotDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot8, MiscSystemSlotDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot9, MiscSystemSlotDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot10, MiscSystemSlotDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot11, MiscSystemSlotDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot12, MiscSystemSlotDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot13, MiscSystemSlotDesignator); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot14, MiscSystemSlotDesignator); + + +// +// Data Table +// +EFI_MISC_SMBIOS_DATA_TABLE mSmbiosMiscDataTable[] = { + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscBiosVendor, MiscBiosVendor), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemManufacturer, MiscSystemManufacturer), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscBaseBoardManufacturer, MiscBaseBoardManufacturer), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscChassisManufacturer, MiscChassisManufacturer), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector1, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector2, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector3, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector4, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector5, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector6, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector7, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector8, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector9, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector10, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector11, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector12, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector13, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector14, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot1, MiscSystemSlotDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot2, MiscSystemSlotDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot3, MiscSystemSlotDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot4, MiscSystemSlotDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot5, MiscSystemSlotDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot6, MiscSystemSlotDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot7, MiscSystemSlotDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot8, MiscSystemSlotDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot9, MiscSystemSlotDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot10, MiscSystemSlotDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot11, MiscSystemSlotDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot12, MiscSystemSlotDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot13, MiscSystemSlotDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot14, MiscSystemSlotDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscOnboardDeviceVideo, MiscOnboardDevice), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscOemString, MiscOemString), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(SystemOptionString, SystemOptionString), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(NumberOfInstallableLanguages, NumberOfInstallableLanguages), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscBootInfoStatus, MiscBootInfoStatus) +}; + +// +// Number of Data Table entries. +// +UINTN mSmbiosMiscDataTableEntries = + (sizeof mSmbiosMiscDataTable) / sizeof(EFI_MISC_SMBIOS_DATA_TABLE); diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscDxe.inf b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscDxe.inf new file mode 100644 index 0000000000..d2b6123a7a --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscDxe.inf @@ -0,0 +1,308 @@ +## @file +# Component description file for Smbios Misc module. +# +# This driver parses the mSmbiosMiscDataTable structure +# and reports any generated data using SMBIOS protocol. +# SmBios To Misc.Subclass Map Table. +# SMBIOS Type |SMBIOS Name |Misc Subclass Record |Misc Subclass Name +# 0 | BIOS Information | 0x2 | BiosVendor +# 3 | System/Chassis Enclosure | 0x5 | ChassisManufacturer +# 8 | Port Connector Information | 0x6 | PortInternalConnectorDesignator +# 9 | System Slot Information | 0x7 | SystemSlotDesignator +# 10 | On Board Device Information | 0x8 | OnboardDevice +# 12 | System Configuration Options| 0xA | SystemOptionString +# 13 | BIOS Language Information | 0xB | NumberOfInstallableLanguages +# 32 | Boot Information | 0x1A | BootInformationStatus +# The uni files tagged with "ToolCode="DUMMY"" are included by SmbiosMiscStrings.uni file which is input +# file for StrGather tool. +# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SmbiosMisc + FILE_GUID = EF0C99B6-B1D3-4025-9405-BF6A560FE0E0 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = SmbiosMiscEntryPoint + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 EBC +# + +[Sources] + MiscOemStringFunction.c + MiscOemStringData.c + SmbiosMiscEntryPoint.c + SmbiosMiscDataTable.c + MiscSystemManufacturerData.c + MiscSystemManufacturerFunction.c + MiscBaseBoardManufacturerData.c + MiscBaseBoardManufacturerFunction.c + MiscOnboardDeviceFunction.c + MiscOnboardDeviceData.c + MiscSystemSlotDesignationFunction.c + MiscSystemSlotDesignationData.c + MiscNumberOfInstallableLanguagesFunction.c + MiscNumberOfInstallableLanguagesData.c + MiscChassisManufacturerFunction.c + MiscChassisManufacturerData.c + MiscBootInformationFunction.c + MiscBootInformationData.c + MiscBiosVendorFunction.c + MiscBiosVendorData.c + MiscSystemOptionStringFunction.c + MiscSystemOptionStringData.c + MiscPortInternalConnectorDesignatorFunction.c + MiscPortInternalConnectorDesignatorData.c + SmbiosMisc.h + MiscDevicePath.h + SmbiosMiscStrings.uni + CommonHeader.h + + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFrameworkPkg/IntelFrameworkPkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + +[LibraryClasses] + PcdLib + HiiLib + MemoryAllocationLib + DevicePathLib + BaseMemoryLib + BaseLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + +[Protocols] + gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLang + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision + gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName + gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosVendor + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosReleaseDate + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosStartAddress + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosChar + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosCharEx1 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosCharEx2 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemManufacturer + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemProductName + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemVersion + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSerialNumber + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemUuid + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSKUNumber + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemFamily + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBoardManufacturer + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBoardProductName + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBoardVersion + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBoardSerialNumber + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisManufacturer + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisVersion + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisSerialNumber + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisAssetTag + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisBootupState + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisPowerSupplyState + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisSecurityState + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisOemDefined + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisHeight + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisNumberPowerCords + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisElementCount + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisElementRecordLength + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSConnectorNumber + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort1InternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort1ExternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort1InternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort1ExternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort1Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort2InternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort2ExternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort2InternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort2ExternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort2Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort3InternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort3ExternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort3InternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort3ExternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort3Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort4InternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort4ExternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort4InternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort4ExternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort4Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort5InternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort5ExternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort5InternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort5ExternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort5Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort6InternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort6ExternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort6InternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort6ExternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort6Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort7InternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort7ExternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort7InternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort7ExternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort7Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort8InternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort8ExternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort8InternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort8ExternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort8Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort9InternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort9ExternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort9InternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort9ExternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort9Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort10InternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort10ExternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort10InternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort10ExternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort10Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort11InternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort11ExternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort11InternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort11ExternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort11Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort12InternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort12ExternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort12InternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort12ExternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort12Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort13InternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort13ExternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort13InternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort13ExternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort13Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort14InternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort14ExternalConnectorDesignator + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort14InternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort14ExternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort14Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort15InternalConnectorDesignator + + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort15InternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort15ExternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort15Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort16InternalConnectorDesignator + + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort16InternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort16ExternalConnectorType + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort16Type + + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlotNumber + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Designation + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1DataBusWidth + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Usage + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Length + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Id + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Characteristics + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Designation + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2DataBusWidth + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Usage + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Length + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Id + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Characteristics + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Designation + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3DataBusWidth + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Usage + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Length + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Id + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Characteristics + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Designation + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4DataBusWidth + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Usage + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Length + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Id + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Characteristics + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Designation + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5DataBusWidth + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Usage + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Length + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Id + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Characteristics + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Designation + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6DataBusWidth + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Usage + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Length + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Id + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Characteristics + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Designation + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7DataBusWidth + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Usage + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Length + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Id + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Characteristics + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Designation + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8DataBusWidth + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Usage + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Length + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Id + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Characteristics + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Designation + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9DataBusWidth + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Usage + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Length + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Id + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Characteristics + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Designation + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10DataBusWidth + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Usage + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Length + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Id + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Characteristics + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Designation + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11DataBusWidth + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Usage + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Length + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Id + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Characteristics + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Designation + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12DataBusWidth + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Usage + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Length + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Id + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Characteristics + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Designation + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13DataBusWidth + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Usage + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Length + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Id + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Characteristics + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Designation + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14DataBusWidth + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Usage + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Length + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Id + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Characteristics + +[Depex] + gEfiSmbiosProtocolGuid diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscEntryPoint.c b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscEntryPoint.c new file mode 100644 index 0000000000..c8bc7ef901 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscEntryPoint.c @@ -0,0 +1,82 @@ +/** @file +This driver parses the mSmbiosMiscDataTable structure and reports +any generated data using SMBIOS protocol. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + + +#include "CommonHeader.h" + +#include "SmbiosMisc.h" + + +extern UINT8 SmbiosMiscStrings[]; +EFI_HANDLE mImageHandle; + +EFI_HII_HANDLE mHiiHandle; + + + +/** + Standard EFI driver point. This driver parses the mSmbiosMiscDataTable + structure and reports any generated data using SMBIOS protocol. + + @param ImageHandle Handle for the image of this driver + @param SystemTable Pointer to the EFI System Table + + @retval EFI_SUCCESS The data was successfully stored. + +**/ +EFI_STATUS +EFIAPI +SmbiosMiscEntryPoint( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINTN Index; + EFI_STATUS EfiStatus; + EFI_SMBIOS_PROTOCOL *Smbios; + + + mImageHandle = ImageHandle; + + EfiStatus = gBS->LocateProtocol(&gEfiSmbiosProtocolGuid, NULL, (VOID**)&Smbios); + + if (EFI_ERROR(EfiStatus)) { + DEBUG((EFI_D_ERROR, "Could not locate SMBIOS protocol. %r\n", EfiStatus)); + return EfiStatus; + } + + mHiiHandle = HiiAddPackages ( + &gEfiCallerIdGuid, + mImageHandle, + SmbiosMiscStrings, + NULL + ); + ASSERT (mHiiHandle != NULL); + + for (Index = 0; Index < mSmbiosMiscDataTableEntries; ++Index) { + // + // If the entry have a function pointer, just log the data. + // + if (mSmbiosMiscDataTable[Index].Function != NULL) { + EfiStatus = (*mSmbiosMiscDataTable[Index].Function)( + mSmbiosMiscDataTable[Index].RecordData, + Smbios + ); + + if (EFI_ERROR(EfiStatus)) { + DEBUG((EFI_D_ERROR, "Misc smbios store error. Index=%d, ReturnStatus=%r\n", Index, EfiStatus)); + return EfiStatus; + } + } + } + + return EfiStatus; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscStrings.uni b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscStrings.uni new file mode 100644 index 0000000000..d8e6d0df78 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscStrings.uni @@ -0,0 +1,26 @@ +// /** @file +// SmbiosMisc formset. +// +// Copyright (c) 2013-2015 Intel Corporation. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// +// **/ + +/=# + +#langdef en-US "English" + +#string STR_MISC_SUBCLASS_DRIVER_TITLE #language en-US "SMBIOS Misc subclass driver" + + +#include "MiscBiosVendor.uni" +#include "MiscChassisManufacturer.uni" +#include "MiscPortInternalConnectorDesignator.uni" +#include "MiscSystemManufacturer.uni" +#include "MiscBaseBoardManufacturer.uni" +#include "MiscSystemOptionString.uni" +#include "MiscSystemSlotDesignation.uni" +#include "MiscOnboardDevice.uni" +#include "MiscOemString.uni" diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.c b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.c new file mode 100644 index 0000000000..024dff89df --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.c @@ -0,0 +1,81 @@ +/** @file +Principle source module for Clanton Peak platform config PEIM driver. + +Copyright (c) 2013 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +VOID +EFIAPI +LegacySpiProtect ( + VOID + ) +{ + UINT32 RegVal; + + RegVal = PcdGet32 (PcdLegacyProtectedBIOSRange0Pei); + if (RegVal != 0) { + PlatformWriteFirstFreeSpiProtect ( + RegVal, + 0, + 0 + ); + } + RegVal = PcdGet32 (PcdLegacyProtectedBIOSRange1Pei); + if (RegVal != 0) { + PlatformWriteFirstFreeSpiProtect ( + RegVal, + 0, + 0 + ); + } + RegVal = PcdGet32 (PcdLegacyProtectedBIOSRange2Pei); + if (RegVal != 0) { + PlatformWriteFirstFreeSpiProtect ( + RegVal, + 0, + 0 + ); + } + + // + // Make legacy SPI READ/WRITE enabled if not a secure build + // + LpcPciCfg32And (R_QNC_LPC_BIOS_CNTL, ~B_QNC_LPC_BIOS_CNTL_BIOSWE); +} + +/** PlatformConfigPei driver entry point. + + Platform config in PEI stage. + + @param[in] FfsHeader Pointer to Firmware File System file header. + @param[in] PeiServices General purpose services available to every PEIM. + + @retval EFI_SUCCESS Platform config success. +*/ +EFI_STATUS +EFIAPI +PlatformConfigPeiInit ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + // + // Do SOC Init Pre memory init. + // + PeiQNCPreMemInit (); + + // + // Protect areas specified by PCDs. + // + LegacySpiProtect (); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.inf b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.inf new file mode 100644 index 0000000000..e6c92850b2 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.inf @@ -0,0 +1,45 @@ +## @file +# Component description file for Clanton Peak platform config PEIM module. +# +# Copyright (c) 2013 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformConfigPei + FILE_GUID = 55961E20-B0D9-4553-9948-E3ECF0BE0889 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = PlatformConfigPeiInit + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 +# + +[Sources] + PlatformConfigPei.c + +[Packages] + MdePkg/MdePkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + QuarkSocPkg/QuarkSocPkg.dec + +[LibraryClasses] + PeimEntryPoint + PcdLib + IntelQNCLib + PlatformHelperLib + QNCAccessLib + +[Pcd] + gQuarkPlatformTokenSpaceGuid.PcdLegacyProtectedBIOSRange0Pei + gQuarkPlatformTokenSpaceGuid.PcdLegacyProtectedBIOSRange1Pei + gQuarkPlatformTokenSpaceGuid.PcdLegacyProtectedBIOSRange2Pei + +[Depex] + TRUE diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/BootMode.c b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/BootMode.c new file mode 100644 index 0000000000..2e22e80c8e --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/BootMode.c @@ -0,0 +1,218 @@ +/** @file +This file provide the function to detect boot mode + +Copyright (c) 2013 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "CommonHeader.h" +#include + +EFI_PEI_PPI_DESCRIPTOR mPpiListRecoveryBootMode = { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiBootInRecoveryModePpiGuid, + NULL +}; + +/** + If the box was opened, it's boot with full config. + If the box is closed, then + 1. If it's first time to boot, it's boot with full config . + 2. If the ChassisIntrution is selected, force to be a boot with full config + 3. Otherwise it's boot with no change. + + @param PeiServices General purpose services available to every PEIM. + + @retval TRUE If it's boot with no change. + + @retval FALSE If boot with no change. +**/ +BOOLEAN +IsBootWithNoChange ( + IN EFI_PEI_SERVICES **PeiServices + ) +{ + BOOLEAN IsFirstBoot = FALSE; + + BOOLEAN EnableFastBoot = FALSE; + IsFirstBoot = PcdGetBool(PcdBootState); + EnableFastBoot = PcdGetBool (PcdEnableFastBoot); + + DEBUG ((EFI_D_INFO, "IsFirstBoot = %x , EnableFastBoot= %x. \n", IsFirstBoot, EnableFastBoot)); + + if ((!IsFirstBoot) && EnableFastBoot) { + return TRUE; + } else { + return FALSE; + } +} + + +/** + +Routine Description: + + This function is used to verify if the FV header is validate. + + @param FwVolHeader - The FV header that to be verified. + + @retval EFI_SUCCESS - The Fv header is valid. + @retval EFI_NOT_FOUND - The Fv header is invalid. + +**/ +EFI_STATUS +ValidateFvHeader ( + EFI_BOOT_MODE *BootMode + ) +{ + UINT16 *Ptr; + UINT16 HeaderLength; + UINT16 Checksum; + + EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader; + + if (BOOT_IN_RECOVERY_MODE == *BootMode) { + DEBUG ((EFI_D_INFO, "Boot mode recovery\n")); + return EFI_SUCCESS; + } + // + // Let's check whether FvMain header is valid, if not enter into recovery mode + // + // + // Verify the header revision, header signature, length + // Length of FvBlock cannot be 2**64-1 + // HeaderLength cannot be an odd number + // + FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32(PcdFlashFvMainBase); + if ((FwVolHeader->Revision != EFI_FVH_REVISION)|| + (FwVolHeader->Signature != EFI_FVH_SIGNATURE) || + (FwVolHeader->FvLength == ((UINT64) -1)) || + ((FwVolHeader->HeaderLength & 0x01) != 0) + ) { + return EFI_NOT_FOUND; + } + // + // Verify the header checksum + // + HeaderLength = (UINT16) (FwVolHeader->HeaderLength / 2); + Ptr = (UINT16 *) FwVolHeader; + Checksum = 0; + while (HeaderLength > 0) { + Checksum = Checksum +*Ptr; + Ptr++; + HeaderLength--; + } + + if (Checksum != 0) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +/** + Peform the boot mode determination logic + If the box is closed, then + 1. If it's first time to boot, it's boot with full config . + 2. If the ChassisIntrution is selected, force to be a boot with full config + 3. Otherwise it's boot with no change. + + @param PeiServices General purpose services available to every PEIM. + + @param BootMode The detected boot mode. + + @retval EFI_SUCCESS if the boot mode could be set +**/ +EFI_STATUS +UpdateBootMode ( + IN EFI_PEI_SERVICES **PeiServices, + OUT EFI_BOOT_MODE *BootMode + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE NewBootMode; + PEI_CAPSULE_PPI *Capsule; + UINT32 RegValue; + + NewBootMode = *BootMode; + + // + // Read Sticky R/W Bits + // + RegValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW); + DEBUG ((EFI_D_ERROR, "RegValue = %08x\n", RegValue)); + + // + // Check if we need to boot in recovery mode + // + if ((RegValue & B_CFG_STICKY_RW_FORCE_RECOVERY) != 0) { + NewBootMode = BOOT_IN_RECOVERY_MODE; + DEBUG ((EFI_D_ERROR, "RECOVERY from sticky bit\n"));; + + // + // Clear force recovery sticky bit + // + QNCAltPortWrite ( + QUARK_SCSS_SOC_UNIT_SB_PORT_ID, + QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW, + RegValue &(~B_CFG_STICKY_RW_FORCE_RECOVERY) + ); + + } else if (ValidateFvHeader (BootMode) != EFI_SUCCESS) { + NewBootMode = BOOT_IN_RECOVERY_MODE; + DEBUG ((EFI_D_ERROR, "RECOVERY from corrupt FV\n"));; + } else if (QNCCheckS3AndClearState ()) { + // + // Determine if we're in capsule update mode + // + Status = PeiServicesLocatePpi ( + &gPeiCapsulePpiGuid, + 0, + NULL, + (VOID **)&Capsule + ); + if (Status == EFI_SUCCESS) { + Status = Capsule->CheckCapsuleUpdate (PeiServices); + if (Status == EFI_SUCCESS) { + DEBUG ((EFI_D_INFO, "Boot mode Flash Update\n")); + NewBootMode = BOOT_ON_FLASH_UPDATE; + } else { + DEBUG ((EFI_D_INFO, "Boot mode S3 resume\n")); + NewBootMode = BOOT_ON_S3_RESUME; + } + } else { + DEBUG ((EFI_D_INFO, "Boot mode S3 resume\n")); + NewBootMode = BOOT_ON_S3_RESUME; + } + } else { + // + // Check if this is a power on reset + // + if (QNCCheckPowerOnResetAndClearState ()) { + DEBUG ((EFI_D_INFO, "Power On Reset\n")); + } + if (IsBootWithNoChange (PeiServices)) { + DEBUG ((EFI_D_INFO, "Boot with Minimum cfg\n")); + NewBootMode = BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; + } else { + DEBUG ((EFI_D_INFO, "Boot with Full cfg\n")); + NewBootMode = BOOT_WITH_FULL_CONFIGURATION; + } + } + + if (NewBootMode == BOOT_IN_RECOVERY_MODE) { + DEBUG ((EFI_D_INFO, "Boot mode recovery\n")); + Status = PeiServicesInstallPpi (&mPpiListRecoveryBootMode); + ASSERT_EFI_ERROR (Status); + } + + Status = PeiServicesSetBootMode (NewBootMode); + ASSERT_EFI_ERROR (Status); + + *BootMode = NewBootMode; + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/CommonHeader.h b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/CommonHeader.h new file mode 100644 index 0000000000..ce78bc1075 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/CommonHeader.h @@ -0,0 +1,81 @@ +/** @file +Common header file shared by all source files. + +This file includes package header files, library classes and protocol, PPI & GUID definitions. + +Copyright (c) 2013 - 2016 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __COMMON_HEADER_H_ +#define __COMMON_HEADER_H_ + + + +#include +#include +#include "Ioh.h" +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/Generic/Recovery.c b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/Generic/Recovery.c new file mode 100644 index 0000000000..67299a68b7 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/Generic/Recovery.c @@ -0,0 +1,467 @@ +/** @file +Install Platform EFI_PEI_RECOVERY_MODULE_PPI and Implementation of +EFI_PEI_LOAD_RECOVERY_CAPSULE service. + +Copyright (c) 2013-2019 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "CommonHeader.h" +#include "PlatformEarlyInit.h" + +#include + +// +// Capsule Types supported in this platform module +// +#include +#include +#include +#include +#include + +#include +#include + +#include + +// +// Required Service +// +EFI_STATUS +EFIAPI +PlatformRecoveryModule ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_RECOVERY_MODULE_PPI *This + ); + +VOID +AssertNoCapsulesError ( + IN EFI_PEI_SERVICES **PeiServices + ); + +VOID +AssertMediaDeviceError ( + IN EFI_PEI_SERVICES **PeiServices + ); + +VOID +ReportLoadCapsuleSuccess ( + IN EFI_PEI_SERVICES **PeiServices + ); + +VOID +CheckIfMediaPresentOnBlockIoDevice ( + IN EFI_PEI_SERVICES **PeiServices, + IN OUT BOOLEAN *MediaDeviceError, + IN OUT BOOLEAN *MediaPresent + ); + +// +// Module globals +// +EFI_PEI_RECOVERY_MODULE_PPI mRecoveryPpi = { PlatformRecoveryModule }; + +EFI_PEI_PPI_DESCRIPTOR mRecoveryPpiList = { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiRecoveryModulePpiGuid, + &mRecoveryPpi +}; + +EFI_STATUS +EFIAPI +PeimInitializeRecovery ( + IN EFI_PEI_SERVICES **PeiServices + ) +/*++ + +Routine Description: + + Provide the functionality of the Recovery Module. + +Arguments: + + PeiServices - General purpose services available to every PEIM. + +Returns: + + EFI_SUCCESS - If the interface could be successfully + installed. + +--*/ +{ + EFI_STATUS Status; + + Status = PeiServicesInstallPpi (&mRecoveryPpiList); + + return Status; +} + +EFI_STATUS +EFIAPI +PlatformRecoveryModule ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_RECOVERY_MODULE_PPI *This + ) +/*++ + +Routine Description: + + Provide the functionality of the Platform Recovery Module. + +Arguments: + + PeiServices - General purpose services available to every PEIM. + This - Pointer to EFI_PEI_RECOVERY_MODULE_PPI. + +Returns: + + EFI_SUCCESS - If the interface could be successfully + installed. + EFI_UNSUPPORTED - Not supported. + +--*/ +{ + EFI_STATUS Status; + EFI_PEI_DEVICE_RECOVERY_MODULE_PPI *DeviceRecoveryModule; + UINTN NumberOfImageProviders; + BOOLEAN ProviderAvailable; + UINTN NumberRecoveryCapsules; + UINTN RecoveryCapsuleSize; + EFI_GUID DeviceId; + EFI_PHYSICAL_ADDRESS Address; + VOID *Buffer; + EFI_CAPSULE_HEADER *CapsuleHeader; + EFI_PEI_HOB_POINTERS Hob; + BOOLEAN HobUpdate; + EFI_FIRMWARE_VOLUME_HEADER *FvHeader; + UINTN Index; + EFI_GUID mEfiCapsuleHeaderGuid = QUARK_CAPSULE_GUID; + + Index = 0; + + Status = EFI_SUCCESS; + HobUpdate = FALSE; + + ProviderAvailable = TRUE; + NumberOfImageProviders = 0; + + DeviceRecoveryModule = NULL; + + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Recovery Entry\n")); + + // + // Search the platform for some recovery capsule if the DXE IPL + // discovered a recovery condition and has requested a load. + // + while (ProviderAvailable) { + + Status = PeiServicesLocatePpi ( + &gEfiPeiDeviceRecoveryModulePpiGuid, + Index, + NULL, + (VOID **)&DeviceRecoveryModule + ); + + if (!EFI_ERROR (Status)) { + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Device Recovery PPI located\n")); + NumberOfImageProviders++; + + Status = DeviceRecoveryModule->GetNumberRecoveryCapsules ( + PeiServices, + DeviceRecoveryModule, + &NumberRecoveryCapsules + ); + + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Number Of Recovery Capsules: %d\n", NumberRecoveryCapsules)); + + if (NumberRecoveryCapsules == 0) { + Index++; + } else { + break; + } + } else { + ProviderAvailable = FALSE; + } + } + // + // The number of recovery capsules is 0. + // + if (!ProviderAvailable) { + AssertNoCapsulesError (PeiServices); + } + // + // If there is an image provider, get the capsule ID + // + if (ProviderAvailable) { + RecoveryCapsuleSize = 0; + Status = DeviceRecoveryModule->GetRecoveryCapsuleInfo ( + PeiServices, + DeviceRecoveryModule, + 1, + &RecoveryCapsuleSize, + &DeviceId + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Recovery Capsule Size: %d\n", RecoveryCapsuleSize)); + + // + // Only support the 2 capsule types known + // Future enhancement is to rank-order the selection + // + if ((!CompareGuid (&DeviceId, &gPeiCapsuleOnFatIdeDiskGuid)) && + (!CompareGuid (&DeviceId, &gPeiCapsuleOnDataCDGuid)) && + (!CompareGuid (&DeviceId, &gPeiCapsuleOnFatUsbDiskGuid)) + ) { + return EFI_UNSUPPORTED; + } + + Buffer = NULL; + Address = (UINTN) AllocatePages ((RecoveryCapsuleSize - 1) / 0x1000 + 1); + ASSERT (Address); + + Buffer = (UINT8 *) (UINTN) Address; + Status = DeviceRecoveryModule->LoadRecoveryCapsule ( + PeiServices, + DeviceRecoveryModule, + 1, + Buffer + ); + + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "LoadRecoveryCapsule Returns: %r\n", Status)); + + if (Status == EFI_DEVICE_ERROR) { + AssertMediaDeviceError (PeiServices); + } + + if (EFI_ERROR (Status)) { + return Status; + } else { + ReportLoadCapsuleSuccess (PeiServices); + } + + // + // Update FV Hob if found + // + Buffer = (VOID *)((UINT8 *) Buffer); + Status = PeiServicesGetHobList ((VOID **)&Hob.Raw); + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType == EFI_HOB_TYPE_FV) { + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Hob FV Length: %x\n", Hob.FirmwareVolume->Length)); + + if (Hob.FirmwareVolume->BaseAddress == (UINTN) PcdGet32 (PcdFlashFvMainBase)) { + HobUpdate = TRUE; + // + // This looks like the Hob we are interested in + // + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Hob Updated\n")); + Hob.FirmwareVolume->BaseAddress = (UINTN) Buffer; + Hob.FirmwareVolume->Length = RecoveryCapsuleSize; + } + } + + Hob.Raw = GET_NEXT_HOB (Hob); + } + // + // Check if the top of the file is a firmware volume header + // + FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *) Buffer; + CapsuleHeader = (EFI_CAPSULE_HEADER *) Buffer; + if (FvHeader->Signature == EFI_FVH_SIGNATURE) { + // + // build FV Hob if it is not built before + // + if (!HobUpdate) { + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "FV Hob is not found, Build FV Hob then..\n")); + BuildFvHob ( + (UINTN) Buffer, + FvHeader->FvLength + ); + + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Install FV Info PPI..\n")); + + PeiServicesInstallFvInfoPpi ( + NULL, + Buffer, + (UINT32) FvHeader->FvLength, + NULL, + NULL + ); + } + // + // Point to the location immediately after the FV. + // + CapsuleHeader = (EFI_CAPSULE_HEADER *) ((UINT8 *) Buffer + FvHeader->FvLength); + } + + // + // Check if pointer is still within the buffer + // + if ((UINTN) CapsuleHeader < (UINTN) ((UINT8 *) Buffer + RecoveryCapsuleSize)) { + + // + // Check if it is a capsule + // + if (CompareGuid ((EFI_GUID *) CapsuleHeader, &mEfiCapsuleHeaderGuid)) { + + // + // Set bootmode to capsule update so the capsule hob gets the right bootmode in the hob header. + // + Status = PeiServicesSetBootMode (BOOT_ON_FLASH_UPDATE); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Build capsule hob + // + BuildCvHob ((EFI_PHYSICAL_ADDRESS)(UINTN)CapsuleHeader, (UINT64)CapsuleHeader->CapsuleImageSize); + } + } + } + + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Recovery Module Returning: %r\n", Status)); + return Status; +} + +/* + AssertNoCapsulesError: + There were no recovery capsules found. + Case 1: Report the error that no recovery block io device/media is readable and assert. + Case 2: Report the error that there is no media present on any recovery block io device and assert. + Case 3: There is media present on some recovery block io device, + but there is no recovery capsule on it. Report the error and assert. +*/ +VOID +AssertNoCapsulesError ( + IN EFI_PEI_SERVICES **PeiServices + ) +{ + BOOLEAN MediaDeviceError; + BOOLEAN MediaPresent; + + MediaDeviceError = TRUE; + MediaPresent = FALSE; + + CheckIfMediaPresentOnBlockIoDevice (PeiServices, &MediaDeviceError, &MediaPresent); +/* if (MediaDeviceError) { + ReportStatusCode ( + (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED), + (EFI_PERIPHERAL_RECOVERY_MEDIA | EFI_P_EC_MEDIA_DEVICE_ERROR) + ); + + } else if (!MediaPresent) { + ReportStatusCode ( + (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED), + (EFI_PERIPHERAL_RECOVERY_MEDIA | EFI_P_EC_MEDIA_NOT_PRESENT) + ); + + } else { + ReportStatusCode ( + (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED), + (EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_EC_NO_RECOVERY_CAPSULE) + ); + }*/ + // + // Hang. + // + CpuDeadLoop(); +} + +#define MAX_BLOCK_IO_PPI 32 + +/* + CheckIfMediaPresentOnBlockIoDevice: + Checks to see whether there was a media device error or to see if there is media present. +*/ +VOID +CheckIfMediaPresentOnBlockIoDevice ( + IN EFI_PEI_SERVICES **PeiServices, + IN OUT BOOLEAN *MediaDeviceError, + IN OUT BOOLEAN *MediaPresent + ) +{ + EFI_STATUS Status; + UINTN BlockIoPpiInstance; + EFI_PEI_RECOVERY_BLOCK_IO_PPI *BlockIoPpi; + UINTN NumberBlockDevices; + EFI_PEI_BLOCK_IO_MEDIA Media; + + *MediaDeviceError = TRUE; + *MediaPresent = FALSE; + + for (BlockIoPpiInstance = 0; BlockIoPpiInstance < MAX_BLOCK_IO_PPI; BlockIoPpiInstance++) { + Status = PeiServicesLocatePpi ( + &gEfiPeiVirtualBlockIoPpiGuid, + BlockIoPpiInstance, + NULL, + (VOID **)&BlockIoPpi + ); + if (EFI_ERROR (Status)) { + // + // Done with all Block Io Ppis + // + break; + } + + Status = BlockIoPpi->GetNumberOfBlockDevices ( + PeiServices, + BlockIoPpi, + &NumberBlockDevices + ); + if (EFI_ERROR (Status) || (NumberBlockDevices == 0)) { + continue; + } + // + // Just retrieve the first block + // + Status = BlockIoPpi->GetBlockDeviceMediaInfo ( + PeiServices, + BlockIoPpi, + 0, + &Media + ); + if (!EFI_ERROR (Status)) { + *MediaDeviceError = FALSE; + if (Media.MediaPresent) { + *MediaPresent = TRUE; + break; + } + } + } +} + +VOID +AssertMediaDeviceError ( + IN EFI_PEI_SERVICES **PeiServices + ) +{ +/* ReportStatusCode ( + (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED), + (EFI_PERIPHERAL_RECOVERY_MEDIA | EFI_P_EC_MEDIA_DEVICE_ERROR) + ); +*/ + CpuDeadLoop (); +} + +VOID +ReportLoadCapsuleSuccess ( + IN EFI_PEI_SERVICES **PeiServices + ) +{ + // + // EFI_SW_PEI_PC_CAPSULE_START: (from the status code spec): + // Loaded the recovery capsule. About to hand off control to the capsule. + // +/* ReportStatusCode ( + EFI_PROGRESS_CODE, + (EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_CAPSULE_LOAD_SUCCESS) + );*/ +} + diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/MemoryCallback.c b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/MemoryCallback.c new file mode 100644 index 0000000000..cfdcba8e02 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/MemoryCallback.c @@ -0,0 +1,279 @@ +/** @file +This file includes a memory call back function notified when MRC is done, +following action is performed in this file, + 1. ICH initialization after MRC. + 2. SIO initialization. + 3. Install ResetSystem and FinvFv PPI. + 4. Set MTRR for PEI + 5. Create FV HOB and Flash HOB + +Copyright (c) 2013 - 2019, Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "CommonHeader.h" + +#include "PlatformEarlyInit.h" + +extern EFI_PEI_PPI_DESCRIPTOR mPpiStall[]; + +EFI_PEI_RESET_PPI mResetPpi = { PlatformResetSystem }; + +EFI_PEI_PPI_DESCRIPTOR mPpiList[1] = { + { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiResetPpiGuid, + &mResetPpi + } +}; + +/** + This function reset the entire platform, including all processor and devices, and + reboots the system. + + @param PeiServices General purpose services available to every PEIM. + + @retval EFI_SUCCESS if it completed successfully. +**/ +EFI_STATUS +EFIAPI +PlatformResetSystem ( + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + ResetCold(); + return EFI_SUCCESS; +} + +/** + This function provides a blocking stall for reset at least the given number of microseconds + stipulated in the final argument. + + @param PeiServices General purpose services available to every PEIM. + + @param this Pointer to the local data for the interface. + + @param Microseconds number of microseconds for which to stall. + + @retval EFI_SUCCESS the function provided at least the required stall. +**/ +EFI_STATUS +EFIAPI +Stall ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_STALL_PPI *This, + IN UINTN Microseconds + ) +{ + MicroSecondDelay (Microseconds); + return EFI_SUCCESS; +} + + +/** + This function will be called when MRC is done. + + @param PeiServices General purpose services available to every PEIM. + + @param NotifyDescriptor Information about the notify event.. + + @param Ppi The notify context. + + @retval EFI_SUCCESS If the function completed successfully. +**/ +EFI_STATUS +EFIAPI +MemoryDiscoveredPpiNotifyCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + UINT64 MemoryLength; + EFI_SMRAM_DESCRIPTOR *SmramDescriptor; + UINTN NumSmramRegions; + UINT32 RmuMainBaseAddress; + UINT32 RegData32; + UINT8 CpuAddressWidth; + UINT32 RegEax; + MTRR_SETTINGS MtrrSettings; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices; + UINT8 MorControl; + UINTN DataSize; + + DEBUG ((EFI_D_INFO, "Platform PEIM Memory Callback\n")); + + NumSmramRegions = 0; + SmramDescriptor = NULL; + RmuMainBaseAddress = 0; + + PERF_START (NULL, "SetCache", NULL, 0); + + InfoPostInstallMemory (&RmuMainBaseAddress, &SmramDescriptor, &NumSmramRegions); + ASSERT (SmramDescriptor != NULL); + ASSERT (RmuMainBaseAddress != 0); + + MemoryLength = ((UINT64) RmuMainBaseAddress) + 0x10000; + + Status = PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + // + // Get current MTRR settings + // + MtrrGetAllMtrrs (&MtrrSettings); + + // + // Set all DRAM cachability to CacheWriteBack + // + Status = MtrrSetMemoryAttributeInMtrrSettings (&MtrrSettings, 0, MemoryLength, CacheWriteBack); + ASSERT_EFI_ERROR (Status); + + // + // RTC:28208 - System hang/crash when entering probe mode(ITP) when relocating SMBASE + // Workaround to make default SMRAM UnCachable + // + Status = MtrrSetMemoryAttributeInMtrrSettings (&MtrrSettings, 0x30000, SIZE_64KB, CacheUncacheable); + ASSERT_EFI_ERROR (Status); + + // + // Set new MTRR settings + // + MtrrSetAllMtrrs (&MtrrSettings); + + PERF_END (NULL, "SetCache", NULL, 0); + + // + // Get necessary PPI + // + Status = PeiServicesLocatePpi ( + &gEfiPeiReadOnlyVariable2PpiGuid, // GUID + 0, // INSTANCE + NULL, // EFI_PEI_PPI_DESCRIPTOR + (VOID **)&VariableServices // PPI + ); + ASSERT_EFI_ERROR (Status); + + // + // Detect MOR request by the OS. + // + MorControl = 0; + DataSize = sizeof (MorControl); + Status = VariableServices->GetVariable ( + VariableServices, + MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME, + &gEfiMemoryOverwriteControlDataGuid, + NULL, + &DataSize, + &MorControl + ); + // + // If OS requested a memory overwrite perform it now for Embedded SRAM + // + if (MOR_CLEAR_MEMORY_VALUE (MorControl)) { + DEBUG ((EFI_D_INFO, "Clear Embedded SRAM per MOR request.\n")); + if (PcdGet32 (PcdESramMemorySize) > 0) { + if (PcdGet32 (PcdEsramStage1Base) == 0) { + // + // ZeroMem() generates an ASSERT() if Buffer parameter is NULL. + // Clear byte at 0 and start clear operation at address 1. + // + *(UINT8 *)(0) = 0; + ZeroMem ((VOID *)1, (UINTN)PcdGet32 (PcdESramMemorySize) - 1); + } else { + ZeroMem ( + (VOID *)(UINTN)PcdGet32 (PcdEsramStage1Base), + (UINTN)PcdGet32 (PcdESramMemorySize) + ); + } + } + } + + // + // Install PeiReset for PeiResetSystem service + // + Status = PeiServicesInstallPpi (&mPpiList[0]); + ASSERT_EFI_ERROR (Status); + + // + // Do QNC initialization after MRC + // + PeiQNCPostMemInit (); + + Status = PeiServicesInstallPpi (&mPpiStall[0]); + ASSERT_EFI_ERROR (Status); + + // + // Set E000/F000 Routing + // + RegData32 = QNCPortRead (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC); + RegData32 |= (BIT2|BIT1); + QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC, RegData32); + + if (BootMode == BOOT_IN_RECOVERY_MODE) { + // Do nothing here. A generic RecoveryModule will handle it. + } else if (BootMode == BOOT_ON_S3_RESUME) { + return EFI_SUCCESS; + } else { + PeiServicesInstallFvInfoPpi ( + NULL, + (VOID *) (UINTN) PcdGet32 (PcdFlashFvMainBase), + PcdGet32 (PcdFlashFvMainSize), + NULL, + NULL + ); + + // + // Publish the FVMAIN FV so the DXE Phase can dispatch drivers from this FV + // and produce Load File Protocols for UEFI Applications in this FV. + // + BuildFvHob ( + PcdGet32 (PcdFlashFvMainBase), + PcdGet32 (PcdFlashFvMainSize) + ); + + // + // Publish the Payload FV so the DXE Phase can dispatch drivers from this FV + // and produce Load File Protocols for UEFI Applications in this FV. + // + BuildFvHob ( + PcdGet32 (PcdFlashFvPayloadBase), + PcdGet32 (PcdFlashFvPayloadSize) + ); + } + + // + // Build flash HOB, it's going to be used by GCD and E820 building + // Map full SPI flash decode range (regardless of smaller SPI flash parts installed) + // + BuildResourceDescriptorHob ( + EFI_RESOURCE_FIRMWARE_DEVICE, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + (SIZE_4GB - SIZE_8MB), + SIZE_8MB + ); + + // + // Create a CPU hand-off information + // + CpuAddressWidth = 32; + AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); + if (RegEax >= CPUID_VIR_PHY_ADDRESS_SIZE) { + AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &RegEax, NULL, NULL, NULL); + CpuAddressWidth = (UINT8) (RegEax & 0xFF); + } + DEBUG ((EFI_D_INFO, "CpuAddressWidth: %d\n", CpuAddressWidth)); + + BuildCpuHob (CpuAddressWidth, 16); + + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.c b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.c new file mode 100644 index 0000000000..fcb5c79aaf --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.c @@ -0,0 +1,1565 @@ +/** @file +Framework PEIM to initialize memory on a Quark Memory Controller. + +Copyright (c) 2013 - 2016, Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "CommonHeader.h" +#include "MrcWrapper.h" +#include +#include "Platform.h" + +#include + +// +// ------------------------ TSEG Base +// +// ------------------------ RESERVED_CPU_S3_SAVE_OFFSET +// CPU S3 data +// ------------------------ RESERVED_ACPI_S3_RANGE_OFFSET +// S3 Memory base structure +// ------------------------ TSEG + 1 page + +#define RESERVED_CPU_S3_SAVE_OFFSET (RESERVED_ACPI_S3_RANGE_OFFSET - sizeof (SMM_S3_RESUME_STATE)) + +// Strap configuration register specifying DDR setup +#define QUARK_SCSS_REG_STPDDRCFG 0x00 + +// Macro counting array elements +#define COUNT(a) (sizeof(a)/sizeof(*a)) + + +EFI_MEMORY_TYPE_INFORMATION mDefaultQncMemoryTypeInformation[] = { + { EfiReservedMemoryType, EDKII_RESERVED_SIZE_PAGES }, // BIOS Reserved + { EfiACPIMemoryNVS, ACPI_NVS_SIZE_PAGES }, // S3, SMM, etc + { EfiRuntimeServicesData, RUNTIME_SERVICES_DATA_SIZE_PAGES }, + { EfiRuntimeServicesCode, RUNTIME_SERVICES_CODE_SIZE_PAGES }, + { EfiACPIReclaimMemory, ACPI_RECLAIM_SIZE_PAGES }, // ACPI ASL + { EfiMaxMemoryType, 0 } +}; + +/** + Configure Uart mmio base for MRC serial log purpose + + @param MrcData - MRC configuration data updated + +**/ +VOID +MrcUartConfig( + MRC_PARAMS *MrcData + ) +{ + UINT8 UartIdx; + UINT32 RegData32; + UINT8 IohUartBus; + UINT8 IohUartDev; + + UartIdx = PcdGet8(PcdIohUartFunctionNumber); + IohUartBus = PcdGet8(PcdIohUartBusNumber); + IohUartDev = PcdGet8(PcdIohUartDevNumber); + + RegData32 = PciRead32 (PCI_LIB_ADDRESS(IohUartBus, IohUartDev, UartIdx, PCI_BASE_ADDRESSREG_OFFSET)); + MrcData->uart_mmio_base = RegData32 & 0xFFFFFFF0; +} + +/** + Configure MRC from memory controller fuse settings. + + @param MrcData - MRC configuration data to be updated. + + @return EFI_SUCCESS MRC Config parameters updated from platform data. +**/ +EFI_STATUS +MrcConfigureFromMcFuses ( + OUT MRC_PARAMS *MrcData + ) +{ + UINT32 McFuseStat; + + McFuseStat = QNCPortRead ( + QUARK_NC_MEMORY_CONTROLLER_SB_PORT_ID, + QUARK_NC_MEMORY_CONTROLLER_REG_DFUSESTAT + ); + + DEBUG ((EFI_D_INFO, "MRC McFuseStat 0x%08x\n", McFuseStat)); + + if ((McFuseStat & B_DFUSESTAT_ECC_DIS) != 0) { + DEBUG ((EFI_D_INFO, "MRC Fuse : fus_dun_ecc_dis.\n")); + MrcData->ecc_enables = 0; + } else { + MrcData->ecc_enables = 1; + } + return EFI_SUCCESS; +} + +/** + Configure MRC from platform info hob. + + @param MrcData - MRC configuration data to be updated. + + @return EFI_SUCCESS MRC Config parameters updated from hob. + @return EFI_NOT_FOUND Platform Info or MRC Config parameters not found. + @return EFI_INVALID_PARAMETER Wrong params in hob. +**/ +EFI_STATUS +MrcConfigureFromInfoHob ( + OUT MRC_PARAMS *MrcData + ) +{ + PDAT_MRC_ITEM *ItemData; + + ItemData = (PDAT_MRC_ITEM *)PcdGetPtr (PcdMrcParameters); + + MrcData->channel_enables = ItemData->ChanMask; + MrcData->channel_width = ItemData->ChanWidth; + MrcData->address_mode = ItemData->AddrMode; + // Enable scrambling if requested. + MrcData->scrambling_enables = (ItemData->Flags & PDAT_MRC_FLAG_SCRAMBLE_EN) != 0; + MrcData->ddr_type = ItemData->DramType; + MrcData->dram_width = ItemData->DramWidth; + MrcData->ddr_speed = ItemData->DramSpeed; + // Enable ECC if requested. + MrcData->rank_enables = ItemData->RankMask; + MrcData->params.DENSITY = ItemData->DramDensity; + MrcData->params.tCL = ItemData->tCL; + MrcData->params.tRAS = ItemData->tRAS; + MrcData->params.tWTR = ItemData->tWTR; + MrcData->params.tRRD = ItemData->tRRD; + MrcData->params.tFAW = ItemData->tFAW; + + MrcData->refresh_rate = ItemData->SrInt; + MrcData->sr_temp_range = ItemData->SrTemp; + MrcData->ron_value = ItemData->DramRonVal; + MrcData->rtt_nom_value = ItemData->DramRttNomVal; + MrcData->rd_odt_value = ItemData->SocRdOdtVal; + + DEBUG ((EFI_D_INFO, "MRC dram_width %d\n", MrcData->dram_width)); + DEBUG ((EFI_D_INFO, "MRC rank_enables %d\n",MrcData->rank_enables)); + DEBUG ((EFI_D_INFO, "MRC ddr_speed %d\n", MrcData->ddr_speed)); + DEBUG ((EFI_D_INFO, "MRC flags: %s\n", + (MrcData->scrambling_enables) ? L"SCRAMBLE_EN" : L"" + )); + + DEBUG ((EFI_D_INFO, "MRC density=%d tCL=%d tRAS=%d tWTR=%d tRRD=%d tFAW=%d\n", + MrcData->params.DENSITY, + MrcData->params.tCL, + MrcData->params.tRAS, + MrcData->params.tWTR, + MrcData->params.tRRD, + MrcData->params.tFAW + )); + + return EFI_SUCCESS; +} + +/** + + Configure ECC scrub + + @param MrcData - MRC configuration + +**/ +VOID +EccScrubSetup( + const MRC_PARAMS *MrcData + ) +{ + UINT32 BgnAdr = 0; + UINT32 EndAdr = MrcData->mem_size; + UINT32 BlkSize = PcdGet8(PcdEccScrubBlkSize) & SCRUB_CFG_BLOCKSIZE_MASK; + UINT32 Interval = PcdGet8(PcdEccScrubInterval) & SCRUB_CFG_INTERVAL_MASK; + + if( MrcData->ecc_enables == 0 || MrcData->boot_mode == bmS3 || Interval == 0) { + // No scrub configuration needed if ECC not enabled + // On S3 resume reconfiguration is done as part of resume + // script, see SNCS3Save.c ==> SaveRuntimeScriptTable() + // Also if PCD disables scrub, then we do nothing. + return; + } + + QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_END_MEM_REG, EndAdr); + QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_START_MEM_REG, BgnAdr); + QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_NEXT_READ_REG, BgnAdr); + QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_CONFIG_REG, + Interval << SCRUB_CFG_INTERVAL_SHIFT | + BlkSize << SCRUB_CFG_BLOCKSIZE_SHIFT); + + McD0PciCfg32 (QNC_ACCESS_PORT_MCR) = SCRUB_RESUME_MSG(); +} + +/** Post InstallS3Memory / InstallEfiMemory tasks given MrcData context. + + @param[in] MrcData MRC configuration. + @param[in] IsS3 TRUE if after InstallS3Memory. + +**/ +VOID +PostInstallMemory ( + IN MRC_PARAMS *MrcData, + IN BOOLEAN IsS3 + ) +{ + UINT32 RmuMainDestBaseAddress; + UINT32 *RmuMainSrcBaseAddress; + UINTN RmuMainSize; + EFI_STATUS Status; + + // + // Setup ECC policy (All boot modes). + // + QNCPolicyDblEccBitErr (V_WDT_CONTROL_DBL_ECC_BIT_ERR_WARM); + + // + // Find the 64KB of memory for Rmu Main at the top of available memory. + // + InfoPostInstallMemory (&RmuMainDestBaseAddress, NULL, NULL); + DEBUG ((EFI_D_INFO, "RmuMain Base Address : 0x%x\n", RmuMainDestBaseAddress)); + + // + // Relocate RmuMain. + // + if (IsS3) { + QNCSendOpcodeDramReady (RmuMainDestBaseAddress); + } else { + Status = PlatformFindFvFileRawDataSection (NULL, PcdGetPtr(PcdQuarkMicrocodeFile), (VOID **) &RmuMainSrcBaseAddress, &RmuMainSize); + ASSERT_EFI_ERROR (Status); + if (!EFI_ERROR (Status)) { + DEBUG ((EFI_D_INFO, "Found Microcode ADDR:SIZE 0x%08x:0x%04x\n", (UINTN) RmuMainSrcBaseAddress, RmuMainSize)); + } + + RmuMainRelocation (RmuMainDestBaseAddress, (UINT32) RmuMainSrcBaseAddress, RmuMainSize); + QNCSendOpcodeDramReady (RmuMainDestBaseAddress); + EccScrubSetup (MrcData); + } +} + +/** + + Do memory initialisation for QNC DDR3 SDRAM Controller + + @param FfsHeader Not used. + @param PeiServices General purpose services available to every PEIM. + + @return EFI_SUCCESS Memory initialisation completed successfully. + All other error conditions encountered result in an ASSERT. + +**/ +EFI_STATUS +MemoryInit ( + IN EFI_PEI_SERVICES **PeiServices + ) +{ + MRC_PARAMS MrcData; + EFI_BOOT_MODE BootMode; + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices; + EFI_STATUS_CODE_VALUE ErrorCodeValue; + PEI_QNC_MEMORY_INIT_PPI *QncMemoryInitPpi; + UINT16 PmswAdr; + + ErrorCodeValue = 0; + + // + // It is critical that both of these data structures are initialized to 0. + // This PEIM knows the number of DIMMs in the system and works with that + // information. The MCH PEIM that consumes these data structures does not + // know the number of DIMMs so it expects the entire structure to be + // properly initialized. By initializing these to zero, all flags indicating + // that the SPD is present or the row should be configured are set to false. + // + ZeroMem (&MrcData, sizeof(MrcData)); + + // + // Get necessary PPI + // + Status = PeiServicesLocatePpi ( + &gEfiPeiReadOnlyVariable2PpiGuid, // GUID + 0, // INSTANCE + NULL, // EFI_PEI_PPI_DESCRIPTOR + (VOID **)&VariableServices // PPI + ); + ASSERT_EFI_ERROR (Status); + + // + // Determine boot mode + // + Status = PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + // + // Initialize Error type for reporting status code + // + switch (BootMode) { + case BOOT_ON_FLASH_UPDATE: + ErrorCodeValue = EFI_COMPUTING_UNIT_MEMORY + EFI_CU_MEMORY_EC_UPDATE_FAIL; + break; + case BOOT_ON_S3_RESUME: + ErrorCodeValue = EFI_COMPUTING_UNIT_MEMORY + EFI_CU_MEMORY_EC_S3_RESUME_FAIL; + break; + default: + ErrorCodeValue = EFI_COMPUTING_UNIT_MEMORY; + break; + } + + // + // Specify MRC boot mode + // + switch (BootMode) { + case BOOT_ON_S3_RESUME: + case BOOT_ON_FLASH_UPDATE: + MrcData.boot_mode = bmS3; + break; + case BOOT_ASSUMING_NO_CONFIGURATION_CHANGES: + MrcData.boot_mode = bmFast; + break; + default: + MrcData.boot_mode = bmCold; + break; + } + + // + // Configure MRC input parameters. + // + Status = MrcConfigureFromMcFuses (&MrcData); + ASSERT_EFI_ERROR (Status); + Status = MrcConfigureFromInfoHob (&MrcData); + ASSERT_EFI_ERROR (Status); + MrcUartConfig(&MrcData); + + if (BootMode == BOOT_IN_RECOVERY_MODE) { + // + // Always do bmCold on recovery. + // + DEBUG ((DEBUG_INFO, "MemoryInit:Force bmCold on Recovery\n")); + MrcData.boot_mode = bmCold; + } else { + + // + // Load Memory configuration data saved in previous boot from variable + // + Status = LoadConfig ( + PeiServices, + VariableServices, + &MrcData + ); + + if (EFI_ERROR (Status)) { + + switch (BootMode) { + case BOOT_ON_S3_RESUME: + case BOOT_ON_FLASH_UPDATE: + REPORT_STATUS_CODE ( + EFI_ERROR_CODE + EFI_ERROR_UNRECOVERED, + ErrorCodeValue + ); + PeiServicesResetSystem (); + break; + + default: + MrcData.boot_mode = bmCold; + break; + } + } + } + + // + // Locate Memory Reference Code PPI + // + Status = PeiServicesLocatePpi ( + &gQNCMemoryInitPpiGuid, // GUID + 0, // INSTANCE + NULL, // EFI_PEI_PPI_DESCRIPTOR + (VOID **)&QncMemoryInitPpi // PPI + ); + ASSERT_EFI_ERROR (Status); + + PmswAdr = (UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_PMSW; + if( IoRead32 (PmswAdr) & B_QNC_GPE0BLK_PMSW_DRAM_INIT) { + // MRC did not complete last execution, force cold boot path + MrcData.boot_mode = bmCold; + } + + // Mark MRC pending + IoOr32 (PmswAdr, (UINT32)B_QNC_GPE0BLK_PMSW_DRAM_INIT); + + // + // Call Memory Reference Code's Routines + // + QncMemoryInitPpi->MrcStart (&MrcData); + + // Mark MRC completed + IoAnd32 (PmswAdr, ~(UINT32)B_QNC_GPE0BLK_PMSW_DRAM_INIT); + + + // + // Note emulation platform has to read actual memory size + // MrcData.mem_size from PcdGet32 (PcdMemorySize); + + if (BootMode == BOOT_ON_S3_RESUME) { + + DEBUG ((EFI_D_INFO, "Following BOOT_ON_S3_RESUME boot path.\n")); + + Status = InstallS3Memory (PeiServices, VariableServices, MrcData.mem_size); + if (EFI_ERROR (Status)) { + REPORT_STATUS_CODE ( + EFI_ERROR_CODE + EFI_ERROR_UNRECOVERED, + ErrorCodeValue + ); + PeiServicesResetSystem (); + } + PostInstallMemory (&MrcData, TRUE); + return EFI_SUCCESS; + } + + // + // Assign physical memory to PEI and DXE + // + DEBUG ((EFI_D_INFO, "InstallEfiMemory.\n")); + + Status = InstallEfiMemory ( + PeiServices, + VariableServices, + BootMode, + MrcData.mem_size + ); + ASSERT_EFI_ERROR (Status); + + PostInstallMemory (&MrcData, FALSE); + + // + // Save current configuration into Hob and will save into Variable later in DXE + // + DEBUG ((EFI_D_INFO, "SaveConfig.\n")); + Status = SaveConfig ( + &MrcData + ); + ASSERT_EFI_ERROR (Status); + + DEBUG ((EFI_D_INFO, "MemoryInit Complete.\n")); + + return EFI_SUCCESS; +} + +/** + + This function saves a config to a HOB. + + @param RowInfo The MCH row configuration information. + @param TimingData Timing data to be saved. + @param RowConfArray Row configuration information for each row in the system. + @param SpdData SPD info read for each DIMM slot in the system. + + @return EFI_SUCCESS: The function completed successfully. + +**/ +EFI_STATUS +SaveConfig ( + IN MRC_PARAMS *MrcData + ) +{ + // + // Build HOB data for Memory Config + // HOB data size (stored in variable) is required to be multiple of 8 bytes + // + BuildGuidDataHob ( + &gEfiMemoryConfigDataGuid, + (VOID *) &MrcData->timings, + ((sizeof (MrcData->timings) + 0x7) & (~0x7)) + ); + + DEBUG ((EFI_D_INFO, "IIO IoApicBase = %x IoApicLimit=%x\n", IOAPIC_BASE, (IOAPIC_BASE + IOAPIC_SIZE - 1))); + DEBUG ((EFI_D_INFO, "IIO RcbaAddress = %x\n", (UINT32)PcdGet64 (PcdRcbaMmioBaseAddress))); + + return EFI_SUCCESS; +} + +/** + + Load a configuration stored in a variable. + + @param TimingData Timing data to be loaded from NVRAM. + @param RowConfArray Row configuration information for each row in the system. + + @return EFI_SUCCESS The function completed successfully. + Other Could not read variable. + +**/ +EFI_STATUS +LoadConfig ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices, + IN OUT MRC_PARAMS *MrcData + ) +{ + EFI_STATUS Status; + UINTN BufferSize; + PLATFORM_VARIABLE_MEMORY_CONFIG_DATA VarData; + + BufferSize = ((sizeof (VarData.timings) + 0x7) & (~0x7)); // HOB data size (stored in variable) is required to be multiple of 8bytes + + Status = VariableServices->GetVariable ( + VariableServices, + EFI_MEMORY_CONFIG_DATA_NAME, + &gEfiMemoryConfigDataGuid, + NULL, + &BufferSize, + &VarData.timings + ); + if (!EFI_ERROR (Status)) { + CopyMem (&MrcData->timings, &VarData.timings, sizeof(MrcData->timings)); + } + return Status; +} + +/** + + This function installs memory. + + @param PeiServices PEI Services table. + @param BootMode The specific boot path that is being followed + @param Mch Pointer to the DualChannelDdrMemoryInit PPI + @param RowConfArray Row configuration information for each row in the system. + + @return EFI_SUCCESS The function completed successfully. + EFI_INVALID_PARAMETER One of the input parameters was invalid. + EFI_ABORTED An error occurred. + +**/ +EFI_STATUS +InstallEfiMemory ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices, + IN EFI_BOOT_MODE BootMode, + IN UINT32 TotalMemorySize + ) +{ + EFI_PHYSICAL_ADDRESS PeiMemoryBaseAddress; + EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock; + EFI_STATUS Status; + EFI_PEI_HOB_POINTERS Hob; + PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE MemoryMap[MAX_RANGES]; + UINT8 Index; + UINT8 NumRanges; + UINT8 SmramIndex; + UINT8 SmramRanges; + UINT64 PeiMemoryLength; + UINTN BufferSize; + UINTN PeiMemoryIndex; + EFI_RESOURCE_ATTRIBUTE_TYPE Attribute; + EFI_PHYSICAL_ADDRESS BadMemoryAddress; + EFI_SMRAM_DESCRIPTOR DescriptorAcpiVariable; + VOID *CapsuleBuffer; + UINTN CapsuleBufferLength; + PEI_CAPSULE_PPI *Capsule; + VOID *LargeMemRangeBuf; + UINTN LargeMemRangeBufLen; + UINT8 MorControl; + UINTN DataSize; + + // + // Test the memory from 1M->TOM + // + if (BootMode != BOOT_ON_FLASH_UPDATE) { + Status = BaseMemoryTest ( + PeiServices, + 0x100000, + (TotalMemorySize - 0x100000), + Quick, + &BadMemoryAddress + ); + ASSERT_EFI_ERROR (Status); + } + + + // + // Get the Memory Map + // + NumRanges = MAX_RANGES; + + ZeroMem (MemoryMap, sizeof (PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE) * NumRanges); + + Status = GetMemoryMap ( + PeiServices, + TotalMemorySize, + (PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *) MemoryMap, + &NumRanges + ); + ASSERT_EFI_ERROR (Status); + + // + // Find the highest memory range in processor native address space to give to + // PEI. Then take the top. + // + PeiMemoryBaseAddress = 0; + + // + // Query the platform for the minimum memory size + // + + Status = GetPlatformMemorySize ( + PeiServices, + BootMode, + &PeiMemoryLength + ); + ASSERT_EFI_ERROR (Status); + + // + // Detect MOR request by the OS. + // + MorControl = 0; + DataSize = sizeof (MorControl); + Status = VariableServices->GetVariable ( + VariableServices, + MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME, + &gEfiMemoryOverwriteControlDataGuid, + NULL, + &DataSize, + &MorControl + ); + + PeiMemoryIndex = 0; + + for (Index = 0; Index < NumRanges; Index++) + { + DEBUG ((EFI_D_INFO, "Found 0x%x bytes at ", MemoryMap[Index].RangeLength)); + DEBUG ((EFI_D_INFO, "0x%x.\n", MemoryMap[Index].PhysicalAddress)); + + // + // If OS requested a memory overwrite perform it now. Only do it for memory + // used by the OS. + // + if (MOR_CLEAR_MEMORY_VALUE (MorControl) && MemoryMap[Index].Type == DualChannelDdrMainMemory) { + DEBUG ((EFI_D_INFO, "Clear memory per MOR request.\n")); + if ((UINTN)MemoryMap[Index].RangeLength > 0) { + if ((UINTN)MemoryMap[Index].PhysicalAddress == 0) { + // + // ZeroMem() generates an ASSERT() if Buffer parameter is NULL. + // Clear byte at 0 and start clear operation at address 1. + // + *(UINT8 *)(0) = 0; + ZeroMem ((VOID *)1, (UINTN)MemoryMap[Index].RangeLength - 1); + } else { + ZeroMem ( + (VOID *)(UINTN)MemoryMap[Index].PhysicalAddress, + (UINTN)MemoryMap[Index].RangeLength + ); + } + } + } + + if ((MemoryMap[Index].Type == DualChannelDdrMainMemory) && + (MemoryMap[Index].PhysicalAddress + MemoryMap[Index].RangeLength < MAX_ADDRESS) && + (MemoryMap[Index].PhysicalAddress >= PeiMemoryBaseAddress) && + (MemoryMap[Index].RangeLength >= PeiMemoryLength)) { + PeiMemoryBaseAddress = MemoryMap[Index].PhysicalAddress + + MemoryMap[Index].RangeLength - + PeiMemoryLength; + PeiMemoryIndex = Index; + } + } + + // + // Find the largest memory range excluding that given to PEI. + // + LargeMemRangeBuf = NULL; + LargeMemRangeBufLen = 0; + for (Index = 0; Index < NumRanges; Index++) { + if ((MemoryMap[Index].Type == DualChannelDdrMainMemory) && + (MemoryMap[Index].PhysicalAddress + MemoryMap[Index].RangeLength < MAX_ADDRESS)) { + if (Index != PeiMemoryIndex) { + if (MemoryMap[Index].RangeLength > LargeMemRangeBufLen) { + LargeMemRangeBuf = (VOID *) ((UINTN) MemoryMap[Index].PhysicalAddress); + LargeMemRangeBufLen = (UINTN) MemoryMap[Index].RangeLength; + } + } else { + if ((MemoryMap[Index].RangeLength - PeiMemoryLength) >= LargeMemRangeBufLen) { + LargeMemRangeBuf = (VOID *) ((UINTN) MemoryMap[Index].PhysicalAddress); + LargeMemRangeBufLen = (UINTN) (MemoryMap[Index].RangeLength - PeiMemoryLength); + } + } + } + } + + Capsule = NULL; + CapsuleBuffer = NULL; + CapsuleBufferLength = 0; + if (BootMode == BOOT_ON_FLASH_UPDATE) { + Status = PeiServicesLocatePpi ( + &gPeiCapsulePpiGuid, // GUID + 0, // INSTANCE + NULL, // EFI_PEI_PPI_DESCRIPTOR + (VOID **)&Capsule // PPI + ); + ASSERT_EFI_ERROR (Status); + + if (Status == EFI_SUCCESS) { + CapsuleBuffer = LargeMemRangeBuf; + CapsuleBufferLength = LargeMemRangeBufLen; + + // + // Call the Capsule PPI Coalesce function to coalesce the capsule data. + // + Status = Capsule->Coalesce ( + PeiServices, + &CapsuleBuffer, + &CapsuleBufferLength + ); + // + // If it failed, then NULL out our capsule PPI pointer so that the capsule + // HOB does not get created below. + // + if (Status != EFI_SUCCESS) { + Capsule = NULL; + } + } + } + + // + // Set up the IMR policy required for this platform + // + Status = SetPlatformImrPolicy ( + PeiMemoryBaseAddress, + PeiMemoryLength + ); + ASSERT_EFI_ERROR (Status); + + // + // Carve out the top memory reserved for ACPI + // + Status = PeiServicesInstallPeiMemory (PeiMemoryBaseAddress, PeiMemoryLength); + ASSERT_EFI_ERROR (Status); + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, // MemoryType, + ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_TESTED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE + ), + PeiMemoryBaseAddress, // MemoryBegin + PeiMemoryLength // MemoryLength + ); + + // + // Install physical memory descriptor hobs for each memory range. + // + SmramRanges = 0; + for (Index = 0; Index < NumRanges; Index++) { + Attribute = 0; + if (MemoryMap[Index].Type == DualChannelDdrMainMemory) + { + if (Index == PeiMemoryIndex) { + // + // This is a partially tested Main Memory range, give it to EFI + // + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE + ), + MemoryMap[Index].PhysicalAddress, + MemoryMap[Index].RangeLength - PeiMemoryLength + ); + } else { + // + // This is an untested Main Memory range, give it to EFI + // + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, // MemoryType, + ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE + ), + MemoryMap[Index].PhysicalAddress, // MemoryBegin + MemoryMap[Index].RangeLength // MemoryLength + ); + } + } else { + if ((MemoryMap[Index].Type == DualChannelDdrSmramCacheable) || + (MemoryMap[Index].Type == DualChannelDdrSmramNonCacheable)) { + SmramRanges++; + } + if ((MemoryMap[Index].Type == DualChannelDdrSmramNonCacheable) || + (MemoryMap[Index].Type == DualChannelDdrGraphicsMemoryNonCacheable)) { + Attribute |= EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE; + } + if ((MemoryMap[Index].Type == DualChannelDdrSmramCacheable) || + (MemoryMap[Index].Type == DualChannelDdrGraphicsMemoryCacheable)) { + // + // TSEG and HSEG can be used with a write-back(WB) cache policy; however, + // the specification requires that the TSEG and HSEG space be cached only + // inside of the SMI handler. when using HSEG or TSEG an IA-32 processor + // does not automatically write back and invalidate its cache before entering + // SMM or before existing SMM therefore any MTRR defined for the active TSEG + // or HSEG must be set to un-cacheable(UC) outside of SMM. + // + Attribute |= EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE; + } + if (MemoryMap[Index].Type == DualChannelDdrReservedMemory) { + Attribute |= EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE; + } + // + // Make sure non-system memory is marked as reserved + // + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_RESERVED, // MemoryType, + Attribute, // MemoryAttribute + MemoryMap[Index].PhysicalAddress, // MemoryBegin + MemoryMap[Index].RangeLength // MemoryLength + ); + } + } + + // + // Allocate one extra EFI_SMRAM_DESCRIPTOR to describe a page of SMRAM memory that contains a pointer + // to the SMM Services Table that is required on the S3 resume path + // + ASSERT (SmramRanges > 0); + BufferSize = sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK); + BufferSize += ((SmramRanges - 1) * sizeof (EFI_SMRAM_DESCRIPTOR)); + + Hob.Raw = BuildGuidHob ( + &gEfiSmmPeiSmramMemoryReserveGuid, + BufferSize + ); + ASSERT (Hob.Raw); + + SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Hob.Raw); + SmramHobDescriptorBlock->NumberOfSmmReservedRegions = SmramRanges; + + SmramIndex = 0; + for (Index = 0; Index < NumRanges; Index++) { + if ((MemoryMap[Index].Type == DualChannelDdrSmramCacheable) || + (MemoryMap[Index].Type == DualChannelDdrSmramNonCacheable) + ) { + // + // This is an SMRAM range, create an SMRAM descriptor + // + SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalStart = MemoryMap[Index].PhysicalAddress; + SmramHobDescriptorBlock->Descriptor[SmramIndex].CpuStart = MemoryMap[Index].CpuAddress; + SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalSize = MemoryMap[Index].RangeLength; + if (MemoryMap[Index].Type == DualChannelDdrSmramCacheable) { + SmramHobDescriptorBlock->Descriptor[SmramIndex].RegionState = EFI_SMRAM_CLOSED | EFI_CACHEABLE; + } else { + SmramHobDescriptorBlock->Descriptor[SmramIndex].RegionState = EFI_SMRAM_CLOSED; + } + + SmramIndex++; + } + } + + // + // Build a HOB with the location of the reserved memory range. + // + CopyMem(&DescriptorAcpiVariable, &SmramHobDescriptorBlock->Descriptor[SmramRanges-1], sizeof(EFI_SMRAM_DESCRIPTOR)); + DescriptorAcpiVariable.CpuStart += RESERVED_CPU_S3_SAVE_OFFSET; + BuildGuidDataHob ( + &gEfiAcpiVariableGuid, + &DescriptorAcpiVariable, + sizeof (EFI_SMRAM_DESCRIPTOR) + ); + + // + // If we found the capsule PPI (and we didn't have errors), then + // call the capsule PEIM to allocate memory for the capsule. + // + if (Capsule != NULL) { + Status = Capsule->CreateState (PeiServices, CapsuleBuffer, CapsuleBufferLength); + } + + return EFI_SUCCESS; +} + +/** + + Find memory that is reserved so PEI has some to use. + + @param PeiServices PEI Services table. + @param VariableSevices Variable PPI instance. + + @return EFI_SUCCESS The function completed successfully. + Error value from LocatePpi() + Error Value from VariableServices->GetVariable() + +**/ +EFI_STATUS +InstallS3Memory ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices, + IN UINT32 TotalMemorySize + ) +{ + EFI_STATUS Status; + UINTN S3MemoryBase; + UINTN S3MemorySize; + UINT8 SmramRanges; + UINT8 NumRanges; + UINT8 Index; + UINT8 SmramIndex; + UINTN BufferSize; + EFI_PEI_HOB_POINTERS Hob; + EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock; + PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE MemoryMap[MAX_RANGES]; + RESERVED_ACPI_S3_RANGE *S3MemoryRangeData; + EFI_SMRAM_DESCRIPTOR DescriptorAcpiVariable; + + // + // Get the Memory Map + // + NumRanges = MAX_RANGES; + + ZeroMem (MemoryMap, sizeof (PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE) * NumRanges); + + Status = GetMemoryMap ( + PeiServices, + TotalMemorySize, + (PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *) MemoryMap, + &NumRanges + ); + ASSERT_EFI_ERROR (Status); + + // + // Install physical memory descriptor hobs for each memory range. + // + SmramRanges = 0; + for (Index = 0; Index < NumRanges; Index++) { + if ((MemoryMap[Index].Type == DualChannelDdrSmramCacheable) || + (MemoryMap[Index].Type == DualChannelDdrSmramNonCacheable)) { + SmramRanges++; + } + } + + ASSERT (SmramRanges > 0); + + // + // Allocate one extra EFI_SMRAM_DESCRIPTOR to describe a page of SMRAM memory that contains a pointer + // to the SMM Services Table that is required on the S3 resume path + // + BufferSize = sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK); + if (SmramRanges > 0) { + BufferSize += ((SmramRanges - 1) * sizeof (EFI_SMRAM_DESCRIPTOR)); + } + + Hob.Raw = BuildGuidHob ( + &gEfiSmmPeiSmramMemoryReserveGuid, + BufferSize + ); + ASSERT (Hob.Raw); + + SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Hob.Raw); + SmramHobDescriptorBlock->NumberOfSmmReservedRegions = SmramRanges; + + SmramIndex = 0; + for (Index = 0; Index < NumRanges; Index++) { + if ((MemoryMap[Index].Type == DualChannelDdrSmramCacheable) || + (MemoryMap[Index].Type == DualChannelDdrSmramNonCacheable) + ) { + // + // This is an SMRAM range, create an SMRAM descriptor + // + SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalStart = MemoryMap[Index].PhysicalAddress; + SmramHobDescriptorBlock->Descriptor[SmramIndex].CpuStart = MemoryMap[Index].CpuAddress; + SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalSize = MemoryMap[Index].RangeLength; + if (MemoryMap[Index].Type == DualChannelDdrSmramCacheable) { + SmramHobDescriptorBlock->Descriptor[SmramIndex].RegionState = EFI_SMRAM_CLOSED | EFI_CACHEABLE; + } else { + SmramHobDescriptorBlock->Descriptor[SmramIndex].RegionState = EFI_SMRAM_CLOSED; + } + + SmramIndex++; + } + } + + // + // Build a HOB with the location of the reserved memory range. + // + CopyMem(&DescriptorAcpiVariable, &SmramHobDescriptorBlock->Descriptor[SmramRanges-1], sizeof(EFI_SMRAM_DESCRIPTOR)); + DescriptorAcpiVariable.CpuStart += RESERVED_CPU_S3_SAVE_OFFSET; + BuildGuidDataHob ( + &gEfiAcpiVariableGuid, + &DescriptorAcpiVariable, + sizeof (EFI_SMRAM_DESCRIPTOR) + ); + + // + // Get the location and size of the S3 memory range in the reserved page and + // install it as PEI Memory. + // + + DEBUG ((EFI_D_INFO, "TSEG Base = 0x%08x\n", SmramHobDescriptorBlock->Descriptor[SmramRanges-1].PhysicalStart)); + S3MemoryRangeData = (RESERVED_ACPI_S3_RANGE*)(UINTN) + (SmramHobDescriptorBlock->Descriptor[SmramRanges-1].PhysicalStart + RESERVED_ACPI_S3_RANGE_OFFSET); + + S3MemoryBase = (UINTN) (S3MemoryRangeData->AcpiReservedMemoryBase); + DEBUG ((EFI_D_INFO, "S3MemoryBase = 0x%08x\n", S3MemoryBase)); + S3MemorySize = (UINTN) (S3MemoryRangeData->AcpiReservedMemorySize); + DEBUG ((EFI_D_INFO, "S3MemorySize = 0x%08x\n", S3MemorySize)); + + Status = PeiServicesInstallPeiMemory (S3MemoryBase, S3MemorySize); + ASSERT_EFI_ERROR (Status); + + // + // Retrieve the system memory length and build memory hob for the system + // memory above 1MB. So Memory Callback can set cache for the system memory + // correctly on S3 boot path, just like it does on Normal boot path. + // + ASSERT ((S3MemoryRangeData->SystemMemoryLength - 0x100000) > 0); + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE + ), + 0x100000, + S3MemoryRangeData->SystemMemoryLength - 0x100000 + ); + + for (Index = 0; Index < NumRanges; Index++) { + if ((MemoryMap[Index].Type == DualChannelDdrMainMemory) && + (MemoryMap[Index].PhysicalAddress + MemoryMap[Index].RangeLength < 0x100000)) { + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE + ), + MemoryMap[Index].PhysicalAddress, + MemoryMap[Index].RangeLength + ); + DEBUG ((EFI_D_INFO, "Build resource HOB for Legacy Region on S3 patch :")); + DEBUG ((EFI_D_INFO, " Memory Base:0x%lX Length:0x%lX\n", MemoryMap[Index].PhysicalAddress, MemoryMap[Index].RangeLength)); + } + } + + return EFI_SUCCESS; +} + +/** + + This function returns the memory ranges to be enabled, along with information + describing how the range should be used. + + @param PeiServices PEI Services Table. + @param TimingData Detected DDR timing parameters for installed memory. + @param RowConfArray Pointer to an array of EFI_DUAL_CHANNEL_DDR_ROW_CONFIG structures. The number + of items in the array must match MaxRows returned by the McGetRowInfo() function. + @param MemoryMap Buffer to record details of the memory ranges tobe enabled. + @param NumRanges On input, this contains the maximum number of memory ranges that can be described + in the MemoryMap buffer. + + @return MemoryMap The buffer will be filled in + NumRanges will contain the actual number of memory ranges that are to be anabled. + EFI_SUCCESS The function completed successfully. + +**/ +EFI_STATUS +GetMemoryMap ( + IN EFI_PEI_SERVICES **PeiServices, + IN UINT32 TotalMemorySize, + IN OUT PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *MemoryMap, + IN OUT UINT8 *NumRanges + ) +{ + EFI_PHYSICAL_ADDRESS MemorySize; + EFI_PHYSICAL_ADDRESS RowLength; + EFI_STATUS Status; + PEI_MEMORY_RANGE_PCI_MEMORY PciMemoryMask; + PEI_MEMORY_RANGE_OPTION_ROM OptionRomMask; + PEI_MEMORY_RANGE_SMRAM SmramMask; + PEI_MEMORY_RANGE_SMRAM TsegMask; + UINT32 BlockNum; + UINT8 ExtendedMemoryIndex; + UINT32 Register; + + if ((*NumRanges) < MAX_RANGES) { + return EFI_BUFFER_TOO_SMALL; + } + + *NumRanges = 0; + + // + // Find out which memory ranges to reserve on this platform + // + Status = ChooseRanges ( + &OptionRomMask, + &SmramMask, + &PciMemoryMask + ); + ASSERT_EFI_ERROR (Status); + + // + // Generate Memory ranges for the memory map. + // + MemorySize = 0; + + RowLength = TotalMemorySize; + + // + // Add memory below 640KB to the memory map. Make sure memory between + // 640KB and 1MB are reserved, even if not used for SMRAM + // + MemoryMap[*NumRanges].PhysicalAddress = MemorySize; + MemoryMap[*NumRanges].CpuAddress = MemorySize; + MemoryMap[*NumRanges].RangeLength = 0xA0000; + MemoryMap[*NumRanges].Type = DualChannelDdrMainMemory; + (*NumRanges)++; + + // + // Just mark this range reserved + // + MemoryMap[*NumRanges].PhysicalAddress = 0xA0000; + MemoryMap[*NumRanges].CpuAddress = 0xA0000; + MemoryMap[*NumRanges].RangeLength = 0x60000; + MemoryMap[*NumRanges].Type = DualChannelDdrReservedMemory; + (*NumRanges)++; + + RowLength -= (0x100000 - MemorySize); + MemorySize = 0x100000; + + // + // Add remaining memory to the memory map + // + MemoryMap[*NumRanges].PhysicalAddress = MemorySize; + MemoryMap[*NumRanges].CpuAddress = MemorySize; + MemoryMap[*NumRanges].RangeLength = RowLength; + MemoryMap[*NumRanges].Type = DualChannelDdrMainMemory; + (*NumRanges)++; + MemorySize += RowLength; + + ExtendedMemoryIndex = (UINT8) (*NumRanges - 1); + + // See if we need to trim TSEG out of the highest memory range + // + if (SmramMask & PEI_MR_SMRAM_TSEG_MASK) {//pcd + // + // Create the new range for TSEG and remove that range from the previous SdrDdrMainMemory range + // + TsegMask = (SmramMask & PEI_MR_SMRAM_SIZE_MASK); + + BlockNum = 1; + while (TsegMask) { + TsegMask >>= 1; + BlockNum <<= 1; + } + + BlockNum >>= 1; + + if (BlockNum) { + + MemoryMap[*NumRanges].RangeLength = (BlockNum * 128 * 1024); + Register = (UINT32)((MemorySize - 1) & SMM_END_MASK); + MemorySize -= MemoryMap[*NumRanges].RangeLength; + MemoryMap[*NumRanges].PhysicalAddress = MemorySize; + MemoryMap[*NumRanges].CpuAddress = MemorySize; + MemoryMap[ExtendedMemoryIndex].RangeLength -= MemoryMap[*NumRanges].RangeLength; + + // + // Update QuarkNcSoc HSMMCTL register + // + Register |= (UINT32)(((RShiftU64(MemorySize, 16)) & SMM_START_MASK) + (SMM_WRITE_OPEN | SMM_READ_OPEN | SMM_CODE_RD_OPEN)); + QncHsmmcWrite (Register); + } + + // + // Chipset only supports cacheable SMRAM + // + MemoryMap[*NumRanges].Type = DualChannelDdrSmramCacheable; + + (*NumRanges)++; + } + + // + // trim 64K memory from highest memory range for Rmu Main binary shadow + // + MemoryMap[*NumRanges].RangeLength = 0x10000; + MemorySize -= MemoryMap[*NumRanges].RangeLength; + MemoryMap[*NumRanges].PhysicalAddress = MemorySize; + MemoryMap[*NumRanges].CpuAddress = MemorySize; + MemoryMap[ExtendedMemoryIndex].RangeLength -= MemoryMap[*NumRanges].RangeLength; + MemoryMap[*NumRanges].Type = DualChannelDdrReservedMemory; + (*NumRanges)++; + + return EFI_SUCCESS; +} + +/** + +Routine Description: + + Fill in bit masks to specify reserved memory ranges on the Lakeport platform + +Arguments: + +Returns: + + OptionRomMask - Bit mask specifying memory regions reserved for Legacy option + ROM use (if any) + + SmramMask - Bit mask specifying memory regions reserved for SMM use (if any) + +**/ +EFI_STATUS +ChooseRanges ( + IN OUT PEI_MEMORY_RANGE_OPTION_ROM *OptionRomMask, + IN OUT PEI_MEMORY_RANGE_SMRAM *SmramMask, + IN OUT PEI_MEMORY_RANGE_PCI_MEMORY *PciMemoryMask + ) +{ + + // + // Choose regions to reserve for Option ROM use + // + *OptionRomMask = PEI_MR_OPTION_ROM_NONE; + + // + // Choose regions to reserve for SMM use (AB/H SEG and TSEG). Size is in 128K blocks + // + *SmramMask = PEI_MR_SMRAM_CACHEABLE_MASK | PEI_MR_SMRAM_TSEG_MASK | ((PcdGet32(PcdTSegSize)) >> 17); + + *PciMemoryMask = 0; + + return EFI_SUCCESS; +} + +EFI_STATUS +GetPlatformMemorySize ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_BOOT_MODE BootMode, + IN OUT UINT64 *MemorySize + ) +{ + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable; + UINTN DataSize; + EFI_MEMORY_TYPE_INFORMATION MemoryData [EfiMaxMemoryType + 1]; + UINTN Index; + + DataSize = sizeof (MemoryData); + + if (BootMode == BOOT_IN_RECOVERY_MODE) { + + // + // // Treat recovery as if variable not found (eg 1st boot). + // + Status = EFI_NOT_FOUND; + + } else { + Status = PeiServicesLocatePpi ( + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + (VOID **)&Variable + ); + + ASSERT_EFI_ERROR (Status); + + DataSize = sizeof (MemoryData); + Status = Variable->GetVariable ( + Variable, + EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME, + &gEfiMemoryTypeInformationGuid, + NULL, + &DataSize, + &MemoryData + ); + } + + // + // Accumulate maximum amount of memory needed + // + if (EFI_ERROR (Status)) { + // + // Start with minimum memory + // + *MemorySize = PEI_MIN_MEMORY_SIZE; + + for (Index = 0; Index < sizeof(mDefaultQncMemoryTypeInformation) / sizeof (EFI_MEMORY_TYPE_INFORMATION); Index++) { + *MemorySize += mDefaultQncMemoryTypeInformation[Index].NumberOfPages * EFI_PAGE_SIZE; + } + + // + // Build the GUID'd HOB for DXE + // + BuildGuidDataHob ( + &gEfiMemoryTypeInformationGuid, + mDefaultQncMemoryTypeInformation, + sizeof(mDefaultQncMemoryTypeInformation) + ); + } else { + // + // Start with at least PEI_MIN_MEMORY_SIZE pages of memory for the DXE Core and the DXE Stack + // + + *MemorySize = PEI_MIN_MEMORY_SIZE; + for (Index = 0; Index < DataSize / sizeof (EFI_MEMORY_TYPE_INFORMATION); Index++) { + DEBUG ((EFI_D_INFO, "Index %d, Page: %d\n", Index, MemoryData[Index].NumberOfPages)); + *MemorySize += MemoryData[Index].NumberOfPages * EFI_PAGE_SIZE; + } + + // + // Build the GUID'd HOB for DXE + // + BuildGuidDataHob ( + &gEfiMemoryTypeInformationGuid, + MemoryData, + DataSize + ); + + } + + return EFI_SUCCESS; +} + + +EFI_STATUS +BaseMemoryTest ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS BeginAddress, + IN UINT64 MemoryLength, + IN PEI_MEMORY_TEST_OP Operation, + OUT EFI_PHYSICAL_ADDRESS *ErrorAddress + ) +{ + UINT32 TestPattern; + EFI_PHYSICAL_ADDRESS TempAddress; + UINT32 SpanSize; + + TestPattern = 0x5A5A5A5A; + SpanSize = 0; + + // + // Make sure we don't try and test anything above the max physical address range + // + ASSERT (BeginAddress + MemoryLength < MAX_ADDRESS); + + switch (Operation) { + case Extensive: + SpanSize = 0x4; + break; + + case Sparse: + case Quick: + SpanSize = 0x40000; + break; + + case Ignore: + goto Done; + break; + } + // + // Write the test pattern into memory range + // + TempAddress = BeginAddress; + while (TempAddress < BeginAddress + MemoryLength) { + (*(UINT32 *) (UINTN) TempAddress) = TestPattern; + TempAddress += SpanSize; + } + // + // Read pattern from memory and compare it + // + TempAddress = BeginAddress; + while (TempAddress < BeginAddress + MemoryLength) { + if ((*(UINT32 *) (UINTN) TempAddress) != TestPattern) { + *ErrorAddress = TempAddress; + DEBUG ((EFI_D_ERROR, "Memory test failed at 0x%x.\n", TempAddress)); + return EFI_DEVICE_ERROR; + } + + TempAddress += SpanSize; + } + +Done: + return EFI_SUCCESS; +} + +/** + + This function sets up the platform specific IMR protection for the various + memory regions. + + @param PeiMemoryBaseAddress Base address of memory allocated for PEI. + @param PeiMemoryLength Length in bytes of the PEI memory (includes ACPI memory). + + @return EFI_SUCCESS The function completed successfully. + EFI_ACCESS_DENIED Access to IMRs failed. + +**/ +EFI_STATUS +SetPlatformImrPolicy ( + IN EFI_PHYSICAL_ADDRESS PeiMemoryBaseAddress, + IN UINT64 PeiMemoryLength + ) +{ + UINT8 Index; + UINT32 Register; + UINT16 DeviceId; + + // + // Check what Soc we are running on (read Host bridge DeviceId) + // + DeviceId = QNCMmPci16(0, MC_BUS, MC_DEV, MC_FUN, PCI_DEVICE_ID_OFFSET); + + // + // If any IMR register is locked then we cannot proceed + // + for (Index = (QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXL); Index <=(QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXL); Index=Index+4) + { + Register = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, Index); + if (Register & IMR_LOCK) { + return EFI_ACCESS_DENIED; + } + } + + // + // Add IMR2 protection for shadowed RMU binary. + // + QncImrWrite ( + QUARK_NC_MEMORY_MANAGER_IMR2, + (UINT32)(((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength), 8)) & IMRH_MASK) | IMR_EN), + (UINT32)((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength+PcdGet32(PcdFlashQNCMicrocodeSize)-1), 8)) & IMRH_MASK), + (UINT32)(CPU_SNOOP + RMU + CPU0_NON_SMM), + (UINT32)(CPU_SNOOP + RMU + CPU0_NON_SMM) + ); + + // + // Add IMR3 protection for the default SMRAM. + // + QncImrWrite ( + QUARK_NC_MEMORY_MANAGER_IMR3, + (UINT32)(((RShiftU64((SMM_DEFAULT_SMBASE), 8)) & IMRL_MASK) | IMR_EN), + (UINT32)((RShiftU64((SMM_DEFAULT_SMBASE+SMM_DEFAULT_SMBASE_SIZE_BYTES-1), 8)) & IMRH_MASK), + (UINT32)(CPU_SNOOP + CPU0_NON_SMM), + (UINT32)(CPU_SNOOP + CPU0_NON_SMM) + ); + + // + // Enable IMR4 protection of eSRAM. + // + QncImrWrite ( + QUARK_NC_MEMORY_MANAGER_IMR4, + (UINT32)(((RShiftU64((UINTN)PcdGet32 (PcdEsramStage1Base), 8)) & IMRL_MASK) | IMR_EN), + (UINT32)((RShiftU64(((UINTN)PcdGet32 (PcdEsramStage1Base) + (UINTN)PcdGet32 (PcdESramMemorySize) - 1), 8)) & IMRH_MASK), + (UINT32)(CPU_SNOOP + CPU0_NON_SMM), + (UINT32)(CPU_SNOOP + CPU0_NON_SMM) + ); + + // + // Enable Interrupt on IMR/SMM Violation + // + QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_BIMRVCTL, (UINT32)(EnableIMRInt)); + if (DeviceId == QUARK2_MC_DEVICE_ID) { + QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_BSMMVCTL, (UINT32)(EnableSMMInt)); + } + + // + // Disable IMR7 memory protection (eSRAM + DDR3 memory) since our policies + // are now setup. + // + QncImrWrite ( + QUARK_NC_MEMORY_MANAGER_IMR7, + (UINT32)(IMRL_RESET & ~IMR_EN), + (UINT32)IMRH_RESET, + (UINT32)IMRX_ALL_ACCESS, + (UINT32)IMRX_ALL_ACCESS + ); + + return EFI_SUCCESS; +} + +/** Return info derived from Installing Memory by MemoryInit. + + @param[out] RmuMainBaseAddressPtr Return RmuMainBaseAddress to this location. + @param[out] SmramDescriptorPtr Return start of Smram descriptor list to this location. + @param[out] NumSmramRegionsPtr Return numbers of Smram regions to this location. + + @return Address of RMU shadow region at the top of available memory. + @return List of Smram descriptors for each Smram region. + @return Numbers of Smram regions. +**/ +VOID +EFIAPI +InfoPostInstallMemory ( + OUT UINT32 *RmuMainBaseAddressPtr OPTIONAL, + OUT EFI_SMRAM_DESCRIPTOR **SmramDescriptorPtr OPTIONAL, + OUT UINTN *NumSmramRegionsPtr OPTIONAL + ) +{ + EFI_STATUS Status; + EFI_PEI_HOB_POINTERS Hob; + UINT64 CalcLength; + EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock; + + if ((RmuMainBaseAddressPtr == NULL) && (SmramDescriptorPtr == NULL) && (NumSmramRegionsPtr == NULL)) { + return; + } + + SmramHobDescriptorBlock = NULL; + if (SmramDescriptorPtr != NULL) { + *SmramDescriptorPtr = NULL; + } + if (NumSmramRegionsPtr != NULL) { + *NumSmramRegionsPtr = 0; + } + + // + // Calculate RMU shadow region base address. + // Set to 1 MB. Since 1MB cacheability will always be set + // until override by CSM. + // + CalcLength = 0x100000; + + Status = PeiServicesGetHobList ((VOID **) &Hob.Raw); + ASSERT_EFI_ERROR (Status); + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) { + // + // Skip the memory region below 1MB + // + if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) { + CalcLength += (UINT64) (Hob.ResourceDescriptor->ResourceLength); + } + } + } else if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION) { + if (CompareGuid (&(Hob.Guid->Name), &gEfiSmmPeiSmramMemoryReserveGuid)) { + SmramHobDescriptorBlock = (VOID*) (Hob.Raw + sizeof (EFI_HOB_GUID_TYPE)); + if (SmramDescriptorPtr != NULL) { + *SmramDescriptorPtr = SmramHobDescriptorBlock->Descriptor; + } + if (NumSmramRegionsPtr != NULL) { + *NumSmramRegionsPtr = SmramHobDescriptorBlock->NumberOfSmmReservedRegions; + } + } + } + Hob.Raw = GET_NEXT_HOB (Hob); + } + + if (RmuMainBaseAddressPtr != NULL) { + *RmuMainBaseAddressPtr = (UINT32) CalcLength; + } +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.h b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.h new file mode 100644 index 0000000000..e24eb4b475 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.h @@ -0,0 +1,225 @@ +/** @file +Framework PEIM to initialize memory on an DDR2 SDRAM Memory Controller. + +Copyright (c) 2013 - 2016 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MRC_WRAPPER_H +#define _MRC_WRAPPER_H + +#include +#include "PlatformEarlyInit.h" + +// +// Define the default memory areas required +// +#define EDKII_RESERVED_SIZE_PAGES 0x20 +#define ACPI_NVS_SIZE_PAGES 0x60 +#define RUNTIME_SERVICES_DATA_SIZE_PAGES 0x20 +#define RUNTIME_SERVICES_CODE_SIZE_PAGES 0x80 +#define ACPI_RECLAIM_SIZE_PAGES 0x20 +#define EDKII_DXE_MEM_SIZE_PAGES 0x20 + +// +// Maximum number of "Socket Sets", where a "Socket Set is a set of matching +// DIMM's from the various channels +// +#define MAX_SOCKET_SETS 2 + +// +// Maximum number of memory ranges supported by the memory controller +// +#define MAX_RANGES (MAX_ROWS + 5) + +// +// Min. of 48MB PEI phase +// +#define PEI_MIN_MEMORY_SIZE (6 * 0x800000) +#define PEI_RECOVERY_MIN_MEMORY_SIZE (6 * 0x800000) + +#define PEI_MEMORY_RANGE_OPTION_ROM UINT32 +#define PEI_MR_OPTION_ROM_NONE 0x00000000 + +// +// SMRAM Memory Range +// +#define PEI_MEMORY_RANGE_SMRAM UINT32 +#define PEI_MR_SMRAM_ALL 0xFFFFFFFF +#define PEI_MR_SMRAM_NONE 0x00000000 +#define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000 +#define PEI_MR_SMRAM_SEGTYPE_MASK 0x00FF0000 +#define PEI_MR_SMRAM_ABSEG_MASK 0x00010000 +#define PEI_MR_SMRAM_HSEG_MASK 0x00020000 +#define PEI_MR_SMRAM_TSEG_MASK 0x00040000 +// +// SMRAM Size is a multiple of 128KB. +// +#define PEI_MR_SMRAM_SIZE_MASK 0x0000FFFF + +// +// Pci Memory Hole +// +#define PEI_MEMORY_RANGE_PCI_MEMORY UINT32 + +typedef enum { + Ignore, + Quick, + Sparse, + Extensive +} PEI_MEMORY_TEST_OP; + +// +// MRC Params Variable structure. +// + +typedef struct { + MrcTimings_t timings; // Actual MRC config values saved in variable store. + UINT8 VariableStorePad[8]; // Allow for data stored in variable is required to be multiple of 8bytes. +} PLATFORM_VARIABLE_MEMORY_CONFIG_DATA; + +/// +/// MRC Params Platform Data Flags bits +/// +#define PDAT_MRC_FLAG_ECC_EN BIT0 +#define PDAT_MRC_FLAG_SCRAMBLE_EN BIT1 +#define PDAT_MRC_FLAG_MEMTEST_EN BIT2 +#define PDAT_MRC_FLAG_TOP_TREE_EN BIT3 ///< 0b DDR "fly-by" topology else 1b DDR "tree" topology. +#define PDAT_MRC_FLAG_WR_ODT_EN BIT4 ///< If set ODR signal is asserted to DRAM devices on writes. + +/// +/// MRC Params Platform Data. +/// +typedef struct { + UINT32 Flags; ///< Bitmap of PDAT_MRC_FLAG_XXX defs above. + UINT8 DramWidth; ///< 0=x8, 1=x16, others=RESERVED. + UINT8 DramSpeed; ///< 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory. + UINT8 DramType; ///< 0=DDR3,1=DDR3L, others=RESERVED. + UINT8 RankMask; ///< bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED. + UINT8 ChanMask; ///< bit[0] CHAN0_EN, others=RESERVED. + UINT8 ChanWidth; ///< 1=x16, others=RESERVED. + UINT8 AddrMode; ///< 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED. + UINT8 SrInt; ///< 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE. + UINT8 SrTemp; ///< 0=normal, 1=extended, others=RESERVED. + UINT8 DramRonVal; ///< 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control. + UINT8 DramRttNomVal; ///< 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED. + UINT8 DramRttWrVal; ///< 0=off others=RESERVED. + UINT8 SocRdOdtVal; ///< 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED. + UINT8 SocWrRonVal; ///< 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED. + UINT8 SocWrSlewRate; ///< 0=2.5V/ns, 1=4V/ns, others=RESERVED. + UINT8 DramDensity; ///< 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED. + UINT32 tRAS; ///< ACT to PRE command period in picoseconds. + UINT32 tWTR; ///< Delay from start of internal write transaction to internal read command in picoseconds. + UINT32 tRRD; ///< ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds. + UINT32 tFAW; ///< Four activate window (JESD79 specific to page size 1K/2K) in picoseconds. + UINT8 tCL; ///< DRAM CAS Latency in clocks. +} PDAT_MRC_ITEM; + +// +// Memory range types +// +typedef enum { + DualChannelDdrMainMemory, + DualChannelDdrSmramCacheable, + DualChannelDdrSmramNonCacheable, + DualChannelDdrGraphicsMemoryCacheable, + DualChannelDdrGraphicsMemoryNonCacheable, + DualChannelDdrReservedMemory, + DualChannelDdrMaxMemoryRangeType +} PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE; + +// +// Memory map range information +// +typedef struct { + EFI_PHYSICAL_ADDRESS PhysicalAddress; + EFI_PHYSICAL_ADDRESS CpuAddress; + EFI_PHYSICAL_ADDRESS RangeLength; + PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE Type; +} PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE; + +// +// Function prototypes. +// + +EFI_STATUS +InstallEfiMemory ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices, + IN EFI_BOOT_MODE BootMode, + IN UINT32 TotalMemorySize + ); + +EFI_STATUS +InstallS3Memory ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices, + IN UINT32 TotalMemorySize + ); + +EFI_STATUS +MemoryInit ( + IN EFI_PEI_SERVICES **PeiServices + ); + + +EFI_STATUS +LoadConfig ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices, + IN OUT MRCParams_t *MrcData + ); + +EFI_STATUS +SaveConfig ( + IN MRCParams_t *MrcData + ); + +EFI_STATUS +GetMemoryMap ( + IN EFI_PEI_SERVICES **PeiServices, + IN UINT32 TotalMemorySize, + IN OUT PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *MemoryMap, + IN OUT UINT8 *NumRanges + ); + +EFI_STATUS +ChooseRanges ( + IN OUT PEI_MEMORY_RANGE_OPTION_ROM *OptionRomMask, + IN OUT PEI_MEMORY_RANGE_SMRAM *SmramMask, + IN OUT PEI_MEMORY_RANGE_PCI_MEMORY *PciMemoryMask + ); + +EFI_STATUS +GetPlatformMemorySize ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_BOOT_MODE BootMode, + IN OUT UINT64 *MemorySize + ); + +EFI_STATUS +BaseMemoryTest ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS BeginAddress, + IN UINT64 MemoryLength, + IN PEI_MEMORY_TEST_OP Operation, + OUT EFI_PHYSICAL_ADDRESS *ErrorAddress + ); + +EFI_STATUS +SetPlatformImrPolicy ( + IN EFI_PHYSICAL_ADDRESS PeiMemoryBaseAddress, + IN UINT64 PeiMemoryLength + ); + +VOID +EFIAPI +InfoPostInstallMemory ( + OUT UINT32 *RmuBaseAddressPtr OPTIONAL, + OUT EFI_SMRAM_DESCRIPTOR **SmramDescriptorPtr OPTIONAL, + OUT UINTN *NumSmramRegionsPtr OPTIONAL + ); + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/PeiFvSecurity.c b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/PeiFvSecurity.c new file mode 100644 index 0000000000..f94d3ca567 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/PeiFvSecurity.c @@ -0,0 +1,111 @@ +/** @file +EFI PEI Platform Security services + +Copyright (c) 2013 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PeiFvSecurity.h" + +EFI_PEI_NOTIFY_DESCRIPTOR mNotifyOnFvInfoSecurityList = { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiFirmwareVolumeInfoPpiGuid, + FirmwareVolmeInfoPpiNotifySecurityCallback +}; + +/** + Callback function to perform FV security checking on a FV Info PPI. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation + @param NotifyDescriptor Address of the notification descriptor data structure. + @param Ppi Address of the PPI that was installed. + + @retval EFI_SUCCESS + +**/ +EFI_STATUS +EFIAPI +FirmwareVolmeInfoPpiNotifySecurityCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + EFI_PEI_FIRMWARE_VOLUME_INFO_PPI *FvInfoPpi; + EFI_PEI_FIRMWARE_VOLUME_PPI *FvPpi; + + FvInfoPpi = (EFI_PEI_FIRMWARE_VOLUME_INFO_PPI *)Ppi; + + // + // Locate the corresponding FV_PPI according to founded FV's format guid + // + Status = PeiServicesLocatePpi ( + &FvInfoPpi->FvFormat, + 0, + NULL, + (VOID**)&FvPpi + ); + ASSERT_EFI_ERROR (Status); + + // + // Only authenticate parent Firmware Volume (child firmware volumes are covered by the parent) + // + if ((VOID *)FvInfoPpi->ParentFvName == NULL && (VOID *)FvInfoPpi->ParentFileName == NULL) { + Status = PeiSecurityVerifyFv ((EFI_FIRMWARE_VOLUME_HEADER*) FvInfoPpi->FvInfo); + ASSERT_EFI_ERROR (Status); + } + + return EFI_SUCCESS; +} + +/** + Authenticates the Firmware Volume + + @param CurrentFvAddress Pointer to the current Firmware Volume under consideration + + @retval EFI_SUCCESS Firmware Volume is legal + +**/ +EFI_STATUS +PeiSecurityVerifyFv ( + IN EFI_FIRMWARE_VOLUME_HEADER *CurrentFvAddress + ) +{ + EFI_STATUS Status; + + // + // Call Security library to authenticate the Firmware Volume + // + DEBUG ((DEBUG_INFO, "PeiSecurityVerifyFv - CurrentFvAddress=0x%8x\n", (UINT32)CurrentFvAddress)); + Status = EFI_SUCCESS; + + return Status; +} + +/** + + Entry point for the PEI Security PEIM + Sets up a notification to perform PEI security checking + + @param FfsHeader Not used. + @param PeiServices General purpose services available to every PEIM. + + @return EFI_SUCCESS PEI Security notification installed successfully. + All others: PEI Security notification failed to install. + +**/ +EFI_STATUS +PeiInitializeFvSecurity ( + VOID + ) +{ + EFI_STATUS Status; + + Status = PeiServicesNotifyPpi (&mNotifyOnFvInfoSecurityList); + + return Status; +} + diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/PeiFvSecurity.h b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/PeiFvSecurity.h new file mode 100644 index 0000000000..fb6c4969dd --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/PeiFvSecurity.h @@ -0,0 +1,67 @@ +/** @file +Definition of Pei Core Structures and Services + +Copyright (c) 2013 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PEI_FV_SECURITY_H_ +#define _PEI_FV_SECURITY_H_ + +#include +#include +#include +#include +#include + +/** + Callback function to perform FV security checking on a FV Info PPI. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation + @param NotifyDescriptor Address of the notification descriptor data structure. + @param Ppi Address of the PPI that was installed. + + @retval EFI_SUCCESS + +**/ +EFI_STATUS +EFIAPI +FirmwareVolmeInfoPpiNotifySecurityCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ); + +/** + Authenticates the Firmware Volume + + @param CurrentFvAddress Pointer to the current Firmware Volume under consideration + + @retval EFI_SUCCESS Firmware Volume is legal + +**/ +EFI_STATUS +PeiSecurityVerifyFv ( + IN EFI_FIRMWARE_VOLUME_HEADER *CurrentFvAddress + ); + +/** + + Entry point for the PEI Security PEIM + Sets up a notification to perform PEI security checking + + @param FfsHeader Not used. + @param PeiServices General purpose services available to every PEIM. + + @return EFI_SUCCESS PEI Security notification installed successfully. + All others: PEI Security notification failed to install. + +**/ +EFI_STATUS +PeiInitializeFvSecurity ( + VOID + ); + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.c b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.c new file mode 100644 index 0000000000..afc6e71d5f --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.c @@ -0,0 +1,1227 @@ +/** @file +This PEIM initialize platform for MRC, following action is performed, +1. Initizluize GMCH +2. Detect boot mode +3. Detect video adapter to determine whether we need pre allocated memory +4. Calls MRC to initialize memory and install a PPI notify to do post memory initialization. +This file contains the main entrypoint of the PEIM. + +Copyright (c) 2013 - 2016 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "CommonHeader.h" +#include "PlatformEarlyInit.h" +#include "PeiFvSecurity.h" + +EFI_STATUS +EFIAPI +EndOfPeiSignalPpiNotifyCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ); + +// +// Function prototypes to routines implemented in other source modules +// within this component. +// + +EFI_STATUS +EFIAPI +PlatformErratasPostMrc ( + VOID + ); + +// +// The global indicator, the FvFileLoader callback will modify it to TRUE after loading PEIM into memory +// +BOOLEAN ImageInMemory = FALSE; + +BOARD_LEGACY_GPIO_CONFIG mBoardLegacyGpioConfigTable[] = { PLATFORM_LEGACY_GPIO_TABLE_DEFINITION }; +UINTN mBoardLegacyGpioConfigTableLen = (sizeof(mBoardLegacyGpioConfigTable) / sizeof(BOARD_LEGACY_GPIO_CONFIG)); +BOARD_GPIO_CONTROLLER_CONFIG mBoardGpioControllerConfigTable[] = { PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION }; +UINTN mBoardGpioControllerConfigTableLen = (sizeof(mBoardGpioControllerConfigTable) / sizeof(BOARD_GPIO_CONTROLLER_CONFIG)); +UINT8 ChipsetDefaultMac [6] = {0xff,0xff,0xff,0xff,0xff,0xff}; + +EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[1] = { + { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiMasterBootModePpiGuid, + NULL + } +}; + +EFI_PEI_NOTIFY_DESCRIPTOR mMemoryDiscoveredNotifyList[1] = { + { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiMemoryDiscoveredPpiGuid, + MemoryDiscoveredPpiNotifyCallback + } +}; + +EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiSignalPpiNotifyList[1] = { + { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiEndOfPeiSignalPpiGuid, + EndOfPeiSignalPpiNotifyCallback + } +}; + +EFI_PEI_STALL_PPI mStallPpi = { + PEI_STALL_RESOLUTION, + Stall +}; + +EFI_PEI_PPI_DESCRIPTOR mPpiStall[1] = { + { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiStallPpiGuid, + &mStallPpi + } +}; + +/** + Set Mac address on chipset ethernet device. + + @param Bus PCI Bus number of chipset ethernet device. + @param Device Device number of chipset ethernet device. + @param Func PCI Function number of chipset ethernet device. + @param MacAddr MAC Address to set. + +**/ +VOID +EFIAPI +SetLanControllerMacAddr ( + IN CONST UINT8 Bus, + IN CONST UINT8 Device, + IN CONST UINT8 Func, + IN CONST UINT8 *MacAddr, + IN CONST UINT32 Bar0 + ) +{ + UINT32 Data32; + UINT16 PciVid; + UINT16 PciDid; + UINT32 Addr; + UINT32 MacVer; + volatile UINT8 *Wrote; + UINT32 DevPcieAddr; + UINT16 SaveCmdReg; + UINT32 SaveBarReg; + + DevPcieAddr = PCI_LIB_ADDRESS ( + Bus, + Device, + Func, + 0 + ); + + // + // Do nothing if not a supported device. + // + PciVid = PciRead16 (DevPcieAddr + PCI_VENDOR_ID_OFFSET); + PciDid = PciRead16 (DevPcieAddr + PCI_DEVICE_ID_OFFSET); + if((PciVid != V_IOH_MAC_VENDOR_ID) || (PciDid != V_IOH_MAC_DEVICE_ID)) { + return; + } + + // + // Save current settings for PCI CMD/BAR registers + // + SaveCmdReg = PciRead16 (DevPcieAddr + PCI_COMMAND_OFFSET); + SaveBarReg = PciRead32 (DevPcieAddr + R_IOH_MAC_MEMBAR); + + // + // Use predefined temporary memory resource + // + PciWrite32 ( DevPcieAddr + R_IOH_MAC_MEMBAR, Bar0); + PciWrite8 ( DevPcieAddr + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE); + + Addr = Bar0 + R_IOH_MAC_GMAC_REG_8; + MacVer = *((volatile UINT32 *) (UINTN)(Addr)); + + DEBUG ((EFI_D_INFO, "Ioh MAC [B:%d, D:%d, F:%d] VER:%04x ADDR:", + (UINTN) Bus, + (UINTN) Device, + (UINTN) Func, + (UINTN) MacVer + )); + + // + // Set MAC Address0 Low Register (GMAC_REG_17) ADDRLO bits. + // + Addr = Bar0 + R_IOH_MAC_GMAC_REG_17; + Data32 = *((UINT32 *) (UINTN)(&MacAddr[0])); + *((volatile UINT32 *) (UINTN)(Addr)) = Data32; + Wrote = (volatile UINT8 *) (UINTN)(Addr); + DEBUG ((EFI_D_INFO, "%02x-%02x-%02x-%02x-", + (UINTN) Wrote[0], + (UINTN) Wrote[1], + (UINTN) Wrote[2], + (UINTN) Wrote[3] + )); + + // + // Set MAC Address0 High Register (GMAC_REG_16) ADDRHI bits + // and Address Enable (AE) bit. + // + Addr = Bar0 + R_IOH_MAC_GMAC_REG_16; + Data32 = + ((UINT32) MacAddr[4]) | + (((UINT32)MacAddr[5]) << 8) | + B_IOH_MAC_AE; + *((volatile UINT32 *) (UINTN)(Addr)) = Data32; + Wrote = (volatile UINT8 *) (UINTN)(Addr); + + DEBUG ((EFI_D_INFO, "%02x-%02x\n", (UINTN) Wrote[0], (UINTN) Wrote[1])); + + // + // Restore settings for PCI CMD/BAR registers + // + PciWrite32 ((DevPcieAddr + R_IOH_MAC_MEMBAR), SaveBarReg); + PciWrite16 (DevPcieAddr + PCI_COMMAND_OFFSET, SaveCmdReg); +} + +/** + Initialize state of I2C GPIO expanders. + + @param PlatformType Platform type for GPIO expander init. + +**/ +EFI_STATUS +EarlyPlatformConfigGpioExpanders ( + IN CONST EFI_PLATFORM_TYPE PlatformType, + EFI_BOOT_MODE BootMode + ) +{ + EFI_STATUS Status; + EFI_I2C_DEVICE_ADDRESS I2CSlaveAddress; + UINTN Length; + UINTN ReadLength; + UINT8 Buffer[2]; + + // + // Configure GPIO expanders for Galileo Gen 2 + // Route I2C pins to Arduino header + // Set all GPIO expander pins connected to the Reset Button as inputs + // + if (PlatformType == GalileoGen2) { + // + // Configure AMUX1_IN (EXP2.P1_4) as an output + // + PlatformPcal9555GpioSetDir ( + GALILEO_GEN2_IOEXP2_7BIT_SLAVE_ADDR, // IO Expander 2. + 12, // P1-4. + FALSE // Configure as output + ); + + // + // Set AMUX1_IN(EXP2.P1_4) low to route I2C to Arduino Shield connector + // + PlatformPcal9555GpioSetLevel ( + GALILEO_GEN2_IOEXP2_7BIT_SLAVE_ADDR, // IO Expander 2. + 12, // P1-4. + FALSE // Set pin low + ); + + // + // Configure Reset Button(EXP1.P1_7) as an input + // + PlatformPcal9555GpioSetDir ( + GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1. + 15, // P1-7. + TRUE + ); + + // + // Disable pullup on Reset Button(EXP1.P1_7) + // + PlatformPcal9555GpioDisablePull ( + GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1. + 15 // P1-7. + ); + + // + // Configure Reset Button(EXP2.P1_7) as an input + // + PlatformPcal9555GpioSetDir ( + GALILEO_GEN2_IOEXP2_7BIT_SLAVE_ADDR, // IO Expander 2. + 15, // P1-7. + TRUE + ); + + // + // Disable pullup on Reset Button(EXP2.P1_7) + // + PlatformPcal9555GpioDisablePull ( + GALILEO_GEN2_IOEXP2_7BIT_SLAVE_ADDR, // IO Expander 2. + 15 // P1-7. + ); + + if (BootMode != BOOT_IN_RECOVERY_MODE) { + // + // Read state of Reset Button - EXP2.P1_7 + // This GPIO is pulled high when the button is not pressed + // This GPIO reads low when button is pressed + // + if (!PlatformPcal9555GpioGetState ( + GALILEO_GEN2_IOEXP2_7BIT_SLAVE_ADDR, // IO Expander 2 + 15 // P1-7 + )) { + DEBUG ((EFI_D_INFO, " Force Recovery mode and reset\n")); + + // + // Set 'B_CFG_STICKY_RW_FORCE_RECOVERY' sticky bit so we know we need to do a recovery following warm reset + // + QNCAltPortWrite ( + QUARK_SCSS_SOC_UNIT_SB_PORT_ID, + QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW, + QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW) | B_CFG_STICKY_RW_FORCE_RECOVERY + ); + ResetWarm(); + } + } + } + + // + // Configure GPIO expanders for Galileo Gen 2 + // Set all GPIO expander pins connected to the Reset Button as inputs + // Route I2C pins to Arduino header + // + if (PlatformType == Galileo) { + // + // Detect the I2C Slave Address of the GPIO Expander + // + if (PlatformLegacyGpioGetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)) { + I2CSlaveAddress.I2CDeviceAddress = GALILEO_IOEXP_J2HI_7BIT_SLAVE_ADDR; + } else { + I2CSlaveAddress.I2CDeviceAddress = GALILEO_IOEXP_J2LO_7BIT_SLAVE_ADDR; + } + DEBUG ((EFI_D_INFO, "Galileo GPIO Expender Slave Address = %02x\n", I2CSlaveAddress.I2CDeviceAddress)); + + // + // Set I2C_MUX (GPORT1_BIT5) low to route I2C to Arduino Shield connector + // + + // + // Select GPIO Expander GPORT1 + // + Length = 2; + Buffer[0] = 0x18; //sub-address + Buffer[1] = 0x01; //data + Status = I2cWriteMultipleByte ( + I2CSlaveAddress, + EfiI2CSevenBitAddrMode, + &Length, + &Buffer + ); + ASSERT_EFI_ERROR (Status); + + // + // Read "Pin Direction" of GPIO Expander GPORT1 + // + Length = 1; + ReadLength = 1; + Buffer[1] = 0x1C; + Status = I2cReadMultipleByte ( + I2CSlaveAddress, + EfiI2CSevenBitAddrMode, + &Length, + &ReadLength, + &Buffer[1] + ); + ASSERT_EFI_ERROR (Status); + + // + // Configure GPIO Expander GPORT1_BIT5 as an output + // + Length = 2; + Buffer[0] = 0x1C; //sub-address + Buffer[1] = (UINT8)(Buffer[1] & (~BIT5)); //data + + Status = I2cWriteMultipleByte ( + I2CSlaveAddress, + EfiI2CSevenBitAddrMode, + &Length, + &Buffer + ); + ASSERT_EFI_ERROR (Status); + + // + // Set GPIO Expander GPORT1_BIT5 low + // + Length = 2; + Buffer[0] = 0x09; //sub-address + Buffer[1] = (UINT8)(~BIT5); //data + + Status = I2cWriteMultipleByte ( + I2CSlaveAddress, + EfiI2CSevenBitAddrMode, + &Length, + &Buffer + ); + ASSERT_EFI_ERROR (Status); + + // + // Configure RESET_N_SHLD (GPORT5_BIT0) and SW_RESET_N_SHLD (GPORT5_BIT1) as inputs + // + + // + // Select GPIO Expander GPORT5 + // + Length = 2; + Buffer[0] = 0x18; + Buffer[1] = 0x05; + Status = I2cWriteMultipleByte ( + I2CSlaveAddress, + EfiI2CSevenBitAddrMode, + &Length, + &Buffer + ); + ASSERT_EFI_ERROR (Status); + + // + // Read "Pin Direction" of GPIO Expander GPORT5 + // + Length = 1; + ReadLength = 1; + Buffer[1] = 0x1C; + Status = I2cReadMultipleByte ( + I2CSlaveAddress, + EfiI2CSevenBitAddrMode, + &Length, + &ReadLength, + &Buffer[1] + ); + ASSERT_EFI_ERROR (Status); + + // + // Configure GPIO Expander GPORT5_BIT0 and GPORT5_BIT1 as inputs + // + Length = 2; + Buffer[0] = 0x1C; + Buffer[1] = Buffer[1] | BIT0 | BIT1; + Status = I2cWriteMultipleByte ( + I2CSlaveAddress, + EfiI2CSevenBitAddrMode, + &Length, + &Buffer + ); + ASSERT_EFI_ERROR (Status); + + if (BootMode != BOOT_IN_RECOVERY_MODE) { + // + // Read state of RESET_N_SHLD (GPORT5_BIT0) + // + Buffer[1] = 5; + Length = 1; + ReadLength = 1; + Status = I2cReadMultipleByte ( + I2CSlaveAddress, + EfiI2CSevenBitAddrMode, + &Length, + &ReadLength, + &Buffer[1] + ); + ASSERT_EFI_ERROR (Status); + + // + // Return the state of GPORT5_BIT0 + // + if ((Buffer[1] & BIT0) == 0) { + DEBUG ((EFI_D_INFO, " Force Recovery mode and reset\n")); + + // + // Set 'B_CFG_STICKY_RW_FORCE_RECOVERY' sticky bit so we know we need to do a recovery following warm reset + // + QNCAltPortWrite ( + QUARK_SCSS_SOC_UNIT_SB_PORT_ID, + QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW, + QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW) | B_CFG_STICKY_RW_FORCE_RECOVERY + ); + ResetWarm(); + } + } + } + + return EFI_SUCCESS; +} + +/** + This is the entrypoint of PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS if it completed successfully. +**/ +EFI_STATUS +EFIAPI +PeiInitPlatform ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + EFI_PEI_STALL_PPI *StallPpi; + EFI_PEI_PPI_DESCRIPTOR *StallPeiPpiDescriptor; + EFI_FV_FILE_INFO FileInfo; + EFI_PLATFORM_TYPE PlatformType; + + PlatformType = (EFI_PLATFORM_TYPE)PcdGet16 (PcdPlatformType); + + // + // Initialize Firmware Volume security. + // This must be done before any firmware volume accesses (excl. BFV) + // + Status = PeiInitializeFvSecurity(); + ASSERT_EFI_ERROR (Status); + + // + // Do any early platform specific initialization. + // + EarlyPlatformInit (); + + // + // This is a second path on entry, in recovery boot path the Stall PPI need to be memory-based + // to improve recovery performance. + // + Status = PeiServicesFfsGetFileInfo (FileHandle, &FileInfo); + ASSERT_EFI_ERROR (Status); + // + // The follow conditional check only works for memory-mapped FFS, + // so we ASSERT that the file is really a MM FFS. + // + ASSERT (FileInfo.Buffer != NULL); + if (!(((UINTN) FileInfo.Buffer <= (UINTN) PeiInitPlatform) && + ((UINTN) PeiInitPlatform <= (UINTN) FileInfo.Buffer + FileInfo.BufferSize))) { + // + // Now that module in memory, update the + // PPI that describes the Stall to other modules + // + Status = PeiServicesLocatePpi ( + &gEfiPeiStallPpiGuid, + 0, + &StallPeiPpiDescriptor, + (VOID **) &StallPpi + ); + + if (!EFI_ERROR (Status)) { + + Status = PeiServicesReInstallPpi ( + StallPeiPpiDescriptor, + &mPpiStall[0] + ); + } else { + + Status = PeiServicesInstallPpi (&mPpiStall[0]); + } + return Status; + } + + // + // Initialize System Phys + // + + // Program USB Phy + InitializeUSBPhy(); + + // + // Do platform specific logic to create a boot mode + // + Status = UpdateBootMode ((EFI_PEI_SERVICES**)PeiServices, &BootMode); + ASSERT_EFI_ERROR (Status); + + // + // Signal possible dependent modules that there has been a + // final boot mode determination + // + if (!EFI_ERROR(Status)) { + Status = PeiServicesInstallPpi (&mPpiBootMode[0]); + ASSERT_EFI_ERROR (Status); + } + + if (BootMode != BOOT_ON_S3_RESUME) { + QNCClearSmiAndWake (); + } + + DEBUG ((EFI_D_INFO, "MRC Entry\n")); + MemoryInit ((EFI_PEI_SERVICES**)PeiServices); + + // + // Do Early PCIe init. + // + DEBUG ((EFI_D_INFO, "Early PCIe controller initialization\n")); + PlatformPciExpressEarlyInit (PlatformType); + + + DEBUG ((EFI_D_INFO, "Platform Erratas After MRC\n")); + PlatformErratasPostMrc (); + + // + // + // + DEBUG ((EFI_D_INFO, "EarlyPlatformConfigGpioExpanders ()\n")); + EarlyPlatformConfigGpioExpanders (PlatformType, BootMode); + + // + // Now that all of the pre-permanent memory activities have + // been taken care of, post a call-back for the permanent-memory + // resident services, such as HOB construction. + // PEI Core will switch stack after this PEIM exit. After that the MTRR + // can be set. + // + Status = PeiServicesNotifyPpi (&mMemoryDiscoveredNotifyList[0]); + ASSERT_EFI_ERROR (Status); +/* + + if (BootMode != BOOT_ON_S3_RESUME) { + Status = PeiServicesNotifyPpi (mEndOfPeiSignalPpiNotifyList); + ASSERT_EFI_ERROR (Status); + } +*/ + if (BootMode == BOOT_IN_RECOVERY_MODE) { + PeiServicesRegisterForShadow (FileHandle); + } + + return Status; +} + +EFI_STATUS +EFIAPI +EndOfPeiSignalPpiNotifyCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + + DEBUG ((EFI_D_INFO, "End of PEI Signal Callback\n")); + + // + // Restore the flash region to be UC + // for both normal boot as we build a Resource Hob to + // describe this region as UC to DXE core. + // + WriteBackInvalidateDataCacheRange ( + (VOID *) (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), + PcdGet32 (PcdFlashAreaSize) + ); + + Status = MtrrSetMemoryAttribute (PcdGet32 (PcdFlashAreaBaseAddress), PcdGet32 (PcdFlashAreaSize), CacheUncacheable); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +/** + This function will initialize USB Phy registers associated with QuarkSouthCluster. + + @param VOID No Argument + + @retval EFI_SUCCESS All registers have been initialized +**/ +VOID +EFIAPI +InitializeUSBPhy ( + VOID + ) +{ + UINT32 RegData32; + + /** In order to configure the PHY to use clk120 (ickusbcoreclk) as PLL reference clock + * and Port2 as a USB device port, the following sequence must be followed + * + **/ + + // Sideband register write to USB AFE (Phy) + RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_GLOBAL_PORT); + RegData32 &= ~(BIT1); + // + // Sighting #4930631 PDNRESCFG [8:7] of USB2_GLOBAL_PORT = 11b. + // For port 0 & 1 as host and port 2 as device. + // + RegData32 |= (BIT8 | BIT7); + QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_GLOBAL_PORT, RegData32); + + // + // Sighting #4930653 Required BIOS change on Disconnect vref to change to 600mV. + // + RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_COMPBG); + RegData32 &= ~(BIT10 | BIT9 | BIT8 | BIT7); + RegData32 |= (BIT10 | BIT7); + QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_COMPBG, RegData32); + + // Sideband register write to USB AFE (Phy) + // (pllbypass) to bypass/Disable PLL before switch + RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2); + RegData32 |= BIT29; + QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2, RegData32); + + // Sideband register write to USB AFE (Phy) + // (coreclksel) to select 120MHz (ickusbcoreclk) clk source. + // (Default 0 to select 96MHz (ickusbclk96_npad/ppad)) + RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL1); + RegData32 |= BIT1; + QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL1, RegData32); + + // Sideband register write to USB AFE (Phy) + // (divide by 8) to achieve internal 480MHz clock + // for 120MHz input refclk. (Default: 4'b1000 (divide by 10) for 96MHz) + RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL1); + RegData32 &= ~(BIT5 | BIT4 | BIT3); + RegData32 |= BIT6; + QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL1, RegData32); + + // Sideband register write to USB AFE (Phy) + // Clear (pllbypass) + RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2); + RegData32 &= ~BIT29; + QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2, RegData32); + + // Sideband register write to USB AFE (Phy) + // Set (startlock) to force the PLL FSM to restart the lock + // sequence due to input clock/freq switch. + RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2); + RegData32 |= BIT24; + QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2, RegData32); + + // At this point the PLL FSM and COMP FSM will complete + +} + +/** + This function provides early platform Thermal sensor initialisation. +**/ +VOID +EFIAPI +EarlyPlatformThermalSensorInit ( + VOID + ) +{ + DEBUG ((EFI_D_INFO, "Early Platform Thermal Sensor Init\n")); + + // + // Set Thermal sensor mode. + // + QNCThermalSensorSetRatiometricMode (); + + // + // Enable RMU Thermal sensor with a Catastrophic Trip point. + // + QNCThermalSensorEnableWithCatastrophicTrip (PLATFORM_CATASTROPHIC_TRIP_CELSIUS); + + // + // Lock all RMU Thermal sensor control & trip point registers. + // + QNCThermalSensorLockAllRegisters (); +} + +/** + Print early platform info messages includeing the Stage1 module that's + running, MFH item list and platform data item list. +**/ +VOID +EFIAPI +EarlyPlatformInfoMessages ( + VOID + ) +{ + DEBUG_CODE_BEGIN (); + QUARK_EDKII_STAGE1_HEADER *Edk2ImageHeader; + + // + // Find which 'Stage1' image we are running and print the details + // + Edk2ImageHeader = (QUARK_EDKII_STAGE1_HEADER *) PcdGet32 (PcdEsramStage1Base); + DEBUG ((EFI_D_INFO, "\n************************************************************\n")); + + switch ((UINT8)Edk2ImageHeader->ImageIndex & QUARK_STAGE1_IMAGE_TYPE_MASK) { + case QUARK_STAGE1_BOOT_IMAGE_TYPE: + DEBUG ((EFI_D_INFO, "**** Quark EDKII Stage 1 Boot Image %d ****\n", ((UINT8)Edk2ImageHeader->ImageIndex & ~(QUARK_STAGE1_IMAGE_TYPE_MASK)))); + break; + + case QUARK_STAGE1_RECOVERY_IMAGE_TYPE: + DEBUG ((EFI_D_INFO, "**** Quark EDKII Stage 1 Recovery Image %d ****\n", ((UINT8)Edk2ImageHeader->ImageIndex & ~(QUARK_STAGE1_IMAGE_TYPE_MASK)))); + break; + + default: + DEBUG ((EFI_D_INFO, "**** Quark EDKII Unknown Stage 1 Image !!!! ****\n")); + break; + } + DEBUG ( + (EFI_D_INFO, + "**** Quark EDKII Stage 2 Image 0x%08X:0x%08X ****\n" , + (UINTN) PcdGet32 (PcdFlashFvMainBase), + (UINTN) PcdGet32 (PcdFlashFvMainSize) + )); + + DEBUG ( + (EFI_D_INFO, + "**** Quark EDKII Payload Image 0x%08X:0x%08X ****\n" , + (UINTN) PcdGet32 (PcdFlashFvPayloadBase), + (UINTN) PcdGet32 (PcdFlashFvPayloadSize) + )); + + DEBUG ((EFI_D_INFO, "************************************************************\n\n")); + + DEBUG_CODE_END (); +} + +/** + Check if system reset due to error condition. + + @param ClearErrorBits If TRUE clear error flags and value bits. + + @retval TRUE if system reset due to error condition. + @retval FALSE if NO reset error conditions. +**/ +BOOLEAN +CheckForResetDueToErrors ( + IN BOOLEAN ClearErrorBits + ) +{ + UINT32 RegValue; + BOOLEAN ResetDueToError; + + ResetDueToError = FALSE; + + // + // Check if RMU reset system due to access violations. + // RMU updates a SOC Unit register before resetting the system. + // + RegValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW); + if ((RegValue & B_CFG_STICKY_RW_VIOLATION) != 0) { + ResetDueToError = TRUE; + + DEBUG ( + (EFI_D_ERROR, + "\nReset due to access violation: %s %s %s %s\n", + ((RegValue & B_CFG_STICKY_RW_IMR_VIOLATION) != 0) ? L"'IMR'" : L".", + ((RegValue & B_CFG_STICKY_RW_DECC_VIOLATION) != 0) ? L"'DECC'" : L".", + ((RegValue & B_CFG_STICKY_RW_SMM_VIOLATION) != 0) ? L"'SMM'" : L".", + ((RegValue & B_CFG_STICKY_RW_HMB_VIOLATION) != 0) ? L"'HMB'" : L"." + )); + + // + // Clear error bits. + // + if (ClearErrorBits) { + RegValue &= ~(B_CFG_STICKY_RW_VIOLATION); + QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW, RegValue); + } + } + + return ResetDueToError; +} + +/** + This function provides early platform initialization. + + @param PlatformInfo Pointer to platform Info structure. + +**/ +VOID +EFIAPI +EarlyPlatformInit ( + VOID + ) +{ + EFI_PLATFORM_TYPE PlatformType; + + PlatformType = (EFI_PLATFORM_TYPE) PcdGet16 (PcdPlatformType); + + DEBUG ((EFI_D_INFO, "EarlyPlatformInit for PlatType=0x%02x\n", (UINTN) PlatformType)); + + // + // Check if system reset due to error condition. + // + if (CheckForResetDueToErrors (TRUE)) { + if(FeaturePcdGet (WaitIfResetDueToError)) { + DEBUG ((EFI_D_ERROR, "Wait 10 seconds.\n")); + MicroSecondDelay(10000000); + } + } + + // + // Display platform info messages. + // + EarlyPlatformInfoMessages (); + + // + // Early Legacy Gpio Init. + // + EarlyPlatformLegacyGpioInit (PlatformType); + + // + // Early platform Legacy GPIO manipulation depending on GPIOs + // setup by EarlyPlatformLegacyGpioInit. + // + EarlyPlatformLegacyGpioManipulation (PlatformType); + + // + // Early platform specific GPIO Controller init & manipulation. + // Combined for sharing of temp. memory bar. + // + EarlyPlatformGpioCtrlerInitAndManipulation (PlatformType); + + // + // Early Thermal Sensor Init. + // + EarlyPlatformThermalSensorInit (); + + // + // Early Lan Ethernet Mac Init. + // + EarlyPlatformMacInit ( + PcdGetPtr (PcdIohEthernetMac0), + PcdGetPtr (PcdIohEthernetMac1) + ); +} + +/** + This function provides early platform Legacy GPIO initialisation. + + @param PlatformType Platform type for GPIO init. + +**/ +VOID +EFIAPI +EarlyPlatformLegacyGpioInit ( + IN CONST EFI_PLATFORM_TYPE PlatformType + ) +{ + BOARD_LEGACY_GPIO_CONFIG *LegacyGpioConfig; + UINT32 NewValue; + UINT32 GpioBaseAddress; + + // + // Assert if platform type outside table range. + // + ASSERT ((UINTN) PlatformType < mBoardLegacyGpioConfigTableLen); + LegacyGpioConfig = &mBoardLegacyGpioConfigTable[(UINTN) PlatformType]; + + GpioBaseAddress = (UINT32)PcdGet16 (PcdGbaIoBaseAddress); + + NewValue = 0x0; + // + // Program QNC GPIO Registers. + // + NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGEN_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellEnable; + IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGEN_CORE_WELL, NewValue ); + NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGIO_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellIoSelect; + IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGIO_CORE_WELL, NewValue); + NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGLVL_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellLvlForInputOrOutput; + IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGLVL_CORE_WELL, NewValue); + NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGTPE_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellTriggerPositiveEdge; + IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGTPE_CORE_WELL, NewValue ); + NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGTNE_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellTriggerNegativeEdge; + IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGTNE_CORE_WELL, NewValue); + NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGGPE_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellGPEEnable; + IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGGPE_CORE_WELL, NewValue); + NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGSMI_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellSMIEnable; + IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGSMI_CORE_WELL, NewValue ); + NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGTS_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellTriggerStatus; + IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGTS_CORE_WELL, NewValue); + NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CNMIEN_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellNMIEnable; + IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CNMIEN_CORE_WELL, NewValue); + + NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGEN_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellEnable; + IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGEN_RESUME_WELL, NewValue ); + NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGIO_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellIoSelect; + IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGIO_RESUME_WELL, NewValue) ; + NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGLVL_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellLvlForInputOrOutput; + IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGLVL_RESUME_WELL, NewValue); + NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGTPE_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellTriggerPositiveEdge; + IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGTPE_RESUME_WELL, NewValue ); + NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGTNE_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellTriggerNegativeEdge; + IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGTNE_RESUME_WELL, NewValue) ; + NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGGPE_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellGPEEnable; + IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGGPE_RESUME_WELL, NewValue); + NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGSMI_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellSMIEnable; + IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGSMI_RESUME_WELL, NewValue ); + NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGTS_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellTriggerStatus; + IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGTS_RESUME_WELL, NewValue) ; + NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RNMIEN_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellNMIEnable; + IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RNMIEN_RESUME_WELL, NewValue); +} + +/** + Performs any early platform specific Legacy GPIO manipulation. + + @param PlatformType Platform type GPIO manipulation. + +**/ +VOID +EFIAPI +EarlyPlatformLegacyGpioManipulation ( + IN CONST EFI_PLATFORM_TYPE PlatformType + ) +{ + if (PlatformType == CrossHill) { + + // + // Pull TPM reset low for 80us (equivalent to cold reset, Table 39 + // Infineon SLB9645 Databook), then pull TPM reset high and wait for + // 150ms to give time for TPM to stabilise (Section 4.7.1 Infineon + // SLB9645 Databook states TPM is ready to receive command after 30ms + // but section 4.7 states some TPM commands may take longer to execute + // upto 150ms after test). + // + + PlatformLegacyGpioSetLevel ( + R_QNC_GPIO_RGLVL_RESUME_WELL, + PLATFORM_RESUMEWELL_TPM_RST_GPIO, + FALSE + ); + MicroSecondDelay (80); + + PlatformLegacyGpioSetLevel ( + R_QNC_GPIO_RGLVL_RESUME_WELL, + PLATFORM_RESUMEWELL_TPM_RST_GPIO, + TRUE + ); + MicroSecondDelay (150000); + } + +} + +/** + Performs any early platform specific GPIO Controller init & manipulation. + + @param PlatformType Platform type for GPIO init & manipulation. + +**/ +VOID +EFIAPI +EarlyPlatformGpioCtrlerInitAndManipulation ( + IN CONST EFI_PLATFORM_TYPE PlatformType + ) +{ + UINT32 IohGpioBase; + UINT32 Data32; + UINT32 Addr; + BOARD_GPIO_CONTROLLER_CONFIG *GpioConfig; + UINT32 DevPcieAddr; + UINT16 SaveCmdReg; + UINT32 SaveBarReg; + UINT16 PciVid; + UINT16 PciDid; + + ASSERT ((UINTN) PlatformType < mBoardGpioControllerConfigTableLen); + GpioConfig = &mBoardGpioControllerConfigTable[(UINTN) PlatformType]; + + IohGpioBase = (UINT32) PcdGet64 (PcdIohGpioMmioBase); + + DevPcieAddr = PCI_LIB_ADDRESS ( + PcdGet8 (PcdIohGpioBusNumber), + PcdGet8 (PcdIohGpioDevNumber), + PcdGet8 (PcdIohGpioFunctionNumber), + 0 + ); + + // + // Do nothing if not a supported device. + // + PciVid = PciRead16 (DevPcieAddr + PCI_VENDOR_ID_OFFSET); + PciDid = PciRead16 (DevPcieAddr + PCI_DEVICE_ID_OFFSET); + if((PciVid != V_IOH_I2C_GPIO_VENDOR_ID) || (PciDid != V_IOH_I2C_GPIO_DEVICE_ID)) { + return; + } + + // + // Save current settings for PCI CMD/BAR registers. + // + SaveCmdReg = PciRead16 (DevPcieAddr + PCI_COMMAND_OFFSET); + SaveBarReg = PciRead32 (DevPcieAddr + PcdGet8 (PcdIohGpioBarRegister)); + + // + // Use predefined temporary memory resource. + // + PciWrite32 ( DevPcieAddr + PcdGet8 (PcdIohGpioBarRegister), IohGpioBase); + PciWrite8 ( DevPcieAddr + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE); + + // + // Gpio Controller Init Tasks. + // + + // + // IEN- Interrupt Enable Register + // + Addr = IohGpioBase + GPIO_INTEN; + Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8] + Data32 |= (GpioConfig->IntEn & 0x000FFFFF); + *((volatile UINT32 *) (UINTN)(Addr)) = Data32; + + // + // ISTATUS- Interrupt Status Register + // + Addr = IohGpioBase + GPIO_INTSTATUS; + Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8] + *((volatile UINT32 *) (UINTN)(Addr)) = Data32; + + // + // GPIO SWPORTA Direction Register - GPIO_SWPORTA_DR + // + Addr = IohGpioBase + GPIO_SWPORTA_DR; + Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8] + Data32 |= (GpioConfig->PortADR & 0x000FFFFF); + *((volatile UINT32 *) (UINTN)(Addr)) = Data32; + + // + // GPIO SWPORTA Data Direction Register - GPIO_SWPORTA_DDR - default input + // + Addr = IohGpioBase + GPIO_SWPORTA_DDR; + Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8] + Data32 |= (GpioConfig->PortADir & 0x000FFFFF); + *((volatile UINT32 *) (UINTN)(Addr)) = Data32; + + // + // Interrupt Mask Register - GPIO_INTMASK - default interrupts unmasked + // + Addr = IohGpioBase + GPIO_INTMASK; + Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8] + Data32 |= (GpioConfig->IntMask & 0x000FFFFF); + *((volatile UINT32 *) (UINTN)(Addr)) = Data32; + + // + // Interrupt Level Type Register - GPIO_INTTYPE_LEVEL - default is level sensitive + // + Addr = IohGpioBase + GPIO_INTTYPE_LEVEL; + Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8] + Data32 |= (GpioConfig->IntType & 0x000FFFFF); + *((volatile UINT32 *) (UINTN)(Addr)) = Data32; + + // + // Interrupt Polarity Type Register - GPIO_INT_POLARITY - default is active low + // + Addr = IohGpioBase + GPIO_INT_POLARITY; + Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8] + Data32 |= (GpioConfig->IntPolarity & 0x000FFFFF); + *((volatile UINT32 *) (UINTN)(Addr)) = Data32; + + // + // Interrupt Debounce Type Register - GPIO_DEBOUNCE - default no debounce + // + Addr = IohGpioBase + GPIO_DEBOUNCE; + Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8] + Data32 |= (GpioConfig->Debounce & 0x000FFFFF); + *((volatile UINT32 *) (UINTN)(Addr)) = Data32; + + // + // Interrupt Clock Synchronisation Register - GPIO_LS_SYNC - default no sync with pclk_intr(APB bus clk) + // + Addr = IohGpioBase + GPIO_LS_SYNC; + Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8] + Data32 |= (GpioConfig->LsSync & 0x000FFFFF); + *((volatile UINT32 *) (UINTN)(Addr)) = Data32; + + // + // Gpio Controller Manipulation Tasks. + // + + if (PlatformType == (EFI_PLATFORM_TYPE) Galileo) { + // + // Reset Cypress Expander on Galileo Platform + // + Addr = IohGpioBase + GPIO_SWPORTA_DR; + Data32 = *((volatile UINT32 *) (UINTN)(Addr)); + Data32 |= BIT4; // Cypress Reset line controlled by GPIO<4> + *((volatile UINT32 *) (UINTN)(Addr)) = Data32; + + Data32 = *((volatile UINT32 *) (UINTN)(Addr)); + Data32 &= ~BIT4; // Cypress Reset line controlled by GPIO<4> + *((volatile UINT32 *) (UINTN)(Addr)) = Data32; + + } + + // + // Restore settings for PCI CMD/BAR registers + // + PciWrite32 ((DevPcieAddr + PcdGet8 (PcdIohGpioBarRegister)), SaveBarReg); + PciWrite16 (DevPcieAddr + PCI_COMMAND_OFFSET, SaveCmdReg); +} + +/** + Performs any early platform init of SoC Ethernet Mac devices. + + @param IohMac0Address Mac address to program into Mac0 device. + @param IohMac1Address Mac address to program into Mac1 device. + +**/ +VOID +EFIAPI +EarlyPlatformMacInit ( + IN CONST UINT8 *IohMac0Address, + IN CONST UINT8 *IohMac1Address + ) +{ + BOOLEAN SetMacAddr; + + // + // Set chipset MAC0 address if configured. + // + SetMacAddr = + (CompareMem (ChipsetDefaultMac, IohMac0Address, sizeof (ChipsetDefaultMac))) != 0; + if (SetMacAddr) { + if ((*(IohMac0Address) & BIT0) != 0) { + DEBUG ((EFI_D_ERROR, "HALT: Multicast Mac Address configured for Ioh MAC [B:%d, D:%d, F:%d]\n", + (UINTN) IOH_MAC0_BUS_NUMBER, + (UINTN) IOH_MAC0_DEVICE_NUMBER, + (UINTN) IOH_MAC0_FUNCTION_NUMBER + )); + ASSERT (FALSE); + } else { + SetLanControllerMacAddr ( + IOH_MAC0_BUS_NUMBER, + IOH_MAC0_DEVICE_NUMBER, + IOH_MAC0_FUNCTION_NUMBER, + IohMac0Address, + (UINT32) PcdGet64(PcdIohMac0MmioBase) + ); + } + } else { + DEBUG ((EFI_D_WARN, "WARNING: Ioh MAC [B:%d, D:%d, F:%d] NO HW ADDR CONFIGURED!!!\n", + (UINTN) IOH_MAC0_BUS_NUMBER, + (UINTN) IOH_MAC0_DEVICE_NUMBER, + (UINTN) IOH_MAC0_FUNCTION_NUMBER + )); + } + + // + // Set chipset MAC1 address if configured. + // + SetMacAddr = + (CompareMem (ChipsetDefaultMac, IohMac1Address, sizeof (ChipsetDefaultMac))) != 0; + if (SetMacAddr) { + if ((*(IohMac1Address) & BIT0) != 0) { + DEBUG ((EFI_D_ERROR, "HALT: Multicast Mac Address configured for Ioh MAC [B:%d, D:%d, F:%d]\n", + (UINTN) IOH_MAC1_BUS_NUMBER, + (UINTN) IOH_MAC1_DEVICE_NUMBER, + (UINTN) IOH_MAC1_FUNCTION_NUMBER + )); + ASSERT (FALSE); + } else { + SetLanControllerMacAddr ( + IOH_MAC1_BUS_NUMBER, + IOH_MAC1_DEVICE_NUMBER, + IOH_MAC1_FUNCTION_NUMBER, + IohMac1Address, + (UINT32) PcdGet64(PcdIohMac1MmioBase) + ); + } + } else { + DEBUG ((EFI_D_WARN, "WARNING: Ioh MAC [B:%d, D:%d, F:%d] NO HW ADDR CONFIGURED!!!\n", + (UINTN) IOH_MAC1_BUS_NUMBER, + (UINTN) IOH_MAC1_DEVICE_NUMBER, + (UINTN) IOH_MAC1_FUNCTION_NUMBER + )); + } +} + diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.h b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.h new file mode 100644 index 0000000000..84def44717 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.h @@ -0,0 +1,301 @@ +/** @file +The header file of Platform PEIM. + +Copyright (c) 2013 - 2019 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef __PLATFORM_EARLY_INIT_H__ +#define __PLATFORM_EARLY_INIT_H__ + +#define PEI_STALL_RESOLUTION 1 +#define STALL_PEIM_SIGNATURE SIGNATURE_32('p','p','u','s') + +typedef struct { + UINT32 Signature; + EFI_FFS_FILE_HEADER *FfsHeader; + EFI_PEI_NOTIFY_DESCRIPTOR StallNotify; +} STALL_CALLBACK_STATE_INFORMATION; + +#define STALL_PEIM_FROM_THIS(a) CR (a, STALL_CALLBACK_STATE_INFORMATION, StallNotify, STALL_PEIM_SIGNATURE) + +// +// USB Phy Registers +// +#define USB2_GLOBAL_PORT 0x4001 +#define USB2_PLL1 0x7F02 +#define USB2_PLL2 0x7F03 +#define USB2_COMPBG 0x7F04 + +/** + Peform the boot mode determination logic + If the box is closed, then + 1. If it's first time to boot, it's boot with full config . + 2. If the ChassisIntrution is selected, force to be a boot with full config + 3. Otherwise it's boot with no change. + + @param PeiServices General purpose services available to every PEIM. + + @param BootMode The detected boot mode. + + @retval EFI_SUCCESS if the boot mode could be set +**/ +EFI_STATUS +UpdateBootMode ( + IN EFI_PEI_SERVICES **PeiServices, + OUT EFI_BOOT_MODE *BootMode + ); + +/** + This function reset the entire platform, including all processor and devices, and + reboots the system. + + @param PeiServices General purpose services available to every PEIM. + + @retval EFI_SUCCESS if it completed successfully. +**/ +EFI_STATUS +EFIAPI +PlatformResetSystem ( + IN CONST EFI_PEI_SERVICES **PeiServices + ); + +/** + This function will be called when MRC is done. + + @param PeiServices General purpose services available to every PEIM. + + @param NotifyDescriptor Information about the notify event.. + + @param Ppi The notify context. + + @retval EFI_SUCCESS If the function completed successfully. +**/ +EFI_STATUS +EFIAPI +MemoryDiscoveredPpiNotifyCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ); + +/** + This is the callback function notified by FvFileLoader PPI, it depends on FvFileLoader PPI to load + the PEIM into memory. + + @param PeiServices General purpose services available to every PEIM. + @param NotifyDescriptor The context of notification. + @param Ppi The notify PPI. + + @retval EFI_SUCCESS if it completed successfully. +**/ +EFI_STATUS +EFIAPI +FvFileLoaderPpiNotifyCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ); + +/** + This function provides a blocking stall for reset at least the given number of microseconds + stipulated in the final argument. + + @param PeiServices General purpose services available to every PEIM. + + @param this Pointer to the local data for the interface. + + @param Microseconds number of microseconds for which to stall. + + @retval EFI_SUCCESS the function provided at least the required stall. +**/ +EFI_STATUS +EFIAPI +Stall ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_STALL_PPI *This, + IN UINTN Microseconds + ); + +/** + This function initialize recovery functionality by installing the recovery PPI. + + @param PeiServices General purpose services available to every PEIM. + + @retval EFI_SUCCESS if the interface could be successfully installed. +**/ +EFI_STATUS +EFIAPI +PeimInitializeRecovery ( + IN EFI_PEI_SERVICES **PeiServices + ); + +/** + This function + 1. Calling MRC to initialize memory. + 2. Install EFI Memory. + 3. Create HOB of system memory. + + @param PeiServices Pointer to the PEI Service Table + + @retval EFI_SUCCESS If it completes successfully. + +**/ +EFI_STATUS +MemoryInit ( + IN EFI_PEI_SERVICES **PeiServices + ); + +/** Return info derived from Installing Memory by MemoryInit. + + @param[out] RmuMainBaseAddressPtr Return RmuMainBaseAddress to this location. + @param[out] SmramDescriptorPtr Return start of Smram descriptor list to this location. + @param[out] NumSmramRegionsPtr Return numbers of Smram regions to this location. + + @return Address of RMU shadow region at the top of available memory. + @return List of Smram descriptors for each Smram region. + @return Numbers of Smram regions. +**/ +VOID +EFIAPI +InfoPostInstallMemory ( + OUT UINT32 *RmuMainBaseAddressPtr OPTIONAL, + OUT EFI_SMRAM_DESCRIPTOR **SmramDescriptorPtr OPTIONAL, + OUT UINTN *NumSmramRegionsPtr OPTIONAL + ); + +/** + This function provides the implementation of AtaController PPI Enable Channel function. + + @param PeiServices General purpose services available to every PEIM. + @param this Pointer to the local data for the interface. + @param ChannelMask This parameter is used to specify primary or slavery IDE channel. + + @retval EFI_SUCCESS Procedure returned successfully. +**/ + +EFI_STATUS +EnableAtaChannel ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_ATA_CONTROLLER_PPI *This, + IN UINT8 ChannelMask + ); + +/** + This function provides the implementation of AtaController PPI Get IDE channel Register Base Address + + @param PeiServices General purpose services available to every PEIM. + @param this Pointer to the local data for the interface. + @param IdeRegsBaseAddr Pointer to IDE_REGS_BASE_ADDR struct, which is used to record + IDE Command and Control regeisters Base Address. + + @retval EFI_SUCCESS Procedure returned successfully. +**/ + +EFI_STATUS +GetIdeRegsBaseAddr ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_ATA_CONTROLLER_PPI *This, + IN IDE_REGS_BASE_ADDR *IdeRegsBaseAddr + ); + +VOID +EFIAPI +InitializeUSBPhy ( + VOID + ); + +/** + This function provides early platform initialisation. + + @param PlatformInfo Pointer to platform Info structure. + +**/ +VOID +EFIAPI +EarlyPlatformInit ( + VOID + ); + +/** + This function provides early platform GPIO initialisation. + + @param PlatformType Platform type for GPIO init. + +**/ +VOID +EFIAPI +EarlyPlatformLegacyGpioInit ( + IN CONST EFI_PLATFORM_TYPE PlatformType + ); + +/** + Performs any early platform specific GPIO manipulation. + + @param PlatformType Platform type GPIO manipulation. + +**/ +VOID +EFIAPI +EarlyPlatformLegacyGpioManipulation ( + IN CONST EFI_PLATFORM_TYPE PlatformType + ); + +/** + Performs any early platform specific GPIO Controller init & manipulation. + + @param PlatformType Platform type for GPIO init & manipulation. + +**/ +VOID +EFIAPI +EarlyPlatformGpioCtrlerInitAndManipulation ( + IN CONST EFI_PLATFORM_TYPE PlatformType + ); + +/** + Performs any early platform init of SoC Ethernet Mac devices. + + @param IohMac0Address Mac address to program into Mac0 device. + @param IohMac1Address Mac address to program into Mac1 device. + +**/ +VOID +EFIAPI +EarlyPlatformMacInit ( + IN CONST UINT8 *IohMac0Address, + IN CONST UINT8 *IohMac1Address + ); + +/** + Find security headers using EFI_CAPSULE_VARIABLE_NAME variables and build Hobs. + + @param PeiServices General purpose services available to every PEIM. + + @retval 0 if no security headers found. + @return number of security header hobs built. +**/ +UINTN +EFIAPI +FindCapsuleSecurityHeadersAndBuildHobs ( + IN EFI_PEI_SERVICES **PeiServices + ); + +/** + Build capsule security header hob. + + @param SecHdr Pointer to security header. + + @retval NULL if failure to build HOB. + @return pointer to built hob. +**/ +VOID * +EFIAPI +BuildCapsuleSecurityHeaderHob ( + IN VOID *SecHdr + ); + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf new file mode 100644 index 0000000000..df8b0dd3bd --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf @@ -0,0 +1,193 @@ +## @file +# This is the Platform PEIM to initialize whole platform on PEI phase. +# +# This PEIM includes 3 parts, pre memory initialization, MRC +# wrapper and post memory initialization. +# On pre memory, following action is performed, +# 1. Initizluize GMCH. +# 2. Detect boot mode. +# 3. Detect video adapter to determine whether we need pre allocated +# memory. +# +# After that MRC wrapper calls MRC to initialize memory and install a PPI +# notify to do post memory +# initialization. MRC wrapper performance following actions, +# 1. Install EFI Memory. +# 2. Create HOB of system memory. +# +# On post memory, following action is performed, +# 1. QNC initialization after MRC. +# 2. SIO initialization. +# 3. Install ResetSystem and FinvFv PPI, relocate Stall to memory on +# recovery boot mode. +# 4. Set MTRR for PEI +# 5. Create FV HOB and Flash HOB +# 6. Install RecoveryModule and AtaController PPI if on recovery boot mode. +# +# This PEIM does not have any register access directly, it depends on +# IntelQNCLib, QNCAccess libraries to access Chipset +# registers. +# +# Platform.c - Provide main flow and entrypoint of PEIM. +# MemoryCallback.c - Includes a memory call back function notified when +# MRC is done. +# Recovery.c - provides the platform recoveyr functionality. +# MrcWrapper.c - Contains the logic to call MRC PPI and do Framework +# memory specific stuff like build memory map, build +# resource description hob for DXE phase,etc. +# Bootmode.c - Detect boot mode. +# Copyright (c) 2013 - 2019 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformEarlyInitPei + FILE_GUID = 9618C0DC-50A4-496c-994F-7241F282ED01 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = PeiInitPlatform + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 +# + +[Sources] + Generic/Recovery.c + PlatformErratas.c + MrcWrapper.c + MrcWrapper.h + PlatformEarlyInit.c + PlatformEarlyInit.h + MemoryCallback.c + BootMode.c + CommonHeader.h + PeiFvSecurity.c + PeiFvSecurity.h + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + IntelFrameworkPkg/IntelFrameworkPkg.dec + IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + QuarkSocPkg/QuarkSocPkg.dec + +[LibraryClasses] + ResetSystemLib + PrintLib + TimerLib + PcdLib + IntelQNCLib + ReportStatusCodeLib + PciLib + PciExpressLib + IoLib + PciCf8Lib + HobLib + BaseMemoryLib + PeiServicesTablePointerLib + PeiServicesLib + BaseLib + PeimEntryPoint + DebugLib + MemoryAllocationLib + PerformanceLib + CacheMaintenanceLib + MtrrLib + QNCAccessLib + PlatformHelperLib + PlatformPcieHelperLib + I2cLib + +[Guids] + gEfiMemoryConfigDataGuid # ALWAYS_CONSUMED L"MemoryConfig" + gEfiAcpiVariableGuid # ALWAYS_CONSUMED L"AcpiGlobalVariab" + gEfiMemoryTypeInformationGuid # ALWAYS_CONSUMED L"MemoryTypeInformation" + gEfiMemoryConfigDataGuid # SOMETIMES_PRODUCED Hob: GUID_EXTENSION + gEfiSmmPeiSmramMemoryReserveGuid # ALWAYS_PRODUCED Hob: GUID_EXTENSION + gEfiFirmwareFileSystem2Guid # ALWAYS_CONSUMED + gEfiCapsuleGuid # ALWAYS_CONSUMED + gPeiCapsuleOnDataCDGuid + gPeiCapsuleOnFatIdeDiskGuid + gPeiCapsuleOnFatUsbDiskGuid + gEfiMemoryOverwriteControlDataGuid # SOMETIMES_CONSUMED + gEfiQuarkCapsuleGuid + +[Ppis] + gQNCMemoryInitPpiGuid # PPI ALWAYS_CONSUMED + gEfiPeiMemoryDiscoveredPpiGuid # PPI ALWAYS_PRODUCED + gPeiAtaControllerPpiGuid # PPI SOMETIMES_PRODUCED + gEfiPeiStallPpiGuid # PPI ALWAYS_PRODUCED + gEfiPeiDeviceRecoveryModulePpiGuid # PPI SOMETIMES_CONSUMED + gEfiPeiRecoveryModulePpiGuid # PPI SOMETIMES_PRODUCED + gEfiPeiResetPpiGuid # PPI ALWAYS_PRODUCED + gEfiPeiReadOnlyVariable2PpiGuid # PPI ALWAYS_CONSUMED + gEfiPeiBootInRecoveryModePpiGuid # PPI SOMETIMES_PRODUCED + gEfiPeiMasterBootModePpiGuid # PPI ALWAYS_PRODUCED + gEfiPeiFirmwareVolumeInfoPpiGuid + gEfiEndOfPeiSignalPpiGuid + gEfiPeiVirtualBlockIoPpiGuid + gPeiCapsulePpiGuid # PPI ALWAYS_CONSUMED + +[FeaturePcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnFatUsbDisk + gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnDataCD + gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnFatFloppyDisk + gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnIdeDisk + gQuarkPlatformTokenSpaceGuid.WaitIfResetDueToError + +[Pcd] + gQuarkPlatformTokenSpaceGuid.PcdEsramStage1Base + gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize + gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress + gQuarkPlatformTokenSpaceGuid.PcdEccScrubBlkSize + gQuarkPlatformTokenSpaceGuid.PcdEccScrubInterval + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gQuarkPlatformTokenSpaceGuid.PcdFlashQNCMicrocodeSize + gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoBaseAddress + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeIoBase + gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeIoSize + gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartFunctionNumber + gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartBusNumber + gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartDevNumber + gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBusNumber + gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioDevNumber + gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioFunctionNumber + gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBarRegister + gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioMmioBase + gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohMac0MmioBase + gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohMac1MmioBase + gEfiQuarkSCSocIdTokenSpaceGuid.PcdPeiQNCUsbControllerMemoryBaseAddress + gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioBaseAddress + gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory32Base + gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory32Size + gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory64Base + gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory64Size + gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciExpressSize + gEfiQuarkNcSocIdTokenSpaceGuid.PcdGbaIoBaseAddress + gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkMicrocodeFile + gEfiQuarkNcSocIdTokenSpaceGuid.PcdTSegSize + gEfiQuarkNcSocIdTokenSpaceGuid.PcdESramMemorySize + gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoverySize + gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoveryBase + gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainSize + gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainBase + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState + gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadBase + gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadSize + gQuarkPlatformTokenSpaceGuid.PcdEnableFastBoot + gQuarkPlatformTokenSpaceGuid.PcdPlatformType + gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters + gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac0 + gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac1 + +[Depex] + gEfiPeiReadOnlyVariable2PpiGuid AND gQNCMemoryInitPpiGuid diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformErratas.c b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformErratas.c new file mode 100644 index 0000000000..9e013840fc --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformErratas.c @@ -0,0 +1,178 @@ +/** @file +Platform Erratas performed by early init PEIM driver. + +Copyright (c) 2013 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "CommonHeader.h" +#include "PlatformEarlyInit.h" + +// +// Constants. +// + +// +// Platform EHCI Packet Buffer OUT/IN Thresholds, values in number of DWORDs. +// +#define EHCI_OUT_THRESHOLD_VALUE (0x7f) +#define EHCI_IN_THRESHOLD_VALUE (0x7f) + +// +// Platform init USB device interrupt masks. +// +#define V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG (0x0000007f) +#define V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG (B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_OUT_EP_MASK | B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_IN_EP_MASK) + +// +// Global variables defined within this source module. +// + +UINTN IohEhciPciReg[IOH_MAX_EHCI_USB_CONTROLLERS] = { + PCI_LIB_ADDRESS (IOH_USB_BUS_NUMBER, IOH_USB_EHCI_DEVICE_NUMBER, IOH_EHCI_FUNCTION_NUMBER, 0), +}; + +UINTN IohUsbDevicePciReg[IOH_MAX_USBDEVICE_USB_CONTROLLERS] = { + PCI_LIB_ADDRESS (IOH_USB_BUS_NUMBER, IOH_USBDEVICE_DEVICE_NUMBER, IOH_USBDEVICE_FUNCTION_NUMBER, 0), +}; + +// +// Routines local to this source module. +// + +/** Perform USB erratas after MRC init. + +**/ +VOID +PlatformUsbErratasPostMrc ( + VOID + ) +{ + UINT32 Index; + UINT32 TempBar0Addr; + UINT16 SaveCmdReg; + UINT32 SaveBar0Reg; + + TempBar0Addr = PcdGet32(PcdPeiQNCUsbControllerMemoryBaseAddress); + + // + // Apply EHCI controller erratas. + // + for (Index = 0; Index < IOH_MAX_EHCI_USB_CONTROLLERS; Index++, TempBar0Addr += IOH_USB_CONTROLLER_MMIO_RANGE) { + + if ((PciRead16 (IohEhciPciReg[Index] + R_IOH_USB_VENDOR_ID)) != V_IOH_USB_VENDOR_ID) { + continue; // Device not enabled, skip. + } + + // + // Save current settings for PCI CMD/BAR0 registers + // + SaveCmdReg = PciRead16 (IohEhciPciReg[Index] + R_IOH_USB_COMMAND); + SaveBar0Reg = PciRead32 (IohEhciPciReg[Index] + R_IOH_USB_MEMBAR); + + // + // Temp. assign base address register, Enable Memory Space. + // + PciWrite32 ((IohEhciPciReg[Index] + R_IOH_USB_MEMBAR), TempBar0Addr); + PciWrite16 (IohEhciPciReg[Index] + R_IOH_USB_COMMAND, SaveCmdReg | B_IOH_USB_COMMAND_MSE); + + + // + // Set packet buffer OUT/IN thresholds. + // + MmioAndThenOr32 ( + TempBar0Addr + R_IOH_EHCI_INSNREG01, + (UINT32) (~(B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_MASK | B_IOH_EHCI_INSNREG01_IN_THRESHOLD_MASK)), + (UINT32) ((EHCI_OUT_THRESHOLD_VALUE << B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP) | (EHCI_IN_THRESHOLD_VALUE << B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP)) + ); + + // + // Restore settings for PCI CMD/BAR0 registers + // + PciWrite32 ((IohEhciPciReg[Index] + R_IOH_USB_MEMBAR), SaveBar0Reg); + PciWrite16 (IohEhciPciReg[Index] + R_IOH_USB_COMMAND, SaveCmdReg); + } + + // + // Apply USB device controller erratas. + // + for (Index = 0; Index < IOH_MAX_USBDEVICE_USB_CONTROLLERS; Index++, TempBar0Addr += IOH_USB_CONTROLLER_MMIO_RANGE) { + + if ((PciRead16 (IohUsbDevicePciReg[Index] + R_IOH_USB_VENDOR_ID)) != V_IOH_USB_VENDOR_ID) { + continue; // Device not enabled, skip. + } + + // + // Save current settings for PCI CMD/BAR0 registers + // + SaveCmdReg = PciRead16 (IohUsbDevicePciReg[Index] + R_IOH_USB_COMMAND); + SaveBar0Reg = PciRead32 (IohUsbDevicePciReg[Index] + R_IOH_USB_MEMBAR); + + // + // Temp. assign base address register, Enable Memory Space. + // + PciWrite32 ((IohUsbDevicePciReg[Index] + R_IOH_USB_MEMBAR), TempBar0Addr); + PciWrite16 (IohUsbDevicePciReg[Index] + R_IOH_USB_COMMAND, SaveCmdReg | B_IOH_USB_COMMAND_MSE); + + // + // Erratas for USB Device interrupt registers. + // + + // + // 1st Mask interrupts. + // + MmioWrite32 ( + TempBar0Addr + R_IOH_USBDEVICE_D_INTR_MSK_UDC_REG, + V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG + ); + // + // 2nd RW/1C of equivalent status bits. + // + MmioWrite32 ( + TempBar0Addr + R_IOH_USBDEVICE_D_INTR_UDC_REG, + V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG + ); + + // + // 1st Mask end point interrupts. + // + MmioWrite32 ( + TempBar0Addr + R_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG, + V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG + ); + // + // 2nd RW/1C of equivalent end point status bits. + // + MmioWrite32 ( + TempBar0Addr + R_IOH_USBDEVICE_EP_INTR_UDC_REG, + V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG + ); + + // + // Restore settings for PCI CMD/BAR0 registers + // + PciWrite32 ((IohUsbDevicePciReg[Index] + R_IOH_USB_MEMBAR), SaveBar0Reg); + PciWrite16 (IohUsbDevicePciReg[Index] + R_IOH_USB_COMMAND, SaveCmdReg); + } +} + +// +// Routines exported by this source module. +// + +/** Perform Platform Erratas after MRC. + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +PlatformErratasPostMrc ( + VOID + ) +{ + PlatformUsbErratasPostMrc (); + return EFI_SUCCESS; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/FvbInfo.c b/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/FvbInfo.c new file mode 100644 index 0000000000..8a21c5e33f --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/FvbInfo.c @@ -0,0 +1,332 @@ +/** @file +Defines data structure that is the volume header found.These data is intent +to decouple FVB driver with FV header. + +Copyright (c) 2013 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#include +#include "FwBlockService.h" + + +//#define FVB_MEDIA_BLOCK_SIZE PcdGet32(PcdFlashMinEraseSize) +#define FVB_MEDIA_BLOCK_SIZE 0x1000 + +typedef struct { + EFI_PHYSICAL_ADDRESS BaseAddress; + EFI_FIRMWARE_VOLUME_HEADER FvbInfo; + // + //EFI_FV_BLOCK_MAP_ENTRY ExtraBlockMap[n];//n=0 + // + EFI_FV_BLOCK_MAP_ENTRY End[1]; +} EFI_FVB2_MEDIA_INFO; + +// +// This data structure contains a template of all correct FV headers, which is used to restore +// Fv header if it's corrupted. +// +EFI_FVB2_MEDIA_INFO mPlatformFvbMediaInfo[] = { + // + // Main BIOS FVB + // + { + 0, + { + {0,}, //ZeroVector[16] + EFI_FIRMWARE_FILE_SYSTEM2_GUID, + 0, + EFI_FVH_SIGNATURE, + 0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details on EFI_FVB_ATTRIBUTES_2 + sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY), + 0, //CheckSum, check the FD for the value. + 0, //ExtHeaderOffset + {0,}, //Reserved[1] + 2, //Revision + { + { + 0, + 0, + } + } + }, + { + { + 0, + 0 + } + } + }, + // + // Systen NvStorage FVB + // + { + 0, + { + {0,}, //ZeroVector[16] + EFI_SYSTEM_NV_DATA_FV_GUID, + 0, + EFI_FVH_SIGNATURE, + 0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details on EFI_FVB_ATTRIBUTES_2 + sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY), + 0, //CheckSum which will be calucated dynamically. + 0, //ExtHeaderOffset + {0,}, //Reserved[1] + 2, //Revision + { + { + 0, + 0, + } + } + }, + { + { + 0, + 0 + } + } + }, + // + // Recovery BIOS FVB + // + { + 0, + { + {0,}, //ZeroVector[16] + EFI_FIRMWARE_FILE_SYSTEM2_GUID, + 0, + EFI_FVH_SIGNATURE, + 0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details on EFI_FVB_ATTRIBUTES_2 + sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY), + 0, //CheckSum which will be calucated dynamically. + 0, //ExtHeaderOffset + {0,}, //Reserved[1] + 2, //Revision + { + { + 0, + 0, + } + } + }, + { + { + 0, + 0 + } + } + }, + // + // Payload FVB + // + { + 0, + { + {0,}, //ZeroVector[16] + EFI_FIRMWARE_FILE_SYSTEM2_GUID, + 0, + EFI_FVH_SIGNATURE, + 0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details on EFI_FVB_ATTRIBUTES_2 + sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY), + 0, //CheckSum which will be calucated dynamically. + 0x60, //ExtHeaderOffset + {0,}, //Reserved[1] + 2, //Revision + { + { + 0, + 0, + } + } + }, + { + { + 0, + 0 + } + } + } +}; + + +// +// FTW working space and FTW spare space don't have FV header. +// We need create one for them and use it for FVB protocol. +// +EFI_FVB2_MEDIA_INFO mPlatformFtwFvbInfo[] = { + // + // System variable FTW working FVB + // + { + 0, + { + {0,}, //ZeroVector[16] + EFI_SYSTEM_NV_DATA_FV_GUID, + 0, + EFI_FVH_SIGNATURE, + 0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details on EFI_FVB_ATTRIBUTES_2 + sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY), + 0, //CheckSum which will be calucated dynamically. + 0, //ExtHeaderOffset + {0,}, //Reserved[1] + 2, //Revision + { + { + 0, + 0, + } + } + }, + { + { + 0, + 0 + } + } + }, + // + // Systen NV variable FTW spare FVB + // + { + 0, + { + {0,}, //ZeroVector[16] + EFI_SYSTEM_NV_DATA_FV_GUID, + 0, + EFI_FVH_SIGNATURE, + 0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details on EFI_FVB_ATTRIBUTES_2 + sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY), + 0, //CheckSum which will be calucated dynamically. + 0, //ExtHeaderOffset + {0,}, //Reserved[1] + 2, //Revision + { + { + 0, + 0, + } + } + }, + { + { + 0, + 0 + } + } + } +}; + + + +EFI_STATUS +GetFtwFvbInfo ( + IN EFI_PHYSICAL_ADDRESS FvBaseAddress, + OUT EFI_FIRMWARE_VOLUME_HEADER **FvbInfo + ) +{ + UINTN Index; + EFI_FIRMWARE_VOLUME_HEADER *FvHeader; + + // + // Init Fvb data + // + mPlatformFtwFvbInfo[0].BaseAddress = PcdGet32 (PcdFlashNvStorageFtwWorkingBase); + mPlatformFtwFvbInfo[0].FvbInfo.FvLength = PcdGet32 (PcdFlashNvStorageFtwWorkingSize); + mPlatformFtwFvbInfo[0].FvbInfo.BlockMap[0].NumBlocks = PcdGet32 (PcdFlashNvStorageFtwWorkingSize) / FVB_MEDIA_BLOCK_SIZE; + mPlatformFtwFvbInfo[0].FvbInfo.BlockMap[0].Length = FVB_MEDIA_BLOCK_SIZE; + ASSERT ((PcdGet32 (PcdFlashNvStorageFtwWorkingSize) % FVB_MEDIA_BLOCK_SIZE) == 0); + + mPlatformFtwFvbInfo[1].BaseAddress = PcdGet32 (PcdFlashNvStorageFtwSpareBase); + mPlatformFtwFvbInfo[1].FvbInfo.FvLength = PcdGet32 (PcdFlashNvStorageFtwSpareSize); + mPlatformFtwFvbInfo[1].FvbInfo.BlockMap[0].NumBlocks = PcdGet32 (PcdFlashNvStorageFtwSpareSize) / FVB_MEDIA_BLOCK_SIZE; + mPlatformFtwFvbInfo[1].FvbInfo.BlockMap[0].Length = FVB_MEDIA_BLOCK_SIZE; + ASSERT ((PcdGet32 (PcdFlashNvStorageFtwSpareSize) % FVB_MEDIA_BLOCK_SIZE) == 0); + + for (Index=0; Index < sizeof (mPlatformFtwFvbInfo)/sizeof (mPlatformFtwFvbInfo[0]); Index += 1) { + if (mPlatformFtwFvbInfo[Index].BaseAddress == FvBaseAddress) { + FvHeader = &mPlatformFtwFvbInfo[Index].FvbInfo; + // + // Update the checksum value of FV header. + // + FvHeader->Checksum = CalculateCheckSum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16)); + + *FvbInfo = FvHeader; + + DEBUG ((EFI_D_INFO, "\nFTW BaseAddr: 0x%lx \n", FvBaseAddress)); + DEBUG ((EFI_D_INFO, "FvLength: 0x%lx \n", (*FvbInfo)->FvLength)); + DEBUG ((EFI_D_INFO, "HeaderLength: 0x%x \n", (*FvbInfo)->HeaderLength)); + DEBUG ((EFI_D_INFO, "FvBlockMap[0].NumBlocks: 0x%x \n", (*FvbInfo)->BlockMap[0].NumBlocks)); + DEBUG ((EFI_D_INFO, "FvBlockMap[0].BlockLength: 0x%x \n", (*FvbInfo)->BlockMap[0].Length)); + DEBUG ((EFI_D_INFO, "FvBlockMap[1].NumBlocks: 0x%x \n", (*FvbInfo)->BlockMap[1].NumBlocks)); + DEBUG ((EFI_D_INFO, "FvBlockMap[1].BlockLength: 0x%x \n\n", (*FvbInfo)->BlockMap[1].Length)); + + return EFI_SUCCESS; + } + } + return EFI_NOT_FOUND; +} + + +EFI_STATUS +GetFvbInfo ( + IN EFI_PHYSICAL_ADDRESS FvBaseAddress, + OUT EFI_FIRMWARE_VOLUME_HEADER **FvbInfo + ) +{ + UINTN Index; + EFI_FIRMWARE_VOLUME_HEADER *FvHeader; + + // + // Init Fvb data + // + mPlatformFvbMediaInfo[0].BaseAddress = PcdGet32 (PcdFlashFvMainBase); + mPlatformFvbMediaInfo[0].FvbInfo.FvLength = PcdGet32 (PcdFlashFvMainSize); + mPlatformFvbMediaInfo[0].FvbInfo.BlockMap[0].NumBlocks = PcdGet32 (PcdFlashFvMainSize) / FVB_MEDIA_BLOCK_SIZE; + mPlatformFvbMediaInfo[0].FvbInfo.BlockMap[0].Length = FVB_MEDIA_BLOCK_SIZE; + ASSERT ((PcdGet32 (PcdFlashFvMainSize) % FVB_MEDIA_BLOCK_SIZE) == 0); + + mPlatformFvbMediaInfo[1].BaseAddress = PcdGet32 (PcdFlashNvStorageVariableBase); + mPlatformFvbMediaInfo[1].FvbInfo.FvLength = PcdGet32 (PcdFlashNvStorageVariableSize); + mPlatformFvbMediaInfo[1].FvbInfo.BlockMap[0].NumBlocks = PcdGet32 (PcdFlashNvStorageVariableSize) / FVB_MEDIA_BLOCK_SIZE; + mPlatformFvbMediaInfo[1].FvbInfo.BlockMap[0].Length = FVB_MEDIA_BLOCK_SIZE; + ASSERT ((PcdGet32 (PcdFlashNvStorageVariableSize) % FVB_MEDIA_BLOCK_SIZE) == 0); + + mPlatformFvbMediaInfo[2].BaseAddress = PcdGet32 (PcdFlashFvRecoveryBase); + mPlatformFvbMediaInfo[2].FvbInfo.FvLength = PcdGet32 (PcdFlashFvRecoverySize); + mPlatformFvbMediaInfo[2].FvbInfo.BlockMap[0].NumBlocks = PcdGet32 (PcdFlashFvRecoverySize) / FVB_MEDIA_BLOCK_SIZE; + mPlatformFvbMediaInfo[2].FvbInfo.BlockMap[0].Length = FVB_MEDIA_BLOCK_SIZE; + ASSERT ((PcdGet32 (PcdFlashFvRecoverySize) % FVB_MEDIA_BLOCK_SIZE) == 0); + + mPlatformFvbMediaInfo[3].BaseAddress = PcdGet32 (PcdFlashFvPayloadBase); + mPlatformFvbMediaInfo[3].FvbInfo.FvLength = PcdGet32 (PcdFlashFvPayloadSize); + mPlatformFvbMediaInfo[3].FvbInfo.BlockMap[0].NumBlocks = PcdGet32 (PcdFlashFvPayloadSize) / FVB_MEDIA_BLOCK_SIZE; + mPlatformFvbMediaInfo[3].FvbInfo.BlockMap[0].Length = FVB_MEDIA_BLOCK_SIZE; + ASSERT ((PcdGet32 (PcdFlashFvPayloadSize) % FVB_MEDIA_BLOCK_SIZE) == 0); + + for (Index=0; Index < sizeof (mPlatformFvbMediaInfo)/sizeof (mPlatformFvbMediaInfo[0]); Index += 1) { + if (mPlatformFvbMediaInfo[Index].BaseAddress == FvBaseAddress) { + FvHeader = &mPlatformFvbMediaInfo[Index].FvbInfo; + // + // Update the checksum value of FV header. + // + FvHeader->Checksum = CalculateCheckSum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16)); + + *FvbInfo = FvHeader; + + DEBUG ((EFI_D_INFO, "\nBaseAddr: 0x%lx \n", FvBaseAddress)); + DEBUG ((EFI_D_INFO, "FvLength: 0x%lx \n", (*FvbInfo)->FvLength)); + DEBUG ((EFI_D_INFO, "HeaderLength: 0x%x \n", (*FvbInfo)->HeaderLength)); + DEBUG ((EFI_D_INFO, "FvBlockMap[0].NumBlocks: 0x%x \n", (*FvbInfo)->BlockMap[0].NumBlocks)); + DEBUG ((EFI_D_INFO, "FvBlockMap[0].BlockLength: 0x%x \n", (*FvbInfo)->BlockMap[0].Length)); + DEBUG ((EFI_D_INFO, "FvBlockMap[1].NumBlocks: 0x%x \n", (*FvbInfo)->BlockMap[1].NumBlocks)); + DEBUG ((EFI_D_INFO, "FvBlockMap[1].BlockLength: 0x%x \n\n", (*FvbInfo)->BlockMap[1].Length)); + + return EFI_SUCCESS; + } + } + return EFI_NOT_FOUND; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/FwBlockService.c b/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/FwBlockService.c new file mode 100644 index 0000000000..5ecb1cfdc7 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/FwBlockService.c @@ -0,0 +1,2053 @@ +/** @file + +Copyright (c) 2013-2016 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#include "FwBlockService.h" + +ESAL_FWB_GLOBAL *mFvbModuleGlobal; + +EFI_FW_VOL_BLOCK_DEVICE mFvbDeviceTemplate = { + FVB_DEVICE_SIGNATURE, // Signature + // + // FV_DEVICE_PATH FvDevicePath + // + { + { + { + HARDWARE_DEVICE_PATH, + HW_MEMMAP_DP, + { + (UINT8)(sizeof (MEMMAP_DEVICE_PATH)), + (UINT8)(sizeof (MEMMAP_DEVICE_PATH) >> 8) + } + }, + EfiMemoryMappedIO, + (EFI_PHYSICAL_ADDRESS) 0, + (EFI_PHYSICAL_ADDRESS) 0 + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, + // + // UEFI_FV_DEVICE_PATH UefiFvDevicePath + // + { + { + { + MEDIA_DEVICE_PATH, + MEDIA_PIWG_FW_VOL_DP, + { + (UINT8)(sizeof (MEDIA_FW_VOL_DEVICE_PATH)), + (UINT8)(sizeof (MEDIA_FW_VOL_DEVICE_PATH) >> 8) + } + }, + { 0 } + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, + 0, // Instance + // + // EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL FwVolBlockInstance + // + { + FvbProtocolGetAttributes, + FvbProtocolSetAttributes, + FvbProtocolGetPhysicalAddress, + FvbProtocolGetBlockSize, + FvbProtocolRead, + FvbProtocolWrite, + FvbProtocolEraseBlocks, + NULL + } +}; + +UINT32 mInSmmMode = 0; +EFI_SMM_SYSTEM_TABLE2* mSmst = NULL; + +VOID +PublishFlashDeviceInfo ( + IN SPI_INIT_TABLE *Found + ) +/*++ + +Routine Description: + + Publish info on found flash device to other drivers via PcdSpiFlashDeviceSize. + +Arguments: + Found - Pointer to entry in mSpiInitTable for found flash part. + +Returns: + None + +--*/ +{ + EFI_STATUS Status; + + // + // Publish Byte Size of found flash device. + // + Status = PcdSet32S (PcdSpiFlashDeviceSize, (UINT32)(Found->BiosStartOffset + Found->BiosSize)); + ASSERT_EFI_ERROR (Status); +} + +VOID +FvbVirtualddressChangeEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +/*++ + +Routine Description: + + Fixup internal data so that EFI and SAL can be call in virtual mode. + Call the passed in Child Notify event and convert the mFvbModuleGlobal + date items to there virtual address. + + mFvbModuleGlobal->FvInstance[FVB_PHYSICAL] - Physical copy of instance data + mFvbModuleGlobal->FvInstance[FVB_VIRTUAL] - Virtual pointer to common + instance data. + +Arguments: + + (Standard EFI notify event - EFI_EVENT_NOTIFY) + +Returns: + + None + +--*/ +{ + EFI_FW_VOL_INSTANCE *FwhInstance; + UINTN Index; + + gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID **) &mFvbModuleGlobal->FvInstance[FVB_VIRTUAL]); + + // + // Convert the base address of all the instances + // + Index = 0; + FwhInstance = mFvbModuleGlobal->FvInstance[FVB_PHYSICAL]; + while (Index < mFvbModuleGlobal->NumFv) { + + gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID **) &FwhInstance->FvBase[FVB_VIRTUAL]); + // + // SpiWrite and SpiErase always use Physical Address instead of + // Virtual Address, even in Runtime. So we need not convert pointer + // for FvWriteBase[FVB_VIRTUAL] + // + // EfiConvertPointer (0, (VOID **) &FwhInstance->FvWriteBase[FVB_VIRTUAL]); + // + FwhInstance = (EFI_FW_VOL_INSTANCE *) + ( + (UINTN) ((UINT8 *) FwhInstance) + FwhInstance->VolumeHeader.HeaderLength + + (sizeof (EFI_FW_VOL_INSTANCE) - sizeof (EFI_FIRMWARE_VOLUME_HEADER)) + ); + Index++; + } + + gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID **) &mFvbModuleGlobal->FvbScratchSpace[FVB_VIRTUAL]); + // + // Convert SPI_PROTOCOL instance for runtime + // + gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID **) &mFvbModuleGlobal->SpiProtocol); + gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID **) &mFvbModuleGlobal); +} + +VOID +FvbMemWrite8 ( + IN UINT64 Dest, + IN UINT8 Byte + ) +{ + MmioWrite8 ((UINTN)Dest, Byte); + + return ; +} + +EFI_STATUS +GetFvbInstance ( + IN UINTN Instance, + IN ESAL_FWB_GLOBAL *Global, + OUT EFI_FW_VOL_INSTANCE **FwhInstance, + IN BOOLEAN Virtual + ) +/*++ + +Routine Description: + Retrieves the physical address of a memory mapped FV + +Arguments: + Instance - The FV instance whose base address is going to be + returned + Global - Pointer to ESAL_FWB_GLOBAL that contains all + instance data + FwhInstance - The EFI_FW_VOL_INSTANCE fimrware instance structure + Virtual - Whether CPU is in virtual or physical mode + +Returns: + EFI_SUCCESS - Successfully returns + EFI_INVALID_PARAMETER - Instance not found + +--*/ +{ + EFI_FW_VOL_INSTANCE *FwhRecord; + + if (Instance >= Global->NumFv) { + return EFI_INVALID_PARAMETER; + } + // + // Find the right instance of the FVB private data + // + FwhRecord = Global->FvInstance[Virtual]; + while (Instance > 0) { + FwhRecord = (EFI_FW_VOL_INSTANCE *) + ( + (UINTN) ((UINT8 *) FwhRecord) + FwhRecord->VolumeHeader.HeaderLength + + (sizeof (EFI_FW_VOL_INSTANCE) - sizeof (EFI_FIRMWARE_VOLUME_HEADER)) + ); + Instance--; + } + + *FwhInstance = FwhRecord; + + return EFI_SUCCESS; +} + +EFI_STATUS +FvbGetPhysicalAddress ( + IN UINTN Instance, + OUT EFI_PHYSICAL_ADDRESS *Address, + IN ESAL_FWB_GLOBAL *Global, + IN BOOLEAN Virtual + ) +/*++ + +Routine Description: + Retrieves the physical address of a memory mapped FV + +Arguments: + Instance - The FV instance whose base address is going to be + returned + Address - Pointer to a caller allocated EFI_PHYSICAL_ADDRESS + that on successful return, contains the base address + of the firmware volume. + Global - Pointer to ESAL_FWB_GLOBAL that contains all + instance data + Virtual - Whether CPU is in virtual or physical mode + +Returns: + EFI_SUCCESS - Successfully returns + EFI_INVALID_PARAMETER - Instance not found + +--*/ +{ + EFI_FW_VOL_INSTANCE *FwhInstance; + EFI_STATUS Status; + + FwhInstance = NULL; + + // + // Find the right instance of the FVB private data + // + Status = GetFvbInstance (Instance, Global, &FwhInstance, Virtual); + ASSERT_EFI_ERROR (Status); + *Address = FwhInstance->FvBase[Virtual]; + + return EFI_SUCCESS; +} + +EFI_STATUS +FvbGetVolumeAttributes ( + IN UINTN Instance, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes, + IN ESAL_FWB_GLOBAL *Global, + IN BOOLEAN Virtual + ) +/*++ + +Routine Description: + Retrieves attributes, insures positive polarity of attribute bits, returns + resulting attributes in output parameter + +Arguments: + Instance - The FV instance whose attributes is going to be + returned + Attributes - Output buffer which contains attributes + Global - Pointer to ESAL_FWB_GLOBAL that contains all + instance data + Virtual - Whether CPU is in virtual or physical mode + +Returns: + EFI_SUCCESS - Successfully returns + EFI_INVALID_PARAMETER - Instance not found + +--*/ +{ + EFI_FW_VOL_INSTANCE *FwhInstance; + EFI_STATUS Status; + + FwhInstance = NULL; + + // + // Find the right instance of the FVB private data + // + Status = GetFvbInstance (Instance, Global, &FwhInstance, Virtual); + ASSERT_EFI_ERROR (Status); + *Attributes = FwhInstance->VolumeHeader.Attributes; + + return EFI_SUCCESS; +} + +EFI_STATUS +FvbGetLbaAddress ( + IN UINTN Instance, + IN EFI_LBA Lba, + OUT UINTN *LbaAddress, + OUT UINTN *LbaWriteAddress, + OUT UINTN *LbaLength, + OUT UINTN *NumOfBlocks, + IN ESAL_FWB_GLOBAL *Global, + IN BOOLEAN Virtual + ) +/*++ + +Routine Description: + Retrieves the starting address of an LBA in an FV + +Arguments: + Instance - The FV instance which the Lba belongs to + Lba - The logical block address + LbaAddress - On output, contains the physical starting address + of the Lba + LbaWriteAddress - On output, contains the physical starting address + of the Lba for writing + LbaLength - On output, contains the length of the block + NumOfBlocks - A pointer to a caller allocated UINTN in which the + number of consecutive blocks starting with Lba is + returned. All blocks in this range have a size of + BlockSize + Global - Pointer to ESAL_FWB_GLOBAL that contains all + instance data + Virtual - Whether CPU is in virtual or physical mode + +Returns: + EFI_SUCCESS - Successfully returns + EFI_INVALID_PARAMETER - Instance not found + +--*/ +{ + UINT32 NumBlocks; + UINT32 BlockLength; + UINTN Offset; + EFI_LBA StartLba; + EFI_LBA NextLba; + EFI_FW_VOL_INSTANCE *FwhInstance; + EFI_FV_BLOCK_MAP_ENTRY *BlockMap; + EFI_STATUS Status; + + FwhInstance = NULL; + + // + // Find the right instance of the FVB private data + // + Status = GetFvbInstance (Instance, Global, &FwhInstance, Virtual); + ASSERT_EFI_ERROR (Status); + + StartLba = 0; + Offset = 0; + BlockMap = &(FwhInstance->VolumeHeader.BlockMap[0]); + + // + // Parse the blockmap of the FV to find which map entry the Lba belongs to + // + while (TRUE) { + NumBlocks = BlockMap->NumBlocks; + BlockLength = BlockMap->Length; + + if ((NumBlocks == 0) || (BlockLength == 0)) { + return EFI_INVALID_PARAMETER; + } + + NextLba = StartLba + NumBlocks; + + // + // The map entry found + // + if (Lba >= StartLba && Lba < NextLba) { + Offset = Offset + (UINTN) MultU64x32 ((Lba - StartLba), BlockLength); + if (LbaAddress) { + *LbaAddress = FwhInstance->FvBase[Virtual] + Offset; + } + + if (LbaWriteAddress) { + *LbaWriteAddress = FwhInstance->FvWriteBase[Virtual] + Offset; + } + + if (LbaLength) { + *LbaLength = BlockLength; + } + + if (NumOfBlocks) { + *NumOfBlocks = (UINTN) (NextLba - Lba); + } + + return EFI_SUCCESS; + } + + StartLba = NextLba; + Offset = Offset + NumBlocks * BlockLength; + BlockMap++; + } +} + +EFI_STATUS +FvbReadBlock ( + IN UINTN Instance, + IN EFI_LBA Lba, + IN UINTN BlockOffset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer, + IN ESAL_FWB_GLOBAL *Global, + IN BOOLEAN Virtual + ) +/*++ + +Routine Description: + Reads specified number of bytes into a buffer from the specified block + +Arguments: + Instance - The FV instance to be read from + Lba - The logical block address to be read from + BlockOffset - Offset into the block at which to begin reading + NumBytes - Pointer that on input contains the total size of + the buffer. On output, it contains the total number + of bytes read + Buffer - Pointer to a caller allocated buffer that will be + used to hold the data read + Global - Pointer to ESAL_FWB_GLOBAL that contains all + instance data + Virtual - Whether CPU is in virtual or physical mode + +Returns: + EFI_SUCCESS - The firmware volume was read successfully and + contents are in Buffer + EFI_BAD_BUFFER_SIZE - Read attempted across a LBA boundary. On output, + NumBytes contains the total number of bytes returned + in Buffer + EFI_ACCESS_DENIED - The firmware volume is in the ReadDisabled state + EFI_DEVICE_ERROR - The block device is not functioning correctly and + could not be read + EFI_INVALID_PARAMETER - Instance not found, or NumBytes, Buffer are NULL + +--*/ +{ + EFI_FVB_ATTRIBUTES_2 Attributes; + UINTN LbaAddress; + UINTN LbaLength; + EFI_STATUS Status; + + // + // Check for invalid conditions + // + if ((NumBytes == NULL) || (Buffer == NULL)) { + return EFI_INVALID_PARAMETER; + } + + if (*NumBytes == 0) { + return EFI_INVALID_PARAMETER; + } + + Status = FvbGetLbaAddress (Instance, Lba, &LbaAddress, NULL, &LbaLength, NULL, Global, Virtual); + if (EFI_ERROR (Status)) { + return Status; + } + // + // Check if the FV is read enabled + // + FvbGetVolumeAttributes (Instance, &Attributes, Global, Virtual); + + if ((Attributes & EFI_FVB2_READ_STATUS) == 0) { + return EFI_ACCESS_DENIED; + } + // + // Perform boundary checks and adjust NumBytes + // + if (BlockOffset > LbaLength) { + return EFI_INVALID_PARAMETER; + } + + if (LbaLength < (*NumBytes + BlockOffset)) { + *NumBytes = (UINT32) (LbaLength - BlockOffset); + Status = EFI_BAD_BUFFER_SIZE; + } + + MmioReadBuffer8 (LbaAddress + BlockOffset, (UINTN) *NumBytes, Buffer); + + return Status; +} + +EFI_STATUS +FlashFdWrite ( + IN UINTN WriteAddress, + IN UINTN Address, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer, + IN UINTN LbaLength + ) +/*++ + +Routine Description: + Writes specified number of bytes from the input buffer to the address + +Arguments: + +Returns: + +--*/ +{ + EFI_STATUS Status; + + Status = EFI_SUCCESS; + + // + // TODO: Suggested that this code be "critical section" + // + WriteAddress -= ( PcdGet32 (PcdFlashAreaBaseAddress) ); + if (mInSmmMode == 0) { // !(EfiInManagementInterrupt ())) { + Status = mFvbModuleGlobal->SpiProtocol->Execute ( + mFvbModuleGlobal->SpiProtocol, + SPI_OPCODE_WRITE_INDEX, // OpcodeIndex + 0, // PrefixOpcodeIndex + TRUE, // DataCycle + TRUE, // Atomic + TRUE, // ShiftOut + WriteAddress, // Address + (UINT32) (*NumBytes), // Data Number + Buffer, + EnumSpiRegionBios + ); + + } else { + Status = mFvbModuleGlobal->SmmSpiProtocol->Execute ( + mFvbModuleGlobal->SmmSpiProtocol, + SPI_OPCODE_WRITE_INDEX, // OpcodeIndex + 0, // PrefixOpcodeIndex + TRUE, // DataCycle + TRUE, // Atomic + TRUE, // ShiftOut + WriteAddress, // Address + (UINT32) (*NumBytes), // Data Number + Buffer, + EnumSpiRegionBios + ); + } + + AsmWbinvd (); + + return Status; +} + +EFI_STATUS +FlashFdErase ( + IN UINTN WriteAddress, + IN UINTN Address, + IN UINTN LbaLength + ) +/*++ + +Routine Description: + Erase a certain block from address LbaWriteAddress + +Arguments: + +Returns: + +--*/ +{ + EFI_STATUS Status; + + WriteAddress -= (PcdGet32 (PcdFlashAreaBaseAddress)); + if (mInSmmMode == 0 ) { // !(EfiInManagementInterrupt ())) { + Status = mFvbModuleGlobal->SpiProtocol->Execute ( + mFvbModuleGlobal->SpiProtocol, + SPI_OPCODE_ERASE_INDEX, // OpcodeIndex + 0, // PrefixOpcodeIndex + FALSE, // DataCycle + TRUE, // Atomic + FALSE, // ShiftOut + WriteAddress, // Address + 0, // Data Number + NULL, + EnumSpiRegionBios // SPI_REGION_TYPE + ); + } else { + Status = mFvbModuleGlobal->SmmSpiProtocol->Execute ( + mFvbModuleGlobal->SmmSpiProtocol, + SPI_OPCODE_ERASE_INDEX, // OpcodeIndex + 0, // PrefixOpcodeIndex + FALSE, // DataCycle + TRUE, // Atomic + FALSE, // ShiftOut + WriteAddress, // Address + 0, // Data Number + NULL, + EnumSpiRegionBios // SPI_REGION_TYPE + ); + } + + AsmWbinvd (); + + return Status; +} + +EFI_STATUS +FvbWriteBlock ( + IN UINTN Instance, + IN EFI_LBA Lba, + IN UINTN BlockOffset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer, + IN ESAL_FWB_GLOBAL *Global, + IN BOOLEAN Virtual + ) +/*++ + +Routine Description: + Writes specified number of bytes from the input buffer to the block + +Arguments: + Instance - The FV instance to be written to + Lba - The starting logical block index to write to + BlockOffset - Offset into the block at which to begin writing + NumBytes - Pointer that on input contains the total size of + the buffer. On output, it contains the total number + of bytes actually written + Buffer - Pointer to a caller allocated buffer that contains + the source for the write + Global - Pointer to ESAL_FWB_GLOBAL that contains all + instance data + Virtual - Whether CPU is in virtual or physical mode + +Returns: + EFI_SUCCESS - The firmware volume was written successfully + EFI_BAD_BUFFER_SIZE - Write attempted across a LBA boundary. On output, + NumBytes contains the total number of bytes + actually written + EFI_ACCESS_DENIED - The firmware volume is in the WriteDisabled state + EFI_DEVICE_ERROR - The block device is not functioning correctly and + could not be written + EFI_INVALID_PARAMETER - Instance not found, or NumBytes, Buffer are NULL + +--*/ +{ + EFI_FVB_ATTRIBUTES_2 Attributes; + UINTN LbaAddress; + UINTN LbaWriteAddress; + UINTN LbaLength; + EFI_FW_VOL_INSTANCE *FwhInstance; + EFI_STATUS Status; + EFI_STATUS ReturnStatus; + + FwhInstance = NULL; + + // + // Find the right instance of the FVB private data + // + Status = GetFvbInstance (Instance, Global, &FwhInstance, Virtual); + ASSERT_EFI_ERROR (Status); + + // + // Writes are enabled in the init routine itself + // + if (!FwhInstance->WriteEnabled) { + return EFI_ACCESS_DENIED; + } + // + // Check for invalid conditions + // + if ((NumBytes == NULL) || (Buffer == NULL)) { + return EFI_INVALID_PARAMETER; + } + + if (*NumBytes == 0) { + return EFI_INVALID_PARAMETER; + } + + Status = FvbGetLbaAddress (Instance, Lba, &LbaAddress, &LbaWriteAddress, &LbaLength, NULL, Global, Virtual); + if (EFI_ERROR (Status)) { + return Status; + } + // + // Check if the FV is write enabled + // + FvbGetVolumeAttributes (Instance, &Attributes, Global, Virtual); + + if ((Attributes & EFI_FVB2_WRITE_STATUS) == 0) { + return EFI_ACCESS_DENIED; + } + // + // Perform boundary checks and adjust NumBytes + // + if (BlockOffset > LbaLength) { + return EFI_INVALID_PARAMETER; + } + + if (LbaLength < (*NumBytes + BlockOffset)) { + *NumBytes = (UINT32) (LbaLength - BlockOffset); + Status = EFI_BAD_BUFFER_SIZE; + } + + ReturnStatus = FlashFdWrite ( + LbaWriteAddress + BlockOffset, + LbaAddress, + NumBytes, + Buffer, + LbaLength + ); + if (EFI_ERROR (ReturnStatus)) { + return ReturnStatus; + } + + return Status; +} + +EFI_STATUS +FvbEraseBlock ( + IN UINTN Instance, + IN EFI_LBA Lba, + IN ESAL_FWB_GLOBAL *Global, + IN BOOLEAN Virtual + ) +/*++ + +Routine Description: + Erases and initializes a firmware volume block + +Arguments: + Instance - The FV instance to be erased + Lba - The logical block index to be erased + Global - Pointer to ESAL_FWB_GLOBAL that contains all + instance data + Virtual - Whether CPU is in virtual or physical mode + +Returns: + EFI_SUCCESS - The erase request was successfully completed + EFI_ACCESS_DENIED - The firmware volume is in the WriteDisabled state + EFI_DEVICE_ERROR - The block device is not functioning correctly and + could not be written. Firmware device may have been + partially erased + EFI_INVALID_PARAMETER - Instance not found + +--*/ +{ + + EFI_FVB_ATTRIBUTES_2 Attributes; + UINTN LbaAddress; + UINTN LbaWriteAddress; + EFI_FW_VOL_INSTANCE *FwhInstance; + UINTN LbaLength; + EFI_STATUS Status; + UINTN SectorNum; + UINTN Index; + + FwhInstance = NULL; + + // + // Find the right instance of the FVB private data + // + Status = GetFvbInstance (Instance, Global, &FwhInstance, Virtual); + ASSERT_EFI_ERROR (Status); + + // + // Writes are enabled in the init routine itself + // + if (!FwhInstance->WriteEnabled) { + return EFI_ACCESS_DENIED; + } + // + // Check if the FV is write enabled + // + FvbGetVolumeAttributes (Instance, &Attributes, Global, Virtual); + + if ((Attributes & EFI_FVB2_WRITE_STATUS) == 0) { + return EFI_ACCESS_DENIED; + } + // + // Get the starting address of the block for erase. For debug reasons, + // LbaWriteAddress may not be the same as LbaAddress. + // + Status = FvbGetLbaAddress (Instance, Lba, &LbaAddress, &LbaWriteAddress, &LbaLength, NULL, Global, Virtual); + if (EFI_ERROR (Status)) { + return Status; + } + + SectorNum = LbaLength / SPI_ERASE_SECTOR_SIZE; + for (Index = 0; Index < SectorNum; Index++){ + Status = FlashFdErase ( + LbaWriteAddress + Index * SPI_ERASE_SECTOR_SIZE, + LbaAddress, + SPI_ERASE_SECTOR_SIZE + ); + if (Status != EFI_SUCCESS){ + break; + } + } + + return Status; +} + +EFI_STATUS +FvbEraseCustomBlockRange ( + IN UINTN Instance, + IN EFI_LBA StartLba, + IN UINTN OffsetStartLba, + IN EFI_LBA LastLba, + IN UINTN OffsetLastLba, + IN ESAL_FWB_GLOBAL *Global, + IN BOOLEAN Virtual + ) +/*++ + +Routine Description: + Erases and initializes a specified range of a firmware volume + +Arguments: + Instance - The FV instance to be erased + StartLba - The starting logical block index to be erased + OffsetStartLba - Offset into the starting block at which to + begin erasing + LastLba - The last logical block index to be erased + OffsetStartLba - Offset into the last block at which to end erasing + Global - Pointer to ESAL_FWB_GLOBAL that contains all + instance data + Virtual - Whether CPU is in virtual or physical mode + +Returns: + EFI_SUCCESS - The firmware volume was erased successfully + EFI_ACCESS_DENIED - The firmware volume is in the WriteDisabled state + EFI_DEVICE_ERROR - The block device is not functioning correctly and + could not be written. Firmware device may have been + partially erased + EFI_INVALID_PARAMETER - Instance not found + +--*/ +{ + EFI_LBA Index; + UINTN LbaSize; + UINTN ScratchLbaSizeData; + + // + // First LBA. + // + FvbGetLbaAddress (Instance, StartLba, NULL, NULL, &LbaSize, NULL, Global, Virtual); + + // + // Use the scratch space as the intermediate buffer to transfer data + // Back up the first LBA in scratch space. + // + FvbReadBlock (Instance, StartLba, 0, &LbaSize, Global->FvbScratchSpace[Virtual], Global, Virtual); + + // + // erase now + // + FvbEraseBlock (Instance, StartLba, Global, Virtual); + ScratchLbaSizeData = OffsetStartLba; + + // + // write the data back to the first block + // + if (ScratchLbaSizeData > 0) { + FvbWriteBlock (Instance, StartLba, 0, &ScratchLbaSizeData, Global->FvbScratchSpace[Virtual], Global, Virtual); + } + // + // Middle LBAs + // + if (LastLba > (StartLba + 1)) { + for (Index = (StartLba + 1); Index <= (LastLba - 1); Index++) { + FvbEraseBlock (Instance, Index, Global, Virtual); + } + } + // + // Last LBAs, the same as first LBAs + // + if (LastLba > StartLba) { + FvbGetLbaAddress (Instance, LastLba, NULL, NULL, &LbaSize, NULL, Global, Virtual); + FvbReadBlock (Instance, LastLba, 0, &LbaSize, Global->FvbScratchSpace[Virtual], Global, Virtual); + FvbEraseBlock (Instance, LastLba, Global, Virtual); + } + + ScratchLbaSizeData = LbaSize - (OffsetStartLba + 1); + + return FvbWriteBlock ( + Instance, + LastLba, + (OffsetLastLba + 1), + &ScratchLbaSizeData, + Global->FvbScratchSpace[Virtual], + Global, + Virtual + ); +} + +EFI_STATUS +FvbSetVolumeAttributes ( + IN UINTN Instance, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes, + IN ESAL_FWB_GLOBAL *Global, + IN BOOLEAN Virtual + ) +/*++ + +Routine Description: + Modifies the current settings of the firmware volume according to the + input parameter, and returns the new setting of the volume + +Arguments: + Instance - The FV instance whose attributes is going to be + modified + Attributes - On input, it is a pointer to EFI_FVB_ATTRIBUTES_2 + containing the desired firmware volume settings. + On successful return, it contains the new settings + of the firmware volume + Global - Pointer to ESAL_FWB_GLOBAL that contains all + instance data + Virtual - Whether CPU is in virtual or physical mode + +Returns: + EFI_SUCCESS - Successfully returns + EFI_ACCESS_DENIED - The volume setting is locked and cannot be modified + EFI_INVALID_PARAMETER - Instance not found, or The attributes requested are + in conflict with the capabilities as declared in the + firmware volume header + +--*/ +{ + EFI_FW_VOL_INSTANCE *FwhInstance; + EFI_FVB_ATTRIBUTES_2 OldAttributes; + EFI_FVB_ATTRIBUTES_2 *AttribPtr; + UINT32 Capabilities; + UINT32 OldStatus; + UINT32 NewStatus; + EFI_STATUS Status; + + FwhInstance = NULL; + + // + // Find the right instance of the FVB private data + // + Status = GetFvbInstance (Instance, Global, &FwhInstance, Virtual); + ASSERT_EFI_ERROR (Status); + + AttribPtr = (EFI_FVB_ATTRIBUTES_2 *) &(FwhInstance->VolumeHeader.Attributes); + OldAttributes = *AttribPtr; + Capabilities = OldAttributes & EFI_FVB2_CAPABILITIES; + OldStatus = OldAttributes & EFI_FVB2_STATUS; + NewStatus = *Attributes & EFI_FVB2_STATUS; + + // + // If firmware volume is locked, no status bit can be updated + // + if (OldAttributes & EFI_FVB2_LOCK_STATUS) { + if (OldStatus ^ NewStatus) { + return EFI_ACCESS_DENIED; + } + } + // + // Test read disable + // + if ((Capabilities & EFI_FVB2_READ_DISABLED_CAP) == 0) { + if ((NewStatus & EFI_FVB2_READ_STATUS) == 0) { + return EFI_INVALID_PARAMETER; + } + } + // + // Test read enable + // + if ((Capabilities & EFI_FVB2_READ_ENABLED_CAP) == 0) { + if (NewStatus & EFI_FVB2_READ_STATUS) { + return EFI_INVALID_PARAMETER; + } + } + // + // Test write disable + // + if ((Capabilities & EFI_FVB2_WRITE_DISABLED_CAP) == 0) { + if ((NewStatus & EFI_FVB2_WRITE_STATUS) == 0) { + return EFI_INVALID_PARAMETER; + } + } + // + // Test write enable + // + if ((Capabilities & EFI_FVB2_WRITE_ENABLED_CAP) == 0) { + if (NewStatus & EFI_FVB2_WRITE_STATUS) { + return EFI_INVALID_PARAMETER; + } + } + // + // Test lock + // + if ((Capabilities & EFI_FVB2_LOCK_CAP) == 0) { + if (NewStatus & EFI_FVB2_LOCK_STATUS) { + return EFI_INVALID_PARAMETER; + } + } + + *AttribPtr = (*AttribPtr) & (0xFFFFFFFF & (~EFI_FVB2_STATUS)); + *AttribPtr = (*AttribPtr) | NewStatus; + *Attributes = *AttribPtr; + + return EFI_SUCCESS; +} +// +// FVB protocol APIs +// +EFI_STATUS +EFIAPI +FvbProtocolGetPhysicalAddress ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + OUT EFI_PHYSICAL_ADDRESS *Address + ) +/*++ + +Routine Description: + + Retrieves the physical address of the device. + +Arguments: + + This - Calling context + Address - Output buffer containing the address. + +Returns: + +Returns: + EFI_SUCCESS - Successfully returns + +--*/ +{ + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice; + + FvbDevice = FVB_DEVICE_FROM_THIS (This); + + return FvbGetPhysicalAddress (FvbDevice->Instance, Address, mFvbModuleGlobal, EfiGoneVirtual ()); +} + +EFI_STATUS +FvbProtocolGetBlockSize ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN EFI_LBA Lba, + OUT UINTN *BlockSize, + OUT UINTN *NumOfBlocks + ) +/*++ + +Routine Description: + Retrieve the size of a logical block + +Arguments: + This - Calling context + Lba - Indicates which block to return the size for. + BlockSize - A pointer to a caller allocated UINTN in which + the size of the block is returned + NumOfBlocks - a pointer to a caller allocated UINTN in which the + number of consecutive blocks starting with Lba is + returned. All blocks in this range have a size of + BlockSize + +Returns: + EFI_SUCCESS - The firmware volume was read successfully and + contents are in Buffer + +--*/ +{ + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice; + + FvbDevice = FVB_DEVICE_FROM_THIS (This); + + return FvbGetLbaAddress ( + FvbDevice->Instance, + Lba, + NULL, + NULL, + BlockSize, + NumOfBlocks, + mFvbModuleGlobal, + EfiGoneVirtual () + ); +} + +EFI_STATUS +EFIAPI +FvbProtocolGetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ) +/*++ + +Routine Description: + Retrieves Volume attributes. No polarity translations are done. + +Arguments: + This - Calling context + Attributes - output buffer which contains attributes + +Returns: + EFI_SUCCESS - Successfully returns + +--*/ +{ + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice; + + FvbDevice = FVB_DEVICE_FROM_THIS (This); + + return FvbGetVolumeAttributes (FvbDevice->Instance, Attributes, mFvbModuleGlobal, EfiGoneVirtual ()); +} + +EFI_STATUS +EFIAPI +FvbProtocolSetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ) +/*++ + +Routine Description: + Sets Volume attributes. No polarity translations are done. + +Arguments: + This - Calling context + Attributes - output buffer which contains attributes + +Returns: + EFI_SUCCESS - Successfully returns + +--*/ +{ + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice; + + FvbDevice = FVB_DEVICE_FROM_THIS (This); + + return FvbSetVolumeAttributes (FvbDevice->Instance, Attributes, mFvbModuleGlobal, EfiGoneVirtual ()); +} + +EFI_STATUS +EFIAPI +FvbProtocolEraseBlocks ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + ... + ) +/*++ + +Routine Description: + + The EraseBlock() function erases one or more blocks as denoted by the + variable argument list. The entire parameter list of blocks must be verified + prior to erasing any blocks. If a block is requested that does not exist + within the associated firmware volume (it has a larger index than the last + block of the firmware volume), the EraseBlock() function must return + EFI_INVALID_PARAMETER without modifying the contents of the firmware volume. + +Arguments: + This - Calling context + ... - Starting LBA followed by Number of Lba to erase. + a -1 to terminate the list. + +Returns: + EFI_SUCCESS - The erase request was successfully completed + EFI_ACCESS_DENIED - The firmware volume is in the WriteDisabled state + EFI_DEVICE_ERROR - The block device is not functioning correctly and + could not be written. Firmware device may have been + partially erased + +--*/ +{ + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice; + EFI_FW_VOL_INSTANCE *FwhInstance; + UINTN NumOfBlocks; + VA_LIST args; + EFI_LBA StartingLba; + UINTN NumOfLba; + EFI_STATUS Status; + + FwhInstance = NULL; + FvbDevice = FVB_DEVICE_FROM_THIS (This); + + Status = GetFvbInstance (FvbDevice->Instance, mFvbModuleGlobal, &FwhInstance, EfiGoneVirtual ()); + ASSERT_EFI_ERROR (Status); + + NumOfBlocks = FwhInstance->NumOfBlocks; + + VA_START (args, This); + + do { + StartingLba = VA_ARG (args, EFI_LBA); + if (StartingLba == EFI_LBA_LIST_TERMINATOR) { + break; + } + + NumOfLba = VA_ARG (args, UINTN); + + // + // Check input parameters + // + if (NumOfLba == 0) { + VA_END (args); + return EFI_INVALID_PARAMETER; + } + + if ((StartingLba + NumOfLba) > NumOfBlocks) { + return EFI_INVALID_PARAMETER; + } + } while (TRUE); + + VA_END (args); + + VA_START (args, This); + do { + StartingLba = VA_ARG (args, EFI_LBA); + if (StartingLba == EFI_LBA_LIST_TERMINATOR) { + break; + } + + NumOfLba = VA_ARG (args, UINTN); + + while (NumOfLba > 0) { + Status = FvbEraseBlock (FvbDevice->Instance, StartingLba, mFvbModuleGlobal, EfiGoneVirtual ()); + if (EFI_ERROR (Status)) { + VA_END (args); + return Status; + } + + StartingLba++; + NumOfLba--; + } + + } while (TRUE); + + VA_END (args); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +FvbProtocolWrite ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ) +/*++ + +Routine Description: + + Writes data beginning at Lba:Offset from FV. The write terminates either + when *NumBytes of data have been written, or when a block boundary is + reached. *NumBytes is updated to reflect the actual number of bytes + written. The write opertion does not include erase. This routine will + attempt to write only the specified bytes. If the writes do not stick, + it will return an error. + +Arguments: + This - Calling context + Lba - Block in which to begin write + Offset - Offset in the block at which to begin write + NumBytes - On input, indicates the requested write size. On + output, indicates the actual number of bytes written + Buffer - Buffer containing source data for the write. + +Returns: + EFI_SUCCESS - The firmware volume was written successfully + EFI_BAD_BUFFER_SIZE - Write attempted across a LBA boundary. On output, + NumBytes contains the total number of bytes + actually written + EFI_ACCESS_DENIED - The firmware volume is in the WriteDisabled state + EFI_DEVICE_ERROR - The block device is not functioning correctly and + could not be written + EFI_INVALID_PARAMETER - NumBytes or Buffer are NULL + +--*/ +{ + + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice; + + FvbDevice = FVB_DEVICE_FROM_THIS (This); + + return FvbWriteBlock (FvbDevice->Instance, Lba, Offset, NumBytes, Buffer, mFvbModuleGlobal, EfiGoneVirtual ()); +} + +EFI_STATUS +EFIAPI +FvbProtocolRead ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ) +/*++ + +Routine Description: + + Reads data beginning at Lba:Offset from FV. The Read terminates either + when *NumBytes of data have been read, or when a block boundary is + reached. *NumBytes is updated to reflect the actual number of bytes + written. The write opertion does not include erase. This routine will + attempt to write only the specified bytes. If the writes do not stick, + it will return an error. + +Arguments: + This - Calling context + Lba - Block in which to begin Read + Offset - Offset in the block at which to begin Read + NumBytes - On input, indicates the requested write size. On + output, indicates the actual number of bytes Read + Buffer - Buffer containing source data for the Read. + +Returns: + EFI_SUCCESS - The firmware volume was read successfully and + contents are in Buffer + EFI_BAD_BUFFER_SIZE - Read attempted across a LBA boundary. On output, + NumBytes contains the total number of bytes returned + in Buffer + EFI_ACCESS_DENIED - The firmware volume is in the ReadDisabled state + EFI_DEVICE_ERROR - The block device is not functioning correctly and + could not be read + EFI_INVALID_PARAMETER - NumBytes or Buffer are NULL + +--*/ +{ + + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice; + EFI_STATUS Status; + + FvbDevice = FVB_DEVICE_FROM_THIS (This); + Status = FvbReadBlock (FvbDevice->Instance, Lba, Offset, NumBytes, Buffer, mFvbModuleGlobal, EfiGoneVirtual ()); + + return Status; +} + +EFI_STATUS +ValidateFvHeader ( + EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader + ) +/*++ + +Routine Description: + Check the integrity of firmware volume header + +Arguments: + FwVolHeader - A pointer to a firmware volume header + +Returns: + EFI_SUCCESS - The firmware volume is consistent + EFI_NOT_FOUND - The firmware volume has corrupted. So it is not an FV + +--*/ +{ + UINT16 *Ptr; + UINT16 HeaderLength; + UINT16 Checksum; + + // + // Verify the header revision, header signature, length + // Length of FvBlock cannot be 2**64-1 + // HeaderLength cannot be an odd number + // + #ifndef R864_BUILD + if (((FwVolHeader->Revision != EFI_FVH_REVISION) && (FwVolHeader->Revision != EFI_FVH_REVISION)) || + #else + if ((FwVolHeader->Revision != EFI_FVH_REVISION) || + #endif + (FwVolHeader->Signature != EFI_FVH_SIGNATURE) || + (FwVolHeader->FvLength == ((UINTN) -1)) || + ((FwVolHeader->HeaderLength & 0x01) != 0) + ) { + return EFI_NOT_FOUND; + } + // + // Verify the header checksum + // + HeaderLength = (UINT16) (FwVolHeader->HeaderLength / 2); + Ptr = (UINT16 *) FwVolHeader; + Checksum = 0; + while (HeaderLength > 0) { + Checksum = Checksum + (*Ptr); + Ptr++; + HeaderLength--; + } + + if (Checksum != 0) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +GetFvbHeader ( + VOID **HobList, + OUT EFI_FIRMWARE_VOLUME_HEADER **FwVolHeader, + OUT EFI_PHYSICAL_ADDRESS *BaseAddress, + OUT BOOLEAN *WriteBack + ) +{ + EFI_STATUS Status; + + Status = EFI_SUCCESS; + *WriteBack = FALSE; + + if (*FwVolHeader == NULL) { + *BaseAddress = PcdGet32 (PcdFlashFvRecoveryBase); + } else if (*FwVolHeader == (VOID *)(UINTN)PcdGet32 (PcdFlashFvRecoveryBase)) { + *BaseAddress = PcdGet32 (PcdFlashFvMainBase); + } else if (*FwVolHeader == (VOID *)(UINTN)PcdGet32 (PcdFlashFvMainBase)) { + *BaseAddress = PcdGet32 (PcdFlashNvStorageVariableBase); + } else { + return EFI_NOT_FOUND; + } + + DEBUG((EFI_D_INFO, "Fvb base : %08x\n",*BaseAddress)); + + *FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) (*BaseAddress); + Status = ValidateFvHeader (*FwVolHeader); + if (EFI_ERROR (Status)) { + // + // Get FvbInfo + // + *WriteBack = TRUE; + + Status = GetFvbInfo (*BaseAddress, FwVolHeader); + DEBUG(( DEBUG_ERROR, "Through GetFvbInfo: %08x!\n",*BaseAddress)); + + ASSERT_EFI_ERROR (Status); + } + + return EFI_SUCCESS; +} + + +EFI_STATUS +SmmSpiInit ( + VOID + ) +{ + UINT8 SpiStatus; + UINT8 FlashIndex; + UINT8 FlashID[3]; + EFI_STATUS Status; + + // + // Obtain a handle for ICH SPI Protocol + // + ASSERT(mSmst != NULL); + if (mFvbModuleGlobal->SmmSpiProtocol == NULL){ + Status = mSmst->SmmLocateProtocol (&gEfiSmmSpiProtocolGuid, NULL, (VOID **) &mFvbModuleGlobal->SmmSpiProtocol); + ASSERT_EFI_ERROR(Status); + } + // + // attempt to identify flash part and initialize spi table + // + for (FlashIndex = 0; FlashIndex < EnumSpiFlashMax; FlashIndex++) { + Status = mFvbModuleGlobal->SmmSpiProtocol->Init ( + mFvbModuleGlobal->SmmSpiProtocol, + &(mSpiInitTable[FlashIndex]) + ); + if (!EFI_ERROR (Status)) { + // + // read vendor/device IDs to check if flash device is supported + // + Status = mFvbModuleGlobal->SmmSpiProtocol->Execute ( + mFvbModuleGlobal->SmmSpiProtocol, + SPI_OPCODE_JEDEC_ID_INDEX, + SPI_WREN_INDEX, + TRUE, + FALSE, + FALSE, + 0, + 3, + FlashID, + EnumSpiRegionAll + ); + if (!EFI_ERROR (Status)) { + if (((FlashID[0] == mSpiInitTable[FlashIndex].VendorId) && + (FlashID[2] == mSpiInitTable[FlashIndex].DeviceId1)) || + ((FlashID[0] == SPI_AT26DF321_ID1) && + (FlashID[0] == mSpiInitTable[FlashIndex].VendorId) && + (FlashID[1] == mSpiInitTable[FlashIndex].DeviceId0))) { + // + // Supported SPI device found + // + DEBUG ( + ((EFI_D_INFO), + "Smm Mode: Supported SPI Flash device found, Vendor Id: 0x%02x, Device ID: 0x%02x%02x!\n", + FlashID[0], + FlashID[1], + FlashID[2]) + ); + break; + } + } + } + } + + if (FlashIndex >= EnumSpiFlashMax) { + Status = EFI_UNSUPPORTED; + DEBUG ( + (EFI_D_ERROR, + "ERROR - Unknown SPI Flash Device, Vendor Id: 0x%02x, Device ID: 0x%02x%02x!\n", + FlashID[0], + FlashID[1], + FlashID[2]) + ); + ASSERT_EFI_ERROR (Status); + } + + SpiStatus = 0; + Status = mFvbModuleGlobal->SmmSpiProtocol->Execute ( + mFvbModuleGlobal->SmmSpiProtocol, + SPI_OPCODE_WRITE_S_INDEX, // OpcodeIndex + 1, // PrefixOpcodeIndex + TRUE, // DataCycle + TRUE, // Atomic + TRUE, // ShiftOut + 0, // Address + 1, // Data Number + &SpiStatus, + EnumSpiRegionAll // SPI_REGION_TYPE + ); + return Status; +} + +EFI_STATUS +SmmSpiNotificationFunction ( + IN CONST EFI_GUID *Protocol, + IN VOID *Interface, + IN EFI_HANDLE Handle + ) +{ + return SmmSpiInit(); +} + + +VOID +EFIAPI +GetFullDriverPath ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable, + OUT EFI_DEVICE_PATH_PROTOCOL **CompleteFilePath + ) +/*++ + +Routine Description: + + Function is used to get the full device path for this driver. + +Arguments: + + ImageHandle - The loaded image handle of this driver. + SystemTable - The pointer of system table. + CompleteFilePath - The pointer of returned full file path + +Returns: + + none + +--*/ +{ + EFI_STATUS Status; + EFI_LOADED_IMAGE_PROTOCOL *LoadedImage; + EFI_DEVICE_PATH_PROTOCOL *ImageDevicePath; + + + Status = gBS->HandleProtocol ( + ImageHandle, + &gEfiLoadedImageProtocolGuid, + (VOID **) &LoadedImage + ); + ASSERT_EFI_ERROR (Status); + + Status = gBS->HandleProtocol ( + LoadedImage->DeviceHandle, + &gEfiDevicePathProtocolGuid, + (VOID *) &ImageDevicePath + ); + ASSERT_EFI_ERROR (Status); + + *CompleteFilePath = AppendDevicePath ( + ImageDevicePath, + LoadedImage->FilePath + ); + + return ; +} + + + +EFI_STATUS +FvbInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +/*++ + +Routine Description: + This function does common initialization for FVB services + +Arguments: + +Returns: + +--*/ +{ + EFI_STATUS Status; + EFI_FW_VOL_INSTANCE *FwhInstance; + EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader; + EFI_FIRMWARE_VOLUME_HEADER *TempFwVolHeader; + VOID *HobList; + VOID *FirmwareVolumeHobList; + UINT32 BufferSize; + EFI_FV_BLOCK_MAP_ENTRY *PtrBlockMapEntry; + BOOLEAN WriteEnabled; + BOOLEAN WriteLocked; + EFI_HANDLE FwbHandle; + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice; + EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *OldFwbInterface; + EFI_DEVICE_PATH_PROTOCOL *FwbDevicePath; + EFI_DEVICE_PATH_PROTOCOL *TempFwbDevicePath; + UINT32 MaxLbaSize; + EFI_PHYSICAL_ADDRESS BaseAddress; + BOOLEAN WriteBack; + UINTN NumOfBlocks; + UINTN HeaderLength; + UINT8 SpiStatus; + UINT8 FlashIndex; + UINT8 FlashID[3]; + EFI_DEVICE_PATH_PROTOCOL *CompleteFilePath; + UINT8 PrefixOpcodeIndex; + BOOLEAN InSmm; + EFI_SMM_BASE2_PROTOCOL *mSmmBase2; + EFI_HANDLE Handle; + + VOID *Registration; + EFI_EVENT Event; + + CompleteFilePath = NULL; + GetFullDriverPath (ImageHandle, SystemTable, &CompleteFilePath); + + Status = EfiGetSystemConfigurationTable (&gEfiHobListGuid, &HobList); + + // + // No FV HOBs found + // + ASSERT_EFI_ERROR (Status); + + + // + // Allocate runtime services data for global variable, which contains + // the private data of all firmware volume block instances + // + mFvbModuleGlobal = (ESAL_FWB_GLOBAL *)AllocateRuntimeZeroPool(sizeof (ESAL_FWB_GLOBAL )); + ASSERT(mFvbModuleGlobal); + mSmmBase2 = NULL; + Status = gBS->LocateProtocol ( + &gEfiSmmBase2ProtocolGuid, + NULL, + (VOID **) &mSmmBase2 + ); + + if (mSmmBase2 == NULL) { + InSmm = FALSE; + } else { + mSmmBase2->InSmm (mSmmBase2, &InSmm); + mSmmBase2->GetSmstLocation (mSmmBase2, &mSmst); + + } + + if (!InSmm) { + mInSmmMode = 0; + // + // Obtain a handle for ICH SPI Protocol + // + Status = gBS->LocateProtocol (&gEfiSpiProtocolGuid, NULL, (VOID **) &mFvbModuleGlobal->SpiProtocol); + ASSERT_EFI_ERROR (Status); + + // + // attempt to identify flash part and initialize spi table + // + for (FlashIndex = 0; FlashIndex < EnumSpiFlashMax; FlashIndex++) { + Status = mFvbModuleGlobal->SpiProtocol->Init ( + mFvbModuleGlobal->SpiProtocol, + &(mSpiInitTable[FlashIndex]) + ); + if (!EFI_ERROR (Status)) { + // + // read vendor/device IDs to check if flash device is supported + // + Status = mFvbModuleGlobal->SpiProtocol->Execute ( + mFvbModuleGlobal->SpiProtocol, + SPI_OPCODE_JEDEC_ID_INDEX, + SPI_WREN_INDEX, + TRUE, + FALSE, + FALSE, + 0, + 3, + FlashID, + EnumSpiRegionAll + ); + if (!EFI_ERROR (Status)) { + if (((FlashID[0] == mSpiInitTable[FlashIndex].VendorId) && + (FlashID[2] == mSpiInitTable[FlashIndex].DeviceId1)) || + ((FlashID[0] == SPI_AT26DF321_ID1) && + (FlashID[0] == mSpiInitTable[FlashIndex].VendorId) && + (FlashID[1] == mSpiInitTable[FlashIndex].DeviceId0))) { + // + // Supported SPI device found + // + DEBUG ( + ((EFI_D_INFO), + "Supported SPI Flash device found, Vendor Id: 0x%02x, Device ID: 0x%02x%02x!\n", + FlashID[0], + FlashID[1], + FlashID[2]) + ); + + PublishFlashDeviceInfo (&mSpiInitTable[FlashIndex]); + break; + } + } + } + } + + if (FlashIndex >= EnumSpiFlashMax) { + Status = EFI_UNSUPPORTED; + DEBUG ( + (DEBUG_ERROR, + "ERROR - Unknown SPI Flash Device, Vendor Id: 0x%02x, Device ID: 0x%02x%02x!\n", + FlashID[0], + FlashID[1], + FlashID[2]) + ); + ASSERT_EFI_ERROR (Status); + } + + // + // Unlock all regions by writing to status register + // This could be SPI device specific, need to follow the datasheet + // To write to Write Status Register the Spi PrefixOpcode needs to be: + // 0 for Atmel parts + // 0 for Intel parts + // 0 for Macronix parts + // 0 for Winbond parts + // 1 for SST parts + SpiStatus = 0; + if (FlashID[0] == SPI_SST25VF016B_ID1) { + PrefixOpcodeIndex = 1; + } else { + PrefixOpcodeIndex = 0; + } + Status = mFvbModuleGlobal->SpiProtocol->Execute ( + mFvbModuleGlobal->SpiProtocol, + SPI_OPCODE_WRITE_S_INDEX, // OpcodeIndex + PrefixOpcodeIndex, // PrefixOpcodeIndex + TRUE, // DataCycle + TRUE, // Atomic + TRUE, // ShiftOut + 0, // Address + 1, // Data Number + &SpiStatus, + EnumSpiRegionAll // SPI_REGION_TYPE + ); + + + } else { + mInSmmMode = 1; + + Status = mSmst->SmmLocateProtocol (&gEfiSmmSpiProtocolGuid, NULL, (VOID **) &mFvbModuleGlobal->SmmSpiProtocol); + if (EFI_ERROR(Status)) { + Registration = NULL; + Status = mSmst->SmmRegisterProtocolNotify ( + &gEfiSmmSpiProtocolGuid, + SmmSpiNotificationFunction, + &Registration + ); + } else { + Status = SmmSpiInit(); + } + + } + + // + // Calculate the total size for all firmware volume block instances + // + BufferSize = 0; + FirmwareVolumeHobList = HobList; + FwVolHeader = NULL; + do { + Status = GetFvbHeader (&FirmwareVolumeHobList, &FwVolHeader, &BaseAddress, &WriteBack); + if (EFI_ERROR (Status)) { + break; + } + + if (FwVolHeader) { + BufferSize += (FwVolHeader->HeaderLength + sizeof (EFI_FW_VOL_INSTANCE) - sizeof (EFI_FIRMWARE_VOLUME_HEADER)); + } + } while (TRUE); + + // + // Only need to allocate once. There is only one copy of physical memory for + // the private data of each FV instance. But in virtual mode or in physical + // mode, the address of the the physical memory may be different. + // + mFvbModuleGlobal->FvInstance[FVB_PHYSICAL] = (EFI_FW_VOL_INSTANCE *) AllocateRuntimeZeroPool (BufferSize); + ASSERT(mFvbModuleGlobal->FvInstance[FVB_PHYSICAL]); + // + // Make a virtual copy of the FvInstance pointer. + // + FwhInstance = mFvbModuleGlobal->FvInstance[FVB_PHYSICAL]; + mFvbModuleGlobal->FvInstance[FVB_VIRTUAL] = FwhInstance; + + mFvbModuleGlobal->NumFv = 0; + FirmwareVolumeHobList = HobList; + TempFwVolHeader = NULL; + + MaxLbaSize = 0; + + // + // Fill in the private data of each firmware volume block instance + // + // Foreach Fv HOB in the FirmwareVolumeHobList, loop + // + do { + Status = GetFvbHeader (&FirmwareVolumeHobList, &TempFwVolHeader, &BaseAddress, &WriteBack); + if (EFI_ERROR (Status)) { + break; + } + FwVolHeader = TempFwVolHeader; + + if (!FwVolHeader) { + continue; + } + + + CopyMem ((UINTN *) &(FwhInstance->VolumeHeader), (UINTN *) FwVolHeader, FwVolHeader->HeaderLength); + FwVolHeader = &(FwhInstance->VolumeHeader); + + FwhInstance->FvBase[FVB_PHYSICAL] = (UINTN) BaseAddress; + FwhInstance->FvBase[FVB_VIRTUAL] = (UINTN) BaseAddress; + + // + // FwhInstance->FvWriteBase may not be the same as FwhInstance->FvBase + // + FwhInstance->FvWriteBase[FVB_PHYSICAL] = (UINTN) BaseAddress; + WriteEnabled = TRUE; + + // + // Every pointer should have a virtual copy. + // + FwhInstance->FvWriteBase[FVB_VIRTUAL] = FwhInstance->FvWriteBase[FVB_PHYSICAL]; + + FwhInstance->WriteEnabled = WriteEnabled; + EfiInitializeLock (&(FwhInstance->FvbDevLock), TPL_HIGH_LEVEL); + + NumOfBlocks = 0; + WriteLocked = FALSE; + + if (WriteEnabled) { + for (PtrBlockMapEntry = FwVolHeader->BlockMap; PtrBlockMapEntry->NumBlocks != 0; PtrBlockMapEntry++) { + // + // Get the maximum size of a block. The size will be used to allocate + // buffer for Scratch space, the intermediate buffer for FVB extension + // protocol + // + if (MaxLbaSize < PtrBlockMapEntry->Length) { + MaxLbaSize = PtrBlockMapEntry->Length; + } + + NumOfBlocks = NumOfBlocks + PtrBlockMapEntry->NumBlocks; + } + // + // Write back a healthy FV header + // + if (WriteBack && (!WriteLocked)) { + + Status = FlashFdErase ( + (UINTN) FwhInstance->FvWriteBase[0], + (UINTN) BaseAddress, + FwVolHeader->BlockMap->Length + ); + + HeaderLength = (UINTN) FwVolHeader->HeaderLength; + Status = FlashFdWrite ( + (UINTN) FwhInstance->FvWriteBase[0], + (UINTN) BaseAddress, + &HeaderLength, + (UINT8 *) FwVolHeader, + FwVolHeader->BlockMap->Length + ); + + } + } + // + // The total number of blocks in the FV. + // + FwhInstance->NumOfBlocks = NumOfBlocks; + + // + // If the FV is write locked, set the appropriate attributes + // + if (WriteLocked) { + // + // write disabled + // + FwhInstance->VolumeHeader.Attributes &= ~EFI_FVB2_WRITE_STATUS; + // + // lock enabled + // + FwhInstance->VolumeHeader.Attributes |= EFI_FVB2_LOCK_STATUS; + } + + // + // Allocate and initialize FVB Device in a runtime data buffer + // + FvbDevice = AllocateRuntimeCopyPool (sizeof (EFI_FW_VOL_BLOCK_DEVICE), &mFvbDeviceTemplate); + ASSERT (FvbDevice); + + FvbDevice->Instance = mFvbModuleGlobal->NumFv; + mFvbModuleGlobal->NumFv++; + + // + // FV does not contains extension header, then produce MEMMAP_DEVICE_PATH + // + if (FwVolHeader->ExtHeaderOffset == 0) { + FvbDevice->FvDevicePath.MemMapDevPath.StartingAddress = BaseAddress; + FvbDevice->FvDevicePath.MemMapDevPath.EndingAddress = BaseAddress + (FwVolHeader->FvLength - 1); + FwbDevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&FvbDevice->FvDevicePath; + } else { + CopyGuid ( + &FvbDevice->UefiFvDevicePath.FvDevPath.FvName, + (EFI_GUID *)(UINTN)(BaseAddress + FwVolHeader->ExtHeaderOffset) + ); + FwbDevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&FvbDevice->UefiFvDevicePath; + } + + if (!InSmm) { + // + // Find a handle with a matching device path that has supports FW Block protocol + // + TempFwbDevicePath = FwbDevicePath; + Status = gBS->LocateDevicePath (&gEfiFirmwareVolumeBlockProtocolGuid, &TempFwbDevicePath, &FwbHandle); + if (EFI_ERROR (Status)) { + // + // LocateDevicePath fails so install a new interface and device path + // + FwbHandle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces ( + &FwbHandle, + &gEfiFirmwareVolumeBlockProtocolGuid, + &FvbDevice->FwVolBlockInstance, + &gEfiDevicePathProtocolGuid, + FwbDevicePath, + NULL + ); + ASSERT_EFI_ERROR (Status); + } else if (EfiIsDevicePathEnd (TempFwbDevicePath)) { + // + // Device already exists, so reinstall the FVB protocol + // + Status = gBS->HandleProtocol ( + FwbHandle, + &gEfiFirmwareVolumeBlockProtocolGuid, + (VOID **) &OldFwbInterface + ); + ASSERT_EFI_ERROR (Status); + + Status = gBS->ReinstallProtocolInterface ( + FwbHandle, + &gEfiFirmwareVolumeBlockProtocolGuid, + OldFwbInterface, + &FvbDevice->FwVolBlockInstance + ); + ASSERT_EFI_ERROR (Status); + + } else { + // + // There was a FVB protocol on an End Device Path node + // + ASSERT (FALSE); + } + } else { + FwbHandle = NULL; + Status = mSmst->SmmInstallProtocolInterface ( + &FwbHandle, + &gEfiSmmFirmwareVolumeBlockProtocolGuid, + EFI_NATIVE_INTERFACE, + &FvbDevice->FwVolBlockInstance + ); + ASSERT_EFI_ERROR (Status); + } + + FwhInstance = (EFI_FW_VOL_INSTANCE *) + ( + (UINTN) ((UINT8 *) FwhInstance) + FwVolHeader->HeaderLength + + (sizeof (EFI_FW_VOL_INSTANCE) - sizeof (EFI_FIRMWARE_VOLUME_HEADER)) + ); + } while (TRUE); + + // + // Allocate for scratch space, an intermediate buffer for FVB extention + // + + mFvbModuleGlobal->FvbScratchSpace[FVB_PHYSICAL] = AllocateRuntimeZeroPool (MaxLbaSize); + + ASSERT (mFvbModuleGlobal->FvbScratchSpace[FVB_PHYSICAL]); + + mFvbModuleGlobal->FvbScratchSpace[FVB_VIRTUAL] = mFvbModuleGlobal->FvbScratchSpace[FVB_PHYSICAL]; + + if (!InSmm) { + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + FvbVirtualddressChangeEvent, + NULL, + &gEfiEventVirtualAddressChangeGuid, + &Event + ); + ASSERT_EFI_ERROR (Status); + } else { + // + // Inform other platform drivers that SPI device discovered and + // SPI interface ready for use. + // + Handle = NULL; + Status = gBS->InstallProtocolInterface ( + &Handle, + &gEfiSmmSpiReadyProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + } + return EFI_SUCCESS; +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/FwBlockService.h b/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/FwBlockService.h new file mode 100644 index 0000000000..11dcf12230 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/FwBlockService.h @@ -0,0 +1,308 @@ +/** @file +Firmware volume block driver for SPI device + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#ifndef _FW_BLOCK_SERVICE_H +#define _FW_BLOCK_SERVICE_H + + +#include "SpiFlashDevice.h" + +// +// Statements that include other header files + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +// +// Define two helper macro to extract the Capability field or Status field in FVB +// bit fields +// +#define EFI_FVB2_CAPABILITIES (EFI_FVB2_READ_DISABLED_CAP | \ + EFI_FVB2_READ_ENABLED_CAP | \ + EFI_FVB2_WRITE_DISABLED_CAP | \ + EFI_FVB2_WRITE_ENABLED_CAP | \ + EFI_FVB2_LOCK_CAP \ + ) + +#define EFI_FVB2_STATUS (EFI_FVB2_READ_STATUS | EFI_FVB2_WRITE_STATUS | EFI_FVB2_LOCK_STATUS) + +#define EFI_INTERNAL_POINTER 0x00000004 +#define FVB_PHYSICAL 0 +#define FVB_VIRTUAL 1 + +typedef struct { + EFI_LOCK FvbDevLock; + UINTN FvBase[2]; + UINTN FvWriteBase[2]; + UINTN NumOfBlocks; + BOOLEAN WriteEnabled; + EFI_FIRMWARE_VOLUME_HEADER VolumeHeader; +} EFI_FW_VOL_INSTANCE; + +typedef struct { + UINT32 NumFv; + EFI_FW_VOL_INSTANCE *FvInstance[2]; + UINT8 *FvbScratchSpace[2]; + EFI_SPI_PROTOCOL *SpiProtocol; + EFI_SPI_PROTOCOL *SmmSpiProtocol; +} ESAL_FWB_GLOBAL; + +// +// SPI default opcode slots +// +#define SPI_OPCODE_JEDEC_ID_INDEX 0 +#define SPI_OPCODE_READ_ID_INDEX 1 +#define SPI_OPCODE_WRITE_S_INDEX 2 +#define SPI_OPCODE_WRITE_INDEX 3 +#define SPI_OPCODE_READ_INDEX 4 +#define SPI_OPCODE_ERASE_INDEX 5 +#define SPI_OPCODE_READ_S_INDEX 6 +#define SPI_OPCODE_CHIP_ERASE_INDEX 7 + +#define SPI_ERASE_SECTOR_SIZE SIZE_4KB //This is the chipset requirement + +// +// Fvb Protocol instance data +// +#define FVB_DEVICE_FROM_THIS(a) CR (a, EFI_FW_VOL_BLOCK_DEVICE, FwVolBlockInstance, FVB_DEVICE_SIGNATURE) +#define FVB_EXTEND_DEVICE_FROM_THIS(a) CR (a, EFI_FW_VOL_BLOCK_DEVICE, FvbExtension, FVB_DEVICE_SIGNATURE) +#define FVB_DEVICE_SIGNATURE SIGNATURE_32 ('F', 'V', 'B', 'C') +// +// Device Path +// +#define EFI_END_ENTIRE_DEVICE_PATH_SUBTYPE 0xff +#define EfiDevicePathType(a) (((a)->Type) & 0x7f) +#define EfiIsDevicePathEndType(a) (EfiDevicePathType (a) == 0x7f) +#define EfiIsDevicePathEndSubType(a) ((a)->SubType == EFI_END_ENTIRE_DEVICE_PATH_SUBTYPE) +#define EfiIsDevicePathEnd(a) (EfiIsDevicePathEndType (a) && EfiIsDevicePathEndSubType (a)) + +typedef struct { + MEMMAP_DEVICE_PATH MemMapDevPath; + EFI_DEVICE_PATH_PROTOCOL EndDevPath; +} FV_DEVICE_PATH; + +// +// UEFI Specification define FV device path format if FV provide name GUID in extension header +// +typedef struct { + MEDIA_FW_VOL_DEVICE_PATH FvDevPath; + EFI_DEVICE_PATH_PROTOCOL EndDevPath; +} UEFI_FV_DEVICE_PATH; + +typedef struct { + UINTN Signature; + FV_DEVICE_PATH FvDevicePath; + UEFI_FV_DEVICE_PATH UefiFvDevicePath; + UINTN Instance; + EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL FwVolBlockInstance; +} EFI_FW_VOL_BLOCK_DEVICE; + +typedef struct { + EFI_PHYSICAL_ADDRESS BaseAddress; + EFI_FIRMWARE_VOLUME_HEADER FvbInfo; + // + // EFI_FV_BLOCK_MAP_ENTRY ExtraBlockMap[n];//n=0 + // + EFI_FV_BLOCK_MAP_ENTRY End[1]; +} EFI_FVB_MEDIA_INFO; + +VOID +FvbVirtualddressChangeEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ); + +EFI_STATUS +GetFvbInfo ( + IN EFI_PHYSICAL_ADDRESS FvBaseAddress, + OUT EFI_FIRMWARE_VOLUME_HEADER **FvbInfo + ); + +BOOLEAN +SetPlatformFvbLock ( + IN UINTN LbaAddress + ); + +EFI_STATUS +FvbReadBlock ( + IN UINTN Instance, + IN EFI_LBA Lba, + IN UINTN BlockOffset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer, + IN ESAL_FWB_GLOBAL *Global, + IN BOOLEAN Virtual + ); + +EFI_STATUS +FvbWriteBlock ( + IN UINTN Instance, + IN EFI_LBA Lba, + IN UINTN BlockOffset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer, + IN ESAL_FWB_GLOBAL *Global, + IN BOOLEAN Virtual + ); + +EFI_STATUS +FvbEraseBlock ( + IN UINTN Instance, + IN EFI_LBA Lba, + IN ESAL_FWB_GLOBAL *Global, + IN BOOLEAN Virtual + ); + +EFI_STATUS +FvbSetVolumeAttributes ( + IN UINTN Instance, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes, + IN ESAL_FWB_GLOBAL *Global, + IN BOOLEAN Virtual + ); + +EFI_STATUS +FvbGetVolumeAttributes ( + IN UINTN Instance, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes, + IN ESAL_FWB_GLOBAL *Global, + IN BOOLEAN Virtual + ); + +EFI_STATUS +FvbGetPhysicalAddress ( + IN UINTN Instance, + OUT EFI_PHYSICAL_ADDRESS *Address, + IN ESAL_FWB_GLOBAL *Global, + IN BOOLEAN Virtual + ); + +EFI_STATUS +FvbInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +VOID +FvbClassAddressChangeEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ); + +EFI_STATUS +FvbSpecificInitialize ( + IN ESAL_FWB_GLOBAL *mFvbModuleGlobal + ); + +EFI_STATUS +FvbGetLbaAddress ( + IN UINTN Instance, + IN EFI_LBA Lba, + OUT UINTN *LbaAddress, + OUT UINTN *LbaWriteAddress, + OUT UINTN *LbaLength, + OUT UINTN *NumOfBlocks, + IN ESAL_FWB_GLOBAL *Global, + IN BOOLEAN Virtual + ); + +EFI_STATUS +FvbEraseCustomBlockRange ( + IN UINTN Instance, + IN EFI_LBA StartLba, + IN UINTN OffsetStartLba, + IN EFI_LBA LastLba, + IN UINTN OffsetLastLba, + IN ESAL_FWB_GLOBAL *Global, + IN BOOLEAN Virtual + ); + +// +// Protocol APIs +// +EFI_STATUS +EFIAPI +FvbProtocolGetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ); + +EFI_STATUS +EFIAPI +FvbProtocolSetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ); + +EFI_STATUS +EFIAPI +FvbProtocolGetPhysicalAddress ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + OUT EFI_PHYSICAL_ADDRESS *Address + ); + +EFI_STATUS +FvbProtocolGetBlockSize ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN EFI_LBA Lba, + OUT UINTN *BlockSize, + OUT UINTN *NumOfBlocks + ); + +EFI_STATUS +EFIAPI +FvbProtocolRead ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ); + +EFI_STATUS +EFIAPI +FvbProtocolWrite ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ); + +EFI_STATUS +EFIAPI +FvbProtocolEraseBlocks ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + ... + ); + +extern SPI_INIT_TABLE mSpiInitTable[]; + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSmmSpi.c b/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSmmSpi.c new file mode 100644 index 0000000000..a658bc9a29 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSmmSpi.c @@ -0,0 +1,31 @@ +/** @file + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#include "FwBlockService.h" + + +/** + This function allows the caller to determine if UEFI SetVirtualAddressMap() has been called. + + This function returns TRUE after all the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE functions have + executed as a result of the OS calling SetVirtualAddressMap(). Prior to this time FALSE + is returned. This function is used by runtime code to decide it is legal to access services + that go away after SetVirtualAddressMap(). + + @retval TRUE The system has finished executing the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event. + @retval FALSE The system has not finished executing the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event. + +**/ +BOOLEAN +EfiGoneVirtual ( + VOID + ) +{ + return FALSE; //Hard coded to FALSE for SMM driver. +} diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSmmSpi.inf b/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSmmSpi.inf new file mode 100644 index 0000000000..6f263a4f19 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSmmSpi.inf @@ -0,0 +1,80 @@ +## @file +# Component description file for SpiFvbServices Module +# +# Copyright (c) 2013-2015 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = FwBlockServiceSmm + FILE_GUID = A469DDBD-16D0-4535-BAE3-77274BD70B4C + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = FvbInitialize + +[Sources] + FwBlockService.c + FwBlockService.h + FvbInfo.c + SpiFlashDevice.c + SpiFlashDevice.h + PlatformSmmSpi.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + QuarkSocPkg/QuarkSocPkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + +[LibraryClasses] + IoLib + PcdLib + HobLib + UefiLib + BaseMemoryLib + UefiDriverEntryPoint + MemoryAllocationLib + UefiRuntimeServicesTableLib + UefiBootServicesTableLib + DxeServicesTableLib + +[Guids] + gEfiEventVirtualAddressChangeGuid + gEfiHobListGuid + + [Protocols] + gEfiFirmwareVolumeBlockProtocolGuid ##Produces + gEfiSpiProtocolGuid + gEfiDevicePathProtocolGuid + gEfiLoadedImageProtocolGuid + gEfiSmmBase2ProtocolGuid + gEfiSmmSpiProtocolGuid + gEfiSmmFirmwareVolumeBlockProtocolGuid + gEfiSmmSpiReadyProtocolGuid + +[FixedPcd] + gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress + gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainSize + gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainBase + gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoveryBase + gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoverySize + gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadBase + gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadSize + gQuarkPlatformTokenSpaceGuid.PcdSpiFlashDeviceSize + +[Depex] + gEfiSpiProtocolGuid diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSpi.inf b/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSpi.inf new file mode 100644 index 0000000000..4ac4d0754a --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSpi.inf @@ -0,0 +1,79 @@ +## @file +# Component description file for SpiFvbServices Module +# +# Copyright (c) 2013-2015 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = FwBlockService + FILE_GUID = 4D35A5A7-622E-4955-A5D2-CDA812940D74 + MODULE_TYPE = DXE_RUNTIME_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = FvbInitialize + +[Sources] + FwBlockService.c + FwBlockService.h + FvbInfo.c + SpiFlashDevice.c + SpiFlashDevice.h + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + QuarkSocPkg/QuarkSocPkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + +[LibraryClasses] + IoLib + PcdLib + HobLib + UefiLib + BaseMemoryLib + UefiDriverEntryPoint + MemoryAllocationLib + UefiRuntimeLib + UefiRuntimeServicesTableLib + UefiBootServicesTableLib + DxeServicesTableLib + +[Guids] + gEfiEventVirtualAddressChangeGuid + gEfiHobListGuid + + [Protocols] + gEfiFirmwareVolumeBlockProtocolGuid ##Produces + gEfiSpiProtocolGuid + gEfiDevicePathProtocolGuid + gEfiLoadedImageProtocolGuid + gEfiSmmBase2ProtocolGuid + gEfiSmmSpiProtocolGuid + gEfiSmmFirmwareVolumeBlockProtocolGuid + gEfiSmmSpiReadyProtocolGuid + +[FixedPcd] + gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress + gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainSize + gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainBase + gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoveryBase + gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoverySize + gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadBase + gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadSize + gQuarkPlatformTokenSpaceGuid.PcdSpiFlashDeviceSize + +[Depex] + gEfiSpiProtocolGuid diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/SpiFlashDevice.c b/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/SpiFlashDevice.c new file mode 100644 index 0000000000..8a86fc406d --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/SpiFlashDevice.c @@ -0,0 +1,331 @@ +/** @file +Initializes Platform Specific Drivers. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#include "SpiFlashDevice.h" + +#define FLASH_SIZE (FixedPcdGet32 (PcdFlashAreaSize)) + +SPI_INIT_TABLE mSpiInitTable[] = { + // + // Macronix 32Mbit part + // + { + SPI_MX25L3205_ID1, + SPI_MX25L3205_ID2, + SPI_MX25L3205_ID3, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase} + }, + 0x400000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // Winbond 32Mbit part + // + { + SPI_W25X32_ID1, + SF_DEVICE_ID0_W25QXX, + SF_DEVICE_ID1_W25Q32, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + 0x400000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // Winbond 32Mbit part + // + { + SPI_W25X32_ID1, + SPI_W25X32_ID2, + SPI_W25X32_ID3, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase} + }, + 0x400000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // Atmel 32Mbit part + // + { + SPI_AT26DF321_ID1, + SPI_AT26DF321_ID2, // issue: byte 2 identifies family/density for Atmel + SPI_AT26DF321_ID3, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase} + }, + 0x400000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + + // + // Intel 32Mbit part bottom boot + // + { + SPI_QH25F320_ID1, + SPI_QH25F320_ID2, + SPI_QH25F320_ID3, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_ENABLE + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase} + }, + 0, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // SST 64Mbit part + // + { + SPI_SST25VF080B_ID1, // VendorId + SF_DEVICE_ID0_25VF064C, // DeviceId 0 + SF_DEVICE_ID1_25VF064C, // DeviceId 1 + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // NUMONYX 64Mbit part + // + { + SF_VENDOR_ID_NUMONYX, // VendorId + SF_DEVICE_ID0_M25PX64, // DeviceId 0 + SF_DEVICE_ID1_M25PX64, // DeviceId 1 + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // Atmel 64Mbit part + // + { + SF_VENDOR_ID_ATMEL, // VendorId + SF_DEVICE_ID0_AT25DF641, // DeviceId 0 + SF_DEVICE_ID1_AT25DF641, // DeviceId 1 + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + + // + // Spansion 64Mbit part + // + { + SF_VENDOR_ID_SPANSION, // VendorId + SF_DEVICE_ID0_S25FL064K, // DeviceId 0 + SF_DEVICE_ID1_S25FL064K, // DeviceId 1 + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + + // + // Macronix 64Mbit part bottom boot + // + { + SF_VENDOR_ID_MX, // VendorId + SF_DEVICE_ID0_25L6405D, // DeviceId 0 + SF_DEVICE_ID1_25L6405D, // DeviceId 1 + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // Winbond 64Mbit part bottom boot + // + { + SPI_W25X64_ID1, + SF_DEVICE_ID0_W25QXX, + SF_DEVICE_ID1_W25Q64, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // Winbond 64Mbit part bottom boot + // + { + SPI_W25X64_ID1, + SPI_W25X64_ID2, + SPI_W25X64_ID3, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // Intel 64Mbit part bottom boot + // + { + SPI_QH25F640_ID1, + SPI_QH25F640_ID2, + SPI_QH25F640_ID3, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + } +}; diff --git a/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/SpiFlashDevice.h b/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/SpiFlashDevice.h new file mode 100644 index 0000000000..ee8d97a2bb --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Platform/SpiFvbServices/SpiFlashDevice.h @@ -0,0 +1,181 @@ +/** @file + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#ifndef _SPI_FLASH_DEVICE_H_ +#define _SPI_FLASH_DEVICE_H_ + +#include +#include +#include + +// +// Supported SPI Flash Devices +// +typedef enum { + EnumSpiFlash25L3205D, // Macronix 32Mbit part + EnumSpiFlashW25Q32, // Winbond 32Mbit part + EnumSpiFlashW25X32, // Winbond 32Mbit part + EnumSpiFlashAT25DF321, // Atmel 32Mbit part + EnumSpiFlashQH25F320, // Intel 32Mbit part + EnumSpiFlash25VF064C, // SST 64Mbit part + EnumSpiFlashM25PX64, // NUMONYX 64Mbit part + EnumSpiFlashAT25DF641, // Atmel 64Mbit part + EnumSpiFlashS25FL064K, // Spansion 64Mbit part + EnumSpiFlash25L6405D, // Macronix 64Mbit part + EnumSpiFlashW25Q64, // Winbond 64Mbit part + EnumSpiFlashW25X64, // Winbond 64Mbit part + EnumSpiFlashQH25F640, // Intel 64Mbit part + EnumSpiFlashMax +} SPI_FLASH_TYPES_SUPPORTED; + +// +// Flash Device commands +// +// If a supported device uses a command different from the list below, a device specific command +// will be defined just below it's JEDEC id section. +// +#define SPI_COMMAND_WRITE 0x02 +#define SPI_COMMAND_WRITE_AAI 0xAD +#define SPI_COMMAND_READ 0x03 +#define SPI_COMMAND_ERASE 0x20 +#define SPI_COMMAND_WRITE_DISABLE 0x04 +#define SPI_COMMAND_READ_S 0x05 +#define SPI_COMMAND_WRITE_ENABLE 0x06 +#define SPI_COMMAND_READ_ID 0xAB +#define SPI_COMMAND_JEDEC_ID 0x9F +#define SPI_COMMAND_WRITE_S_EN 0x50 +#define SPI_COMMAND_WRITE_S 0x01 +#define SPI_COMMAND_CHIP_ERASE 0xC7 +#define SPI_COMMAND_BLOCK_ERASE 0xD8 + +// +// Flash JEDEC device ids +// +// SST 8Mbit part +// +#define SPI_SST25VF080B_ID1 0xBF +#define SPI_SST25VF080B_ID2 0x25 +#define SPI_SST25VF080B_ID3 0x8E +// +// SST 16Mbit part +// +#define SPI_SST25VF016B_ID1 0xBF +#define SPI_SST25VF016B_ID2 0x25 +#define SPI_SST25V016BF_ID3 0x41 +// +// Macronix 32Mbit part +// +// MX25 part does not support WRITE_AAI comand (0xAD) +// +#define SPI_MX25L3205_ID1 0xC2 +#define SPI_MX25L3205_ID2 0x20 +#define SPI_MX25L3205_ID3 0x16 +// +// Intel 32Mbit part bottom boot +// +#define SPI_QH25F320_ID1 0x89 +#define SPI_QH25F320_ID2 0x89 +#define SPI_QH25F320_ID3 0x12 // 32Mbit bottom boot +// +// Intel 64Mbit part bottom boot +// +#define SPI_QH25F640_ID1 0x89 +#define SPI_QH25F640_ID2 0x89 +#define SPI_QH25F640_ID3 0x13 // 64Mbit bottom boot +// +// QH part does not support command 0x20 for erase; only 0xD8 (sector erase) +// QH part has 0x40 command for erase of parameter block (8 x 8K blocks at bottom of part) +// 0x40 command ignored if address outside of parameter block range +// +#define SPI_QH25F320_COMMAND_PBLOCK_ERASE 0x40 +// +// Winbond 32Mbit part +// +#define SPI_W25X32_ID1 0xEF +#define SPI_W25X32_ID2 0x30 // Memory Type +#define SPI_W25X32_ID3 0x16 // Capacity +#define SF_DEVICE_ID1_W25Q32 0x16 + +// +// Winbond 64Mbit part +// +#define SPI_W25X64_ID1 0xEF +#define SPI_W25X64_ID2 0x30 // Memory Type +#define SPI_W25X64_ID3 0x17 // Capacity +#define SF_DEVICE_ID0_W25QXX 0x40 +#define SF_DEVICE_ID1_W25Q64 0x17 +// +// Winbond 128Mbit part +// +#define SF_DEVICE_ID0_W25Q128 0x40 +#define SF_DEVICE_ID1_W25Q128 0x18 + +// +// Atmel 32Mbit part +// +#define SPI_AT26DF321_ID1 0x1F +#define SPI_AT26DF321_ID2 0x47 // [7:5]=Family, [4:0]=Density +#define SPI_AT26DF321_ID3 0x00 + +#define SF_VENDOR_ID_ATMEL 0x1F +#define SF_DEVICE_ID0_AT25DF641 0x48 +#define SF_DEVICE_ID1_AT25DF641 0x00 + +// +// SST 8Mbit part +// +#define SPI_SST25VF080B_ID1 0xBF +#define SPI_SST25VF080B_ID2 0x25 +#define SPI_SST25VF080B_ID3 0x8E +#define SF_DEVICE_ID0_25VF064C 0x25 +#define SF_DEVICE_ID1_25VF064C 0x4B + +// +// SST 16Mbit part +// +#define SPI_SST25VF016B_ID1 0xBF +#define SPI_SST25VF016B_ID2 0x25 +#define SPI_SST25V016BF_ID3 0x41 + +// +// Winbond 32Mbit part +// +#define SPI_W25X32_ID1 0xEF +#define SPI_W25X32_ID2 0x30 // Memory Type +#define SPI_W25X32_ID3 0x16 // Capacity + +#define SF_VENDOR_ID_MX 0xC2 +#define SF_DEVICE_ID0_25L6405D 0x20 +#define SF_DEVICE_ID1_25L6405D 0x17 + +#define SF_VENDOR_ID_NUMONYX 0x20 +#define SF_DEVICE_ID0_M25PX64 0x71 +#define SF_DEVICE_ID1_M25PX64 0x17 + +// +// Spansion 64Mbit part +// +#define SF_VENDOR_ID_SPANSION 0xEF +#define SF_DEVICE_ID0_S25FL064K 0x40 +#define SF_DEVICE_ID1_S25FL064K 0x00 + +// +// index for prefix opcodes +// +#define SPI_WREN_INDEX 0 // Prefix Opcode 0: SPI_COMMAND_WRITE_ENABLE +#define SPI_EWSR_INDEX 1 // Prefix Opcode 1: SPI_COMMAND_WRITE_S_EN +#define BIOS_CTRL 0xDC + +#define PFAB_CARD_DEVICE_ID 0x5150 +#define PFAB_CARD_VENDOR_ID 0x8086 +#define PFAB_CARD_SETUP_REGISTER 0x40 +#define PFAB_CARD_SETUP_BYTE 0x0d + + +#endif diff --git a/Platform/Intel/QuarkPlatformPkg/Quark.dsc b/Platform/Intel/QuarkPlatformPkg/Quark.dsc new file mode 100644 index 0000000000..e5ebeb5e09 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Quark.dsc @@ -0,0 +1,948 @@ +## @file +# Clanton Peak CRB platform with 32-bit DXE for 4MB/8MB flash devices. +# +# This package provides Clanton Peak CRB platform specific modules. +# Copyright (c) 2013 - 2019 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + DSC_SPECIFICATION = 0x00010005 + PLATFORM_NAME = Quark + PLATFORM_GUID = F6E7730E-0C7A-4741-9DFC-6BC8B86CD865 + PLATFORM_VERSION = 0.1 + FLASH_DEFINITION = QuarkPlatformPkg/Quark.fdf + OUTPUT_DIRECTORY = Build/Quark + SUPPORTED_ARCHITECTURES = IA32 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + VPD_TOOL_GUID = 8C3D856A-9BE6-468E-850A-24F7A8D38E08 + + # + # Platform On/Off features are defined here + # + DEFINE SECURE_BOOT_ENABLE = FALSE + DEFINE MEASURED_BOOT_ENABLE = FALSE + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE PERFORMANCE_ENABLE = FALSE + DEFINE LOGGING = FALSE + DEFINE CAPSULE_ENABLE = FALSE + DEFINE RECOVERY_ENABLE = FALSE + + # + # Galileo board. Options are [GEN1, GEN2] + # + DEFINE GALILEO = GEN2 + + # + # TPM 1.2 Hardware. Options are [NONE, LPC, ATMEL_I2C, INFINEON_I2C] + # + DEFINE TPM_12_HARDWARE = NONE + + !if $(TARGET) == "DEBUG" + DEFINE LOGGING = TRUE + !endif + + !if $(PERFORMANCE_ENABLE) + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE LOGGING = FALSE + !endif + +################################################################################ +# +# SKU Identification section - list of all SKU IDs supported by this +# Platform. +# +################################################################################ +[SkuIds] + 0|DEFAULT # The entry: 0|DEFAULT is reserved and always required. + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ +[LibraryClasses] + # + # Entry point + # + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf + + # + # Basic + # + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf + PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf +!if $(SOURCE_DEBUG_ENABLE) + PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf + DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf +!else + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf +!endif + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + + # + # UEFI & PI + # + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiDecompressLib|MdeModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf + + # + # Generic Modules + # + S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf + S3IoLib|MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf + S3PciLib|MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf + IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf + UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf + SmmCorePlatformHookLib|MdeModulePkg/Library/SmmCorePlatformHookLibNull/SmmCorePlatformHookLibNull.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +!if $(LOGGING) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif +!if $(PERFORMANCE_ENABLE) + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf +!else + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf +!endif + + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + +!if $(SECURE_BOOT_ENABLE) + PlatformSecureLib|QuarkPlatformPkg/Library/PlatformSecureLib/PlatformSecureLib.inf + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf +!else + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf +!endif + +!if $(MEASURED_BOOT_ENABLE) + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf + Tpm12CommandLib|SecurityPkg/Library/Tpm12CommandLib/Tpm12CommandLib.inf +!if $(TPM_12_HARDWARE) == LPC + Tpm12DeviceLib|SecurityPkg/Library/Tpm12DeviceLibDTpm/Tpm12DeviceLibDTpm.inf +!endif +!if $(TPM_12_HARDWARE) == ATMEL_I2C + Tpm12DeviceLib|QuarkPlatformPkg/Library/Tpm12DeviceLibAtmelI2c/Tpm12DeviceLibAtmelI2c.inf +!endif +!if $(TPM_12_HARDWARE) == INFINEON_I2C + Tpm12DeviceLib|QuarkPlatformPkg/Library/Tpm12DeviceLibInfineonI2c/Tpm12DeviceLibInfineonI2c.inf +!endif + TcgPpVendorLib|SecurityPkg/Library/TcgPpVendorLibNull/TcgPpVendorLibNull.inf +!else + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf +!endif + + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + + # + # CPU + # + MtrrLib|QuarkSocPkg/QuarkNorthCluster/Library/MtrrLib/MtrrLib.inf + LocalApicLib|UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf + MpInitLib|UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.inf + + # + # Quark North Cluster + # + SmmLib|QuarkSocPkg/QuarkNorthCluster/Library/QNCSmmLib/QNCSmmLib.inf + SmbusLib|QuarkSocPkg/QuarkNorthCluster/Library/SmbusLib/SmbusLib.inf + TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.inf + ResetSystemLib|QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/ResetSystemLib.inf + IntelQNCLib|QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/IntelQNCLib.inf + QNCAccessLib|QuarkSocPkg/QuarkNorthCluster/Library/QNCAccessLib/QNCAccessLib.inf + IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf + + # + # Quark South Cluster + # + IohLib|QuarkSocPkg/QuarkSouthCluster/Library/IohLib/IohLib.inf + I2cLib|QuarkSocPkg/QuarkSouthCluster/Library/I2cLib/I2cLib.inf + SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf + PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf + + # + # Quark Platform + # + PlatformSecLib|QuarkPlatformPkg/Library/PlatformSecLib/PlatformSecLib.inf + PlatformPcieHelperLib|QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.inf + PlatformHelperLib|QuarkPlatformPkg/Library/PlatformHelperLib/DxePlatformHelperLib.inf + +!if $(CAPSULE_ENABLE) + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf + BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.inf + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf +!else + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf +!endif + + EdkiiSystemCapsuleLib|SignedCapsulePkg/Library/EdkiiSystemCapsuleLib/EdkiiSystemCapsuleLib.inf + FmpAuthenticationLib|MdeModulePkg/Library/FmpAuthenticationLibNull/FmpAuthenticationLibNull.inf + IniParsingLib|SignedCapsulePkg/Library/IniParsingLib/IniParsingLib.inf + PlatformFlashAccessLib|QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf + DisplayUpdateProgressLib|MdeModulePkg/Library/DisplayUpdateProgressLibText/DisplayUpdateProgressLibText.inf + +[LibraryClasses.common.SEC] + # + # SEC specific phase + # + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf + +[LibraryClasses.IA32.PEIM,LibraryClasses.IA32.PEI_CORE] + # + # PEI phase common + # + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf + LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf + TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf + PlatformHelperLib|QuarkPlatformPkg/Library/PlatformHelperLib/PeiPlatformHelperLib.inf + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf +!if $(PERFORMANCE_ENABLE) + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf +!endif + +[LibraryClasses.IA32.DXE_CORE] + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf +!if $(PERFORMANCE_ENABLE) + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf +!endif + +[LibraryClasses.IA32.DXE_SMM_DRIVER] + MmServicesTableLib|MdePkg/Library/MmServicesTableLib/MmServicesTableLib.inf + SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/SmmReportStatusCodeLib.inf + MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf + LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf +!if $(PERFORMANCE_ENABLE) + PerformanceLib|MdeModulePkg/Library/SmmPerformanceLib/SmmPerformanceLib.inf +!endif + +[LibraryClasses.IA32.SMM_CORE] + SmmServicesTableLib|MdeModulePkg/Library/PiSmmCoreSmmServicesTableLib/PiSmmCoreSmmServicesTableLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/SmmReportStatusCodeLib.inf + MemoryAllocationLib|MdeModulePkg/Library/PiSmmCoreMemoryAllocationLib/PiSmmCoreMemoryAllocationLib.inf + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf +!if $(SECURE_BOOT_ENABLE) || $(MEASURED_BOOT_ENABLE) + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf +!endif +!if $(PERFORMANCE_ENABLE) + PerformanceLib|MdeModulePkg/Library/SmmCorePerformanceLib/SmmCorePerformanceLib.inf +!endif + +[LibraryClasses.IA32.DXE_RUNTIME_DRIVER] + ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf + QNCAccessLib|QuarkSocPkg/QuarkNorthCluster/Library/QNCAccessLib/RuntimeQNCAccessLib.inf + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +!if $(SECURE_BOOT_ENABLE) || $(MEASURED_BOOT_ENABLE) + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf +!endif + +!if $(CAPSULE_ENABLE) + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeRuntimeCapsuleLib.inf +!endif + +[LibraryClasses.IA32.UEFI_DRIVER,LibraryClasses.IA32.UEFI_APPLICATION] + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ +[PcdsFeatureFlag] + gEfiMdeModulePkgTokenSpaceGuid.PcdDevicePathSupportDevicePathToText|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdDevicePathSupportDevicePathFromText|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE +!if $(SOURCE_DEBUG_ENABLE) + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|TRUE +!endif + +!if $(TARGET) == "RELEASE" + gQuarkPlatformTokenSpaceGuid.WaitIfResetDueToError|FALSE +!else + gQuarkPlatformTokenSpaceGuid.WaitIfResetDueToError|TRUE +!endif + +[PcdsFixedAtBuild] + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|1 + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x20000 + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|TRUE +!if $(LOGGING) + !if $(SOURCE_DEBUG_ENABLE) + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17 + !else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27 + !endif + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0x0 + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3 +!endif + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0x18 + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 +!if $(GALILEO) == GEN1 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|460800 +!endif +!if $(GALILEO) == GEN2 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|921600 +!endif + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0 +!if $(PERFORMANCE_ENABLE) + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|80 +!else + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x00 +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0 +!if $(SECURE_BOOT_ENABLE) + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00002000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x1000 + ## RTC Update Timeout Value, need to increase timeout since also + # waiting for RTC to be busy. + gEfiMdeModulePkgTokenSpaceGuid.PcdRealTimeClockUpdateTimeout|500000 + +!if $(SECURE_BOOT_ENABLE) + # override the default values from SecurityPkg to ensure images from all sources are verified in secure boot + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04 +!endif + gQuarkPlatformTokenSpaceGuid.PcdEsramStage1Base|0x80000000 + +!if $(SOURCE_DEBUG_ENABLE) + gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 +!endif + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x9000B000 +!if $(GALILEO) == GEN1 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|460800 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE +!endif +!if $(GALILEO) == GEN2 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|921600 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|0x03 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x07 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|44236800 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo|{0x14, 0x05, 0x84, 0x00, 0xFF} + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4 + + # + # typedef struct { + # UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries. + # UINT16 DeviceId; ///< Device ID to match the PCI device + # UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz + # UINT64 Offset; ///< The byte offset into to the BAR + # UINT8 BarIndex; ///< Which BAR to get the UART base address + # UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte. + # UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes. + # UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes. + # UINT8 Reserved[2]; + # } PCI_SERIAL_PARAMETER; + # + # Vendor 8086 Device 0936 Prog Interface 2, BAR #0, Offset 0, Stride = 4, Clock 44236800 (0x2a300000) + # Vendor 8086 Device 0936 Prog Interface 2, BAR #0, Offset 0, Stride = 4, Clock 44236800 (0x2a300000) + # + # [Vendor] [Device] [---ClockRate---] [------------Offset-----------] [Bar] [Stride] [RxFifo] [TxFifo] [Rsvd] [Vendor] + gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|{0x86,0x80, 0x36,0x09, 0x0,0x0,0xA3,0x02, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00, 0x04, 0x0,0x0, 0x0,0x0, 0x0,0x0, 0xff,0xff} + + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber |0 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber |31 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber |0 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x4b + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask |0x80 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0x48 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress |0x1000 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008 + + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 } + + gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE + +!if $(RECOVERY_ENABLE) + gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryFileName|L"QUARKREC.Cap" +!endif + + # + # Quark does not support LFENCE. Use CPUID as speculation barrier + # + gEfiMdePkgTokenSpaceGuid.PcdSpeculationBarrierType|0x02 + +[PcdsPatchableInModule] + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803000C7 + gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 + +[PcdsDynamicExHii.common.DEFAULT] +!if $(PERFORMANCE_ENABLE) + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|0 +!else + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 +!endif + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState|L"BootState"|gQuarkPlatformTokenSpaceGuid|0x0|TRUE + +[PcdsDynamicExDefault.common.DEFAULT] + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0 + gQuarkPlatformTokenSpaceGuid.PcdEnableFastBoot|TRUE + gQuarkPlatformTokenSpaceGuid.PcdUserIsPhysicallyPresent|FALSE + gQuarkPlatformTokenSpaceGuid.PcdSpiFlashDeviceSize|0 + +!if $(CAPSULE_ENABLE) || $(RECOVERY_ENABLE) + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor|{0x0}|VOID*|0x100 + gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{0xc0, 0x20, 0xaf, 0x62, 0x16, 0x70, 0x4a, 0x42, 0x9b, 0xf8, 0x9c, 0xcc, 0x86, 0x58, 0x40, 0x90} + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{0x59, 0x3A, 0xD8, 0x14, 0x10, 0xA8, 0x56, 0x45, 0x81, 0x92, 0x1C, 0x0A, 0x59, 0x3C, 0x06, 0x5C} +!endif + +!if $(MEASURED_BOOT_ENABLE) + # + # TPM1.2 { 0x8b01e5b6, 0x4f19, 0x46e8, { 0xab, 0x93, 0x1c, 0x53, 0x67, 0x1b, 0x90, 0xcc } } + # TPM2.0 DTPM { 0x286bf25a, 0xc2c3, 0x408c, { 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17 } } + # + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0xb6, 0xe5, 0x01, 0x8b, 0x19, 0x4f, 0xe8, 0x46, 0xab, 0x93, 0x1c, 0x53, 0x67, 0x1b, 0x90, 0xcc} + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1 + gEfiSecurityPkgTokenSpaceGuid.PcdTpmScrtmPolicy|1 +!endif + +[PcdsDynamicExVpd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|*|32|L"EDK II" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision|*|0x01000400 + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|*|64|L"Galileo 1.0.4" + +# +# ClantonPeakSVP +# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0002 +# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"ClantonPeakSVP" +# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x03, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06} +# +# KipsBay +# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0003 +# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"KipsBay" +# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06} +# +# CrossHill +# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0004 +# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"CrossHill" +# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x03, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06} +# +# ClantonHill +# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0005 +# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"ClantonHill" +# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x02, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06} +# +# Galileo +# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0006 +# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"Galileo" +# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06} +# +# GalileoGen2 +# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0008 +# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"GalileoGen2" +# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06} +# +!if $(GALILEO) == GEN1 + gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0006 + gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"Galileo" + gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06} +!endif +!if $(GALILEO) == GEN2 + gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0008 + gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"GalileoGen2" + gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06} +!endif + gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac0|*|8|{0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac1|*|8|{0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + +################################################################################################### +# +# Components Section - list of the modules and components that will be processed by compilation +# tools and the EDK II tools to generate PE32/PE32+/Coff image files. +# +# Note: The EDK II DSC file is not used to specify how compiled binary images get placed +# into firmware volume images. This section is just a list of modules to compile from +# source into UEFI-compliant binaries. +# It is the FDF file that contains information on combining binary files into firmware +# volume images, whose concept is beyond UEFI and is described in PI specification. +# Binary modules do not need to be listed in this section, as they should be +# specified in the FDF file. For example: Shell binary, FAT binary (Fat.efi), +# Logo (Logo.bmp), and etc. +# There may also be modules listed in this section that are not required in the FDF file, +# When a module listed here is excluded from FDF file, then UEFI-compliant binary will be +# generated for it, but the binary will not be put into any firmware volume. +# +################################################################################################### + +[Components.IA32] + # + # SEC Core + # + UefiCpuPkg/SecCore/SecCore.inf { + !if $(SOURCE_DEBUG_ENABLE) + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf + ResetSystemLib|QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/ResetSystemLib.inf + !endif + } + +!if $(CAPSULE_ENABLE) || $(RECOVERY_ENABLE) + # FMP image decriptor + QuarkPlatformPkg/Feature/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf +!endif + + # + # PEI Core + # + MdeModulePkg/Core/Pei/PeiMain.inf + + # + # PEIM + # + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf + MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf { + + !if $(LOGGING) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf + !endif + } + + MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf + UefiCpuPkg/CpuMpPei/CpuMpPei.inf + MdeModulePkg/Universal/CapsulePei/CapsulePei.inf + + QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/MemoryInitPei.inf + QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf + QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.inf + + UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf + + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + + # + # S3 + # + QuarkSocPkg/QuarkNorthCluster/Smm/Pei/SmmAccessPei/SmmAccessPei.inf + QuarkSocPkg/QuarkNorthCluster/Smm/Pei/SmmControlPei/SmmControlPei.inf + UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf + + # + # Trusted Platform Module + # +!if $(MEASURED_BOOT_ENABLE) + SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigPei.inf + SecurityPkg/Tcg/TcgPei/TcgPei.inf +!endif + + # + # Recovery + # +!if $(RECOVERY_ENABLE) + QuarkSocPkg/QuarkSouthCluster/Usb/Common/Pei/UsbPei.inf + MdeModulePkg/Bus/Pci/EhciPei/EhciPei.inf + QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/OhciPei.inf + MdeModulePkg/Bus/Usb/UsbBotPei/UsbBotPei.inf + MdeModulePkg/Bus/Usb/UsbBusPei/UsbBusPei.inf + FatPkg/FatPei/FatPei.inf + MdeModulePkg/Universal/Disk/CdExpressPei/CdExpressPei.inf + SignedCapsulePkg/Universal/RecoveryModuleLoadPei/RecoveryModuleLoadPei.inf { + + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibRsa2048Sha256/FmpAuthenticationLibRsa2048Sha256.inf + } +!endif + +[Components.IA32] + # + # DXE Core + # + MdeModulePkg/Core/Dxe/DxeMain.inf + +!if $(SOURCE_DEBUG_ENABLE) + SourceLevelDebugPkg/DebugAgentDxe/DebugAgentDxe.inf { + + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf + ResetSystemLib|QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/ResetSystemLib.inf + } +!endif + + + QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.inf + + # + # Components that produce the architectural protocols + # + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { + +!if $(SECURE_BOOT_ENABLE) + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf +!endif + NULL|SecurityPkg/Library/DxeImageAuthenticationStatusLib/DxeImageAuthenticationStatusLib.inf + } + UefiCpuPkg/CpuDxe/CpuDxe.inf + MdeModulePkg/Universal/Metronome/Metronome.inf + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf +!if $(SECURE_BOOT_ENABLE) + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf +!endif + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + NULL|MdeModulePkg/Library/VarCheckHiiLib/VarCheckHiiLib.inf + NULL|MdeModulePkg/Library/VarCheckPcdLib/VarCheckPcdLib.inf + } + + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf + + # + # Following are the DXE drivers (alphabetical order) + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + + QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.inf + QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSpi.inf + QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSmmSpi.inf + UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + + # + # Platform + # + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf { + + PlatformBootManagerLib|QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf +!if $(CAPSULE_ENABLE) + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf +!else + FmpAuthenticationLib|MdeModulePkg/Library/FmpAuthenticationLibNull/FmpAuthenticationLibNull.inf +!endif + } + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + + QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/QNCInitDxe.inf + PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf + QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmAccessDxe/SmmAccess.inf + QuarkPlatformPkg/Platform/Dxe/Setup/DxePlatform.inf + QuarkSocPkg/QuarkNorthCluster/Spi/PchSpiRuntime.inf { + + PciExpressLib|MdePkg/Library/DxeRuntimePciExpressLib/DxeRuntimePciExpressLib.inf + } + QuarkSocPkg/QuarkNorthCluster/Spi/PchSpiSmm.inf + QuarkSocPkg/QuarkNorthCluster/S3Support/Dxe/QncS3Support.inf + MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf + MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf { + + !if $(LOGGING) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf + !endif + } + MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf + MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf { + + !if $(LOGGING) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf + !endif + } + # + # ACPI + # + QuarkPlatformPkg/Platform/Dxe/SaveMemoryConfig/SaveMemoryConfig.inf + MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf +# MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf { + QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/BootScriptExecutorDxe.inf { + + !if $(LOGGING) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf + !endif + !if $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf + ResetSystemLib|QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/ResetSystemLib.inf + !endif + } + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.inf + QuarkPlatformPkg/Acpi/AcpiTables/AcpiTables.inf + QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.inf + + # + # SMM + # + MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf + MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { + + SmmCpuFeaturesLib|QuarkSocPkg/QuarkNorthCluster/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf + SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf + + !if $(LOGGING) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf + !endif + !if $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAgentLib.inf + ResetSystemLib|QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/ResetSystemLib.inf + !endif + + # + # Disable DEBUG_CACHE because SMI entry/exit may change MTRRs + # + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x801000C7 + } + + UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf + QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmControlDxe/SmmControlDxe.inf + QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNCSmmDispatcher.inf + QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.inf + QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.inf + MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf + UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf + + # + # SMBIOS + # + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscDxe.inf + QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClass.inf + # + # PCI + # + QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.inf + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + QuarkSocPkg/QuarkSouthCluster/IohInit/Dxe/IohInitDxe.inf + MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf + + # + # USB + # + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # SDIO + # + QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDControllerDxe.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80300087 + } + QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDMediaDeviceDxe/SDMediaDeviceDxe.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80300087 + } + + # + # Console + # + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf { + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf { + + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf + } + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # File System Modules + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + FatPkg/EnhancedFatDxe/Fat.inf + + # + # Capsule update + # + IntelFrameworkModulePkg/Universal/FirmwareVolume/FwVolDxe/FwVolDxe.inf + IntelFrameworkModulePkg/Universal/FirmwareVolume/UpdateDriverDxe/UpdateDriverDxe.inf + + # + # Trusted Platform Module + # +!if $(MEASURED_BOOT_ENABLE) + SecurityPkg/Tcg/MemoryOverwriteControl/TcgMor.inf + SecurityPkg/Tcg/TcgDxe/TcgDxe.inf + SecurityPkg/Tcg/TcgSmm/TcgSmm.inf +!endif + + # + # Performance Application + # +!if $(PERFORMANCE_ENABLE) + ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + } +!endif + + # + # Force Recovery Application + # + QuarkPlatformPkg/Application/ForceRecovery/ForceRecovery.inf + + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf + + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } + +!if $(CAPSULE_ENABLE) + MdeModulePkg/Universal/EsrtFmpDxe/EsrtFmpDxe.inf + + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf { + + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf + } + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { + + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf + } + + MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf { + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } +!endif + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096 + +# Force PE/COFF sections to be aligned at 4KB boundaries to support page level protection of DXE_SMM_DRIVER/SMM_CORE modules +[BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_CORE] + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096 + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 + diff --git a/Platform/Intel/QuarkPlatformPkg/Quark.fdf b/Platform/Intel/QuarkPlatformPkg/Quark.fdf new file mode 100644 index 0000000000..a48a3d41f2 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Quark.fdf @@ -0,0 +1,907 @@ +## @file +# FDF file of Clanton Peak CRB platform with 32-bit DXE +# +# This package provides QuarkNcSocId platform specific modules. +# Copyright (c) 2013 - 2018 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] +# Address 0x100000000 (4 GB reset address) +# Base Size +# +---------------------------+ +# FLASH_BASE | FD.Quark: | 0x800000 (8 MB) +# 0xFF800000 | BaseAddress | +# +---------------------------+ +# +# Flash offsets are 0 based, but are relative to FD.Quark BaseAddress, e.g. Payload Base is at 0x400000, Flash Base is at 0xFF800000 for 8 MB SPI part. +# 0xFF800000 + 0x400000 = 0xFFC00000. +# +# Address 0x0 (0xFF800000 for 8 MB SPI part) +# +---------------------------+ +# FLASH_FV_PAYLOAD_BASE | Payload Image | FLASH_FV_PAYLOAD_SIZE +# 0x00400000 | | 0x00100000 +# +---------------------------+ +# FLASH_FV_MAIN_BASE | FvMain Image (Compressed) | FLASH_FV_MAIN_SIZE +# 0x00500000 | | 0x001E0000 +# +---------------------------+ +# NVRAM_AREA_BASE | NVRAM Area= | NVRAM_AREA_SIZE +# 0x006E0000 | Variable + FTW Working + | +# | FTW Spare | +# +---+-------------------+---+ +# NVRAM_AREA_VARIABLE_BASE | | NVRAM_AREA_VARIABLE_SIZE +# | | +# +-------------------+ +# FTW_WORKING_BASE | | FTW_WORKING_SIZE +# | | +# +-------------------+ +# FTW_SPARE_BASE | | FTW_SPARE_SIZE +# | | +# +---+-------------------+---+ +# RMU_BINARY_BASE | RMU Binary | RMU_BINARY_SIZE +# 0x00700000 | | 0x00008000 +# +---------------------------+ +# PLATFORM_DATA_BASE | PlatformData Binary | PLATFORM_DATA_SIZE +# 0x00710000 | | 0x00001000 +# +---------------------------+ +# FVRECOVERY_IMAGE_BASE | FVRECOVERY Image | FVRECOVERY_IMAGE_SIZE +# 0x720000 | | 0x000E0000 +# +---------------------------+ + + # + # Define value used to compute FLASH regions below reset vector location just below 4GB + # + DEFINE RESET_ADDRESS = 0x100000000 # 4 GB + + # + # Set size of FLASH to 8MB + # + DEFINE FLASH_SIZE = 0x800000 + DEFINE FLASH_BASE = $(RESET_ADDRESS) - $(FLASH_SIZE) # The base address of the Flash Device + + # + # Set FLASH block size to 4KB + # + DEFINE FLASH_BLOCKSIZE = 0x1000 # 4 KB + + # + # Misc settings + # + DEFINE FLASH_BLOCKSIZE_DATA = 0x00, 0x10, 0x00, 0x00 # equivalent for DATA blocks + + # + # Start PAYLOAD at 4MB into 8MB FLASH + # + DEFINE FLASH_FV_PAYLOAD_BASE = 0x00400000 + DEFINE FLASH_FV_PAYLOAD_SIZE = 0x00100000 + + # + # Put FVMAIN between PAYLOAD and RMU Binary + # + DEFINE FLASH_FV_MAIN_BASE = 0x00500000 + DEFINE FLASH_FV_MAIN_SIZE = 0x001E0000 + + # + # Place NV Storage just above Platform Data Base + # + DEFINE NVRAM_AREA_VARIABLE_BASE = 0x006E0000 + DEFINE NVRAM_AREA_SIZE = 0x00020000 + + DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x0000E000 + DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE) + DEFINE FTW_WORKING_SIZE = 0x00002000 + DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE) + DEFINE FTW_SPARE_SIZE = $(NVRAM_AREA_SIZE) - $(NVRAM_AREA_VARIABLE_SIZE) - $(FTW_WORKING_SIZE) + + # + # RMU Binary must be at fixed address 1MB below 4GB (0xFFF00000) + # + DEFINE RMU_BINARY_BASE = 0x00700000 # HW fixed address + DEFINE RMU_BINARY_SIZE = 0x00008000 # HW fixed address, so fixed size + + # + # Platform Data Base must be 64KB above RMU + # + DEFINE VPD_BASE = 0x00708000 + DEFINE VPD_SIZE = 0x00001000 + + # + # Place FV Recovery above NV Storage + # + DEFINE FVRECOVERY_IMAGE_SIZE = 0x000F0000 + DEFINE FVRECOVERY_IMAGE_BASE = $(FLASH_SIZE) - $(FVRECOVERY_IMAGE_SIZE) + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ +[FD.Quark] +BaseAddress = 0xFF800000 #The base address of the Flash Device; set to same value as FLASH_BASE. +Size = 0x800000 #The size in bytes of the Flash Device; set to same value as FLASH_SIZE. +ErasePolarity = 1 +BlockSize = $(FLASH_BLOCKSIZE) +NumBlocks = 0x800 #The number of blocks for the Flash Device. + +SET gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress = $(FLASH_BASE) +SET gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize = $(FLASH_SIZE) + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +################################################################################ + +######################################################## +# Quark Payload Image +######################################################## +$(FLASH_FV_PAYLOAD_BASE)|$(FLASH_FV_PAYLOAD_SIZE) +gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadBase|gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadSize +FV = PAYLOAD + +######################################################## +# Quark FVMAIN Image (Compressed) +######################################################## +$(FLASH_FV_MAIN_BASE)|$(FLASH_FV_MAIN_SIZE) +gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainBase|gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainSize +FV = FVMAIN_COMPACT + +############################################################################# +# Quark NVRAM Area +# Quark NVRAM Area contains: Variable + FTW Working + FTW Spare +############################################################################# +$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +#NV_VARIABLE_STORE +DATA = { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid = + # { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x20000 + 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + #Signature "_FVH" #Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x19, 0xF9, 0x00, 0x00, 0x00, 0x02, + #Blockmap[0]: 32 Blocks * 0x1000 Bytes / Block + 0x20, 0x00, 0x00, 0x00, $(FLASH_BLOCKSIZE_DATA), + #Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER + !if $(SECURE_BOOT_ENABLE) + # Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 } } + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, + !else + # Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, + !endif + #Size: 0x0E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x0DFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xDF, 0x00, 0x00, + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA = { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0 + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +#NV_FTW_SPARE + +######################################################### +# Quark Remote Management Unit Binary +######################################################### +$(RMU_BINARY_BASE)|$(RMU_BINARY_SIZE) +INF QuarkSocBinPkg/QuarkNorthCluster/Binary/QuarkMicrocode/QuarkMicrocode.inf + +######################################################### +# PlatformData Binary, default for standalone is none built-in so user selects. +######################################################### +$(VPD_BASE)|$(VPD_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress +FILE = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/8C3D856A-9BE6-468E-850A-24F7A8D38E08.bin + +####################### +# Quark FVRECOVERY Image +####################### +$(FVRECOVERY_IMAGE_BASE)|$(FVRECOVERY_IMAGE_SIZE) +gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoveryBase|gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoverySize +FV = FVRECOVERY + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ +[FV.FVRECOVERY] +BlockSize = $(FLASH_BLOCKSIZE) +FvAlignment = 16 #FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 18D6D9F4-2EEF-4913-AEE6-BE61C6DA6CC8 + +################################################################################ +# +# The INF statements point to EDK component and EDK II module INF files, which will be placed into this FV image. +# Parsing tools will scan the INF file to determine the type of component or module. +# The component or module type is used to reference the standard rules +# defined elsewhere in the FDF file. +# +# The format for INF statements is: +# INF $(PathAndInfFileName) +# +################################################################################ + +## +# PEI Apriori file example, more PEIM module added later. +## +APRIORI PEI { + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + # PlatformConfigPei should be immediately after Pcd driver. + INF QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.inf + INF MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf +} + +## +# SEC Phase modules +## +INF UefiCpuPkg/SecCore/SecCore.inf + +!if $(CAPSULE_ENABLE) || $(RECOVERY_ENABLE) + # FMP image decriptor +INF RuleOverride = FMP_IMAGE_DESC QuarkPlatformPkg/Feature/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf +!endif + +INF MdeModulePkg/Core/Pei/PeiMain.inf + +## +# PEI Phase RAW Data files. +## +FILE FREEFORM = PCD(gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkMicrocodeFile) { + SECTION RAW = QuarkSocBinPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin +} + +INF RuleOverride = NORELOC MdeModulePkg/Universal/PCD/Pei/Pcd.inf +INF QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.inf +INF RuleOverride = NORELOC MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf +INF RuleOverride = NORELOC MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf +INF RuleOverride = NORELOC MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf +INF RuleOverride = NORELOC MdeModulePkg/Universal/Variable/Pei/VariablePei.inf +INF RuleOverride = NORELOC UefiCpuPkg/CpuMpPei/CpuMpPei.inf +INF RuleOverride = NORELOC MdeModulePkg/Universal/CapsulePei/CapsulePei.inf +INF RuleOverride = NORELOC QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/MemoryInitPei.inf +INF RuleOverride = NORELOC QuarkSocPkg/QuarkNorthCluster/Smm/Pei/SmmAccessPei/SmmAccessPei.inf +INF RuleOverride = NORELOC QuarkSocPkg/QuarkNorthCluster/Smm/Pei/SmmControlPei/SmmControlPei.inf +INF QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf +INF MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf +INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf +INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf +INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf +!if $(MEASURED_BOOT_ENABLE) +INF SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigPei.inf +INF SecurityPkg/Tcg/TcgPei/TcgPei.inf +!endif + +!if $(RECOVERY_ENABLE) +FILE FV_IMAGE = 1E9D7604-EF45-46a0-BD8A-71AC78C17AC1 { + SECTION PEI_DEPEX_EXP = {gEfiPeiMemoryDiscoveredPpiGuid AND gEfiPeiBootInRecoveryModePpiGuid} + SECTION GUIDED A31280AD-481E-41B6-95E8-127F4C984779 { # TIANO COMPRESS GUID + SECTION FV_IMAGE = FVRECOVERY_COMPONENTS + } +} +!endif + +!if $(RECOVERY_ENABLE) + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ +[FV.FVRECOVERY_COMPONENTS] +BlockSize = $(FLASH_BLOCKSIZE) +FvAlignment = 16 #FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +INF QuarkSocPkg/QuarkSouthCluster/Usb/Common/Pei/UsbPei.inf +INF MdeModulePkg/Bus/Pci/EhciPei/EhciPei.inf +INF QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/OhciPei.inf +INF MdeModulePkg/Bus/Usb/UsbBusPei/UsbBusPei.inf +INF MdeModulePkg/Bus/Usb/UsbBotPei/UsbBotPei.inf +INF FatPkg/FatPei/FatPei.inf +INF MdeModulePkg/Universal/Disk/CdExpressPei/CdExpressPei.inf +INF SignedCapsulePkg/Universal/RecoveryModuleLoadPei/RecoveryModuleLoadPei.inf + +!endif + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ +[FV.FVMAIN] +BlockSize = $(FLASH_BLOCKSIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 30D9ED01-38D2-418a-90D5-C561750BF80F + +## +# DXE Phase modules +## +INF MdeModulePkg/Core/Dxe/DxeMain.inf +INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + +!if $(SOURCE_DEBUG_ENABLE) + INF SourceLevelDebugPkg/DebugAgentDxe/DebugAgentDxe.inf +!endif + +# +# Early SoC / Platform modules +# +INF QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.inf + +## +# EDK Core modules +## +INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf +INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf +INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf +INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf +INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf +INF MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf + +INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +INF UefiCpuPkg/CpuDxe/CpuDxe.inf +INF MdeModulePkg/Universal/Metronome/Metronome.inf +INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf +INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf +INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf +!if $(SECURE_BOOT_ENABLE) + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf +!endif +INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf +INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf +INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf +INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf +INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf +INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf +INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf +INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + +# +# Platform +# +INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf +INF MdeModulePkg/Application/UiApp/UiApp.inf + +INF QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.inf +INF QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSpi.inf +INF QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSmmSpi.inf +INF QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/QNCInitDxe.inf +INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf +INF QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmAccessDxe/SmmAccess.inf +INF QuarkSocPkg/QuarkNorthCluster/S3Support/Dxe/QncS3Support.inf +INF QuarkSocPkg/QuarkNorthCluster/Spi/PchSpiRuntime.inf +INF QuarkSocPkg/QuarkNorthCluster/Spi/PchSpiSmm.inf +INF QuarkPlatformPkg/Platform/Dxe/Setup/DxePlatform.inf + +# +# ACPI +# +INF QuarkPlatformPkg/Platform/Dxe/SaveMemoryConfig/SaveMemoryConfig.inf +INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf +#INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf +INF QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/BootScriptExecutorDxe.inf +INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf +INF IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.inf +INF QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.inf +INF RuleOverride = ACPITABLE QuarkPlatformPkg/Acpi/AcpiTables/AcpiTables.inf + +# +# SMM +# +INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf +INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf +INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf +INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf +INF QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmControlDxe/SmmControlDxe.inf +INF QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNCSmmDispatcher.inf +INF QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.inf +INF QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.inf +INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf +INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf + +# +# SMBIOS +# +INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf +INF QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscDxe.inf +INF QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClass.inf + +# +# PCI +# +INF QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.inf +INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +INF QuarkSocPkg/QuarkSouthCluster/IohInit/Dxe/IohInitDxe.inf +!if $(SOURCE_DEBUG_ENABLE) +!else +INF MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf +!endif + +# +# USB +# +!if $(PERFORMANCE_ENABLE) +!else +INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf +INF QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciDxe.inf +INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf +INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf +INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf +INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf +!endif + +# +# SDIO +# +!if $(PERFORMANCE_ENABLE) +!else +INF QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDControllerDxe.inf +INF QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDMediaDeviceDxe/SDMediaDeviceDxe.inf +!endif + +# +# Console +# +INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf +INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf +INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + +INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf +INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf +INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf +INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + +# +# File System Modules +# +!if $(PERFORMANCE_ENABLE) +!else +INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf +INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf +INF FatPkg/EnhancedFatDxe/Fat.inf +!endif + +# +# Performance Application +# +!if $(PERFORMANCE_ENABLE) +INF ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf +!endif + +# +# Trusted Platform Module +# +!if $(MEASURED_BOOT_ENABLE) +INF SecurityPkg/Tcg/MemoryOverwriteControl/TcgMor.inf +INF SecurityPkg/Tcg/TcgDxe/TcgDxe.inf +INF RuleOverride = DRIVER_ACPITABLE SecurityPkg/Tcg/TcgSmm/TcgSmm.inf +!endif + +!if $(CAPSULE_ENABLE) +INF MdeModulePkg/Universal/EsrtFmpDxe/EsrtFmpDxe.inf +INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf +!endif + +!if $(RECOVERY_ENABLE) +FILE FREEFORM = PCD(gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiRsa2048Sha256TestPublicKeyFileGuid) { + SECTION RAW = BaseTools/Source/Python/Rsa2048Sha256Sign/TestSigningPublicKey.bin + SECTION UI = "Rsa2048Sha256TestSigningPublicKey" + } +!endif + +!if $(CAPSULE_ENABLE) +FILE FREEFORM = PCD(gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiPkcs7TestPublicKeyFileGuid) { + SECTION RAW = BaseTools/Source/Python/Pkcs7Sign/TestRoot.cer + SECTION UI = "Pkcs7TestRoot" + } +!endif + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ +[FV.FVMAIN_COMPACT] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED A31280AD-481E-41B6-95E8-127F4C984779 { # TIANO COMPRESS GUID + SECTION FV_IMAGE = FVMAIN + } +} + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ +[FV.PAYLOAD] +BlockSize = $(FLASH_BLOCKSIZE) +FvAlignment = 16 #FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +# +# Shell and Applications +# +INF RuleOverride = TIANOCOMPRESSED ShellPkg/Application/Shell/Shell.inf + +!if $(CAPSULE_ENABLE) || $(RECOVERY_ENABLE) + +[FV.CapsuleDispatchFv] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +!if $(CAPSULE_ENABLE) +INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf +!endif + +[FV.SystemFirmwareUpdateCargo] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +FILE RAW = 14D83A59-A810-4556-8192-1C0A593C065C { # PcdEdkiiSystemFirmwareFileGuid + FD = Quark + } + +FILE RAW = ce57b167-b0e4-41e8-a897-5f4feb781d40 { # gEdkiiSystemFmpCapsuleDriverFvFileGuid + FV = CapsuleDispatchFv + } + +FILE RAW = 812136D3-4D3A-433A-9418-29BB9BF78F6E { # gEdkiiSystemFmpCapsuleConfigFileGuid + QuarkPlatformPkg/Feature/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini + } + +!endif + +!if $(CAPSULE_ENABLE) +[FmpPayload.FmpPayloadSystemFirmwarePkcs7] +IMAGE_HEADER_INIT_VERSION = 0x02 +IMAGE_TYPE_ID = 62af20c0-7016-424a-9bf8-9ccc86584090 # PcdSystemFmpCapsuleImageTypeIdGuid +IMAGE_INDEX = 0x1 +HARDWARE_INSTANCE = 0x0 +MONOTONIC_COUNT = 0x2 +CERTIFICATE_GUID = 4AAFD29D-68DF-49EE-8AA9-347D375665A7 # PKCS7 + +FV = SystemFirmwareUpdateCargo + +[Capsule.QuarkFirmwareUpdateCapsuleFmpPkcs7] +CAPSULE_GUID = 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # gEfiFmpCapsuleGuid +CAPSULE_FLAGS = PersistAcrossReset,InitiateReset +CAPSULE_HEADER_SIZE = 0x20 +CAPSULE_HEADER_INIT_VERSION = 0x1 + +FMP_PAYLOAD = FmpPayloadSystemFirmwarePkcs7 +!endif + +!if $(RECOVERY_ENABLE) +[FmpPayload.FmpPayloadSystemFirmwareRsa2048] +IMAGE_HEADER_INIT_VERSION = 0x02 +IMAGE_TYPE_ID = 62af20c0-7016-424a-9bf8-9ccc86584090 # PcdSystemFmpCapsuleImageTypeIdGuid +IMAGE_INDEX = 0x1 +HARDWARE_INSTANCE = 0x0 +MONOTONIC_COUNT = 0x2 +CERTIFICATE_GUID = A7717414-C616-4977-9420-844712A735BF # RSA2048SHA256 + +FV = SystemFirmwareUpdateCargo + +[Capsule.QuarkRec] +CAPSULE_GUID = 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # gEfiFmpCapsuleGuid +CAPSULE_FLAGS = PersistAcrossReset,InitiateReset +CAPSULE_HEADER_SIZE = 0x20 +CAPSULE_HEADER_INIT_VERSION = 0x1 + +FMP_PAYLOAD = FmpPayloadSystemFirmwareRsa2048 +!endif + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +[Rule.Common.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi + RAW BIN Align = 16 |.com + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE = $(NAMED_GUID) { + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.PEIM.NORELOC] + FILE PEIM = $(NAMED_GUID) RELOCS_STRIPPED { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.PEIM] + FILE PEIM = $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_SMM_DRIVER] + FILE SMM = $(NAMED_GUID) { + SMM_DEPEX SMM_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_SMM_DRIVER.DRIVER_ACPITABLE] + FILE SMM = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.SMM_CORE] + FILE SMM_CORE = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.TIANOCOMPRESSED] + FILE APPLICATION = $(NAMED_GUID) { + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + SECTION GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { # TIANO COMPRESS GUID + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + } + +[Rule.Common.UEFI_APPLICATION.UI] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="Enter Setup" + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM = $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + } + +[Rule.Common.PEIM.FMP_IMAGE_DESC] + FILE PEIM = $(NAMED_GUID) { + RAW BIN |.acpi + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + diff --git a/Platform/Intel/QuarkPlatformPkg/QuarkMin.dsc b/Platform/Intel/QuarkPlatformPkg/QuarkMin.dsc new file mode 100644 index 0000000000..c95a5fcff9 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/QuarkMin.dsc @@ -0,0 +1,648 @@ +## @file +# Clanton Peak CRB platform with 32-bit DXE for 4MB/8MB flash devices. +# +# This package provides Clanton Peak CRB platform specific modules. +# Copyright (c) 2013 - 2019 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + DSC_SPECIFICATION = 0x00010005 + PLATFORM_NAME = QuarkMin + PLATFORM_GUID = 2655F3CF-4CC7-4e17-A62D-77FE3F10AE7F + PLATFORM_VERSION = 0.1 + FLASH_DEFINITION = QuarkPlatformPkg/QuarkMin.fdf + OUTPUT_DIRECTORY = Build/QuarkMin + SUPPORTED_ARCHITECTURES = IA32 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + VPD_TOOL_GUID = 8C3D856A-9BE6-468E-850A-24F7A8D38E08 + + # + # Platform On/Off features are defined here + # + DEFINE GALILEO = GEN2 + DEFINE SECURE_BOOT_ENABLE = FALSE + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE PERFORMANCE_ENABLE = FALSE + DEFINE LOGGING = FALSE + + !if $(TARGET) == "DEBUG" + DEFINE LOGGING = TRUE + !endif + + !if $(PERFORMANCE_ENABLE) + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE LOGGING = FALSE + !endif + +################################################################################ +# +# SKU Identification section - list of all SKU IDs supported by this +# Platform. +# +################################################################################ +[SkuIds] + 0|DEFAULT # The entry: 0|DEFAULT is reserved and always required. + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ +[LibraryClasses] + # + # Entry point + # + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf + + # + # Basic + # + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf + PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf +!if $(SOURCE_DEBUG_ENABLE) + PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf + DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf +!else + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf +!endif + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + + # + # UEFI & PI + # + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiDecompressLib|MdeModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf + + # + # Generic Modules + # + S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf + S3IoLib|MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf + S3PciLib|MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf + IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf + UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf + SmmCorePlatformHookLib|MdeModulePkg/Library/SmmCorePlatformHookLibNull/SmmCorePlatformHookLibNull.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf +!if $(LOGGING) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif +!if $(PERFORMANCE_ENABLE) + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf +!else + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf +!endif + + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + +!if $(SECURE_BOOT_ENABLE) + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + PlatformSecureLib|QuarkPlatformPkg/Library/PlatformSecureLib/PlatformSecureLib.inf + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf +!else + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf +!endif + + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + + # + # CPU + # + MtrrLib|QuarkSocPkg/QuarkNorthCluster/Library/MtrrLib/MtrrLib.inf + LocalApicLib|UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf + MpInitLib|UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.inf + + # + # Quark North Cluster + # + SmmLib|QuarkSocPkg/QuarkNorthCluster/Library/QNCSmmLib/QNCSmmLib.inf + SmbusLib|QuarkSocPkg/QuarkNorthCluster/Library/SmbusLib/SmbusLib.inf + TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.inf + ResetSystemLib|QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/ResetSystemLib.inf + IntelQNCLib|QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/IntelQNCLib.inf + QNCAccessLib|QuarkSocPkg/QuarkNorthCluster/Library/QNCAccessLib/QNCAccessLib.inf + IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf + + # + # Quark South Cluster + # + IohLib|QuarkSocPkg/QuarkSouthCluster/Library/IohLib/IohLib.inf + I2cLib|QuarkSocPkg/QuarkSouthCluster/Library/I2cLib/I2cLib.inf + SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf + PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf + + # + # Quark Platform + # + PlatformSecLib|QuarkPlatformPkg/Library/PlatformSecLib/PlatformSecLib.inf + PlatformPcieHelperLib|QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.inf + PlatformHelperLib|QuarkPlatformPkg/Library/PlatformHelperLib/DxePlatformHelperLib.inf + +[LibraryClasses.common.SEC] + # + # SEC specific phase + # + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf + +[LibraryClasses.IA32.PEIM,LibraryClasses.IA32.PEI_CORE] + # + # PEI phase common + # + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf + LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf + TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf + PlatformHelperLib|QuarkPlatformPkg/Library/PlatformHelperLib/PeiPlatformHelperLib.inf + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf +!if $(SECURE_BOOT_ENABLE) + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf +!endif +!if $(PERFORMANCE_ENABLE) + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf +!endif + +[LibraryClasses.IA32.DXE_CORE] + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf +!if $(PERFORMANCE_ENABLE) + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf +!endif + +[LibraryClasses.IA32.DXE_SMM_DRIVER] + MmServicesTableLib|MdePkg/Library/MmServicesTableLib/MmServicesTableLib.inf + SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf + MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf + LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf +!if $(SECURE_BOOT_ENABLE) + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf +!endif +!if $(PERFORMANCE_ENABLE) + PerformanceLib|MdeModulePkg/Library/SmmPerformanceLib/SmmPerformanceLib.inf +!endif + +[LibraryClasses.IA32.SMM_CORE] + SmmServicesTableLib|MdeModulePkg/Library/PiSmmCoreSmmServicesTableLib/PiSmmCoreSmmServicesTableLib.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf + MemoryAllocationLib|MdeModulePkg/Library/PiSmmCoreMemoryAllocationLib/PiSmmCoreMemoryAllocationLib.inf + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf +!if $(SECURE_BOOT_ENABLE) + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf +!endif +!if $(PERFORMANCE_ENABLE) + PerformanceLib|MdeModulePkg/Library/SmmCorePerformanceLib/SmmCorePerformanceLib.inf +!endif + +[LibraryClasses.IA32.DXE_RUNTIME_DRIVER] + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf + QNCAccessLib|QuarkSocPkg/QuarkNorthCluster/Library/QNCAccessLib/RuntimeQNCAccessLib.inf + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +!if $(SECURE_BOOT_ENABLE) + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf +!endif + +[LibraryClasses.IA32.UEFI_DRIVER,LibraryClasses.IA32.UEFI_APPLICATION] + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ +[PcdsFeatureFlag] + gEfiMdeModulePkgTokenSpaceGuid.PcdDevicePathSupportDevicePathToText|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdDevicePathSupportDevicePathFromText|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE +!if $(SOURCE_DEBUG_ENABLE) + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|TRUE +!endif + +!if $(TARGET) == "RELEASE" + gQuarkPlatformTokenSpaceGuid.WaitIfResetDueToError|FALSE +!else + gQuarkPlatformTokenSpaceGuid.WaitIfResetDueToError|TRUE +!endif + +[PcdsFixedAtBuild] + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|1 + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x20000 + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE +!if $(LOGGING) + !if $(SOURCE_DEBUG_ENABLE) + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17 + !else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27 + !endif + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0x0 + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3 +!endif + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0x18 + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 +!if $(GALILEO) == GEN1 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|460800 +!endif +!if $(GALILEO) == GEN2 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|921600 +!endif + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0 +!if $(PERFORMANCE_ENABLE) + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|80 +!else + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x00 +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0 +!if $(SECURE_BOOT_ENABLE) + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00002000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x1000 + # + # Make VariableRuntimeDxe work at emulated non-volatile variable mode. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE + ## RTC Update Timeout Value, need to increase timeout since also + # waiting for RTC to be busy. + gEfiMdeModulePkgTokenSpaceGuid.PcdRealTimeClockUpdateTimeout|500000 + +!if $(SECURE_BOOT_ENABLE) + # override the default values from SecurityPkg to ensure images from all sources are verified in secure boot + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04 +!endif + gQuarkPlatformTokenSpaceGuid.PcdEsramStage1Base|0x80000000 + +!if $(SOURCE_DEBUG_ENABLE) + gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 +!endif + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x9000B000 +!if $(GALILEO) == GEN1 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|460800 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE +!endif +!if $(GALILEO) == GEN2 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|921600 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|0x03 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x07 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|44236800 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo|{0x14, 0x05, 0x84, 0x00, 0xFF} + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4 + + # + # typedef struct { + # UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries. + # UINT16 DeviceId; ///< Device ID to match the PCI device + # UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz + # UINT64 Offset; ///< The byte offset into to the BAR + # UINT8 BarIndex; ///< Which BAR to get the UART base address + # UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte. + # UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes. + # UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes. + # UINT8 Reserved[2]; + # } PCI_SERIAL_PARAMETER; + # + # Vendor 8086 Device 0936 Prog Interface 2, BAR #0, Offset 0, Stride = 4, Clock 44236800 (0x2a300000) + # Vendor 8086 Device 0936 Prog Interface 2, BAR #0, Offset 0, Stride = 4, Clock 44236800 (0x2a300000) + # + # [Vendor] [Device] [---ClockRate---] [------------Offset-----------] [Bar] [Stride] [RxFifo] [TxFifo] [Rsvd] [Vendor] + gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|{0x86,0x80, 0x36,0x09, 0x0,0x0,0xA3,0x02, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00, 0x04, 0x0,0x0, 0x0,0x0, 0x0,0x0, 0xff,0xff} + + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber |0 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber |31 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber |0 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x4b + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask |0x80 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0x48 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress |0x1000 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008 + + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 } + + gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE + + # + # Quark does not support LFENCE. Use CPUID as speculation barrier + # + gEfiMdePkgTokenSpaceGuid.PcdSpeculationBarrierType|0x02 + +[PcdsPatchableInModule] + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803000C7 + gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 + +[PcdsDynamicExHii.common.DEFAULT] +!if $(PERFORMANCE_ENABLE) + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|0 +!else + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 +!endif + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState|L"BootState"|gQuarkPlatformTokenSpaceGuid|0x0|TRUE + +[PcdsDynamicExDefault.common.DEFAULT] + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0 + gQuarkPlatformTokenSpaceGuid.PcdEnableFastBoot|TRUE + gQuarkPlatformTokenSpaceGuid.PcdUserIsPhysicallyPresent|FALSE + gQuarkPlatformTokenSpaceGuid.PcdSpiFlashDeviceSize|0 + +[PcdsDynamicExVpd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|*|32|L"EDK II" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision|*|0x01000400 + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|*|64|L"Galileo 1.0.4" + +# +# ClantonPeakSVP +# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0002 +# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"ClantonPeakSVP" +# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x03, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06} +# +# KipsBay +# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0003 +# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"KipsBay" +# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06} +# +# CrossHill +# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0004 +# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"CrossHill" +# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x03, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06} +# +# ClantonHill +# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0005 +# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"ClantonHill" +# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x02, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06} +# +# Galileo +# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0006 +# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"Galileo" +# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06} +# +# GalileoGen2 +# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0008 +# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"GalileoGen2" +# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06} +# +!if $(GALILEO) == GEN1 + gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0006 + gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"Galileo" + gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06} +!endif +!if $(GALILEO) == GEN2 + gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0008 + gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"GalileoGen2" + gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06} +!endif + gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac0|*|8|{0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac1|*|8|{0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + +################################################################################################### +# +# Components Section - list of the modules and components that will be processed by compilation +# tools and the EDK II tools to generate PE32/PE32+/Coff image files. +# +# Note: The EDK II DSC file is not used to specify how compiled binary images get placed +# into firmware volume images. This section is just a list of modules to compile from +# source into UEFI-compliant binaries. +# It is the FDF file that contains information on combining binary files into firmware +# volume images, whose concept is beyond UEFI and is described in PI specification. +# Binary modules do not need to be listed in this section, as they should be +# specified in the FDF file. For example: Shell binary, FAT binary (Fat.efi), +# Logo (Logo.bmp), and etc. +# There may also be modules listed in this section that are not required in the FDF file, +# When a module listed here is excluded from FDF file, then UEFI-compliant binary will be +# generated for it, but the binary will not be put into any firmware volume. +# +################################################################################################### + +[Components.IA32] + # + # SEC Core + # + UefiCpuPkg/SecCore/SecCore.inf { + !if $(SOURCE_DEBUG_ENABLE) + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf + ResetSystemLib|QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/ResetSystemLib.inf + !endif + } + + # + # PEI Core + # + MdeModulePkg/Core/Pei/PeiMain.inf + + # + # PEIM + # + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf + + QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/MemoryInitPei.inf + QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf + QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.inf + + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + +[Components.IA32] + # + # DXE Core + # + MdeModulePkg/Core/Dxe/DxeMain.inf + +!if $(SOURCE_DEBUG_ENABLE) + SourceLevelDebugPkg/DebugAgentDxe/DebugAgentDxe.inf { + + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf + ResetSystemLib|QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/ResetSystemLib.inf + } +!endif + + + QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.inf + + # + # Components that produce the architectural protocols + # + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + UefiCpuPkg/CpuDxe/CpuDxe.inf + MdeModulePkg/Universal/Metronome/Metronome.inf + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf + + # + # Following are the DXE drivers (alphabetical order) + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + + QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.inf + UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + + # + # Platform + # + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf { + + PlatformBootManagerLib|QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf + } + + QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/QNCInitDxe.inf + PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf + QuarkPlatformPkg/Platform/Dxe/Setup/DxePlatform.inf + MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + + # + # PCI + # + QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.inf + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + QuarkSocPkg/QuarkSouthCluster/IohInit/Dxe/IohInitDxe.inf + MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf + + # + # Console + # + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf { + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf { + + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf + } + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # File System Modules + # + MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + + # + # Performance Application + # +!if $(PERFORMANCE_ENABLE) + ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + } +!endif + + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf + + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } diff --git a/Platform/Intel/QuarkPlatformPkg/QuarkMin.fdf b/Platform/Intel/QuarkPlatformPkg/QuarkMin.fdf new file mode 100644 index 0000000000..bdd5af8fb8 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/QuarkMin.fdf @@ -0,0 +1,608 @@ +## @file +# FDF file of Clanton Peak CRB platform with 32-bit DXE +# +# This package provides QuarkNcSocId platform specific modules. +# Copyright (c) 2013 - 2019 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] +# Address 0x100000000 (4 GB reset address) +# Base Size +# +---------------------------+ +# FLASH_BASE | FD.Quark: | 0x800000 (8 MB) +# 0xFF800000 | BaseAddress | +# +---------------------------+ +# +# Flash offsets are 0 based, but are relative to FD.Quark BaseAddress, e.g. Payload Base is at 0x400000, Flash Base is at 0xFF800000 for 8 MB SPI part. +# 0xFF800000 + 0x400000 = 0xFFC00000. +# +# Address 0x0 (0xFF800000 for 8 MB SPI part) +# +---------------------------+ +# FLASH_FV_PAYLOAD_BASE | Payload Image | FLASH_FV_PAYLOAD_SIZE +# 0x00400000 | | 0x00100000 +# +---------------------------+ +# FLASH_FV_MAIN_BASE | FvMain Image (Compressed) | FLASH_FV_MAIN_SIZE +# 0x00500000 | | 0x001E0000 +# +---------------------------+ +# NVRAM_AREA_BASE | NVRAM Area= | NVRAM_AREA_SIZE +# 0x006E0000 | Variable + FTW Working + | +# | FTW Spare | +# +---+-------------------+---+ +# NVRAM_AREA_VARIABLE_BASE | | NVRAM_AREA_VARIABLE_SIZE +# | | +# +-------------------+ +# FTW_WORKING_BASE | | FTW_WORKING_SIZE +# | | +# +-------------------+ +# FTW_SPARE_BASE | | FTW_SPARE_SIZE +# | | +# +---+-------------------+---+ +# RMU_BINARY_BASE | RMU Binary | RMU_BINARY_SIZE +# 0x00700000 | | 0x00008000 +# +---------------------------+ +# PLATFORM_DATA_BASE | PlatformData Binary | PLATFORM_DATA_SIZE +# 0x00710000 | | 0x00001000 +# +---------------------------+ +# FVRECOVERY_IMAGE_BASE | FVRECOVERY Image | FVRECOVERY_IMAGE_SIZE +# 0x720000 | | 0x000E0000 +# +---------------------------+ + + # + # Define value used to compute FLASH regions below reset vector location just below 4GB + # + DEFINE RESET_ADDRESS = 0x100000000 # 4 GB + + # + # Set size of FLASH to 8MB + # + DEFINE FLASH_SIZE = 0x800000 + DEFINE FLASH_BASE = $(RESET_ADDRESS) - $(FLASH_SIZE) # The base address of the Flash Device + + # + # Set FLASH block size to 4KB + # + DEFINE FLASH_BLOCKSIZE = 0x1000 # 4 KB + + # + # Misc settings + # + DEFINE FLASH_BLOCKSIZE_DATA = 0x00, 0x10, 0x00, 0x00 # equivalent for DATA blocks + + # + # Start PAYLOAD at 4MB into 8MB FLASH + # + DEFINE FLASH_FV_PAYLOAD_BASE = 0x00400000 + DEFINE FLASH_FV_PAYLOAD_SIZE = 0x00100000 + + # + # Put FVMAIN between PAYLOAD and RMU Binary + # + DEFINE FLASH_FV_MAIN_BASE = 0x00500000 + DEFINE FLASH_FV_MAIN_SIZE = 0x001E0000 + + # + # Place NV Storage just above Platform Data Base + # + DEFINE NVRAM_AREA_VARIABLE_BASE = 0x006E0000 + DEFINE NVRAM_AREA_SIZE = 0x00020000 + + DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x0000E000 + DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE) + DEFINE FTW_WORKING_SIZE = 0x00002000 + DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE) + DEFINE FTW_SPARE_SIZE = $(NVRAM_AREA_SIZE) - $(NVRAM_AREA_VARIABLE_SIZE) - $(FTW_WORKING_SIZE) + + # + # RMU Binary must be at fixed address 1MB below 4GB (0xFFF00000) + # + DEFINE RMU_BINARY_BASE = 0x00700000 # HW fixed address + DEFINE RMU_BINARY_SIZE = 0x00008000 # HW fixed address, so fixed size + + # + # Platform Data Base must be 64KB above RMU + # + DEFINE VPD_BASE = 0x00708000 + DEFINE VPD_SIZE = 0x00001000 + + # + # Place FV Recovery above NV Storage + # + DEFINE FVRECOVERY_IMAGE_SIZE = 0x000F0000 + DEFINE FVRECOVERY_IMAGE_BASE = $(FLASH_SIZE) - $(FVRECOVERY_IMAGE_SIZE) + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ +[FD.Quark] +BaseAddress = 0xFF800000 #The base address of the Flash Device; set to same value as FLASH_BASE. +Size = 0x800000 #The size in bytes of the Flash Device; set to same value as FLASH_SIZE. +ErasePolarity = 1 +BlockSize = $(FLASH_BLOCKSIZE) +NumBlocks = 0x800 #The number of blocks for the Flash Device. + +SET gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress = $(FLASH_BASE) +SET gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize = $(FLASH_SIZE) + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +################################################################################ + +######################################################## +# Quark Payload Image +######################################################## +$(FLASH_FV_PAYLOAD_BASE)|$(FLASH_FV_PAYLOAD_SIZE) +gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadBase|gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadSize +FV = PAYLOAD + +######################################################## +# Quark FVMAIN Image (Compressed) +######################################################## +$(FLASH_FV_MAIN_BASE)|$(FLASH_FV_MAIN_SIZE) +gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainBase|gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainSize +FV = FVMAIN_COMPACT + +############################################################################# +# Quark NVRAM Area +# Quark NVRAM Area contains: Variable + FTW Working + FTW Spare +############################################################################# +$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +#NV_VARIABLE_STORE +DATA = { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid = + # { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x20000 + 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + #Signature "_FVH" #Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x19, 0xF9, 0x00, 0x00, 0x00, 0x02, + #Blockmap[0]: 32 Blocks * 0x1000 Bytes / Block + 0x20, 0x00, 0x00, 0x00, $(FLASH_BLOCKSIZE_DATA), + #Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER + !if $(SECURE_BOOT_ENABLE) + # Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 } } + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, + !else + # Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, + !endif + #Size: 0x0E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x0DFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xDF, 0x00, 0x00, + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA = { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0 + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +#NV_FTW_SPARE + +######################################################### +# Quark Remote Management Unit Binary +######################################################### +$(RMU_BINARY_BASE)|$(RMU_BINARY_SIZE) +INF QuarkSocBinPkg/QuarkNorthCluster/Binary/QuarkMicrocode/QuarkMicrocode.inf + +######################################################### +# PlatformData Binary, default for standalone is none built-in so user selects. +######################################################### +$(VPD_BASE)|$(VPD_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress +FILE = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/8C3D856A-9BE6-468E-850A-24F7A8D38E08.bin + +####################### +# Quark FVRECOVERY Image +####################### +$(FVRECOVERY_IMAGE_BASE)|$(FVRECOVERY_IMAGE_SIZE) +gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoveryBase|gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoverySize +FV = FVRECOVERY + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ +[FV.FVRECOVERY] +BlockSize = $(FLASH_BLOCKSIZE) +FvAlignment = 16 #FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 18D6D9F4-2EEF-4913-AEE6-BE61C6DA6CC8 + +################################################################################ +# +# The INF statements point to EDK component and EDK II module INF files, which will be placed into this FV image. +# Parsing tools will scan the INF file to determine the type of component or module. +# The component or module type is used to reference the standard rules +# defined elsewhere in the FDF file. +# +# The format for INF statements is: +# INF $(PathAndInfFileName) +# +################################################################################ + +## +# PEI Apriori file example, more PEIM module added later. +## +APRIORI PEI { + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + # PlatformConfigPei should be immediately after Pcd driver. + INF QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.inf + INF MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf +} + +## +# SEC Phase modules +## +INF UefiCpuPkg/SecCore/SecCore.inf + +INF MdeModulePkg/Core/Pei/PeiMain.inf + +## +# PEI Phase RAW Data files. +## +FILE FREEFORM = PCD(gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkMicrocodeFile) { + SECTION RAW = QuarkSocBinPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin +} + +INF RuleOverride = NORELOC MdeModulePkg/Universal/PCD/Pei/Pcd.inf +INF QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.inf +INF RuleOverride = NORELOC MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf +INF RuleOverride = NORELOC MdeModulePkg/Universal/Variable/Pei/VariablePei.inf +INF RuleOverride = NORELOC QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/MemoryInitPei.inf +INF QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf +INF MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf +INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ +[FV.FVMAIN] +BlockSize = $(FLASH_BLOCKSIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 30D9ED01-38D2-418a-90D5-C561750BF80F + +## +# DXE Phase modules +## +INF MdeModulePkg/Core/Dxe/DxeMain.inf +INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + +!if $(SOURCE_DEBUG_ENABLE) + INF SourceLevelDebugPkg/DebugAgentDxe/DebugAgentDxe.inf +!endif + +# +# Early SoC / Platform modules +# +INF QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.inf + +## +# EDK Core modules +## +INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + +INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +INF UefiCpuPkg/CpuDxe/CpuDxe.inf +INF MdeModulePkg/Universal/Metronome/Metronome.inf +INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf +INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf +INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf +INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf +INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf +INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf +INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf +INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf +INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + +# +# Platform +# +INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf +#INF MdeModulePkg/Application/UiApp/UiApp.inf + +INF QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.inf +INF QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/QNCInitDxe.inf +INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf +INF QuarkPlatformPkg/Platform/Dxe/Setup/DxePlatform.inf + +# +# PCI +# +INF QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.inf +INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +INF QuarkSocPkg/QuarkSouthCluster/IohInit/Dxe/IohInitDxe.inf +!if $(SOURCE_DEBUG_ENABLE) +!else +INF MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf +!endif + +# +# Console +# +INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf +INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf +INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + +INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf +INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf +INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf +INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + +# +# File System Modules +# +INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + +# +# Performance Application +# +!if $(PERFORMANCE_ENABLE) +INF ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf +!endif + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ +[FV.FVMAIN_COMPACT] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED A31280AD-481E-41B6-95E8-127F4C984779 { # TIANO COMPRESS GUID + SECTION FV_IMAGE = FVMAIN + } +} + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ +[FV.PAYLOAD] +BlockSize = $(FLASH_BLOCKSIZE) +FvAlignment = 16 #FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +# +# Shell and Applications +# +INF ShellPkg/Application/Shell/Shell.inf + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +[Rule.Common.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi + RAW BIN Align = 16 |.com + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE = $(NAMED_GUID) { + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.PEIM.NORELOC] + FILE PEIM = $(NAMED_GUID) RELOCS_STRIPPED { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.PEIM] + FILE PEIM = $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_SMM_DRIVER] + FILE SMM = $(NAMED_GUID) { + SMM_DEPEX SMM_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.SMM_CORE] + FILE SMM_CORE = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.UI] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="Enter Setup" + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM = $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + } diff --git a/Platform/Intel/QuarkPlatformPkg/QuarkPlatformPkg.dec b/Platform/Intel/QuarkPlatformPkg/QuarkPlatformPkg.dec new file mode 100644 index 0000000000..57bd393bb0 --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/QuarkPlatformPkg.dec @@ -0,0 +1,933 @@ +## @file +# Package for support of Clanton Peak CRB platform +# +# This package provides QuarkNcSocId platform specific modules. +# Copyright (c) 2013-2015 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = QuarkPlatformPkg + PACKAGE_GUID = 46C1F476-A85E-49a8-B258-DD4396B87FEF + PACKAGE_VERSION = 0.1 + + +################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# SEC PEIM DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER +# +################################################################################ +[Includes] + Include + +################################################################################ +# +# Library Class Header section - list of Library Class header files that are +# provided by this package. +# +################################################################################ +[LibraryClasses] + +################################################################################ +# +# Global Guid Definition section - list of Global Guid C Name Data Structures +# that are provided by this package. +# +################################################################################ +[Guids] + gQuarkPlatformTokenSpaceGuid = { 0x199c1ef0, 0x6400, 0x41c5, { 0xb0, 0xa4, 0xff, 0xbf, 0x21, 0x9d, 0xcb, 0xae }} + gEfiMemoryConfigDataGuid = { 0x80dbd530, 0xb74c, 0x4f11, { 0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 }} + gPowerManagementAcpiTableStorageGuid = { 0xc0cc43bd, 0xc920, 0x4064, { 0x93, 0x5b, 0x93, 0xb4, 0x47, 0x37, 0x94, 0x70 }} + gPeiCapsuleOnFatFloppyDiskGuid = {0x2e3d2e75, 0x9b2e, 0x412d, {0xb4, 0xb1, 0x70, 0x41, 0x6b, 0x87, 0x0, 0xff }} + gPeiCapsuleOnFatIdeDiskGuid = {0xb38573b6, 0x6200, 0x4ac5, {0xb5, 0x1d, 0x82, 0xe6, 0x59, 0x38, 0xd7, 0x83 }} + gPeiCapsuleOnFatUsbDiskGuid = {0x0ffbce19, 0x324c, 0x4690, {0xa0, 0x09, 0x98, 0xc6, 0xae, 0x2e, 0xb1, 0x86 }} + gPeiCapsuleOnDataCDGuid = {0x5cac0099, 0x0dc9, 0x48e5, {0x80, 0x68, 0xbb, 0x95, 0xf5, 0x40, 0x0a, 0x9f }} + gEfiQuarkCapsuleGuid = { 0xd400d1e4, 0xa314, 0x442b, { 0x89, 0xed, 0xa9, 0x2e, 0x4c, 0x81, 0x97, 0xcb } } + gQuarkVariableLockGuid = { 0xeef749c2, 0xc047, 0x4d6e, { 0xb1, 0xbc, 0xd3, 0x6e, 0xb3, 0xa5, 0x55, 0x9c }} + +################################################################################ +# +# Global Protocols Definition section - list of Global Protocols C Name Data +# Structures that are provided by this package. +# +################################################################################ +[Protocols] + gEfiGlobalNvsAreaProtocolGuid = { 0x074E1E48, 0x8132, 0x47A1, { 0x8C, 0x2C, 0x3F, 0x14, 0xAD, 0x9A, 0x66, 0xDC }} + gEfiSmmSpiReadyProtocolGuid = { 0x7a5dbc75, 0x5b2b, 0x4e67, { 0xbd, 0xe1, 0xd4, 0x8e, 0xee, 0x76, 0x15, 0x62 }} + gEfiIioUdsProtocolGuid = { 0xa7ced760, 0xc71c, 0x4e1a, { 0xac, 0xb1, 0x89, 0x60, 0x4d, 0x52, 0x16, 0xcb }} + +################################################################################ +# +# PCD Declarations section - list of all PCDs Declared by this Package +# Only this package should be providing the +# declaration, other packages should not. +# +################################################################################ + +[PcdsFeatureFlag] + gQuarkPlatformTokenSpaceGuid.WaitIfResetDueToError|FALSE|BOOLEAN|0x2000000F + +[PcdsFixedAtBuild] + gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000|UINT32|0x20000001 + gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize|0x800000|UINT32|0x20000002 + gQuarkPlatformTokenSpaceGuid.PcdFlashNvStorageBase|0xFFF30000|UINT32|0x20000003 + gQuarkPlatformTokenSpaceGuid.PcdFlashNvStorageSize|0x00020000|UINT32|0x20000004 + gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecovery2Base|0xFFEF0400|UINT32|0x2000001C + gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecovery2Size|0x00007000|UINT32|0x2000001D + gQuarkPlatformTokenSpaceGuid.PcdFlashQNCMicrocodeSize|0x00004000|UINT32|0x2000000C + gQuarkPlatformTokenSpaceGuid.PcdPlatformDataBaseAddress|0xFFF10000|UINT32|0x2000001E + gQuarkPlatformTokenSpaceGuid.PcdPlatformDataMaxLen|0x20000|UINT32|0x2000001F + gQuarkPlatformTokenSpaceGuid.PcdHpetEnable|TRUE|BOOLEAN|0x20000018 + + gQuarkPlatformTokenSpaceGuid.PcdFlashFvDefaultPayloadBase|0xFFC00400|UINT32|0x20000020 + gQuarkPlatformTokenSpaceGuid.PcdFlashFvDefaultPayloadSize|0x000F0000|UINT32|0x20000021 + gQuarkPlatformTokenSpaceGuid.PcdFlashFvDefaultMainBase|0xFFD00400|UINT32|0x20000022 + gQuarkPlatformTokenSpaceGuid.PcdFlashFvDefaultMainSize|0x000D0000|UINT32|0x20000023 + + gQuarkPlatformTokenSpaceGuid.PcdMemorySize|0x80000000|UINT32|0x20000032 + # ECC scrub interval in miliseconds 1..255 (0 works as feature disable) + gQuarkPlatformTokenSpaceGuid.PcdEccScrubInterval|0x00|UINT8|0x20000037 + # Number of 32B blocks read for ECC scrub 2..16 + gQuarkPlatformTokenSpaceGuid.PcdEccScrubBlkSize|0x02|UINT8|0x20000038 + gQuarkPlatformTokenSpaceGuid.PcdFlashNvMfh|0xFFF08000|UINT32|0x20000039 + gQuarkPlatformTokenSpaceGuid.PcdFlashFvFixedStage1AreaBase|0xFFF90000|UINT32|0x2000003A + gQuarkPlatformTokenSpaceGuid.PcdFlashFvFixedStage1AreaSize|0x00040000|UINT32|0x2000003B + gQuarkPlatformTokenSpaceGuid.PcdEsramStage1Base|0x80000000|UINT32|0x2000003C + + # Legacy Bridge protected BIOS range register configs, if == 0 then do nothing since register default. + gQuarkPlatformTokenSpaceGuid.PcdLegacyProtectedBIOSRange0Pei|0x00000000|UINT32|0x2000003D + gQuarkPlatformTokenSpaceGuid.PcdLegacyProtectedBIOSRange1Pei|0x00000000|UINT32|0x2000003E + gQuarkPlatformTokenSpaceGuid.PcdLegacyProtectedBIOSRange2Pei|0x00000000|UINT32|0x2000004F + + # ACPI Power management settings. + + # Power Management flags. + # PpmFlags[5] = PPM_C2 = C2 Capable, Enabled. + gQuarkPlatformTokenSpaceGuid.PcdPpmFlags|0x00000020|UINT32|0xA00000CF + + # Madt Table Initialize settings. + # Defines a flag to Enable/Disable interrupt override setting table0, + # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table0 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0Enable|0x01|UINT8|0xA0000100 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0SourceIrq|0x00|UINT8|0xA0000101 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0Polarity|0x00|UINT8|0xA0000102 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0TrigerMode|0x00|UINT8|0xA0000103 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0GlobalIrq|0x02|UINT32|0xA0000104 + + # Madt Table Initialize settings. + # Defines a flag to Enable/Disable interrupt override setting table1, + # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table1 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1Enable|0x01|UINT8|0xA0000105 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1SourceIrq|0x09|UINT8|0xA0000106 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1Polarity|0x01|UINT8|0xA0000107 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1TrigerMode|0x03|UINT8|0xA0000108 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1GlobalIrq|0x09|UINT32|0xA0000109 + + # Madt Table Initialize settings. + # Defines a flag to Enable/Disable interrupt override setting table2, + # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table2 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2Enable|0x0|UINT8|0xA000010F + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2SourceIrq|0x0|UINT8|0xA0000110 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2Polarity|0x0|UINT8|0xA0000111 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2TrigerMode|0x0|UINT8|0xA0000112 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2GlobalIrq|0x0|UINT32|0xA0000113 + + # Madt Table Initialize settings. + # Defines a flag to Enable/Disable interrupt override setting table3, + # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table3 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3Enable|0x0|UINT8|0xA0000114 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3SourceIrq|0x0|UINT8|0xA0000115 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3Polarity|0x0|UINT8|0xA0000116 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3TrigerMode|0x0|UINT8|0xA0000117 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3GlobalIrq|0x0|UINT32|0xA0000118 + + # Madt Table Initialize settings. + # Defines a flag to Enable/Disable interrupt override setting table4, + # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table4 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4Enable|0x0|UINT8|0xA0000119 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4SourceIrq|0x0|UINT8|0xA000011A + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4Polarity|0x0|UINT8|0xA0000120 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4TrigerMode|0x0|UINT8|0xA0000121 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4GlobalIrq|0x0|UINT32|0xA0000122 + + # Madt Table Initialize settings. + # Defines a flag to Enable/Disable interrupt override setting table5, + # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table5 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5Enable|0x0|UINT8|0xA0000123 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5SourceIrq|0x0|UINT8|0xA0000124 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5Polarity|0x0|UINT8|0xA0000125 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5TrigerMode|0x0|UINT8|0xA0000126 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5GlobalIrq|0x0|UINT32|0xA0000127 + + # Madt Table Initialize settings. + # Defines a flag to Enable/Disable interrupt override setting table6, + # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table6 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6Enable|0x0|UINT8|0xA0000128 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6SourceIrq|0x0|UINT8|0xA0000129 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6Polarity|0x0|UINT8|0xA000012A + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6TrigerMode|0x0|UINT8|0xA000012B + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6GlobalIrq|0x0|UINT32|0xA000012C + + # Madt Table Initialize settings. + # Defines a flag to Enable/Disable interrupt override setting table7, + # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table7 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7Enable|0x0|UINT8|0xA000012D + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7SourceIrq|0x0|UINT8|0xA000012E + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7Polarity|0x0|UINT8|0xA000012F + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7TrigerMode|0x0|UINT8|0xA0000130 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7GlobalIrq|0x0|UINT32|0xA0000131 + + # Madt Table Initialize settings. + # Defines a flag to Enable/Disable interrupt override setting table8, + # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table8 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8Enable|0x0|UINT8|0xA0000132 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8SourceIrq|0x0|UINT8|0xA0000133 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8Polarity|0x0|UINT8|0xA0000134 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8TrigerMode|0x0|UINT8|0xA0000135 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8GlobalIrq|0x0|UINT32|0xA0000136 + + # Madt Table Initialize settings. + # Defines a flag to Enable/Disable interrupt override setting table9, + # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table9 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9Enable|0x0|UINT8|0xA0000137 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9SourceIrq|0x0|UINT8|0xA0000138 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9Polarity|0x0|UINT8|0xA0000139 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9TrigerMode|0x0|UINT8|0xA000013A + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9GlobalIrq|0x0|UINT32|0xA000013B + + # Madt Table Initialize settings. + # Defines a flag to Enable/Disable interrupt override setting table10, + # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table10 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10Enable|0x0|UINT8|0xA000013C + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10SourceIrq|0x0|UINT8|0xA000013D + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10Polarity|0x0|UINT8|0xA000013E + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10TrigerMode|0x0|UINT8|0xA000013F + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10GlobalIrq|0x0|UINT32|0xA0000140 + + # Madt Table Initialize settings. + # Defines a flag to Enable/Disable interrupt override setting table11, + # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table11 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11Enable|0x0|UINT8|0xA0000141 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11SourceIrq|0x0|UINT8|0xA0000142 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11Polarity|0x0|UINT8|0xA0000143 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11TrigerMode|0x0|UINT8|0xA0000144 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11GlobalIrq|0x0|UINT32|0xA0000145 + + # Madt Table Initialize settings. + # Defines a flag to Enable/Disable interrupt override setting table12, + # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table12 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12Enable|0x0|UINT8|0xA0000146 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12SourceIrq|0x0|UINT8|0xA0000147 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12Polarity|0x0|UINT8|0xA0000148 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12TrigerMode|0x0|UINT8|0xA0000149 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12GlobalIrq|0x0|UINT32|0xA000014A + + # Madt Table Initialize settings. + # Defines a flag to Enable/Disable interrupt override setting table13, + # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table13 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13Enable|0x0|UINT8|0xA000014B + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13SourceIrq|0x0|UINT8|0xA000014C + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13Polarity|0x0|UINT8|0xA000014D + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13TrigerMode|0x0|UINT8|0xA000014E + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13GlobalIrq|0x0|UINT32|0xA000014F + + # Madt Table Initialize settings. + # Defines a flag to Enable/Disable interrupt override setting table14, + # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table14 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14Enable|0x0|UINT8|0xA0000150 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14SourceIrq|0x0|UINT8|0xA0000151 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14Polarity|0x0|UINT8|0xA0000152 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14TrigerMode|0x0|UINT8|0xA0000153 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14GlobalIrq|0x0|UINT32|0xA0000154 + + # Madt Table Initialize settings. + # Defines a flag to Enable/Disable interrupt override setting table15, + # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table15 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15Enable|0x0|UINT8|0xA0000155 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15SourceIrq|0x0|UINT8|0xA0000156 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15Polarity|0x0|UINT8|0xA0000157 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15TrigerMode|0x0|UINT8|0xA0000158 + gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15GlobalIrq|0x0|UINT32|0xA0000159 + + # Madt Table Initialize settings. + # Defines a bunch of Pcds for IO APIC setting: + # IoApicAddress, GlobalInterruptBase, IoApicId, NmiEnable, NmiSource, Polarity and TrigerMode + gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingIoApicAddress|0xFEC00000|UINT32|0xA0000170 + gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingGlobalInterruptBase|0x0|UINT32|0xA0000171 + gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingIoApicId|0x01|UINT8|0xA0000172 + gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingNmiEnable|0x0|UINT8|0xA0000173 + gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingNmiSource|0x0|UINT8|0xA0000174 + gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingPolarity|0x0|UINT8|0xA0000175 + gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingTrigerMode|0x0|UINT8|0xA0000176 + + # Madt Table Initialize settings. + # Defines a bunch of Pcds for Local APIC setting: + # NmiEnabelApicIdMask, AddressOverrideEnable, Polarity, TrigerMode, LocalApicLint, LocalApicAddress and LocalApicAddressOverride + gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingNmiEnabelApicIdMask|0x03|UINT8|0xA0000177 + gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingAddressOverrideEnable|0x00|UINT8|0xA0000178 + gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingPolarity|0x01|UINT8|0xA0000179 + gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingTrigerMode|0x01|UINT8|0xA000017A + gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingLocalApicLint|0x01|UINT8|0xA000017B + gQuarkPlatformTokenSpaceGuid.PcdLocalApicAddressOverride|0x00|UINT64|0xA000017C + + # PCDs for auto provisioning of UEFI SecureBoot. + gQuarkPlatformTokenSpaceGuid.PcdPkX509File |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0xA0000180 + gQuarkPlatformTokenSpaceGuid.PcdKekX509File |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0xA0000181 + gQuarkPlatformTokenSpaceGuid.PcdKekRsa2048File |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0xA0000182 + gQuarkPlatformTokenSpaceGuid.PcdDbX509File |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0xA0000183 + gQuarkPlatformTokenSpaceGuid.PcdDbxX509File |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0xA0000184 + +[PcdsFixedAtBuild, PcdsPatchableInModule] + ## This PCD points to the file name GUID of the BootManagerMenuApp + # Platform can customize the PCD to point to different application for Boot Manager Menu + gQuarkPlatformTokenSpaceGuid.PcdBootManagerMenuFile|{ 0xdc, 0x5b, 0xc2, 0xee, 0xf2, 0x67, 0x95, 0x4d, 0xb1, 0xd5, 0xf8, 0x1b, 0x20, 0x39, 0xd1, 0x1d }|VOID*|0x00000003 + + #BIOS Information (Type 0), please refer spec SMBIOS 2.4, section 3.3.1 ,for following SMBIOS relates comments. + + # String number of the BIOS Vendors Name + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosVendor|"Intel Corp."|VOID*|0xA0000033 + # String number of the BIOS Release Data + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosReleaseDate|"01/01/2014"|VOID*|0xA0000035 + # Segment location of BIOS starting address. + # Note: The size of the runtime BIOS image can be computed by subtracting the Starting Address Segment from 10000h and multiplying the result by 16. + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosStartAddress|0xE000|UINT16|0xA0000036 + #Defines which functions the BIOS supports. PCI, PCMCIA, Flash, etc. See 3.3.1.1. + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosChar|0x03037C099880|UINT64|0xA0000037 + #Defines which functions the BIOS supports. etc.See 3.3.1.2.1. + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosCharEx1|0x03|UINT8|0xA0000038 + #Defines which functions the BIOS supports. etc.See 3.3.1.2.2. + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosCharEx2|0x03|UINT8|0xA0000039 + + # System Information (Type 1), Section 3.3.2 + # System Manufacturer String + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemManufacturer|"Intel Corp."|VOID*|0xA000003A + # System Product String + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemProductName|"QUARK"|VOID*|0xA000003B + # System Version + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemVersion|"1.0"|VOID*|0xA000003C + # System SerialNumber String + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSerialNumber|"Unknown"|VOID*|0xA000003D + # System UUID + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemUuid|{0x23, 0xef, 0xff, 0x13,0x54, 0x86, 0xda, 0x46, 0xa4, 0x7, 0x39, 0xc9, 0x12, 0x2, 0xd3, 0x56}|VOID*|0xA000003E + # Manufacturer String + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSKUNumber|"System SKUNumber"|VOID*|0xA000003F + # System Family String + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemFamily|"X1000"|VOID*|0xA0000040 + + # Base Board (or Module) Information (Type 2), Section 3.3.3 + # Board Manufacturer String + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBoardManufacturer|"Intel Corp."|VOID*|0xA0000041 + # Board Product Name| String + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBoardProductName|"QUARK"|VOID*|0xA0000042 + # Board Version String + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBoardVersion|"FAB-D"|VOID*|0xA0000043 + # Board Serial Number + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBoardSerialNumber|"3"|VOID*|0xA0000044 + # System Enclosure or Chassis(Type 3) Section 3.3.4 + # Chassis Manufacturer String + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisManufacturer|"Chassis Manufacturer"|VOID*|0xA0000045 + # ChassisVersion + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisVersion|"Chassis Version"|VOID*|0xA0000046 + # Chassis SerialNumber String + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisSerialNumber|"Chassis Serial Number"|VOID*|0xA0000047 + # Chassis Asset Tag + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisAssetTag|"Chassis Asset Tag"|VOID*|0xA0000051 + # Chassis Type + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisType|0x00000003|UINT8|0xA0000048 + # Identifies the state of the enclosure when it was last booted. See 3.3.4.2 for definitions. + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisBootupState|0x03|UINT8|0xA0000049 + # Identifies the state of the enclosures power supply (or supplies) when last booted. See 3.3.4.2 for definitions. + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisPowerSupplyState|0x03|UINT8|0xA000004A + # Identifies the enclosures physical security status when last booted. See 3.3.4.3 for definitions. + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisSecurityState|0x01|UINT8|0xA000004B + # Contains OEM- or BIOS vendor-specific information. + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisOemDefined|0x0|UINT32|0xA000004C + # The height of the enclosure, in 'U's. A U is a standard unit of measure for the height of a rack or rack-mountable component + # and is equal to 1.75 inches or 4.445 cm. A value of 00h indicates that the enclosure height is unspecified. + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisHeight|0x0|UINT8|0xA000004D + # Identifies the number of power cords associated with the enclosure or chassis. A value of 00h indicates that the number is unspecified. + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisNumberPowerCords|0x0|UINT8|0xA000004E + # Identifies the number of Contained Element records that follow, in the range 0 to 255. + # Each Contained Element group comprises m bytes, as specified by the Contained Element Record Length field that follows. + # If no Contained Elements are included, this field is set to 0. + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisElementCount|0x0|UINT8|0xA000004F + # Identifies the byte length of each Contained Element record that follow, in the range 0 to 255. + # If no Contained Elements are included, this field is set to 0. For v2.3.2 and later of this specification, + # this field is set to at least 03h when Contained Elements are specified. + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisElementRecordLength|0x0|UINT8|0xA0000050 + + # Defines the number of connectors existent on the board + # The valid range is between 0 and 16 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSConnectorNumber|16|UINT8|0xA0000060 + + # Defines the designator of port1 internal connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort1InternalConnectorDesignator|"X14 "|VOID*|0xA0000061 + # Defines the designator of port1 external connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort1ExternalConnectorDesignator|"Keyboard"|VOID*|0xA0000062 + # Defines the type of port1 internal connector + # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort1InternalConnectorType|0x0F|UINT8|0xA0000063 + # Defines the type of port1 external connector + # The valid range is between 0 to 0xFF, and 0x0F here means EfiPortConnectorTypePS2 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort1ExternalConnectorType|0x0F|UINT8|0xA0000064 + # Defines the type of port1 + # The valid range is between 0 to 0xFF, and 0x0D here means EfiPortTypeKeyboard + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort1Type|0x0D|UINT8|0xA0000065 + + # Defines the designator of port2 internal connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort2InternalConnectorDesignator|"X15 "|VOID*|0xA0000066 + # Defines the designator of port2 external connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort2ExternalConnectorDesignator|"Mouse"|VOID*|0xA0000067 + # Defines the type of port2 internal connector + # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort2InternalConnectorType|0x0F|UINT8|0xA0000068 + # Defines the type of port2 external connector + # The valid range is between 0 to 0xFF, and 0x0F here means EfiPortConnectorTypePS2 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort2ExternalConnectorType|0x0F|UINT8|0xA0000069 + # Defines the type of port2 + # The valid range is between 0 to 0xFF, and 0x0E here means EfiPortTypeMouse + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort2Type|0x0E|UINT8|0xA000006A + + # Defines the designator of port3 internal connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort3InternalConnectorDesignator|"X16 "|VOID*|0xA000006B + # Defines the designator of port3 external connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort3ExternalConnectorDesignator|"COM 1"|VOID*|0xA000006C + # Defines the type of port3 internal connector + # The valid range is between 0 to 0xFF, and 0xFF here means EfiPortConnectorTypeOther + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort3InternalConnectorType|0xFF|UINT8|0xA000006D + # Defines the type of port3 external connector + # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort3ExternalConnectorType|0x0|UINT8|0xA000006E + # Defines the type of port3 + # The valid range is between 0 to 0xFF, and 0x09 here means EfiPortTypeSerial16550ACompatible + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort3Type|0x09|UINT8|0xA000006F + + # Defines the designator of port4 internal connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort4InternalConnectorDesignator|"X17 "|VOID*|0xA0000070 + # Defines the designator of port4 external connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort4ExternalConnectorDesignator|"COM 2"|VOID*|0xA0000071 + # Defines the type of port4 internal connector + # The valid range is between 0 to 0xFF, and 0xFF here means EfiPortConnectorTypeOther + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort4InternalConnectorType|0xFF|UINT8|0xA0000072 + # Defines the type of port4 external connector + # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort4ExternalConnectorType|0x0|UINT8|0xA0000073 + # Defines the type of port4 + # The valid range is between 0 to 0xFF, and 0x09 here means EfiPortTypeSerial16550ACompatible + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort4Type|0x09|UINT8|0xA0000074 + + # Defines the designator of port5 internal connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort5InternalConnectorDesignator|"X18 "|VOID*|0xA0000075 + # Defines the designator of port5 external connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort5ExternalConnectorDesignator|"COM 3"|VOID*|0xA0000076 + # Defines the type of port5 internal connector + # The valid range is between 0 to 0xFF, and 0xFF here means EfiPortConnectorTypeOther + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort5InternalConnectorType|0xFF|UINT8|0xA0000077 + # Defines the type of port5 external connector + # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort5ExternalConnectorType|0x0|UINT8|0xA0000078 + # Defines the type of port5 + # The valid range is between 0 to 0xFF, and 0x09 here means EfiPortTypeSerial16550ACompatible + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort5Type|0x09|UINT8|0xA0000079 + + # Defines the designator of port6 internal connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort6InternalConnectorDesignator|"X19 "|VOID*|0xA000007A + # Defines the designator of port6 external connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort6ExternalConnectorDesignator|"COM 4"|VOID*|0xA000007B + # Defines the type of port6 internal connector + # The valid range is between 0 to 0xFF, and 0xFF here means EfiPortConnectorTypeOther + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort6InternalConnectorType|0xFF|UINT8|0xA000007C + # Defines the type of port6 external connector + # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort6ExternalConnectorType|0x0|UINT8|0xA000007D + # Defines the type of port6 + # The valid range is between 0 to 0xFF, and 0x09 here means EfiPortTypeSerial16550ACompatible + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort6Type|0x09|UINT8|0xA000007E + + # Defines the designator of port7 internal connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort7InternalConnectorDesignator|"J4A2"|VOID*|0xA000007F + # Defines the designator of port7 external connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort7ExternalConnectorDesignator|"LPT 1"|VOID*|0xA0000080 + # Defines the type of port7 internal connector + # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort7InternalConnectorType|0x0|UINT8|0xA0000081 + # Defines the type of port7 external connector + # The valid range is between 0 to 0xFF, and 0x12 here means EfiPortConnectorTypeDB25Male + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort7ExternalConnectorType|0x04|UINT8|0xA0000082 + # Defines the type of port7 + # The valid range is between 0 to 0xFF, and 0x10 here means EfiPortTypeEcpEpp + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort7Type|0x05|UINT8|0xA0000083 + + # Defines the designator of port8 internal connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort8InternalConnectorDesignator|"X20 "|VOID*|0xA0000084 + # Defines the designator of port8 external connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort8ExternalConnectorDesignator|"USB1"|VOID*|0xA0000085 + # Defines the type of port8 internal connector + # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort8InternalConnectorType|0x0|UINT8|0xA0000086 + # Defines the type of port8 external connector + # The valid range is between 0 to 0xFF, and 0x12 here means EfiPortConnectorTypeUsb + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort8ExternalConnectorType|0x12|UINT8|0xA0000087 + # Defines the type of port8 + # The valid range is between 0 to 0xFF, and 0x10 here means EfiPortTypeUsb + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort8Type|0x10|UINT8|0xA0000088 + + # Defines the designator of port9 internal connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort9InternalConnectorDesignator|"X21 "|VOID*|0xA0000089 + # Defines the designator of port9 external connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort9ExternalConnectorDesignator|"USB2"|VOID*|0xA000008A + # Defines the type of port9 internal connector + # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort9InternalConnectorType|0x0|UINT8|0xA000008B + # Defines the type of port9 external connector + # The valid range is between 0 to 0xFF, and 0x12 here means EfiPortConnectorTypeUsb + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort9ExternalConnectorType|0x12|UINT8|0xA000008C + # Defines the type of port9 + # The valid range is between 0 to 0xFF, and 0x10 here means EfiPortTypeUsb + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort9Type|0x10|UINT8|0xA000008D + + # Defines the designator of port10 internal connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort10InternalConnectorDesignator|"X22 "|VOID*|0xA000008E + # Defines the designator of port10 external connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort10ExternalConnectorDesignator|"USB3"|VOID*|0xA000008F + # Defines the type of port10 internal connector + # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort10InternalConnectorType|0x0|UINT8|0xA0000090 + # Defines the type of port10 external connector + # The valid range is between 0 to 0xFF, and 0x12 here means EfiPortConnectorTypeUsb + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort10ExternalConnectorType|0x12|UINT8|0xA0000091 + # Defines the type of port10 + # The valid range is between 0 to 0xFF, and 0x10 here means EfiPortTypeUsb + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort10Type|0x10|UINT8|0xA0000092 + + # Defines the designator of port11 internal connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort11InternalConnectorDesignator|"X23 "|VOID*|0xA0000093 + # Defines the designator of port11 external connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort11ExternalConnectorDesignator|"USB4"|VOID*|0xA0000094 + # Defines the type of port11 internal connector + # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort11InternalConnectorType|0x0|UINT8|0xA0000095 + # Defines the type of port11 external connector + # The valid range is between 0 to 0xFF, and 0x12 here means EfiPortConnectorTypeUsb + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort11ExternalConnectorType|0x12|UINT8|0xA0000096 + # Defines the type of port11 + # The valid range is between 0 to 0xFF, and 0x10 here means EfiPortTypeUsb + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort11Type|0x10|UINT8|0xA0000097 + + # Defines the designator of port12 internal connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort12InternalConnectorDesignator|"X28 "|VOID*|0xA0000098 + # Defines the designator of port12 external connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort12ExternalConnectorDesignator|"RJ-45 Type"|VOID*|0xA0000099 + # Defines the type of port12 internal connector + # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort12InternalConnectorType|0x0|UINT8|0xA000009A + # Defines the type of port12 external connector + # The valid range is between 0 to 0xFF, and 0x0B here means EfiPortConnectorTypeRJ45 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort12ExternalConnectorType|0x0B|UINT8|0xA000009B + # Defines the type of port12 + # The valid range is between 0 to 0xFF, and 0x1F here means EfiPortTypeNetworkPort + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort12Type|0x1F|UINT8|0xA000009C + + # Defines the designator of port13 internal connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort13InternalConnectorDesignator|"J1G1"|VOID*|0xA000009D + # Defines the designator of port13 external connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort13ExternalConnectorDesignator|"Floppy"|VOID*|0xA000009E + # Defines the type of port13 internal connector + # The valid range is between 0 to 0xFF, and 0x16 here means EfiPortConnectorTypeOnboardFloppy + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort13InternalConnectorType|0x17|UINT8|0xA000009F + # Defines the type of port13 external connector + # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort13ExternalConnectorType|0x0|UINT8|0xA00000A0 + # Defines the type of port13 + # The valid range is between 0 to 0xFF, and 0xFF here means EfiPortTypeOther + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort13Type|0xFF|UINT8|0xA00000A1 + + # Defines the designator of port14 internal connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort14InternalConnectorDesignator|"J2H2"|VOID*|0xA00000A2 + # Defines the designator of port14 external connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort14ExternalConnectorDesignator|"IDE"|VOID*|0xA00000A3 + # Defines the type of port14 internal connector + # The valid range is between 0 to 0xFF, and 0x16 here means EfiPortConnectorTypeOnboardIde + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort14InternalConnectorType|0x16|UINT8|0xA00000A4 + # Defines the type of port14 external connector + # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort14ExternalConnectorType|0x0|UINT8|0xA00000A5 + # Defines the type of port14 + # The valid range is between 0 to 0xFF, and 0xFF here means EfiPortTypeOther + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort14Type|0xFF|UINT8|0xA00000A6 + + # Defines the designator of port15 internal connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort15InternalConnectorDesignator|"X29 "|VOID*|0xA00000A7 + # Defines the designator of port15 external connector + + # Defines the type of port15 internal connector + # The valid range is between 0 to 0xFF, and 0x16 here means EfiPortConnectorTypeOnboardIde + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort15InternalConnectorType|0x16|UINT8|0xA00000A9 + # Defines the type of port15 external connector + # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort15ExternalConnectorType|0x0|UINT8|0xA00000AA + # Defines the type of port15 + # The valid range is between 0 to 0xFF, and 0xFF here means EfiPortTypeOther + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort15Type|0xFF|UINT8|0xA00000AB + + # Defines the designator of port16 internal connector + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort16InternalConnectorDesignator|"X30 "|VOID*|0xA00000AC + # Defines the designator of port16 external connector + + # Defines the type of port16 internal connector + # The valid range is between 0 to 0xFF, and 0x16 here means EfiPortConnectorTypeOnboardIde + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort16InternalConnectorType|0x16|UINT8|0xA00000AE + # Defines the type of port16 external connector + # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort16ExternalConnectorType|0x0|UINT8|0xA00000AF + # Defines the type of port16 + # The valid range is between 0 to 0xFF, and 0xFF here means EfiPortTypeOther + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort16Type|0xFF|UINT8|0xA00000B0 + + # Defines the number of the slots existent on board + # The valid range is between 0 and 14 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlotNumber|5|UINT8|0xA000023F + # Defines the designation of system slot1 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Designation|"PCI SLOT1"|VOID*|0xA0000240 + # Defines the type of system slot1 + # The valid range is between 0x01 to 0xA5, and 0x06 here means EfiSlotTypePci + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Type|0x6|UINT8|0xA0000241 + # Defines the data bus width of system slot1 + # The valid range is between 0x01 to 0x07, and 0x05 here means EfiSlotDataBusWidth32Bit + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1DataBusWidth|0x5|UINT8|0xA0000242 + # Defines the usage of system slot1 + # The valid range is between 0x01 to 0x04, and 0x03 here means EfiSlotUsageAvailable + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Usage|0x3|UINT8|0xA0000243 + # Defines the length of system slot1 + # The valid range is between 0x01 to 0x04, and 0x04 here means EfiSlotLengthLong + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Length|0x4|UINT8|0xA0000244 + # Defines the ID of system slot1, a number of UINT16 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Id|0x01|UINT16|0xA0000245 + # Defines the characteristics of system slot1 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS + # typedef struct { + # UINT32 CharacteristicsUnknown :1; + # UINT32 Provides50Volts :1; + # UINT32 Provides33Volts :1; + # UINT32 SharedSlot :1; + # UINT32 PcCard16Supported :1; + # UINT32 CardBusSupported :1; + # UINT32 ZoomVideoSupported :1; + # UINT32 ModemRingResumeSupported:1; + # UINT32 PmeSignalSupported :1; + # UINT32 HotPlugDevicesSupported :1; + # UINT32 SmbusSignalSupported :1; + # UINT32 Reserved :21; + # } EFI_MISC_SLOT_CHARACTERISTICS; + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Characteristics|0x504|UINT32|0xA0000246 + + # Defines the designation of system slot2 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Designation|"PCI-Express 1"|VOID*|0xA0000247 + + # Defines the type of system slot2 + # The valid range is between 0x01 to 0xA5, and 0x06 here means EfiSlotTypePci + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Type|0xA5|UINT8|0xA0000248 + # Defines the data bus width of system slot2 + # The valid range is between 0x01 to 0x07, and 0x05 here means EfiSlotDataBusWidth32Bit + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2DataBusWidth|0x5|UINT8|0xA0000249 + # Defines the usage of system slot2 + # The valid range is between 0x01 to 0x04, and 0x03 here means EfiSlotUsageAvailable + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Usage|0x3|UINT8|0xA000024A + # Defines the length of system slot2 + # The valid range is between 0x01 to 0x04, and 0x04 here means EfiSlotLengthLong + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Length|0x4|UINT8|0xA000024B + # Defines the ID of system slot2, a number of UINT16 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Id|0x02|UINT16|0xA000024C + # Defines the characteristics of system slot2 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Characteristics|0x504|UINT32|0xA000024D + + # Defines the designation of system slot3 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Designation|"PCI-Express 2"|VOID*|0xA000024E + # Defines the type of system slot3 + # The valid range is between 0x01 to 0xA5, and 0x06 here means EfiSlotTypePci + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Type|0xA5|UINT8|0xA000024F + # Defines the data bus width of system slot3 + # The valid range is between 0x01 to 0x07, and 0x05 here means EfiSlotDataBusWidth32Bit + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3DataBusWidth|0x5|UINT8|0xA0000250 + # Defines the usage of system slot3 + # The valid range is between 0x01 to 0x04, and 0x03 here means EfiSlotUsageAvailable + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Usage|0x3|UINT8|0xA0000251 + # Defines the length of system slot3 + # The valid range is between 0x01 to 0x04, and 0x04 here means EfiSlotLengthLong + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Length|0x4|UINT8|0xA0000252 + # Defines the ID of system slot3, a number of UINT16 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Id|0x03|UINT16|0xA0000253 + # Defines the characteristics of system slot3 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Characteristics|0x504|UINT32|0xA000254 + + # Defines the designation of system slot4 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Designation|"PCI-Express 3"|VOID*|0xA0000255 + # Defines the type of system slot4 + # The valid range is between 0x01 to 0xA5, and 0xA5 here means EfiSlotTypePciExpress + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Type|0xA5|UINT8|0xA0000256 + # Defines the data bus width of system slot4 + # The valid range is between 0x01 to 0x07, and 0x05 here means EfiSlotDataBusWidth32Bit + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4DataBusWidth|0x5|UINT8|0xA0000257 + # Defines the usage of system slot4 + # The valid range is between 0x01 to 0x04, and 0x03 here means EfiSlotUsageAvailable + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Usage|0x3|UINT8|0xA0000258 + # Defines the length of system slot4 + # The valid range is between 0x01 to 0x04, and 0x04 here means EfiSlotLengthLong + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Length|0x4|UINT8|0xA0000259 + # Defines the ID of system slot4, a number of UINT16 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Id|0x04|UINT16|0xA0000260 + # Defines the characteristics of system slot4 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Characteristics|0x504|UINT32|0xA0000261 + + # Defines the designation of system slot5 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Designation|"Mini PCI-E"|VOID*|0xA0000262 + # Defines the type of system slot5 + # The valid range is between 0x01 to 0xA5, and 0xA5 here means EfiSlotTypePciExpress + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Type|0xA5|UINT8|0xA0000263 + # Defines the data bus width of system slot5 + # The valid range is between 0x01 to 0x07, and 0x05 here means EfiSlotDataBusWidth32Bit + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5DataBusWidth|0x5|UINT8|0xA0000264 + # Defines the usage of system slot5 + # The valid range is between 0x01 to 0x04, and 0x03 here means EfiSlotUsageAvailable + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Usage|0x3|UINT8|0xA0000265 + # Defines the length of system slot5 + # The valid range is between 0x01 to 0x04, and 0x04 here means EfiSlotLengthLong + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Length|0x4|UINT8|0xA0000266 + # Defines the ID of system slot5, a number of UINT16 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Id|0x05|UINT16|0xA0000267 + # Defines the characteristics of system slot5 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Characteristics|0x504|UINT32|0xA0000268 + + # Defines the designation of system slot6 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Designation|"NONE"|VOID*|0xA0000269 + # Defines the type of system slot6 + # The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Type|0x2|UINT8|0xA000026A + # Defines the data bus width of system slot6 + # The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6DataBusWidth|0x2|UINT8|0xA000026B + # Defines the usage of system slot6 + # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Usage|0x2|UINT8|0xA000026C + # Defines the length of system slot6 + # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Length|0x2|UINT8|0xA000026D + # Defines the ID of system slot6, a number of UINT16 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Id|0x0|UINT16|0xA000026E + # Defines the characteristics of system slot6 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Characteristics|0x0|UINT32|0xA000026F + + # Defines the designation of system slot7 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Designation|"NONE"|VOID*|0xA0000270 + # Defines the type of system slot7 + # The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Type|0x2|UINT8|0xA0000271 + # Defines the data bus width of system slot7 + # The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7DataBusWidth|0x2|UINT8|0xA0000272 + # Defines the usage of system slot7 + # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Usage|0x2|UINT8|0xA0000273 + # Defines the length of system slot7 + # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Length|0x2|UINT8|0xA0000274 + # Defines the ID of system slot7, a number of UINT16 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Id|0x0|UINT16|0xA0000275 + # Defines the characteristics of system slot7 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Characteristics|0x0|UINT32|0xA0000276 + + # Defines the designation of system slot8 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Designation|"NONE"|VOID*|0xA0000277 + # Defines the type of system slot8 + # The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Type|0x2|UINT8|0xA0000278 + # Defines the data bus width of system slot8 + # The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8DataBusWidth|0x2|UINT8|0xA0000279 + # Defines the usage of system slot8 + # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Usage|0x2|UINT8|0xA000027A + # Defines the length of system slot8 + # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Length|0x2|UINT8|0xA000027B + # Defines the ID of system slot8, a number of UINT16 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Id|0x0|UINT16|0xA000027C + # Defines the characteristics of system slot8 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Characteristics|0x0|UINT32|0xA000027D + + # Defines the designation of system slot9 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Designation|"NONE"|VOID*|0xA000027E + # Defines the type of system slot9 + # The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Type|0x2|UINT8|0xA000027F + # Defines the data bus width of system slot9 + # The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9DataBusWidth|0x2|UINT8|0xA0000280 + # Defines the usage of system slot9 + # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Usage|0x2|UINT8|0xA0000281 + # Defines the length of system slot9 + # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Length|0x2|UINT8|0xA0000282 + # Defines the ID of system slot9, a number of UINT16 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Id|0x0|UINT16|0xA0000283 + # Defines the characteristics of system slot9 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Characteristics|0x0|UINT32|0xA0000284 + + # Defines the designation of system slot10 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Designation|"None"|VOID*|0xA0000285 + # Defines the type of system slot10 + # The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Type|0x2|UINT8|0xA0000286 + # Defines the data bus width of system slot10 + # The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10DataBusWidth|0x2|UINT8|0xA0000287 + # Defines the usage of system slot10 + # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Usage|0x2|UINT8|0xA0000288 + # Defines the length of system slot10 + # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Length|0x2|UINT8|0xA0000289 + # Defines the ID of system slot10, a number of UINT16 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Id|0x0|UINT16|0xA000028A + # Defines the characteristics of system slot10 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Characteristics|0x0|UINT32|0xA000028B + + # Defines the designation of system slot11 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Designation|"None"|VOID*|0xA000028C + # Defines the type of system slot11 + # The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Type|0x2|UINT8|0xA000028D + # Defines the data bus width of system slot11 + # The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11DataBusWidth|0x2|UINT8|0xA000028E + # Defines the usage of system slot11 + # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Usage|0x2|UINT8|0xA000028F + # Defines the length of system slot11 + # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Length|0x2|UINT8|0xA0000290 + # Defines the ID of system slot11, a number of UINT16 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Id|0x0|UINT16|0xA00000EE + # Defines the characteristics of system slot11 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Characteristics|0x0|UINT32|0xA0000291 + + # Defines the designation of system slot12 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Designation|"None"|VOID*|0xA0000292 + # Defines the type of system slot12 + # The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Type|0x2|UINT8|0xA0000293 + # Defines the data bus width of system slot12 + # The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12DataBusWidth|0x2|UINT8|0xA0000294 + # Defines the usage of system slot12 + # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Usage|0x2|UINT8|0xA0000295 + # Defines the length of system slot12 + # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Length|0x2|UINT8|0xA0000296 + # Defines the ID of system slot12, a number of UINT16 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Id|0x0|UINT16|0xA0000297 + # Defines the characteristics of system slot12 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Characteristics|0x0|UINT32|0xA0000298 + + # Defines the designation of system slot13 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Designation|"None"|VOID*|0xA0000299 + # Defines the type of system slot13 + # The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Type|0x2|UINT8|0xA000029A + # Defines the data bus width of system slot13 + # The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13DataBusWidth|0x2|UINT8|0xA000029B + # Defines the usage of system slot13 + # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Usage|0x2|UINT8|0xA000029C + # Defines the length of system slot13 + # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Length|0x2|UINT8|0xA000029D + # Defines the ID of system slot13, a number of UINT16 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Id|0x0|UINT16|0xA000029E + # Defines the characteristics of system slot13 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Characteristics|0x0|UINT32|0xA000029F + + # Defines the designation of system slot14 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Designation|"None"|VOID*|0xA00002A0 + # Defines the type of system slot14 + # The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Type|0x2|UINT8|0xA00002A1 + # Defines the data bus width of system slot14 + # The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14DataBusWidth|0x2|UINT8|0xA00002A2 + # Defines the usage of system slot14 + # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Usage|0x2|UINT8|0xA00002A3 + # Defines the length of system slot14 + # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Length|0x2|UINT8|0xA00002A4 + # Defines the ID of system slot14, a number of UINT16 + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Id|0x0|UINT16|0xA00002A5 + # Defines the characteristics of system slot14 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS + gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Characteristics|0x0|UINT32|0xA00002A6 + + gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadBase|0xFFC00400|UINT32|0xA00002A7 + gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadSize|0x000F0000|UINT32|0xA00002A8 + gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainBase|0xFFD00400|UINT32|0xA00002A9 + gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainSize|0x000D0000|UINT32|0xA00002AA + gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoveryBase|0xFFEC0400|UINT32|0xA00002AB + gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoverySize|0x0003F000|UINT32|0xA00002AC + +[PcdsDynamic, PcdsDynamicEx] + ## Provides the ability to enable the Fast Boot feature of the BIOS. This + # enables the system to boot faster but may only enumerate the hardware + # that is required to boot the system.
+ # + # @Prompt Fast Boot Support + # + gQuarkPlatformTokenSpaceGuid.PcdEnableFastBoot|FALSE|BOOLEAN|0xB000004 + + ## Determines if the user is physically present. This information is collected and shared + # with all other modules using a dynamic PCD.
+ # + # @Prompt The User is Physically Present + # + gQuarkPlatformTokenSpaceGuid.PcdUserIsPhysicallyPresent|FALSE|BOOLEAN|0xB000006 + + ## The Quark SOC X1000 Based Platform Type.
+ # 0x0000 - Unknown
+ # 0x0001 - Quark Emulation
+ # 0x0002 - ClantonPeak SVP
+ # 0x0003 - KipsBay
+ # 0x0004 - CrossHill
+ # 0x0005 - ClantonHill
+ # 0x0006 - Galileo Gen 1
+ # 0x0007 - Reserved
+ # 0x0008 - Galileo Gen 2
+ # + # @Prompt The Quark SOC X1000 Based Platform Type + # + gQuarkPlatformTokenSpaceGuid.PcdPlatformType|0x0008|UINT16|0xB000007 + + ## The Quark SOC X1000 Based Platform Type Name.
+ # + # @Prompt The Quark SOC X1000 Based Platform Type Name + # + gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|L"GalileoGen2"|VOID*|0xB000008 + + ## The size, in bytes, of the SPI FLASH part attached to Quark SOC X1000 + # + # @Prompt The SPI FALSH Part Size + # + gQuarkPlatformTokenSpaceGuid.PcdSpiFlashDeviceSize|0|UINT32|0xB000009 diff --git a/Platform/Intel/QuarkPlatformPkg/Readme.md b/Platform/Intel/QuarkPlatformPkg/Readme.md new file mode 100644 index 0000000000..126de6937b --- /dev/null +++ b/Platform/Intel/QuarkPlatformPkg/Readme.md @@ -0,0 +1,685 @@ +# **EDK II firmware for Intel(R) Quark SoC X1000 based platforms** + +## **Features** +* UEFI firmware image with ability to enable/disable major features such as + - Logging + - Source level debug using [Intel(R) UEFI Development Kit Debugger Tool]( + https://firmware.intel.com/develop/intel-uefi-tools-and-utilities/intel-uefi-development-kit-debugger-tool) + - Boot Performance Measurements + - UEFI Secure Boot with Physical Presence + - TCG Measured Boot using TPM 1.2 hardware devices on I2C bus +* Minimal firmware image for initial power-on and debug +* UEFI Shell built into FLASH image +* UEFI Linux operating system boot support from Micro SD FLASH +* Hardware Support + - [Intel(R) Quark SoC X1000 CPU]( + http://www.intel.com/content/www/us/en/embedded/products/quark/quark-x1000-datasheet.html) + - [Intel(R) Galileo Development Board]( + http://www.intel.com/content/www/us/en/embedded/products/galileo/galileo-g1-datasheet.html) + - [Intel(R) Galileo Gen 2 Development Board]( + http://www.intel.com/content/www/us/en/embedded/products/galileo/galileo-overview.html) + - HPET Timer + - Real Time Clock +* Major I/O Subsystems + - PCI including support for Mini PCI Express Cards + - USB using EHCI and OHCI host controllers + - Micro SD FLASH with FAT file system support + - Serial UART up to 921600 baud for console, logging, and debug +* ACPI Tables with ACPI S3 sleep state support +* SMBIOS Tables + +## **Windows Build Instructions** + +### Pre-requisites + +* GIT client: Available from https://git-scm.com/downloads +* Microsoft Visual Studio. + - Visual Studio 2015 recommended and is used in the examples below. +* Microsoft Windows Driver Development Kit 3790.1830 + - http://download.microsoft.com/download/9/0/f/90f019ac-8243-48d3-91cf-81fc4093ecfd/1830_usa_ddk.iso + - Mount ISO image + - Right click on ```x86\kitsetup.exe``` & choose **Run as administrator** + - Install to C:\WINDDK\3790.1830 + - Uncheck all Component Groups + - Expand Build Environment Component + - Check Windows Driver Development Kit 16-bit Additional Build Tools + - Install +* ASL compiler: Available from http://www.acpica.org + - Install into ```C:\ASL``` to match default tools_def.txt configuration. +* Python 2.7: Available from http://www.python.org + +Create a new directory for an EDK II WORKSPACE. + +The code block below shows the GIT clone operations required to pull the EDK II +source tree and the edk2-non-osi repository that provides a binary file for the +Quark Remote Management Unit (RMU). + +Next it sets environment variables that must be set before running +```edksetup.bat```. Since content is being pulled from multiple repositories, +the EDK II [Multiple Workspace]( +https://github.com/tianocore/tianocore.github.io/wiki/Multiple_Workspace) +feature is used. + +Next, the EDK II BaseTools required to build firmware images are built. + +Next, the ```edksetup.bat``` file is run to complete the initialization of an +EDK II build environment. Two example build commands are shown. The first one +in ```QuarkPlatformPlg/Quark.dsc``` builds a full UEFI firmware image that is +able to boot the built-in UEFI Shell and Linux from a micro SD FLASH card. The +second one in ```QuarkPlatformPkg/QuarkMin.dsc``` builds a minimal firmware +image that is useful for initial power-on and debug of new features. + +```cmd +git clone https://github.com/tianocore/edk2.git +git clone https://github.com/tianocore/edk2-non-osi.git + +set PYTHON_HOME=c:\Python27 +set WORKSPACE=%CD% +set PACKAGES_PATH=%WORKSPACE%\edk2;%WORKSPACE%\edk2-non-osi\Silicon\Intel +set EDK_TOOLS_PATH=%WORKSPACE%\edk2\BaseTools +cd %WORKSPACE%\edk2 + +BaseTools\toolsetup.bat Rebuild + +edksetup.bat Rebuild + +build -a IA32 -t VS2015x86 -p QuarkPlatformPkg/Quark.dsc +build -a IA32 -t VS2015x86 -p QuarkPlatformPkg/QuarkMin.dsc +``` + +## **Linux Build Instructions** + +### Pre-requisites + +* GIT client +* GCC 4.9 compiler +* ASL compiler: Available from http://www.acpica.org. +* Python 2.7 + +Create a new directory for an EDK II WORKSPACE. + +The code block below shows the GIT clone operations required to pull the EDK II +source tree and the edk2-non-osi repository that provides a binary file for the +Quark Remote Management Unit (RMU). + +Next it sets environment variables that must be set before running +```edksetup.bat```. Since content is being pulled from multiple repositories, +the EDK II [Multiple Workspace]( +https://github.com/tianocore/tianocore.github.io/wiki/Multiple_Workspace) +feature is used. + +Next, the EDK II BaseTools required to build firmware images are built. + +Next, the ```edksetup.sh``` file is run to complete the initialization of an +EDK II build environment. Two example build commands are shown. The first one +in ```QuarkPlatformPlg/Quark.dsc``` builds a full UEFI firmware image that is +able to boot the built-in UEFI Shell and Linux from a micro SD FLASH card. The +second one in ```QuarkPlatformPkg/QuarkMin.dsc``` builds a minimal firmware +image that is useful for initial power-on and debug of new features. + +```sh +git clone https://github.com/tianocore/edk2.git +git clone https://github.com/tianocore/edk2-non-osi.git + +export WORKSPACE=$PWD +export PACKAGES_PATH=$WORKSPACE/edk2:$WORKSPACE/edk2-non-osi/Silicon/Intel +export EDK_TOOLS_PATH=$WORKSPACE/edk2/BaseTools +cd $WORKSPACE/edk2 + +make -C BaseTools + +. edksetup.sh BaseTools + +build -a IA32 -t GCC49 -p QuarkPlatformPkg/Quark.dsc +build -a IA32 -t GCC49 -p QuarkPlatformPkg/QuarkMin.dsc +``` + +## **Build Features** + +The table below contains a summary of the build flags to enable or disable +features on the build command line using ```-D``` flags. + +| **Define Name** | **Default Value** | **Supported Values** | +| -------------------------- | ----------------- | -------------------- | +| ```GALILEO``` | GEN2 | GEN1, GEN2 | +| ```LOGGING``` | TRUE | TRUE, FALSE | +| ```SOURCE_DEBUG_ENABLE``` | FALSE | TRUE, FALSE | +| ```PERFORMANCE_ENABLE``` | FALSE | TRUE, FALSE | +| ```SECURE_BOOT_ENABLE``` | FALSE | TRUE, FALSE | +| ```MEASURED_BOOT_ENABLE``` | FALSE | TRUE, FALSE | +| ```TPM_12_HARDWARE``` | NONE | NONE, LPC, ATMEL_I2C, INFINEON_I2C | +| ```CAPSULE_ENABLE``` | FALSE | TRUE, FALSE | +| ```RECOVERY_ENABLE``` | FALSE | TRUE, FALSE | + +* ```GALILEO``` - Used to specify the type of Intel(R) Galileo board type. The + default is ```GEN2``` for the [Intel(R) Galileo Gen 2 Development Board]( + http://www.intel.com/content/www/us/en/embedded/products/galileo/galileo-overview.html). + The other supported value is ```GEN1``` for the [Intel(R) Galileo Development Board]( + http://www.intel.com/content/www/us/en/embedded/products/galileo/galileo-g1-datasheet.html). + Add ```-D GALILEO=GEN1``` to the build command for [Intel(R) Galileo Development Board]( + http://www.intel.com/content/www/us/en/embedded/products/galileo/galileo-g1-datasheet.html). + +* ```LOGGING``` - Used to enable/disable logging messages from DEBUG() macros to + a serial UART. The default is TRUE for enabled when the BUILDTARGET is DEBUG + (```-b DEBUG```). The default is FALSE for disabled when the BUILDTARGET is + not DEBUG (e.g. ```-b RELEASE```). Add ```-D LOGGING``` to the build command + to force logging enabled. Add ```-D LOGGING=FALSE``` to force logging + disabled. + +* ```SOURCE_DEBUG_ENABLE``` - Used to enable/disable source level debug using the + [Intel(R) UEFI Development Kit Debugger Tool]( + https://firmware.intel.com/develop/intel-uefi-tools-and-utilities/intel-uefi-development-kit-debugger-tool). + The default is FALSE for disabled. Add ```-D SOURCE_DEBUG_ENABLE``` to the + build command line to enable source level debug. + +* ```PERFORMANCE_ENABLE``` - Used to enable/disable boot performance measurement. + The default is FALSE for disabled. Add ```-D PERFORMANCE_ENABLE``` to the + build command line to enable boot performance measurement. When this feature + is enabled, both ```LOGGING``` and ```SOURCE_DEBUG_ENABLE``` are automatically + disabled so there is not boot time overhead from the serial UART for logging + messages or the debug agent. + +* ```SECURE_BOOT_ENABLE``` - Used to enable/disable UEFI Secure Boot features. + The default is FALSE for disabled. Add ```-D SECURE_BOOT_ENABLE``` to the + build command line to enable UEFI Secure Boot features. + +* ```MEASURED_BOOT_ENABLE``` - Used to enable/disable measurement of firmware + code and data into a TPM 1.2 hardware device. The default is FALSE for + disabled. Add ```-D MEASURED_BOOT_ENABLE``` to the build command line to + enable UEFI Secure Boot features. + +* ```TPM_12_HARDWARE``` - Used to specify the type of TPM 1.2 hardware device + that is connected to the Galileo board. This define is valid if the measure + boot feature is enabled using ```-D MEASURED_BOOT_ENABLE```. The default is + NONE for no TPM 1.2 hardware device connected. Add ```-D TPM_12_HARDWARE=LPC``` + for a TPM hardware device attached to an LPC bus (not supported on on Intel(R) + Quark SoC X1000). Add ```-D TPM_12_HARDWARE=ATMEL_I2C``` for an + [Atmel AT97SC3204T](http://www.atmel.com/devices/AT97SC3204T.aspx) or + [Atmel AT97SC3205T](http://www.atmel.com/images/atmel-8883s-tpm-at97sc3205t-datasheet-summary.pdf) + attached to the I2C bus of the Galileo Arduino header. Add + ```-D TPM_12_HARDWARE=INFINION_I2C``` for an [Infineon SLB9645]( + http://www.infineon.com/dgdl/Infineon-TPM+SLB+9645-DS-v01_00-EN.pdf?fileId=5546d4625185e0e201518b83d0c63d7c) + attached to the I2C bus of the Galileo Arduino header. The ATMEL_I2C setting + has been tested with the [CryptoShield](https://www.sparkfun.com/products/13183) + available from [SparkFun](https://www.sparkfun.com/). + +* ```CAPSULE_ENABLE``` - Used to enable/disable capsule update features. + The default is FALSE for disabled. Add ```-D CAPSULE_ENABLE``` to the + build command line to enable capsule update features. + The build process generate capsule update image - QUARKFIRMWAREUPDATECAPSULEFMPPKCS7.Cap. + The user need copy QUARKFIRMWAREUPDATECAPSULEFMPPKCS7.Cap and CapsuleApp.efi + to a storage media attached to the Quark Board. + Then the user can boot to shell and run ```CapsuleApp QUARKFIRMWAREUPDATECAPSULEFMPPKCS7.Cap```. + In next reboot, the system firmware is updated. + +* ```RECOVERY_ENABLE``` - Used to enable/disable recovery features. + The default is FALSE for disabled. Add ```-D RECOVERY_ENABLE``` to the + build command line to enable recovery features. + The build process generates the recovery capsule image - QUARKREC.Cap. + Then the user need copy QUARKREC.Cap to a USB KEY, plug the USB KEY to the Quark Board. + In next boot, if a user runs ForceRecovery.efi in shell, or if a user presses the RESET button during power on, warm reset or REBOOT, + or if the FvMain is corrupted in flash, the system will boot into recovery mode. + +### **Example Build Commands** + +Default build with logging enabled: + +```build -a IA32 -t VS2015x86 -p QuarkPlatformPkg/Quark.dsc``` + +Release build with logging disabled: + +```build -a IA32 -t VS2015x86 -p QuarkPlatformPkg/Quark.dsc -b RELEASE``` + +Enable source level debugging: + +```build -a IA32 -t VS2015x86 -p QuarkPlatformPkg/Quark.dsc -D SOURCE_DEBUG_ENABLE``` + +Enable boot performance metrics: + +```build -a IA32 -t VS2015x86 -p QuarkPlatformPkg/Quark.dsc -D PERFORMANCE_ENABLE``` + +Enable UEFI Secure Boot features: + +```build -a IA32 -t VS2015x86 -p QuarkPlatformPkg/Quark.dsc -D UEFI_SECURE_BOOT``` + +Enable UEFI Secure Boot and Measured Boot using Atmel I2C TPM hardware device: + +```build -a IA32 -t VS2015x86 -p QuarkPlatformPkg/Quark.dsc -D UEFI_SECURE_BOOT -D MEASURED_BOOT_ENABLE -D TPM_12_HARDWARE=ATMEL_I2C``` + +## **FLASH Update using DediProg SF100** + +Once the sources have been downloaded, an EDK II build environment established, +and an EDK II firmware image has been built, the EDK II firmware image needs to +installed into the FLASH device on the target Galileo development board. One +way to do this is with the [Dediprog SF100 IC Programmer]( +http://www.dediprog.com/pd/spi-flash-solution/SF100). + +* Install the DediProg SF100 software. + +* Connect the DediProg SF100 to the Galileo development board. + + ![](https://github.com/tianocore/tianocore.github.io/wiki/Projects/QuarkPlatformPkg/Images/Dediprog.jpg) + +* Make sure ```dpcmd.exe``` is in ```PATH``` + + ```PATH=%PATH%;"c:\Program Files (x86)\DediProg\SF100"``` + +* **NOTE**: It is recommended that the FLASH image that was shipped with the + Galileo development board be read and saved before updating FLASH image. The + command shown below read the FLASH image and saves it to the file + called ```GalileoOriginalFirmware.bin```. + + ```dpcmd.exe -r GalileoOriginalFirmware.bin``` + +* Update FLASH image using either the DediProg SF100 GUI or ```dpcmd.exe```. + - Example update of Galileo firmware image when BUILDTARGET is DEBUG (default) + + ```dpcmd.exe -u%WORKSPACE%\Build\Quark\DEBUG_VS2015x86\FV\QUARK.fd ``` + + - Example update of Galileo firmware image when BUILDTARGET is RELEASE + (```-b RELEASE```) + + ```dpcmd.exe -u%WORKSPACE%\Build\Quark\RELEASE_VS2015x86\FV\QUARK.fd ``` + +## **Setting up a Serial Console and Booting to UEFI Shell** + +After the FLASH is updated on Galileo, a serial cable is connected between the +host system and the Galileo target. A serial terminal emulator (such as +[Tera Term](https://en.osdn.jp/projects/ttssh2/releases/)) can be used to see +the logging messages from DEBUG() macros and the serial console for the UEFI +Boot Manager, UEFI Shell, and operating system. + +The default serial communication parameters for the Intel(R) Galileo Gen 2 +Development Board is 921600,n,8,1 with no hardware flow control. + +![](https://github.com/tianocore/tianocore.github.io/wiki/Projects/QuarkPlatformPkg/Images/TeraTermSerialParameters.png) + +The default serial communication parameters for the Intel(R) Galileo Development +Board is 461800,n,8,1 with no hardware flow control. + +The following changes to the [Tera Term](https://en.osdn.jp/projects/ttssh2/releases/) +configuration files are recommended for UEFI serial console compatibility. +Some of the later use cases involve using the TCPIP mode, so some of these +recommendation apply to the TCPIP use cases. + +* TERATERM.INI - Set terminal size to 80 x 25 and terminal settings to UTF8. + +![](https://github.com/tianocore/tianocore.github.io/wiki/Projects/QuarkPlatformPkg/Images/TeraTermTerminal.png) + +* TERATERM.INI - Set font type to Terminal to support box drawing glyphs. + +![](https://github.com/tianocore/tianocore.github.io/wiki/Projects/QuarkPlatformPkg/Images/TeraTermFont.png) + +* TERATERM.INI - Disable line mode to make TCPIP mode work like COM port mode. + +```ini +; Line at a time mode +EnableLineMode=off +``` + +* KEYBOARD.CNF - Disable VT function keys for F5..F10 + +```ini +[VT function keys] +;F6 key +;F6=64 +;F7 key +;F7=65 +;F8 key +;F8=66 +;F9 key +;F9=67 +;F10 key +;F10=68 +``` + +* KEYBOARD.CNF - Disable X function keys for F1..F4 + +```ini +[X function keys] +; F1 key +XF1=off +; F2 key +;XF2=60 +XF2=off +; F3 key +;XF3=61 +XF3=off +; F4 key +;XF4=62 +XF4=off +; F5 key +;XF5=63 +``` + +* KEYBOARD.CNF - Add UEFI serial console sequences for F1..F10 + +```ini +[User keys] +User1=59,0,$1B[M +User2=60,0,$1B[N +User3=61,0,$1B[O +User4=62,0,$1B[P +User5=63,0,$1B[Q +User6=64,0,$1B[R +User7=65,0,$1B[S +User8=66,0,$1B[T +User9=67,0,$1B[U +User10=68,0,$1B[V +``` + +Connect power adapter to Galileo development board, and the logging messages +should be seen, followed by 5 second countdown, followed by an automatic boot to +the built-in UEFI Shell. + +![](https://github.com/tianocore/tianocore.github.io/wiki/Projects/QuarkPlatformPkg/Images/UefiShell.png) + +## **Source Level Debug Using Intel(R) UEFI Development Kit Debugger Tool** + +### Pre-requisites + +* Intel(R) UEFI Development Kit Debugger Tool User Manual for Ver 1.5 or higher: + Available from https://firmware.intel.com/develop/intel-uefi-tools-and-utilities/intel-uefi-development-kit-debugger-tool +* Intel(R) UEFI Development Kit Debugger Tool Ver 1.5 or higher: Available from + https://firmware.intel.com/develop/intel-uefi-tools-and-utilities/intel-uefi-development-kit-debugger-tool +* [Tera Term](https://en.osdn.jp/projects/ttssh2/releases/) or other serial + terminal emulator with TCPIP support + +Follow instructions in Intel(R) UEFI Development Kit Debugger Tool User manual +to setup host system. + +Build a firmware image with SOURCE_DEBUG_ENABLE enabled +(```-D SOURCE_DEBUG_ENABLE```). This will select the appropriate libraries, +debug agent, and PCDs for Galileo. Galileo does not support a USB 2.0 debug +port, so only the UART based communications library is used. + +Use Dediprog SF100 to update the Galileo development board FLASH image. + +Update the ```[Debug Port]``` section of the SoftDebugger.ini file with the host +side UART configuration settings. The following example uses COM5, which must +be updated with the COM port the Galileo target is attached. The following +example also shows a baud rate of 921600 which is correct for a Galileo Gen 2. +If a Galileo Gen 1 is being used, set the baud rate to 460800. By default, the +Galileo console is redirected to TCPIP port 20715. + +```ini +[Debug Port] +Channel = Serial +Port = COM5 +FlowControl = 0 +BaudRate = 921600 +Server = +``` + +Connect power adapter to Galileo development board and run a command script with +the contents below to start a Tera Term session on TCPIP port 20715 and start +the Intel(R) UEFI Development Kit Debugger Tool using UART connection between +the host and target and WinDbg. The REBOOT button on the Galileo development +board may need to be pressed for the debugger to perform the initial connect. + +```cmd +start "Console" /B "c:\Program Files (x86)\teraterm\ttermpro.exe" localhost:20715 /nossh +start "Debugger" /B "C:\Program Files (x86)\Intel\Intel(R) UEFI Development Kit Debugger Tool\eXdi.exe" /LaunchWinDbg +``` + +The figure below should be seen when a connection is made. The SoftDebugger +Debug Console window shows the status of the connection between the host and the +target. The Tera Term window shows the console output from the SEC phase until +the debug agent is initialized. The WinDbg window shows that the debugger is +connected and the WinDbg application can be used for run control, breakpoint +management, and viewing call stacks, local variables, global variables, etc. + +![](https://github.com/tianocore/tianocore.github.io/wiki/Projects/QuarkPlatformPkg/Images/UdkDebugger.png) + +## **Debug Using Intel(R) System Debugger using OpenOCD** + +Setup hardware and software components following the instructions in the article at: +https://software.intel.com/en-us/articles/using-intel-system-debugger-with-openocd + +Connect power adapter to Galileo development board. + +The following batch file starts Tera Term serial console on COM5 at 921600 baud, +starts OpenOCD using a Flyswatter2, and starts Intel(R) System Studio Debugger. +Select the **Connect** button to complete the host to target connection. + +```cmd +set OPENOCD="C:\Program Files (x86)\IntelSWTools\system_studio_for_windows_2016.0.023\debugger\openocd" +start "Console" /B "c:\Program Files (x86)\teraterm\ttermpro.exe" /C=5 /BAUD=921600 +start "OpenOcd" /B %OPENOCD%\bin\openocd.exe -f ..\scripts\interface\ftdi\flyswatter2.cfg -f ..\scripts\board\quark_x10xx_board.cfg +call "C:\Program Files (x86)\IntelSWTools\System Debugger 2016\system_debugger\start_xdb_gdb_remote.bat" +``` + +When **Reset Target** is selected, the Galileo development board does not always +halt at the first instruction at the reset vector. If debug is required from +the first instruction of the reset vector, then update the file +```UefiCpuPkg/SecCore/Ia32/ResetVector.asm``` and change the two NOP +instructions at the label ```ResetHandler:``` to ```JMP $```. This puts the CPU +into a wait loop until the debugger is connected and the debugger is used to set +instruction pointer to the next instruction. + +``` +; +; For IA32, the reset vector must be at 0xFFFFFFF0, i.e., 4G-16 byte +; Execution starts here upon power-on/platform-reset. +; +ResetHandler: +; nop +; nop + jmp $ +ApStartup: + ; + ; Jmp Rel16 instruction + ; Use machine code directly in case of the assembler optimization + ; SEC entry point relative address will be fixed up by some build tool. + ; + ; Typically, SEC entry point is the function _ModuleEntryPoint() defined in + ; SecEntry.asm + ; + DB 0e9h + DW -3 +``` + +## **Install, Configure, and Boot Linux** + +* Download SD Card Linux Image: Available at + http://www.intel.com/content/www/us/en/support/boards-and-kits/intel-galileo-boards/000005614.html +* Extract the SD Card Linux Image to a FAT formatted Micro SD FLASH device +* Install Micro SD FLASH device into Galileo development board + +Connect power adapter to Galileo development board and boot to the UEFI Shell. + +From the UEFI Shell execute the following commands to copy the GRUB EFI boot +loader to ```\efi\boot\bootia32.efi```. This allows the UEFI Boot Manager, on +all future boots, to auto detect that the Micro SD FLASH device is bootable. + +``` +Shell> connect -r +Shell> map -r +Shell> fs0: +FS0:> mkdir efi +FS0:> mkdir efi\boot +FS0:> cp grub.efi efi\boot\bootia32.efi +``` + +The GRUB boot loader is set to a UART baud rate of 115200. A couple changes are +required to change the baud rate to 460800 for Galileo Gen 1 or 921600 for +Galileo Gen 2. From the UEFI Shell, execute the following commands to make a +backup copy and edit the GRUB configuration file. + +``` +FS0:> cp boot\grub\grub.conf boot\grub\grub.conf.org +FS0:> edit boot\grub\grub.conf +``` + +* Delete the lines associated with the boot option with the following title. + +``` +title Clanton SVP kernel-SPI initrd-SPI IMR-On IO-APIC/HPET NoEMU +``` + +* Replace the two instances of 115200 in the following line to 460800 for + Galileo Gen 1 or 921600 for Galileo Gen 2. + +``` +kernel /bzImage root=/dev/ram0 console=ttyS1,115200n8 earlycon=uart8250,mmio32,$EARLY_CON_ADDR_REPLACE,115200n8 reboot=efi,warm apic=debug rw LABEL=boot debugshell=5 rootimage=image-full-galileo-clanton.ext3 +``` +* Press F3 to save the file +* Run the ```exit``` command to exit from the UEFI Shell and return to the + UEFI Boot Manager +* Select **Boot Manager** +* Select **UEFI Misc Device** for the Micro SD FLASH device. +* GRUB should run and Linux should boot with serial log messages. +* When the serial log messages stop, change the Tera Term baud rate to 115200 +* Login as ```root```. No password is required. +* Use ```vi``` to edit ```/etc/inittab``` +* Change the baud rate of ttyS1 from 115200 to 460800 for Galileo Gen 1 or + 921600 for Galileo Gen 2. The line that need to be updated is shown below + +``` +S:2345:respawn:/sbin/getty 115200 ttyS1 +``` + +* Save the updated ```/etc/inittab``` +* Run ```reboot -f``` to shutdown Linux and reboot the platform. +* Set the Tera Term baud rate back to 460800 for Galileo Gen 1 or 921600 for + Galileo Gen 2. + +After these changes both the EDK II firmware and the Linux operating system use +the same baud rate. + +### **Testing ACPI S3 Sleep** + +The ACPI S3 Sleep and Resume feature can be tested on a Galileo development +board using the Real Time Clock (RTC) for a wake event. The shell script shown +below arms the RTC wake alarm 10 seconds in the future and puts the system to +sleep. A shorter time in seconds can be passed in as the first argument to the +script, but do not use times shorter than 2 or 3 seconds. + +**NOTE**: The stmmac module is unloaded because the module is not compatible +with S3 resume. + +```sh +# +# Unload NIC driver that causes S3 to fail +# +rmmod stmmac + +# +# Disable RTC wake alarm +# +echo 0 > /sys/class/rtc/rtc0/wakealarm + +# +# Compute wake time that is $1 seconds in the future +# +let WakeTime=`date '+%s'` +echo $WakeTime +if ["$1" = ""]; then + let WakeTime=$WakeTime+10 +else + let WakeTime=$WakeTime+$1 +fi +echo $WakeTime + +# +# Enable RTC wake alarm $1 seconds in the future +# +echo $WakeTime > /sys/class/rtc/rtc0/wakealarm + +# +# Put systems into ACPI S3 sleep state +# +echo mem > /sys/power/state +``` + +## **UEFI Secure Boot Feature and Physical Presence** + +Build a firmware image with SECURE_BOOT_ENABLE enabled +(```-D SECURE_BOOT_ENABLE```). This builds in support for UEFI authenticated +variables, UEFI image verification, and UEFI Secure Boot configuration screens +in the Device Manager. In order to change the UEFI Secure Boot configuration, +the user must assert physical presence. The Galileo development board only has +two push buttons (REBOOT and RESET). The REBOOT button unconditionally reboots +the platform. The RESET button asserts the reset signal on the Arduino header +and is also connected to a GPIO pin, so the state of the RESET button can be +read. The user asserts physical presence by holding the RESET button while the +Galileo development board boots, or by holding the RESET button while selecting +the **Secure Boot Configuration** option in the Device Manager. + +Use Dediprog SF100 to update the Galileo development board FLASH image. + +Connect power adapter to Galileo development board and boot to the UEFI Boot +Manager by pressing F2 or running the ```exit``` command from the UEFI Shell. +Select **Device Manager** and then**Secure Boot Configuration**. Change +**Customize Secure Boot** to **Customized** and then select **Custom Secure Boot +Options**. If **Custom Secure Boot Options** can not be selected, then physical +presence was not asserted using one of two methods listed above. Assert +physical presence and try again. + +The **Custom Secure Boot Options** screen allows the Galileo development board +to be enrolled into UEFI Secure Boot. See [How to Sign UEFI Drivers & Application V1.31]( +http://sourceforge.net/projects/edk2/files/General%20Documentation/SigningUefiImages%20-v1dot31.pdf/download) +in the [SecurityPkg Wiki](https://github.com/tianocore/tianocore.github.io/wiki/SecurityPkg) +for details on how to complete the UEFI Secure Boot enrollment. + +## **Enable Measured Boot Feature using Atmel I2C TPM on CryptoShield** + +Build a firmware image with MEASURED_BOOT_ENABLE enabled +(```-D MEASURED_BOOT_ENABLE```) and TPM_12_HARDWARE set to ATMEL_I2C +(```-D TMP_12_HARDWARE=ATMEL_I2C```). This builds in the TCG PEIM and DXE +modules and uses the library for the Atmel I2C TPM hardware device. + +Use Dediprog SF100 to update the Galileo development board FLASH image. + +Attach the CryptoShield to the Arduino header of the Galileo development board +as shown below. + +![](https://github.com/tianocore/tianocore.github.io/wiki/Projects/QuarkPlatformPkg/Images/GalileoCryptoShield.jpg) + +Connect power adapter to Galileo development board and boot to the UEFI Shell. +In the boot logging messages, messages similar to the following should be seen +as the Atmel I2C TPM hardware device is detected and used to measure the +contents of firmware volumes and firmware tables. + +``` +Loading PEIM at 0x0000FC75188 EntryPoint=0x0000FC75260 TrEEConfigPei.efi +PROGRESS CODE: V03020002 I0 +TrEEConfiguration.TpmDevice from Setup: 1 +DetectTpmDevice: +TpmDevice final: 1 +TpmDevice PCD: 8B01E5B6-4F19-46E8-AB93-1C53671B90CC +. . . +Loading PEIM at 0x0000FC70190 EntryPoint=0x0000FC70260 TcgPei.efi +PROGRESS CODE: V03020002 I0 +Install PPI: E9DB0D58-D48D-47F6-9C6E-6F40E86C7B41 +Install PPI: A030D115-54DD-447B-9064-F206883D7CCC +PROGRESS CODE: V03020003 I0 +The FV which is measured by TcgPei starts at: 0xFFF10000 +The FV which is measured by TcgPei has the size: 0xF0000 +The FV which is measured by TcgPei starts at: 0xFFD00000 +The FV which is measured by TcgPei has the size: 0x1E0000 +. . . +Loading driver at 0x0000F620000 EntryPoint=0x0000F620260 TcgDxe.efi +. . . +TPM TcgDxe Measure Data when ReadyToBoot +``` +See the [SecurityPkg Wiki](https://github.com/tianocore/tianocore.github.io/wiki/SecurityPkg) +for additional details on EDK II TPM support + +## **Measuring Boot Performance** + +Build a firmware image with PERFORMANCE_ENABLE enabled +(```-D PERFORMANCE_ENABLE```). This builds in the UEFI Shell and the DP.EFI +(Dump Performance) into a firmware volume and also includes a simple file system +driver for firmware volumes so the DP.EFI command can be run out of the FLASH. + +Use Dediprog SF100 to update the Galileo development board FLASH image. + +Connect power adapter to Galileo development board and let it boot to the UEFI +Shell. Then use the REBOOT button or the ```reset``` UEFI Shell command to +reboot the Galileo development board. The first boot after a FLASH update does +extra work that is only performed one time. In order to get correct performance +measurements, use the 2nd or later boots. After the 2nd boot, run the +```dp -s``` command. The output should look similar to the figure below. + +![](https://github.com/tianocore/tianocore.github.io/wiki/Projects/QuarkPlatformPkg/Images/DpCommand.png) -- 2.21.0.windows.1