From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=RChHt0tD; spf=pass (domain: linaro.org, ip: 209.85.221.66, mailfrom: ard.biesheuvel@linaro.org) Received: from mail-wr1-f66.google.com (mail-wr1-f66.google.com [209.85.221.66]) by groups.io with SMTP; Wed, 29 May 2019 05:50:29 -0700 Received: by mail-wr1-f66.google.com with SMTP id l17so1676692wrm.10 for ; Wed, 29 May 2019 05:50:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PioouVYqzySuzPS/Fhq+0cxVgfkpFzSlTCohEJIuO9w=; b=RChHt0tDc4gUrbO+YZBPH7evC52Q9afHOvWKnZgO4USsDjZ4f1KN4EPEiEyWbVirnc 5lE1tPaSESVZxRx/cZu5qR5t9u+oYPuQENbnm3+hY6mRqH63oXOU7dZerpdFUadEis7i tpmzn2RTFzYg0rkvc3J3rSz5FD35KtFpWaoLMEsSDOgFOsL7iiEzDunJpLkyWUuMvrYi Rj/zYOmT2MRjZ2yraxeaEn6nCHCF+UtxUhwmDoeOniVmdEkJL5gl43CRudH1LG9fswCx zCq5vhtZgRsua0uP3mxM22KZvzFsX8ry3JLDhFmFuIcLy2gVVf8r2DvZizz1dua18Fgu nVjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PioouVYqzySuzPS/Fhq+0cxVgfkpFzSlTCohEJIuO9w=; b=T21ykPlmAPHCSgAyti72LeU4UpnffRoq5dLde9d34q7rZu0lnZP3qNju7NbRP/DGln fz+G2kxVJLLql2cIWNo3aAcYHWzniSE5CdOZ+mmOyocE9Ep0yDs0W9oGnAwcm+onAI/R RGXZj19bL0XjonicIrtJU4JDwfv1DAtWY/Rscmu8rZJB+PhbHVF8razYBJ0On0iQwF5o Lzcn/UiP5cJuppGvVqqcAOiL/iO8KGQkQXDQDrjjClYvBMy0MPC4YkiKa4wX8Nz1RJhi 5OQThN0XZgQymUJUBO0Dd087Uw0QBd/udSMeMzsu793pxbrPd4nXjHeGZZIIJa9F5PE2 fekA== X-Gm-Message-State: APjAAAVyeJNnwRk7oxlYZeynHIZh0NVLi9dwFlrLvwH9MiS3XGVy9wQO ERsy566140fFl7DLYcVcHD5DZF/4KC4HZA== X-Google-Smtp-Source: APXvYqzUHUkqUX9wJshMXxhM/Z++Hr2rMxU01KWq3LwV2Xc2ouDasaOZ1MOPfDUss/HxyHOHUjdPTg== X-Received: by 2002:a5d:6389:: with SMTP id p9mr2655013wru.297.1559134227009; Wed, 29 May 2019 05:50:27 -0700 (PDT) Return-Path: Received: from sudo.home ([2a01:cb1d:112:6f00:c225:e9ff:fe2e:ea8]) by smtp.gmail.com with ESMTPSA id l18sm18112608wrv.38.2019.05.29.05.50.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 29 May 2019 05:50:26 -0700 (PDT) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, masahisa.kojima@linaro.org, Ard Biesheuvel Subject: [PATCH edk2-platforms 1/5] Silicon/SynQuacer: add missing SPI controller interrupt lines to DT Date: Wed, 29 May 2019 14:50:17 +0200 Message-Id: <20190529125021.28308-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190529125021.28308-1-ard.biesheuvel@linaro.org> References: <20190529125021.28308-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Update the DT description of the second SPI controller with the TX, RX and fault interrupt lines as they are assigned on SynQuacer. Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index 8559b5b329a7..f124a223816f 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -545,6 +545,9 @@ spi: spi@54810000 { compatible = "socionext,synquacer-spi"; reg = <0x0 0x54810000 0x0 0x1000>; + interrupts = , + , + ; clocks = <&clk_alw_1_8>; clock-names = "iHCLK"; socionext,use-rtm; -- 2.20.1