From: "Ard Biesheuvel" <ard.biesheuvel@linaro.org>
To: devel@edk2.groups.io
Cc: leif.lindholm@linaro.org, masahisa.kojima@linaro.org,
Ard Biesheuvel <ard.biesheuvel@linaro.org>
Subject: [PATCH edk2-platforms 2/5] Silicon/SynQuacer: add ACPI description of second SPI controller
Date: Wed, 29 May 2019 14:50:18 +0200 [thread overview]
Message-ID: <20190529125021.28308-3-ard.biesheuvel@linaro.org> (raw)
In-Reply-To: <20190529125021.28308-1-ard.biesheuvel@linaro.org>
The primary SPI controller on SynQuacer is reserved for the NOR
flash, and is not exposed to the OS. The second SPI controller is
wired to the low speed 96boards connector on DeveloperBox, and so
in order to use it, we must describe it to the OS (like we already
do in the device tree). So add the description to the DSDT as well.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 19 +++++++++++++++++++
Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 4 ++++
2 files changed, 23 insertions(+)
diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl
index c8d8120d262a..f6ff3988aa91 100644
--- a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl
+++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl
@@ -251,5 +251,24 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", "SYNQUACR",
Device (PWRB) {
Name (_HID, "PNP0C0C")
}
+
+ Device (SPI0) {
+ Name (_HID, "SCX0004")
+ Name (_UID, Zero)
+ Name (_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, SYNQUACER_SPI1_BASE, SYNQUACER_SPI1_SIZE)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 192, 193, 194 }
+ })
+
+ Name (_DSD, Package () // _DSD: Device-Specific Data
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package (2) { "socionext,ihclk-rate", 125000000 },
+ Package (2) { "socionext,use-rtm", 1 },
+ Package (2) { "socionext,set-aces", 1 },
+ }
+ })
+ }
} // Scope (_SB)
}
diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h
index deb9c81e82e6..29c5f73f2057 100644
--- a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h
+++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h
@@ -78,4 +78,8 @@
#define SYNQUACER_UART1_BASE 0x51040000
#define SYNQUACER_UART1_SIZE SIZE_4KB
+// SPI controller #1
+#define SYNQUACER_SPI1_BASE 0x54810000
+#define SYNQUACER_SPI1_SIZE SIZE_4KB
+
#endif
--
2.20.1
next prev parent reply other threads:[~2019-05-29 12:50 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-29 12:50 [PATCH edk2-platforms 0/5] SynQuacer SPI/TPM support Ard Biesheuvel
2019-05-29 12:50 ` [PATCH edk2-platforms 1/5] Silicon/SynQuacer: add missing SPI controller interrupt lines to DT Ard Biesheuvel
2019-05-29 12:50 ` Ard Biesheuvel [this message]
2019-05-29 12:50 ` [PATCH edk2-platforms 3/5] Platform/Secure96Dxe: redefine LS connector CS as platform property Ard Biesheuvel
2019-05-29 13:06 ` [edk2-devel] " Leif Lindholm
2019-05-29 13:14 ` Ard Biesheuvel
2019-05-29 14:43 ` Leif Lindholm
2019-05-29 18:03 ` Ard Biesheuvel
2019-05-29 12:50 ` [PATCH edk2-platforms 4/5] Platform/Secure96Dxe: add TPM description to SSDT Ard Biesheuvel
2019-05-29 12:50 ` [PATCH edk2-platforms 5/5] DO NOT MERGE - temporary hack to reset the TPM at probe time Ard Biesheuvel
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